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| publication# 21728 rev: a amendment/0 issue date: may 1997 this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. interfacing the am188 tm em controller to the dslac tm /qslac tm devices using the ssi application note the purpose of this application note is to show the user how to interface the am188?em micro- controller to the dslac? and qslac? devices using the synchronous serial interface (ssi). these techniques are not restricted to the am188em microcontroller; other members of the am186? microcontroller family with ssi ports can be interfaced in a similar fashion. background traditionally, line cards (if they had a processor at all) used a simple, inexpensive 8-bit microcontroller. how- ever, as the number of lines per card increases, 16-bit controllers like the am188?em microcontroller be- come more attractive for several reasons: n over time 16-bit controller costs have decreased n more peripheral functions are integrated, reducing external components counts n newer, smaller packaging options are available n 16-bit controllers generally offer larger address spaces these reasons, combined with the availability of supe- rior, low-cost development tools like microsoft & bor- land c, reduce time-to-market and long-term maintenance costs. the slac? device connects to the host processor through a 3-pin serial interface. while this interface is used primarily to initialize the slac device, several critical functions of the slic? device can be moni- tored through the serial interface; therefore, it may be necessary to make the interface as fast as possible. using the ssi port of the am188em microcontroller re- duces software overhead making the interface much faster. the serial microprocessor interface (mpi) of the dslac? and qslac? devices pre-dates mostif not allof todays industry standard serial interfaces ports, including the synchronous serial interface (ssi) port of the am188em microcontroller. because these two serial interfaces (mpi and ssi) were not designed to be compatible, it takes a little effort to make them work together. this application note attempts to show that it is worth the effort and explains how to do it. in most line-card designs, the only cost effective alter- native is to interface to the processors pios and ma- nipulate the mpi signal lines directly from software. while this is a perfectly acceptable approacheven desirable in some casesthe use of the ssi port can greatly reduce software overhead and code space. further references the remainder of this application note assumes at least a passing familiarity with the chips involved; the am188em microcontroller, the am79c02 dslac fam- ily, and the am79q02 qslac family. if additional de- tails are needed, the following literature is available from amd: am186?em/emlv and am188?em/emlv microcontrollers data sheet , order #19168 am186?em and am188?em microcontrollers users manual, order #19713 am79c02/03/031(a) dslac? device data sheet , order #18503 am79q02/021/031 qslac? device data sheet, available through your local amd sales office amds complete line of line card devices are found in the linecard products for the public infrastructure mar- ket data book , publication #18503. mpi hardware overview the qslac and dslac devices have very similar mpis; both are serial, master/slave-type interfaces. dif- ferences between the two devices are described in the following paragraphs. a system or line card micropro- cessor is the master and the interface is designed so that multiple slaves (i.e. slac devices) can be at- tached to a single masters mpi bus. the mpi signals, like most digital buses, consist of three types of signals: n clock/control n address n data the data line (dio) is a bidirectional, three-state serial bus. the am79c02 has separate data in (din) and data out (dout) pins that can be strapped together to look
2 interfacing the am188 tm em controller to the dslac tm /qslac tm devices using the ssi like the other slac devices single dio pin. the data on this line consists of eight-bit bytes transmitted most significant bit (msb, d7) first, regardless of direction. the master initiates all transfers by sending a com- mand byte to the slac device. each command has a predetermined length (number of bytes) and direction (read or write). for example, if the master microproces- sor sends out command number 25 (read gx filter co- efficients) to the dslac device, the dslac device knows to transmit two bytes. because the command determines what is transmitting, master or slave; it is important to make sure the software drivers are correct to prevent bus contention, which could damage the de- vices. also, in the case of a read, the slac device will not accept a new command until the old one is finished (i.e. all of the data is clocked out). software verification is critical. the clock signal (dclk) can free run or be active only during data transfers and is an input to the slac de- vice. the dclk maximum frequency is 4.096 mhz for both slac devices. data is clocked into the slac de- vice on the rising edge of dclk, but data is sent out on the falling edge of dclk. this common technique makes it easier to satisfy setup and hold time require- ments. dclk can be stopped indefinitely in either the high or low state if the chip select input is held high. each of the individual slac devices on the mpi bus is addressed (i.e. selected) by pulling one of the chip se- lect inputs low. the qslac device has a single chip select for all four channels while the dslac device has a separate chip select for each channel (cs1 and cs2). the rising edge of the chip select marks or frames the end of each byte; therefore, the chip select line must go high for at least the minimum off period before the next byte is read or written. the dslac de- vices minimum off period is 5 s while the qslac de- vices minimum is 2.5 s. finally, the qslac device does have an interrupt pin as part of the microprocessor interface. a description of this pin is available in the am79q02/03/031 qslac? device data sheet . ssi hardware overview the synchronous serial interface (ssi) on the am188em microcontroller was designed to provide a low pin-count interface to application-specific inte- grated circuits (asics). fortunately, although not by design, it is similar to the slac devices mpi. like the mpi, the ssi is a synchronous, master/slave serial bus protocol that allows multiple slaves on the bus. the maximum clock rate can be as high as 20 mhz. the ssi bus consists of four signals: n sclk n sdata n sden0 n sden1 each of these signals is on a separate pin. all of the pins are shared (i.e. multiplexed) with one of the am188em microcontrollers 32 pios. this allows the ssi pins to be used as pios if their normal ssi function is not needed. the sdata pin, like dio, is a bidirectional, three-state serial bus. unlike dio, a weak pull-up or pull-down re- sistor keeps the last value on the bus for systems that cannot tolerate three-state inputs. the data on this pin consists of eight-bit bytes transmitted least significant bit (lsb, d0) first. the master/slave protocol is con- trolled entirely with software. the clock signal (sclk) is only active during byte transfers and is an output. the frequency is derived from the processors internal clock by dividing it by 2, 4, 8, or 16. in the case of a 40-mhz device, this allows for speeds up to 20 mhz as mentioned above. like the slac device, data is clocked out on the falling edge and clocked in on the rising edge. the two enable pins (sden0 and sden1) are outputs and unlike the chip selects of the mpi, they are high- level active. while the state of the sden pins is con- trolled by software somewhat like a pio, the pin must be high for the interface to transmit or receive. comparing mpi to ssi table 1 summarizes the similarities and differences be- tween the two interfaces. interfacing the am188 tm em controller to the dslac tm /qslac tm devices using the ssi 3 table 1. mpi and ssi comparison solving the reversed-bit-order problem the reversed-bit-order problem is not as severe as it might seem. generally, there are two types of data sent over the serial interface: coefficients and bit flags. in most cases, coefficients are generated by amslac? software and stored as hex values in a table in the microprocessors non-volatile storage. it should not be difficult to rearrange the bit order prior to placing them in the table, preventing the need for the microprocessor to do it. the bit flags are used to monitor or set the state of the slac devices i/o pins in real time, but because the bit flags are independent, the host microprocessors code only needs to know where they are in the byte. order is not important. bit reversal should not be significant as it is taken into account by software. in both cases, it should not be necessary to do bit re- versal in the microprocessor while in use. solving the enable-polarity problem the obvious solution is to use inverters on the sden outputs, but with a little bit of extra software, it is possi- ble to do without the glue logic. because the dslac device requires two chip selects and the qslac de- vice requires one chip select, if inverters are used, this technique can only handle one dslac device or two qslac devices. if more slac devices are required, the easiest solution is to use general pios on the am188em microcontroller to drive the chip selects of the slac devices. the alternate solution is to use the am188em micro- controllers pio pins instead of sden to drive the chip selects. as discussed above, if multiple slac devices are on the bus and more than two chip selects are needed, pios are required anyway. always using pio pins maintains consistency and is the better solution. software will still need to control the de0 and de1 bits as if sden0 and sden1 were used. however, be- cause their pins are not used, they can be programmed as pios and used to drive the chip selects. no pins are wasted. using software to drive the slac devices chip selects through pios also provides a solution for the polarity problem and cs framing issue. because software is controlling the state of the pios directly, it is trivial to in- vert the sense of the pios relative to sden0 or sden1. correctly controlling the chip selects further requires that cs go high after each byte is transmitted or received. the multiple writes and reads illustrated in the am186?em and am188?em microcontrollers users manual in figures 11-5 and 11-6 are not allowed. figure 1 shows the resulting connections for a dslac device. the qslac device is similar, but has only one chip select. figure 1. interface connections timing considerations the following tables compare the timing requirements for the worst case. for each case in the table, the worst case is determined by looking at the most stringent re- quirement to see if the other end of the interface can meet the requirement. there is only one speed grade for the dslac device and the qslac device, but there are multiple speed grades of the am188em microcon- troller, so each case has been looked at with the worst possibility in mind. for example, in table 2, the date setup time for the case where the am188em microcontroller is driving feature mpi ssi comment word size 8 8 ok bit order msb first lsb first bit order is reversed master/slave yes yes ok max frequency 4.096 mhz up ok transmit clock edge falling falling ok receive clock edge rising rising ok clock inactive state either high ok synchronous yes yes ok cs framed yes yes and no yes, with software enable state low high cs and sden are the wrong polarity sdata (pin 23) sclk (pin 26) pio22 (pin 25) dio (pin 21) dclk (pin 19) cs1 (pin 32) pio23 (pin 24) cs2 (pin 31) g am188em(tqfp) am79c03(plcc) 4 interfacing the am188 tm em controller to the dslac tm /qslac tm devices using the ssi data out to the dslac device is calculated as de- scribed in the following paragraph. the dslac device requirement is read directly from the data sheet parameter #10 (t ids - input data setup time). this value is 30 ns for both the dslac and qslac devices. determining what the am188em mi- crocontroller provides takes a little calculation. first, decide what the minimum low period is for sclk. this is really determined by the dslac device, where the minimum dclk low period is determined by parameter #3 (t dcl - data clock low pulse width), which is 97 ns. sdata is guaranteed to be stable no more than 25 ns after the falling edge of sclk by parameter #78 (t sldv - sclk low to data valid) for the slowest pro- cessor (20 mhz). subtracting 25 from 97 leaves 72 ns worst-case setup time before the rising edge of dclk. the previous example assumes worst-case duty cycle for dclk. the fastest clock allowed has a period of 244 ns, but if the clock is not perfectly symmetric, either the low or high period can be as short as 97 ns rather than one half of the clock rate (122 ns). in the case of the am188em microcontroller this is probably over-de- sign. because sclks frequency is related to one half clkouta, it should always be close to a 50% duty cy- cle. in this case, the data setup time provided by the am188em microcontroller is closer to 97 ns. as the tables illustrate, there are generous margins even in the worst case. in the case of the data hold time in table 2, there is no specification given in the am188em microcontroller data sheet for how quickly sdata can change after the clock goes low. it is assumed that the worst case is that sdata will instantaneously change as soon as sclk goes low. this means that the hold time pro- vided by the am188em microcontroller is the same as the minimum sclk high period specified by the dslac device as 97 ns. the cs setup and hold time times are given for the case where sden is driven from inverters as dis- cussed above. even though sden is driven by the ssi interface, it is still controlled by software by writing a one or zero to the de0 or de1 bits in the synchronous serial control (ssc) register. because they are con- trolled by software, the actual delays will be much longer than specified. the same will hold true if pios are used to drive the slac device chip selects. table 3 gives the usable options for each of the avail- able speed grades and the resultant data transfer rate. to achieve the maximum dclk rate of 4 mhz, the am188em microcontrollers internal frequency must be 8, 16, or 32 mhz (2, 4, or 8). table 2. microprocessor output (data write) table 3. microprocessor input (data read) software considerations the basics of using the ssi port from software can be illustrated with two subroutines; the first subroutine writes a byte to the slac device and the second reads a single byte. these two subroutines, along with initial- ization, form the core of the necessary drivers. the ssi port appears as five registers in the am188em microcontrollers peripheral control block. this 256-byte block can be located in either memory or i/o space at the location pointed to by the peripheral con- trol block relocation register. because the base loca- tion of the block can be moved, the location of individual registers is specified as an offset from the peripheral control block relocation register rather than an absolute address. the pio ports and control registers are also located in this block of addresses. at reset, the block is located at 0ff00h in the i/o space. dslac device requires (ns, min) am188em microcontroller provides (ns, min) comments data setup time 30 72 ok data hold time 30 97 ok cs setup time 70 219 ok cs hold time 0 122 ok am188em microcontroller requires (ns, min) dslac device provides (ns, min) comments data setup time 10 47 ok data hold time 3 97 ok interfacing the am188 tm em controller to the dslac tm /qslac tm devices using the ssi 5 table 4. ssi port registers the bit-level definitions from the ssi port registers from table 4 are shown in figure 2. figure 2. bit-level definition of ssi port registers the port busy (pb) bit in the status register goes high when a transmit or receive operation is in progress. the two sden enables (de0 and de1) control the state of sden and enable transmission or reception. a write to the transmit register or a read of the receive register initiates the transfer. for a more complete functional description of these registers, including the features not used here, refer to the am186?em and am188?em microcontrollers users manual . assuming the connections in figure 1, the following steps are required to execute the read revision code number command (#23) of the dslac device. send the command: 1. enable cs1, set pio 22 low [pdata1 bit 6 = 0] 2. enable transmit, set de0 high [ssc bit 0 = 1] 3. write the command, bit reversed [ssd0 = 0ceh] 4. wait for pb to go low [sss bit 0 = 0] 5. disable transmit, set de0 low [ssc bit 0 = 0] 6. disable cs1, set pio 22 high [pdata1 bit 6 = 1] after waiting 5 ms, receive the data: 1. enable cs1, set pio 22 low [pdata1 bit 6 = 0] 2. enable receive, set de0 high [ssc bit 0 = 1] 3. start reception [read ssr] 4. wait for pb to go low [sss bit 0 = 0] 5. disable receive, set de0 low [ssc bit 0 = 0] 6. disable cs1, set pio 22 high [pdata1 bit 6 = 1] 7. read revision number [read ssr] appendix a provides the listings for two general pur- pose read and write routines. they have been coded in assembly language to maximize speed. in most cases the natural flow of the software will guarantee that there is at least 5 ms between bytes. in the listing given, the print commands between writes and reads take much longer than 5 ms. if this is not the case, either a soft- ware delay or the am188em microcontrollers timer could provide the necessary wait. initialization there are two parts to the initialization process. first, the on-board peripheral of the am188em microcontrol- ler (pio and ssi ports) must be set up for proper oper- ation. this includes setting the mode and direction of the pio pins as well as setting the pin itself to a known state. second, now that the interface is operational, the slac device itself should be initialized. each of the slac devices have a recommended power-up se- quence that can be found in the data sheet. as an ex- ample, the dslac devices recommended sequence is as follows: 1. select mclk (command #6), 2. software reset (command #2), 3. program coefficients and parameters, 4. activate (command #5) the am188em microcontrollers pio and ssi port should be initialized as soon as possible after reset to ensure the output pins are in the correct state, but 1 ms is needed after power is stable before commands can be sent to the slac device. because the am188em microcontroller also requires 1 ms for pll lock (param- eter #61 - t lock ), most systems have an external power-up-reset monitor that provides this delay. if not, or if the systems have separate power supplies, soft- ware must wait before sending the first command. the qslac device has a power interruption flag (p1, com- mand 23 bit 7) that should be checked after the delay. offset from pcb register mnemonic register name 10h sss synchronous serial status 12h ssc synchronous serial control 14h ssd1 synchronous serial transmit 1 16h ssd0 synchronous serial transmit 0 18h ssr synchronous serial receive sss 76543210 ssc ssd1 ssd0 ssr re/ de dr/ dt pb sclkdiv de1 de0 transmit register 1 transmit register 0 receive register 6 interfacing the am188 tm em controller to the dslac tm /qslac tm devices using the ssi software listing the software listing in appendix a is written in c and compiled with microsofts c/c++ compiler. this exam- ple code illustrates how to read the dslac devices z filter coefficients. the software was tested on several of the evaluation boards available from amd. an aslac ? interface board (acif) was used to load a known set of coefficients into a dslac device low noise board. an sd186em demonstration board was then connected in place of the acif board to read back the coefficients. the main body of the program first initializes the vari- ous ports, then sends a "read z filter" command. as noted previously, the command must be bit reversed. the "for" loop then reads back the 14 bytes of the z fil- ter coefficients. the subroutines ssi_read and ssi_write are written in assembly language for speed and clarity. they implement the code required to send or receive a single byte. once again, the bytes coming back from the dslac device are bit reversed. summary while the two serial interfaces were not designed to be used together, they are surprisingly compatible. the two simple fixes required to make them work together are worth the effort to save code space and speed up operation. a-1 appendix a software listing #include a-2 for (i=0; i<14; i++) { buf[i] = ssi_read(); printf("byte %d = %x \n",i,buf[i]); } /* end for loop */ exit(0); } //****************************** end of main ******************************* void ssi_init(void) { _asm{ mov dx,piomode1 // point to mode register in ax,dx // read register (in io space) or ax,0x00c0 // set bits low (to make output) out dx,ax // write to register (in io space) mov dx,pdir1 // point to pio1 direction register in ax,dx // read and ax,0xff3f // set pio direction bit (to output) out dx,ax // write mov dx,pdata1 // point to pio1 data register in ax,dx // read or ax,0x00c0 // set pio data bits (to make them high) out dx,ax // write mov dx,ssc // point to sync serial control register mov ax,0x0030 // set clk divisor to 16, enables low (inactive) out dx,ax // write } /* end _asm */ } //============================ end of ssi_init ============================= a-3 uint8 ssi_read(void) { int i; _asm{ mov dx,pdata1 // step 1 - set cs1 low (pio 22) in ax,dx // and ax,p22_low // out dx,ax // mov dx,ssc // step 2 - enable reception in ax,dx // (i.e. set bit de0 = 1) or ax,de0_hi // out dx,ax // mov dx,ssr // step 3 - start reception in ax,dx // (with dummy read of ssr) mov dx,sss // step 4 - wait for data h1: in ax,dx // (done when pb = 0) and ax,pb_hi // jnz h1 // mov dx,ssc // step 5 - disable reception in ax,dx // (set de0 low) and ax,de0_low // out dx,ax // mov dx,pdata1 // step 6 - set cs1 high (pio 22) in ax,dx // or ax,p22_hi // out dx,ax // mov dx,ssr // step 7 - read the data in ax,dx // a-4 mov i,ax // move data to output variable } /* end _asm */ return(i); } //============================ end of ssi_read ============================= static void ssi_write(i) int i; { _asm{ mov dx,pdata1 // step 1 - set cs1 low (pio 22) in ax,dx // and ax,p22_low // out dx,ax // mov dx,ssc // step 2 - enable transmission in ax,dx // (i.e. set bit de0 = 1) or ax,de0_hi // out dx,ax // mov dx,ssd0 // step 3 - transmit byte mov ax,i // out dx,ax // mov dx,sss // step 4 - wait for completion h1: in ax,dx // (done when pb = 0) and ax,pb_hi // jnz h1 // a-5 mov dx,ssc // step 5 - disable transmission in ax,dx // (set de0 low) and ax,de0_low // out dx,ax // mov dx,pdata1 // step 6 - set cs1 high (pio 22) in ax,dx // or ax,p22_hi // out dx,ax // } /* end _asm */ } //========================== end of ssi_write ============================== trademarks amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am186, am188, amslac, dslac, qslac, slac, and slic are trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies. |
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