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1 oki semiconductor Z550 uart 0.5 m m technology mega macrocell for universal asynchronous receiver/transmitter description the Z550 uart mega macrocell is a featured library element in all of oki? 0.5 m m sea of gates and 0.5 m m customer structured array families. the oki implementation of the mega macrocell is fully compatible with industry standard 16550 functions. the Z550 uart mega macrocell is an asynchronous communication element (ace), functionally equiv- alent to the industry standard 16550 with 16 byte fifos available on both the transmitter and receiver. it serves as a serial i/o interface in microcomputer systems performing serial to parallel conversions on data characters received from peripheral devices or modems and parallel to serial conversions on data charac- ters transmitted by the cpu. in fifo mode, the fifos are enabled allowing 16 bytes of data to be stored during both transmit and receive operations. the receive fifo also provides three bits per byte of error data. the status of the ace can be read at any time by the cpu. available information includes the type and condition of transfer operations being performed and error conditions involving parity, overrun, framing or break interrupt. the ace includes a built in baud rate generator with 18 programmable baud rates. features this mega macrocell data sheet contains all necessary information to enable the user to design a circuit using the Z550 functions for oki? 0.5 m m sea of gates and 0.5 m m customer structured array families. supported asic families family name family type msm13r0000 sea of gates msm98r000 customer structured array full double buffering full status reporting 16 byte receive and transmit fifos reduce cpu interrupts independent control of transmit, receive, line status data set interrupts and fifos modem control signals include: cts, dcd, dsr, dtr, ri, rts programmable serial interface characteristics: - 5, 6, 7, or 8 bit characters - odd, even, or no parity generation and detection - 1, 1.5, or 2 stop bits programmable baud rate generator (dc to 56k baud) unique oki methodology for input timing analysis tailored design flow and test procedure alleviates user from test vector generation to verify Z550 functionality specially developed software merges oki test vectors with the user? circuit
n Z550 uart n 2 oki semiconductor figure 1. logic symbol 1. row/column values (aspect ratio) include margin for layout overhead external to the mega macrocell for interconnection of input/output pins and power buses. recommended operating conditions (v ss = 0 v) parameter symbol rated value units min typ max power supply voltage v dd 2.7 3.3 3.6 v operating temperature t j -40 +25 +85 c mega macrocell characteristics mega macrocell description logic gate count used core raw gates number of mega macrocell pins number of core rows [1] number of core columns [1] Z550 asynchronous communication element 5392 9519 (56.6%) 46 57 167 do (0:7) di (0:7) cs 0-1 a (0:2) adsn dis disn dos dosn clk mr cts oe ddis dtr rts out1 out2 sout intr baud dsr ri dcd rclk sin txrdy rxrdy cs2n
n Z550 uart n 3 oki semiconductor figure 2. block diagram dis do 0-7 control logic rclk disn dos dosn adsn mr clk oe rxrdy txrdy ddis cs0 cs1 cs2n chip select logic data buffer di 0-7 a0 a1 a2 register select control and select logic interrupt logic transmitter fifo baud generator receiver fifo control and status register receiver shift register receiver control and timing sin baud transmitter shift register sout intr ri dcd dsr cts rts dtr out2 out1 modem control logic
n Z550 uart n 4 oki semiconductor signal descriptions signal name type fan-in fan-out max signal description di 0-7 i 1 - data input. data inputs 0-7 are used to transfer data and control information from the external system to the ace. di0 is the first data bit to be transferred. cs 0-1, 2n i 1 - chip select. the device is selected when cs0 and cs1 are high and cs2n is low. a 0-2 i 1 - address. address lines 0-2 select the internal registers. adsn i 1.6 - address strobe. the state of the chip select and address lines are latched when adsn is low. dis i 1 - read strobe. data transfers from the ace to the output data bus when dis is high. disn i 1 - read strobe. same as dis but active low. dos i 1 - write strobe. data transfers from the input data bus to the ace when dis is high. dosn i 1 - write strobe. same as dos but active low. clk i 1 - clock. input for external timing reference. mr i 1 - master reset. a high level resets the device, forcing the ace into an idle state and suspends all data activity until programmed to resume. the mcr and its output is cleared. the lsr is cleared except for the thre and temt bits, which are both sets. cts i 1 - clear to send. the state of cts can be read from bit 4 (cts) of the msr. bit 0 (dcts) of the msr is set if the cts input changes state since the last time the msr was read. cts low indicates to the ace that data on sout can be transmitted. dsr i 1 - data send ready. the state of dsr can be read from bit 5 (dsr) of the msr. bit 1 (ddsr) of the msr is set if the dsr input changes state since the last time the msr was read. dsr low indicates to the ace that there is data ready for it to receive. ri i 1 - ring indicator. a low signal indicates that a telephone ringing signal has been received by the modem. the state of ri can be read from bit 6 (ri) of the msr. bit 2 (teri) of the msr is set if the ri input changes from high to low since the last time the msr was read. dcd i 1 - data carrier detect. the dcd signal indicates that the data carrier has been detected by the modem. the state of dcd can be read from bit 7 (dcd) of the msr. bit 3 (ddcd) of the msr is set if the dcd input changed state since the last time the msr is read. rclk i 5 - receive clock. this signal is an external input to the ace's receiver logic (it is 16x the sin data rate). sin i 2.5 - serial input. the serial input receives serial data from the modem or other se- rial data source into the ace. do 0-4 do5 do6-7 o- 16 19 16 data output. data outputs 0-7 are used to transfer data and status informa- tion from the ace to your system. di0 is the first data bit to be received. oe o - 40 output enable. this signal is a 3-state control used to configure the lsi pins of the asic for production testing. ddis o - 15 driver disable. the macrocell asserts this signal low while the system is reading data from the ace.
n Z550 uart n 5 oki semiconductor dtr o - 16 data terminal ready. the macrocell sets this signal low when a logic 1 has bene written to bit 0 (dtr) of the mcr. this signal is set high when a logic 0 is written to bit 0 of the mcr or whenever a reset occurs. a low dtr indicates that the ace is ready to receive data. rts o - 16 request to send. this signal is set low by writing a logic 1 to bit 1 of the mcr. it is set high when a logic 0 is written to bit 1 of the mcr or whenever a reset occurs. a low rts signal indicates that the ace has data ready to transmit. out1 o - 16 output 1. this output is set low by writing a logic 1 to bit 2 of the mcr, and set high by writing a logic 0 to bit 2 of the mcr. out2 o - 16 output 2. this output is set low by writing a logic 1 to bit 3 of the mcr, and set high by writing a logic 0 to bit 3 of the mcr. sout o - 19 serial data out. this output is the serial data output of the ace's transmitter circuitry. intr o - 18 interrupt. the interrupt output goes high whenever a transmitter holding register empty, received data available, receiver error flag, modem status condition or trigger charge timeout (in fifo mode) is detected and it is en- abled in the ier. baud o - 15 baud rate out. this signal is the output of the internal baud rate generator. txrdy o - 19 transmit ready. this signal provides two types of dma signaling selected by bit 3 of the fcr when operating with the fifo's enabled. in mode 0 (bit 3 of the fcr = 0), txrdy will be active (= 0) when the xmit fifo and xmit holding register contain no characters. txrdy will go high when the first character is loaded into the holding register of the xmit fifo. this mode is normally used for single transfer dma operation. in mode 1 (bit 3 of the fcr = 1), txrdy will be active (=0) when there are no characters in the xmit fifo. txrdy will go high when the xmit fifo is com- pletely full. this mode is normally used when continual multiple transfers, that fill the fifo, are made. note: if the fifo's are disabled (fifo mode 0) only single dma transfers are allowed. rxrdy o - 19 receiver ready. this signal provides two types of dma signaling selected by bit 3 of the fcr when operating with the fifo's enabled. in mode 0 (bit 3 of the fcr = 0), rxrdy will be active (=0) when the rcvr fifo and rcvr holding register contain at least one characters. rxrdy will go high when there are no more characters in the fifo or holding register. this mode is normally used for single transfer dma operation. in mode 1 (bit 3 of the fcr = 1), rxrdy will be active (=0) when the timeout or trigger levels are reached. rxrdy will go high when the fifo or holding register is empty. this mode is normally used when continual multiple trans- fers, that fill the fifo, are made. note: if the fifo's are disabled (fifo mode 0) only single dma transfers are allowed. signal descriptions (continued) signal name type fan-in fan-out max signal description
n Z550 uart n 6 oki semiconductor functional description registers three types of internal registers are used in the ace. the three types are the control, status, and data registers. the control registers are the bit rate select register dll (divisor latch lsb) and dlm (divisor latch msb), line control register, interrupt enable register, and the modem control registers. the sta- tus registers are the line status registers and the modem status register. the data registers are the receiver buffer register and the transmitter holding register. the address, read, and write inputs are used in conjunction with the divisor latch access bit in the line control register [lcr(7)] to select the register to be written or read (see the table below). individual bits within these registers are referred to by the register mnemonic and the bit number in parenthesis. as an example, lcr(7) refers to line control register bit 7. transmitter buffer register and receiver buffer register the transmitter buffer register and receiver buffer register are data registers that hold from five to eight bits of data. if less than eight data bits are transmitted, data is right justified to the lsb. bit 0 of a data word is always the first serial data bit received and transmitted. the ace data registers are double-buffered so that read and write operations may be performed when the uart is performing the parallel-to-serial or serial-to-parallel conversion. line control register the format of the data character is controlled by the line control register. the contents of the lcr may be read, eliminating the need for separate storage of the line characteristics in system memory. the con- tents of the lcr is shown in figure 3 and described in the following table. 1. x = ?on? care? 0 = logic low, 1 = logic high. 2. the serial channel is accessed when ?s0 is low. serial channel internal register [1] [2] dlab a2 a1 a0 mnemonic register 0 0 0 x x x x x x 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 rbr thr ier iir lcr mcr lsr msr scr ddl dlm receiver buffer register (read only) transmitter holding register (write only) interrupt enable register interrupt identification register (read only) line control register modem control register line status register modem status register scratch register divisor latch (lsb) divisor latch (msb)
n Z550 uart n 7 oki semiconductor figure 3. line control register line control register description lcr bit(s) description lcr(0) and lcr(1) word length select bits. the number of bits in each serial character is programmed as shown below. lcr(2) stop bit select. lcr(2) specifies the number of stop bits in each transmitted character. if lcr(2) is a logic ?? one stop bit is generated. if lcr(2) is a logic ??when a 5 bit word length is selected, 1.5 stop bits are gener- ated. if lcr(2) is a logic ??when either a 6, 7, or 8 bit word length is selected, two stop bits are generated. the receiver checks for two stop bits if programmed to do so. lcr(3) parity enable. when lcr(3) is high, a parity bit between the last data word bit and stop bit is generated and checked. lcr(4) even parity select. when parity is enabled [lcr(3) = 1], lcr(4) = 0 selects odd parity, and lcr(4) = 1 selects even parity. lcr(5) stick parity. when parity is enabled [lcr(3) = 1], clr(5) = 1 causes the transmission and reception of a parity bit to be in the oppose state from that indicated by lcr(4). this allows parity to be forced to a known state and the receiver to check the parity bit in a known state. lcr(6) break control. when lcr(6) is set to a logic ?? the serial output (sout) is forced to the spacing (logic ?? state. the break is disabled by setting lcr(6) to a logic ?? the break control bit acts only on sout and has no effect on the transmitter logic. break control enables the cpu to alert a terminal in a computer communi- cations system. if the following sequence is used, no invalid characters will be transmitted because of the break. load all ?? (pad character) in response to thre. set the break in response to the next thre. wait for the transmitter to be idle (temt = 1), then clear the break when normal transmission is restored. lcr(7) divisor latch access bit (dlab). lcr(7) must be set high (logic ?? to access the divisor latches dll and dlm of the baud rate generator during read or write operations. lcr(7) must be set low (logic ?? to access the receiver buffer, the transmitter holding, or the interrupt enable registers. lcr 7 lcr 6 lcr 5 lcr 4 lcr 3 lcr 2 lcr 1 lcr 0 word length select stop bit select parity enable even parity select stick parity break control divisor latch access bit lcr(1) lcr(0) word length 0 0 1 1 0 1 0 1 5 data bits 6 data bits 7 data bits 8 data bits
n Z550 uart n 8 oki semiconductor line status register the line status register (lsr) is a single register that provides status indications. the lsr is usually the first register read by the cpu to determine the cause of an interrupt or to poll the status the serial channel. the contents of the lsr is shown in figure 4 and described in the following table. figure 4. line status register line status register description lsr bit(s) description lsr(0) data ready (dr). data ready is set high when an incoming character has been received and transferred into the receiver buffer register. lsr(0) is reset low by a cpu read of the data in the receiver buffer reg- ister. lsr(1) overrun error (oe). overrun error indicates that data in the receiver buffer register was not read by the cpu before the next character was transferred into the receiver buffer register, overwriting the previous character. the oe indicator is reset whenever the cpu reads the contents of the line status register. an overrun error will occur in the fifo mode after the fifo is full and the next character is completely re- ceived. the overrun error is deleted by the cpu on the first lsr read after it happens. the character in the shift register is not transferred to the fifo but it is overwritten. lsr(2) parity error (pe). parity error indicates that the received data character does not have the correct parity, as selected by lcr(3) and lcr(4). the pe bit is set high upon detection of a parity error, and is reset low when the cpu reads the contents of the lsr. in the fifo mode, the parity error is associated with a particular character in the fifo. lcr(2) indicates the error when the character is at the top of the fifo. lsr(3) framing error (fe). framing error indicates that the received character did not have a valid stop bit. lsr(3) is set high when the stop bit following the last data bit or parity bit is detected to be a logic ??(spacing level). the fe indicator is reset low when the cpu reads the contents of the lsr. in the fifo mode, the framing error is associated with a particular character in the fifo. lcr(3) indicates the error when the character is at the top of the fifo. lsr(4) break interrupt (bi). break interrupt is set high when the received data input is held in the spacing (logic ?? state for a full word transmission time (start bit + data bits + parity + stop bits). the bi indicator is reset when the cpu reads the contents of the line status register. in the fifo mode, this is associated with a particular character in the fifo. lcr(4) reflects the bi when the break character is at the top of the fifo. the error is deleted by the cpu when its associated character is at the top of the fifo during the first lsr read. only one zero character is loaded into the fifo when a bi occurs. lsr(1)-lsr(4) are the error conditions that produce a receiver line status interrupt [priority 1 interrupt in the interrupt identification register (iir)] when any of the conditions are detected. this interrupt is enabled by setting ier(2)=1 in the interrupt enable register. lsr 7 lsr 6 lsr 5 lsr 4 lsr 3 lsr 2 lsr 1 lsr 0 overrun error (oe) (error=1, no error=0) parity error (pe) (error=1, no error=0) framing error (fe) (error=1, no error=0) break interrupt (bi) (break=1, no break=0) transmitter holding register empty (thre) (empty=1, not empty=0) transmitter empty (temt) (empty=1, not empty=0) receiver fifo error (error in fifo=1, no error in fifo=0) data ready (dr) (ready=1, not ready=0)
n Z550 uart n 9 oki semiconductor fifo control register the fifo control register is a write only register at the same location as the iir. it is used to enable and clear the fifos, set the trigger level of the rcvr fifo, and select the type of dma signaling. figure 5. fifo control register lsr(5) thre indicates that the ace is ready to accept a new character for transmission. the thre bit is set high when a character is transferred from the transmitter holding roister into the transmitter shift register. lsr(5) is reset low by the loading of the transmitter holding register by the cpu. lsr(5) is not reset by a cpu read of the lsr. in fifo mode, when the xmlt fifo is empty, this bit is set. it is cleared when one byte is written to the xmlt fife. when the thre interrupt is enabled ier(1), thre causes a priority 3 interrupt in the iir. if thre is the in- terrupt source indicated in iir, lntr is cleared by a read of the iir. lsr(6) transmitter empty (temt). temt is set high when the transmitter holding register (thr) and the trans- mitter shift register (tsr) are both empty. lsr(6) is reset low when a character is loaded into the thr and remains low until the character is transferred out of sout. temt is not reset low by a cpu read of the lsr. in the fifo mode, when both the transmitter fifo and shift register are empty, this bit is set to one. lsr(7) this bit is always 0 in the z450 mode. in fifo mode, it is set when at least one of the following data errors is in the fifo: parity error, framing error or break interrupt indication. fifo control register description fcr bit(s) description fcr(0) fifo enable. enables both the xmlt and rcvr fifos. programming of other fcr bits is enabled by set- ting fcr(0)=1. the fifos operate in z450 mode when fcr(0)=0. all bytes in both fifos can be cleared au- tomatically from the fifos when changing from fifo mode to z450 mode and vice versa. fcr(1) rcvr fifo reset. this bit clears all bytes in the rcvr fifo and resets the counter logic to 0 when it is set to a one. it does not clear the receive shift register. fcr(2) xmlt fifo reset. this bit clears all bytes in the xmlt fifo and resets the counter logic to 0 when it is set to a one. this does not clear the transmit shift register. line status register description (continued) lsr bit(s) description fcr 7 fcr 6 fcr 5 fcr 4 fcr 3 fcr 2 fcr 1 fcr 0 receiver fifo reset (reset rx fifo = 1) transmit fifo reset (reset tx fifo = 1) dma mode select (dma mode 1 = 1, dma mode 0 = 0) not used receiver fifo interrupt trigger level fifo enable (fifo enable = 1)
n Z550 uart n 10 oki semiconductor modem control register the modem control register (mcr) controls the interface with a modem or data set as shown in figure 6 and the following table. the mcr can be written and read. the rts and dtr outputs are directly con- trolled by bits in this register. a high input asserts a low (true) at the output pins. figure 6. modem control register fcr(3) dma mode select. this bit controls the method of dma signaling that will be used. if fcr(3)=1, the part will operate in mode 1. it will be in mode 0 if fcr(3)=0. these modes are only valid if fcr(0)=1. it directly affects the operation of the rxrdy and txrdy outputs. fcr(4)-fcr(5) these bits are not used. fcr(6)-fcr(7) rx fifo interrupt trigger level. these two bits are used to set the trigger level for the rcvr fifo interrupt. modem control register description mcr bit(s) bit description mcr(0): when mcr(0) is set high, the dtr output is forced low. when mcr(0) is reset low, the dtr output is forced high. mcr(1): when mcr(1) is set high, the rts output is forced low. when mcr(1) is reset low, the rts output is forced high. mcr(2): when mcr(2) is set high, the out1 output is forced low. when mcr(2) is reset low, the out1 output is forced high. fifo control register description (continued) fcr bit(s) description fcr (7) fcr (6) rx fifo trigger level (bytes) 0 0 1 1 0 1 0 1 01 04 08 14 mcr 7 mcr 6 mcr 5 mcr 4 mcr 3 mcr 2 mcr 1 mcr 0 (rts) request to send (output high=0, output low=1) (out1) output1 (output1 set high=0, output1 set low=1) (out2) output1 (output2 set high=0, output2 set low=1) (loop) loopback function (disabled=0, enabled=1) bit is set to ? bit is set to ? bit is set to ? (dtr) data terminal ready (output high=0, output low=1)
n Z550 uart n 11 oki semiconductor modem status register the modem status register (msr) provides the cpu with status of the modem input lines from modems or peripheral devices. the msr allows the cpu to read the serial channel modem signal inputs by access- ing the data bus interface of the ace. in addition to the current status information, four bits of the msr indicate whether the modem inputs have changed since the last reading of the msr. the delta status bus are set high when a control input from the modem changes state, and reset low when the cpu reads the msr. the modem input lines are cts, dsr, ri, and dcd. msr(4) - msr(7) are status indications of these lines. a status bit = 1 indicates the input is a low. a status bit = 0 indicates the input is high. if the modem status interrupt in the interrupt enable register is enabled [ier(3)=1] an interrupt is generated whenever mcr(3): when mcr(3) is set high, the out2 output is forced low. when mcr(3) is reset low, the out2 output is forced high. mcr(4): mcr(4) provides a local loop back feature for diagnostic testing. when mcr(4) is set high, serial output (sout) is set to the marking (logic ?? state. the receiver data input, serial input (sin) is disconnected and the output of the transmitter shift register is looped back into the receiver shift register input. the four modem control inputs (cts, dsr, dcd, and ri) are disconnected. the four mcr bits dtr, rts, out1, and out2 are internally connected to msr(5), msr(4), msr(6), and msr(7) in that order. the modem control output pins are forced to their inactive state (high). in the diagnostic mode, data transmitted is immediately received. this allows the processor to verify the transmit and receive data paths of the selected serial channel. interrupt control is fully operational. however, interrupts are generated by controlling the lower four mcr bits internally. interrupts are not generated by activity on the external pins represented by those four bus. bits mcr(5) - mcr(7): permanently set to logic ?? modem control register description (continued) mcr bit(s) bit description
n Z550 uart n 12 oki semiconductor msr(0)-msr(3) is set to a one. the msr is a priority 4 interrupt. the contents of the modem status reg- ister are described in figure 7 and the following table. figure 7. modem status register reading the msr register will clear the delta modem status indications but has no effect on the other sta- tus bits. for lsr and msr, the setting of status bits is inhibited during status register read operations. if a status condition is generated during a read operation, the status bit is not set until the trailing edge of the read. if a status bit is set during a read operation, and the same status condition occurs, that status bit will be cleared at the trailing edge of the read instead of being set again. scratchpad register the scratchpad register is an 8-bit, read/ write register that has no effect on either channel in the ace. it is intended to be used by the programmer for temporarily data storage. modem status register description msr bit description msr(0) delta clear to send (dcts): dcts indicates that the cts input to the serial channel has changed state since the last time it was read by the cpu msr(1) delta data set ready (ddsr): ddsr indicates that the dsr input to the serial channel has changed state since the last time it was read by the cpu. msr(2) trailing edge of ring indicator (teri): teri indicates that the ri input to the serial channel has changed state from high to low since the last time it was read by the cpu. low to high transitions on ri do not activate teri. msr(3) delta data carrier detect (ddcd): ddcd indicates that the dcd input to the serial channel has changed state since the last time it was read by the cpu. msr(4) clear to send (cts): cts is the complement of the cts input from the modem indicating to the serial channel that the modem is ready to receive data from the serial channel's transmitter output (sout). if the serial channel is in loop mode [msr(4) = 1], msr(4) is equivalent to the rts value in the mcr. msr(5) data set ready (dsr): data set ready (dsr) is the compliment of the dsr input from the modem to the serial channel which indicates that the modem is ready to provide data to the serial channel receiver circuitry. if the channel is in the loop mode [mcr(4) = 1], msr(5) is equivalent to the dtr value in the mcr. msr(6) ring indicator (ri): is the compliment of the ri input. if the channel is in the loop mode [mcr(4) = 1], msr(6) is equivalent to the out1 value in the mcr. msr(7) msr(7) data carrier detect (dcd): data carrier detect indicates the compliment of the data carrier detect (dcd) input. if the channel is in the loop mode [mcr(4) = 1], msr(7) is equivalent to out2 value in the mcr. msr 7 msr 6 msr 5 msr 4 msr 3 msr 2 msr 1 msr 0 (ddsr) delta data set ready (teri) trailing edge of ring indicator (ddcd) delta data carrier detect (cts) clear to send (dsr) data set ready (ri) ring indicator (rlsd) receiver line signal detect (dcts) delta clear to send
n Z550 uart n 13 oki semiconductor interrupt identi?ation register the interrupt identification register (iir) in the serial channel of the ace provides interrupt interfacing capability. to minimize software overhead, the serial channel prioritizes interrupts into four levels. the four levels of interrupt conditions are: information indicating that a prioritized interrupt is pending and the type of interrupt is stored in the interrupt identification register (iir). when addressed during chip select time, the iir indicates the high- est priority interrupt pending. no other interrupts are acknowledged until that interrupt is serviced by the cpu. the contents of the iir is shown in the following tables. interrupt priorities interrupt condition priority receiver line status 1 received data ready 2 transmitter holding register empty 3 modem status 4 interrupt identification register bits iir bit(s) bit description iir(0) when iir(0) is low, an interrupt is pending. when iir(0) is high, no interrupt is pending. iir(1) and iir(2) these two bits are used to identify the highest priority interrupt pending as indicated in the following table. iir(3) this bit is always logic ??in z450 mode. in fifo mode, this bit is set along with iir(2) when a timeout interrupt is pending. iir(4) and iir(5) these bits of the iir are always logic ?? iir(6) and iir(7) frc(0)=1 sets these bits to logic ?? interrupt identification (iir) register description fifo mode only interrupt identification interrupt set and reset functions bit 3 bit 2 bit 1 bit 0 priority level interrupt flag interrupt source interrupt reset control 0001 - none none 0110 first receiver line status oe, pe, fe, or bi lsr read 0100 second received data available receiver data available for 450 or 550 mode, or trigger level reached for fifo mode rbr read or fifo drops below the trigger level
n Z550 uart n 14 oki semiconductor interrupt enable register the interrupt enable register (ier) is used to independently enable the four serial channel interrupts which activate the interrupt (intr) output. all interrupts are disabled by resetting ier(0) - ier(3) of the interrupt enable register to a logic ?? interrupts are enabled by setting the appropriate bits of the ier high. disabling the interrupt system inhibits the interrupt identification register and the intr output. all other system functions operate in their normal manner, including the setting of the line status and modem status registers. the contents of the interrupt enable register is described in the following table. . baud rate generator the ace serial channel contains a programmable baud rate generator (brg) that divides the clock (dc to 3.1 mhz) by any divisor from 1 to 216-1. the output of the baud rate generator is referred to as rclk. the frequency of rclk 16x the data rate. the desired divisor is calculated by the following equation: [divisor = clock ? (baud rate x 16)]. two 8-bit divisor latch registers store the divisor in a 16-bit binary for- mat. these divisor latch registers must be loaded during initialization. upon loading ether of the divisor latches, a 16-bit baud counter is immediately loaded. this prevents long counts on initial load. setting dll = 1 and dlm = 0 selects a divisor = 1 (dividing by 1 gives maximum baud rate for a given input fre- quency at the clk input). 1. the exact time will be [(word length) x 7 - 2] x 8 + [(trigger level - number of characters) x 8 + 1] rclks. 1100 second trigger change level indication minimum of one character in the rcvr fifo and no character input or removed during a time period depending on how many characters are in fifo and what the trigger level is set at (3.5 to 4.5 character times [1] ). rbr read 0010 third thre thre read of iir or thr write 0000 fourth modem status cts, dsr, ri, or dcd msr read interrupt enable register bits ier bit(s) bit description ier(0): when programmed high (ier(0) = logic ??, erbfi enables the received data available interrupt. ier(1): when programmed high (ier(1) = logic ??, etbei enables the transmitter holding register empty interrupt. ier(2): when programmed high (ier(2) = logic ??, elsi enables the receiver line status interrupt. ier(3): when programmed high (ier(3) = logic ??, edssi enables the modem status interrupt. ier(4) - ier(7): these four bits of the ier are logic ?? interrupt identification (iir) register description fifo mode only interrupt identification interrupt set and reset functions bit 3 bit 2 bit 1 bit 0 priority level interrupt flag interrupt source interrupt reset control
n Z550 uart n 15 oki semiconductor the brg can use any of four different popular frequencies to provide standard baud rates. these frequen- cies are 1.8432 mhz, 2.4576 mhz, 3.072 mhz, and 8 mhz. the following tables illustrate the divisors needed to obtain standard bit rates from 50 to 256k bps using these three clock frequencies. baud rates (1.8432 mhz clock) desired baud rate divisor used percent error difference between desired and actual 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 - - 0.026 0.058 - - - - - 0.69 - - - - - - - 2.86 baud rates (2.4576 mhz clock) desired baud rate divisor used percent error difference between desired and actual 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 3072 2048 1396 1142 1024 512 256 128 85 77 64 43 32 21 16 8 4 - - 0.026 0.0007 - - - - 0.392 0.260 + 0.775 - 1.587 - - -
n Z550 uart n 16 oki semiconductor master reset after power up, the ace mr input should be held high to reset the ace to an idle mode. a high, logic ?? on mr causes the following: 1. initializes the transmitter and receiver internal clock counters. baud rates (3.072 mhz clock) desired baud rate divisor used percent error difference between desired and actual 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 3840 2560 1745 1428 1280 640 320 160 107 96 80 53 40 27 20 10 5 - - 0.026 0.034 - - - - 0.312 - - 0.628 - 1.23 - - - baud rates (8 mhz clock) desired baud rate divisor used to generate 16x clock percent error difference between desired and actual 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 128000 256000 1000 6667 4545 3717 3333 1667 833 417 277 250 208 139 104 69 52 26 13 9 4 2 0.005 0.010 0.013 0.010 0.020 0.040 0.080 0.080 0.160 0.080 0.160 0.644 0.160 0.160 0.160 0.790 2.344 2.344
n Z550 uart n 17 oki semiconductor 2. clears the line status register (lsr), except for transmitter shift register empty (temt) and trans- mit holding register empty (thre), which are set. when interrupts are subsequently enabled, an interrupt occurs due to thre. the modem control register (mcr) is also cleared. all of the discrete lines, memory elements and miscellaneous logic associated with these register bits are also cleared or turned off. the line control register (lcr), divisor latches, receiver buffer register, and transmit- ter buffer register are not effected. a summary of the effect of a reset on the ace is given in the table below. following removal of the reset condition (mr low), the ace remains in the idle mode until programmed. if rclk is connected to the baudout signal, then while loading dll and dlm registers, x? appear on baud- out pins and propagate through to the lsr register. subsequent reads of this lsr register cause x? to appear on the data bus. the following solutions can solve the above problem. at the very beginning of simulation, until data is written into the dll and dlm registers, hold rclk to a known value (either ??or ??. the rclk input can be connected to baudout after writing data to these registers. during real chip operation, the ??or ??value eventually propagates into the lsr register, so this is not a design problem. unknown states are created during simulation because there is a feedback loop in the Z550 latch connection, and unknown states stay in latches permanently once they have propagated there. instead of connecting baudout to rclk, leave these two signals altogether unconnected. additional external circuitry is then required to drive the receiver clock, rclk. reset the uart; write ??to bit 7 of the lcr register; write any data into ddl and dlm; and perform another reset. this procedure should not have any problems, although you will also have to write new data into the ddl and dlm registers. master reset register/signal reset control reset interrupt enable register reset all bits low (0-3 forced and 4-7 permanent) interrupt identification register reset bit 0 is high, bits 1 and 2 low, bits 3-7 are permanently low. line control register reset all bits low. modem control register reset all bits low. line status register reset all bits low, except bits 5 and 6. modem status register reset bits 0-3 low, bits 4-7 input signal. sout reset high interrupt (rcvr errs) read lsr/reset low interrupt (rcvr data ready) read rbr/reset low interrupt (thre) read iir/write thr/reset low interrupt (modem status changes) read msr/reset low out 2 reset high rts reset high dtr reset high out 1 reset high
n Z550 uart n 18 oki semiconductor programming the serial channel of the ace is programmed by the control registers; lcr, ier, dll and dlm, and mcr. these control words define the character length, number of stop bits, parity, baud rate, and modem inter- face. while the control registers can be written to in any order, the ier should be written to last because it con- trols the interrupt enables. once the serial channel is programmed and operational, these registers can be updated any time the serial channel is not transmitting or receiving data. fifo interrupt mode operation the following rcvr interrupts will occur when the rcvr fifo and receive interrupts are enabled. all interrupts reflect the byte at the top of the fifo . the interrupt descriptions are in order of decreasing priority. 1. iir=01 indicates that there are no interrupts pending. 2. iir=06 (receive line status interrupt) indicates that the byte at the top of the fifo has some sort of error in it (oe, pe, fe, or bi). this interrupt is cleared by reading the lsr. reading the lsr will also indicate which one of the errors is in that byte. 3. the iir will equal an 04 when received data is available in the rcvr fifo. in mode 0, this occurs when a complete character is transferred from the receiver shift register to the rcvr fifo. in mode 1, the rcvr fifo must be filled at or above the trigger level with data. this interrupt is cleared by reading the data f from the rbr, until it either is empty (mode 0) or the amount of data in it is less than the trigger level (mode 1). lsr(0)=1 indicates that the data in the top byte in the rcvr fifo is available, when the fifo is emptied by reading the receive buffer register, lsr(0) is reset to a zero. the trigger level change interrupt (iir = 0c) description is found in the following section. it has the same priority as the receiver data available interrupt (iir = 04). a. if the following conditions exist, a fifo trigger change level interrupt will occur. minimum of one character in fifo. last received serial character was longer than 3.5 to 4.5 continuous previous character times (if two stop lets are programmed, the second one is included in the time delay) once 3.5 character times have been met and no accesses have been made to the fifo, the trigger level matches the number of fifo characters and the trigger change level interrupt will be returned to its original programmed value. the last cpu read of the fifo was more than 3.5 to 4.5 continuous character times ago. at 300 baud with 12 bit characters, the fifo timeout interrupt causes a latency of 160ms maximum, from received character to interrupt issued. b. by using the rclk input for a clock signal, the character times can be calculated. (the delay is proportional to the baud rate.) c. the trigger change level timer is reset after the cpu reads the rcvr fifo or after a new character is received when there has been no trigger change level interrupt. d. a trigger change level interrupt is cleared and the timer is reset when the cpu reads a character from the rcvr fifo.
n Z550 uart n 19 oki semiconductor 4. iir=02 (thre interrupt) indicates that the transmit holding register is empty. this interrupt is cleared by ether writing a byte to the thr or by reading the iir. 5. iir=00 (modem status interrupt) indicates that there has been some change in the status of the modem. this interrupt is cleared by reading the msr, will also indicate what type of status change occurred. xmit interrupts will occur as follows when the transmitter and xmit fifo interrupts are enabled (fcr(0)=l, ier(l)=l) 1. the xmit fifo empty indications will be delayed one character time minus the last stop bit time whenever thre=1 and there have not been a minimum of two bytes at the same time in xmlt fifo, since the last thre=1. 2. when the xmit fifo is empty, the transmitter holding register interrupt (iir=02) occurs. the inter- rupt is cleared as soon as the transmitter holding register is written to or the iir is read. when fcr(0) is enabled, an interrupt will not occur immediately even though it is enabled (ier=1).the first xmit interrupt occurs due to the conditions stated in 1 and 2 above only after data has first been loaded into the xmit fifo. xmit fifo empty interrupts have the same priority as rcvr fifo trigger level and character trigger change level interrupts. fifo polled mode operation resetting ier(0), ier(l), ier(2), ier(3) all to zero, with fcr(0)=1, puts the ace into the fifo polled mode. since the rcvr and xmit channels are controlled separately, ether or both can be operated in polled mode. in the fifo polled mode, no timeout condition are indicated or trigger level reached. however, the rcvr and xmit fifos still have the capability of holding characters.
n Z550 uart n 20 oki semiconductor ac characteristics 1. typical condition is 3.3 v, t j = 25 c for typical process. 2. applicable only when adsn is tied low. Z550 uart input timing (10 mhz @ 3.3v) parameter symbol 3.3 v (typ) [1] units address strobe width t ads 5ns address setup time t as 11 ns address hold time t ah 0ns chip select setup time t cs 12 ns chip select hold time t ch 0ns dis/disn strobe width t diw 15 ns read cycle delay t rc 0ns read cycle = t ar [2] + t diw + t rc rc 24 ns dos/dosn strobe width t dow 11 ns write cycle delay t wc 4ns write cycle = t aw + t dow + t wc wc 25 ns data setup time t ds 8ns data hold time t dh 5ns address hold time from dis/disn [2] t ra 0ns chip select hold time from dis/disn [2] t rcs 0ns dis/disn delay from address [2] t ar 9ns dis/disn delay from chip select [2] t csr 0ns address hold time from dos/dosn [2] t wa 0ns chip select hold time from dos/dosn [2] t wcs 0ns dos/dosn delay from address [2] t aw 10 ns dos/dosn delay from select [2] t csw 0ns master reset pulse width t mrw 15 ns duration of clock high pulse t xh 15 ns duration of clock low pulse t xl 7ns
n Z550 uart n 21 oki semiconductor 1. typical condition is 3.3 v, t j = 25 c for typical process. 2. limited by dll/dlm reg. 3. f x = 8 mhz, divider value = 2. 4. maximum 2 m s. 5. maximum 1 rclk cycle. 6. maximum 1 m s. Z550 uart output timing (10 mhz @ 3.3 v) parameter symbol 3 .3 v (typ) [1] units dis/disn to drive disable delay t dd 1ns delay from dis/disn to data t ddd 4ns dis/disn to floating data delay t hz 2ns delay from dos/dosn (wr thr) to reset interrupt t hr 6ns delay from initial intr reset interrupt t irs < 16 baudout delay from initial write to interrupt t si 8 ~ 24 baudout delay from start bit low to interrupt (thre) high t sti 8 baudout delay from dis/disn (rd iir) to reset interrupt (thre) t ir 4ns delay from start to txrdy active t sxa < 8 baudout delay from write to txrdy inactive t wxi 11 ns delay from dos/dosn (wr mcr) to output t mdo 4ns delay to set interrupt from modem input t sim 11 ns delay to reset interrupt for dis/disn (rs msr) t rim 4ns baud divisor n [2] ns baud output negative edge delay t bld 3ns baud output positive edge delay t bhd 3ns baud output down time t lw 125 ns [3] baud output up time t hw 125 ns [3] delay from rclk to sample time t scd [4] m s delay from stop to set interrupt t sint [5] rclk delay from dis/disn (rd rbr/rdlsr) to reset interrupt t rint [6] m s
n Z550 uart n 22 oki semiconductor figure 8. read cycle adsn t ads a0, a1, a2 t ah t as cs0, cs1, cs2n t ra* t rcs valid valid t cs t ch dos/dosn t csr* t ar* active active t diw t rc rc dis/disn active or di 0-7 t hz t ddd valid data ddis t ds t dd * applicable only when adsn is tied low.
n Z550 uart n 23 oki semiconductor figure 9. write cycle timing figure 10. modem timing adsn t ads a0, a1, a2 t ah t as cs0, cs1, cs2n t wa t wcs valid valid t cs t ch dos/dosn t csw t aw active active t dow t wc wc dis/disn active or di 0-7 t dh t ds valid data dos/dosn (wr mcr) (note 1) t mdo rts, otr, out1, out2 cts. dsr. dcd intr disn (rd msr) (note 2) ri t mdo t sim t rim t rim t sim t sim note: 1. see write timing diagram. 2. see read timing diagram.
n Z550 uart n 24 oki semiconductor figure 11. baud out figure 12. receiver timing clk baud (+1) t bhd t bld t hw n t lw baud (+2) t bhd t bld t hw t lw baud (+3) t bld t bhd t hw t lw baud (+n, n>3) t bld t bhd t hw t hw = (n-2) xtal1 cycles sin (receiver input data) t scd intr (data ready or rcvr err) rclk 8 clks sample clk sample clk start data bits (5-8) parity stop disn t sint active t rint note 1 z450 mode
n Z550 uart n 25 oki semiconductor figure 13. receiver ready - mode 0 figure 14. receiver ready - mode 1 dis/disn (rdrbr) sin (first byte) sample clk stop t sint (note 1) active t rint notes:1. if fcr0=1, then t sint = 3 rclks. for a timeout interrupt, t sint = 8 rclks. rxrdy dis/disn (rdrbr) sin (first byte that reaches the trigger level) sample clk stop t sint (note 2) active t rint notes:1. this is the reading of the last byte in the fifo. 2. if fcr0=1, then t sint = 3 rclks. for a timeout interrupt, t sint = 8 rclks. rxrdy (note 1)
n Z550 uart n 26 oki semiconductor figure 15. transmitter timing figure 16. transmitter ready - mode 0 figure 17. transmitter ready - mode 1 dosn (wr thr) (note 1) serial out (sout) intr (thre) start data bits (5-8) parity stop (1-2) disn (rd iir) (note 2) start t hr t hr t ir t irs t sti t si notes:1. this is the reading of the last byte in the fifo. 2. if fcr0=1, then t sint = 3 rclks. for a timeout interrupt, t sint = 8 rclks. txrdy sout data parity stop start t wxi t sxa dos/dosn (wrthr) byte #1 txrdy sout data parity stop start t wxi t sxa dos/dosn (wrthr) fifo full byte #16
n Z550 uart n 27 oki semiconductor figure 18. receiver fifo first byte (this sets rdr) figure 19. receiver fifo remaining bytes intr (trigger level interrupt) (fcr6, 7=0, 0) sample clock data (5-8) stop start t sint (note 1) sin intr (lsr interrupt) disn (rdlsr) disn (rdrbr) par fifo 3 trigger level fifo < trigger level t rint t rint active active intr (timeout or trigger level interrupt) sample clock data (5-8) stop start t sint (note 1) sin intr (lsr interrupt) disn (rdlsr) disn (rdrbr) par fifo 3 trigger level fifo < trigger level t rint t rint active active active t sint top byte of fifo previous byte read from fifo
oki semiconductor the information contained herein can change without notice owing to product and/or technical improvements. please make sure before using the product that the information you are referring to is up-to-date. the outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. when you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. certain parts in this document may need governmental approval before they can be exported to certain countries. the purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. copyright 1995 oki semiconductor oki semiconductor reserves the right to make changes in specifications at anytime and without notice. this information furnished by oki semiconductor in this publication is believed to be accurate and reliable. however, no responsibility is assumed by oki semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. no license is granted under any patents or patent rights of oki.
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n Z550 uart n 30 oki semiconductor

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