motor motor ola netrams ola netrams networking dual-por networking dual-por ted memor ted memor y for the communications market y for the communications market motorola s netram devices are designed to meet an optimal price and performance point for dual-port appli- cations. these devices enable data to flow quickly so local area network (lan) and wide area network (wan) devices can devote more of their resources to application performance product description the netram family is offered in 1, 4, and 8 mb densities. the netram allows the user to concurrently per- form reads or writes in combination on the two data ports. the two address ports determine the read or write locations for their respective data ports. the synchronous design allows for precise control with the use of a single external clock. chip enables, addresses, input data, and write enables for each port are registered on the rising edge of the clock. the output enable for each port is asynchronous in nature. for the case when the addresses for each port are the same, certain protocols are followed. if both ports are read, the reads occur normally. if one port is writing and the other is being read, the read from the array will occur before the new data is written. if both ports are writing, only the data from port-y will be written to the array. functional additions have been made to successive generations of the netram to allow the user more flexibili- ty in design. the 4 mb device offers two chip enables for each port over the single pair of chip enables for each 1 mb device. the 8 mb netram adds a third chip enable per port and byte write capability. product highlights single clock operation self-timed write pipelined read operation two bi-directional data buses asynchronous output enables fact sheet NETRAMFACT/d rev. 8 applications atm routers cell / frame buffers raid systems ethernet switches cellular base stations sna switches netram family summary density configuration powersupply write operation read operation deselect port-to-port pass through byte write capability operating frequency package 1 mb 4 mb 8 mb self-timed early write self-timed early write self-timed early write 32k x 36 and 64k x 18 128k x 36 256k x 36 3.3v 5% 3.3v 5% 3.3v 5% and 2.5v 200mv pipelined pipelined pipelined dual cycle dual cycle dual cycle ye s ye s no no no yes 66, 83, 100 mhz 100, 133 mhz 100 mhz 176 tqfp (100 tqfp for x 18) 176 tqfp 209 mapbga f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
contact information motorola offers data sheets, application notes and models for fast static ram products. in addition, more information is provided for these products at: http://mot-sps.com/products for all other inquiries about motorola products, please contact the motorola customer response center: phone: 800-521-6274 or http://www.motorola.com/semiconductors ? 2000 motorola, inc. all rights reserved. printed in the u.s.a. motorola, the , and digital dna and the digital dna logo are regi stered trademarks of motorola, inc. this document con- tains information on a new product under development. specifications and information herein are subject to change without notice . memory array x-port control y- por t control dqy output dqy input dqx output dqx input dqx dqy ay y- por t write control gy chip ena bles ax x-port write control gx chip ena bles k netram block diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
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