View HY5DU663222Q-55_1930845.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

hy5du663222q 64m(2mx32) ddr sdram hy5du663222q this document is a general product description and is subject to change without notice. hynix electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 0.9/ dec. 01
hy5du663222q rev. 0.9 / dec. 01 2 revision history 1. revision 0.9 (dec. 01) 1) separated ?function description? and ?timing diagram? parts - these are available in web site (www.hynix.com)
description the hynix hy5du663222 is a 67,108,864-bit cmos double data rate(ddr) synchronous dram, ideally suited for the point-to-point applications which requires high bandwidth. the hynix 2mx32 ddr sdrams offer fully synchronous operations referenced to both rising and falling edges of the clock. while all addresses and control inputs are latched on the rising edges of the ck (falling edges of the /ck), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. the data paths are inter- nally pipelined and 2-bit prefetched to achieve very high bandwidth. all input and output voltage levels are compatible with sstl_2. features ? v dd , v ddq = 2.8v 5% ? all inputs and outputs are compatible with sstl_2 interface ? jedec standard 20mm x 14mm 100pin lqfp with 0.65mm pin pitch ? fully differential clock inputs (ck, /ck) operation ? double data rate interface ? source synchronous - data transaction aligned to bidirectional data strobe (dqs) ? data outputs on dqs edges when read (edged dq) data inputs on dqs centers when write (centered dq) ? data(dq) and write masks(dm) latched on the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? write mask byte controls by dm (dm0 ~ dm3) ? programmable /cas latency 2 and 3 supported ? programmable burst length 2 / 4 / 8 with both sequential and interleave mode ? internal 4 bank operations with single pulsed /ras ? auto refresh and self refresh supported ? 2048 refresh cycles / 16ms ? full and half strength driver option controlled by emrs ordering information part no. power supply clock frequency max data rate interface package hy5du663222q-5 v dd/ v ddq = 2.8v 200mhz 400mbps/pin sstl_2 20mm x 14mm 100pin lqfp HY5DU663222Q-55 183mhz 366mbps/pin hy5du663222q-6 166mhz 332mbps/pin hy5du663222q-7 143mhz 286mbps/pin hy5du663222q rev. 0.9 / dec. 01 3
hy5du663222q rev. 0.9 / dec. 01 4 pin configuration row and column address table items 2mx32 organization 512k x 32 x 4banks row address a0 ~ a10 column address a0 ~ a7 bank address ba0, ba1 auto precharge flag a8 refresh 2k 20 mm x 14mm 100 pin qfp 0.65 mm pitch dq3 vddq dq4 dq5 vssq dq6 dq7 vddq dq16 dq17 vssq dq18 dq19 vddq vdd vss dq20 dq21 vssq dq22 dq23 vddq dm0 dm2 / we / cas / ras / cs ba0 ba1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a0 a1 a2 a3 vdd a10 nc nc nc nc nc nc nc nc a9 vss a4 a5 a6 a7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 dq28 vddq dq27 dq26 vssq dq25 dq24 vddq dq15 dq14 vssq dq13 dq12 vddq vss vdd dq11 dq10 vssq dq9 dq8 vddq vref dm3 dm1 clk / clk cke dsf, mcl a8/ap 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 dq2 vssq dq1 dq0 vdd vddq dqs nc vssq nc nc nc nc nc vddq vss dq31 dq30 vssq dq29 top view
hy5du663222q rev. 0.9 / dec. 01 5 pin description pin type description ck, /ck input clock: ck and /ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of /ck. output (read) data is referenced to the crossings of ck and /ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power down and self refresh operation (all banks idle), or active power down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit, and for output disable. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, /ck and cke are disabled during power down. input buffers, excluding cke are disabled during self refresh. cke is an sstl_2 input, but will detect an lvcmos low level after vdd is applied. /cs input chip select : enables or disables all inputs except ck, /ck, cke, dqs and dm. all com- mands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or pre- charge command is being applied. a0 ~ a10 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a8 is sampled during a precharge command to determine whether the precharge applies to one bank (a8 low) or all banks (a8 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op code during a mode register set command. ba0 and ba1 define which mode register is loaded during the mode register set command (mrs or emrs). /ras, /cas, /we input command inputs: /ras, /cas and /we (along with /cs) define the command being entered. dm0 ~ dm3 input input data mask: dm(0~3) is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sam- pled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. dm0 corresponds to the data on dq0-q7; dm1 corresponds to the data on dq8-q15; dm2 corresponds to the data on dq16-q23; dm3 corresponds to the data on dq24-q31. dqs i/o data strobe: output with read data, input with write data. edge aligned with read data, centered in write data. used to capture write data. dq0 ~ dq31 i/o data input / output pin : data bus v dd /v ss supply power supply for internal circuits and input buffers. v ddq /v ssq supply power supply for output buffers for noise immunity. v ref supply reference voltage for inputs for sstl interface. nc nc no connection.
hy5du663222q rev. 0.9 / dec. 01 6 functional block diagram 4banks x 512kbit x 32 i/o double data rate synchronous dram command decoder clk / clk cke / cs / ras / cas / we dm (0~3) address buffer a0 ~ a10 bank control 512 kx32/bank0 column decoder column address counter sense amp 2 - bit prefetch unit 512 kx32 /bank1 512 kx32 /bank2 512 kx32 /bank3 mode register row decoder input buffer output buffer data strobe transmitter data strobe receiver dqs ds write data register 2 - bit prefetch unit ds dq[0:31] 64 32 32 64 ba0, ba1 dll block clk_dll clk, /clk mode register
hy5du663222q rev. 0.9 / dec. 01 7 simplified command truth table command cken-1 cken cs ras cas we addr a8/ ap ba note extended mode register set h x l l l l op code 1,2 mode register set h x l l l l op code 1,2 device deselect h x h x x x x 1 no operation l h h h bank active h x l l h h ra v 1 read h x l h l h ca l v 1 read with autoprecharge h 1,3 write h x l h l l ca l v 1 write with autoprecharge h 1,4 precharge all banks h x l l h l x h x 1,5 precharge selected bank l v 1 read burst stop h x l h h l x 1 auto refresh h h l l l h x 1 self refresh entry h l l l l h x 1 exit l h h x x x 1 l h h h precharge power down mode entry h l h x x x x 1 l h h h 1 exit l h h x x x 1 l h h h 1 active power down mode entry h l h x x x x 1 l v v v 1 exit l h x 1 note : 1. dm(0~3) states are don?t care. refer to below write mask truth table. 2. op code(operand code) consists of a0~a10 and ba0~ba1 used for mode register setting during extended mrs or mrs. before entering mode register set mode, all banks must be in a precharge state and mrs command can be issued after trp period from prechagre command. 3. if a read with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+trp). 4. if a write with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+1+tdpl+trp). last data-in to prechage delay(tdpl) which is also called write recovery time (twr) is needed to guarantee that the last data has been completely written. 5. if a8/ap is high when precharge command being issued, ba0/ba1 are ignored and all banks are selected to be precharged. ( h=logic high level, l=logic low level, x=don?t care, v=valid data input, op code=operand code, nop=no operation )
hy5du663222q rev. 0.9 / dec. 01 8 write mask truth table function cken-1 cken /cs, /ras, /cas, /we dm(0~3) addr a8/ ap ba note data write h x x l x 1,2 data-in mask h x x h x 1,2 note : 1. write mask command masks burst write data with reference to dqs(data strobes) and it is not related with read data. 2. dm0 corresponds to the data on dq0-q7; dm1 corresponds to the data on dq8-q15; dm2 corresponds to the data on dq16-q23; dm3 corresponds to the data on dq24-q31.
hy5du663222q rev. 0.9 / dec. 01 9 operation command truth table - i current state /cs /ras /cas /we address command action idle h x x x x dsel nop or power down 3 l h h h x nop nop or power down 3 l h h l x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4 l h l l ba, ca, ap write/writeap illegal 4 l l h h ba, ra act row activation l l h l ba, ap pre/pall nop l l l h x aref/sref auto refresh or self refresh 5 l l l l opcode mrs mode register set row active h x x x x dsel nop l h h h x nop nop l h h l x bst illegal 4 l h l h ba, ca, ap read/readap begin read : optional ap 6 l h l l ba, ca, ap write/writeap begin write : optional ap 6 l l h h ba, ra act illegal 4 l l h l ba, ap pre/pall precharge 7 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 read h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x bst terminate burst l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap illegal l l h h ba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 write h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x bst illegal 4 l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap term burst, new write:optional ap
hy5du663222q rev. 0.9 / dec. 01 10 operation command truth table - ii current state /cs /ras /cas /we address command action write l l h h ba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 read with autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 l l h h ba, ra act illegal 4,10 l l h l ba, ap pre/pall illegal 4,10 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 write autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 l l h h ba, ra act illegal 4,10 l l h l ba, ap pre/pall illegal 4,10 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 pre- charge h x x x x dsel nop-enter idle after trp l h h h x nop nop-enter idle after trp l h h l x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 l l h h ba, ra act illegal 4,10 l l h l ba, ap pre/pall nop-enter idle after trp l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11
hy5du663222q rev. 0.9 / dec. 01 11 operation command truth table - iii current state /cs /ras /cas /we address command action row activating h x x x x dsel nop - enter row act after trcd l h h h x nop nop - enter row act after trcd l h h l x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 l l h h ba, ra act illegal 4,9,10 l l h l ba, ap pre/pall illegal 4,10 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 write recovering h x x x x dsel nop - enter row act after twr l h h h x nop nop - enter row act after twr l h h l x bst illegal 4 l h l h ba, ca, ap read/readap illegal l h l l ba, ca, ap write/writeap illegal l l h h ba, ra act illegal 4,10 l l h l ba, ap pre/pall illegal 4,11 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 write recovering with autopre- charge h x x x x dsel nop - enter precharge after tdpl l h h h x nop nop - enter precharge after tdpl l h h l x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,8,10 l h l l ba, ca, ap write/writeap illegal 4,10 l l h h ba, ra act illegal 4,10 l l h l ba, ap pre/pall illegal 4,11 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 refreshing h x x x x dsel nop - enter idle after trc l h h h x nop nop - enter idle after trc l h h l x bst illegal 11 l h l h ba, ca, ap read/readap illegal 11
hy5du663222q rev. 0.9 / dec. 01 12 operation command truth table - iv note : 1. h - logic high level, l - logic low level, x - don?t care, v - valid data input, ba - bank address, ap - autoprecharge address, ca - column address, ra - row address, nop - no operation. 2. all entries assume that cke was active(high level) during the preceding clock cycle. 3. if both banks are idle and cke is inactive(low level), then in power down mode. 4. illegal to bank in specified state. function may be legal in the bank indicated by bank address(ba) depending on the state of that bank. 5. if both banks are idle and cke is inactive(low level), then self refresh mode. 6. illegal if trcd is not met. 7. illegal if tras is not met. 8. must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. illegal if trrd is not met. 10. illegal for single bank, but legal for other banks in multi-bank devices. 11. illegal for all banks. current state /cs /ras /cas /we address command action write l h l l ba, ca, ap write/writeap illegal 11 l l h h ba, ra act illegal 11 l l h l ba, ap pre/pall illegal 11 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 mode register accessing h x x x x dsel nop - enter idle after tmrd l h h h x nop nop - enter idle after tmrd l h h l x bst illegal 11 l h l h ba, ca, ap read/readap illegal 11 l h l l ba, ca, ap write/writeap illegal 11 l l h h ba, ra act illegal 11 l l h l ba, ap pre/pall illegal 11 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11
hy5du663222q rev. 0.9 / dec. 01 13 cke function truth table note : when cke=l, all dq and dqs must be in hi-z state. 1. cke and /cs must be kept high for a minimum of 200 stable input clocks before issuing any command. 2. all command can be stored after 2 clocks from low to high transition of cke. 3. illegal if ck is suspended or stopped during the power down mode. 4. self refresh can be entered only from the all banks idle state. 5. disabling ck may cause malfunction of any bank which is in active state. current state cken- 1 cken /cs /ras /cas /we /add action self refresh 1 h x x x x x x invalid l h h x x x x exit self refresh, enter idle after tsrex l h l h h h x exit self refresh, enter idle after tsrex l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop, continue self refresh power down 2 h x x x x x x invalid l h h x x x x exit power down, enter idle l h l h h h x exit power down, enter idle l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop, continue power down mode all banks idle 4 h h x x x x x see operation command truth table h l l l l h x enter self refresh h l h x x x x exit power down h l l h h h x exit power down h l l h h l x illegal h l l h l x x illegal h l l l h x x illegal h l l l l l x illegal l l x x x x x nop any state other than above h h x x x x x see operation command truth table h l x x x x x illegal 5 l h x x x x x invalid l l x x x x x invalid
hy5du663222q rev. 0.9 / dec. 01 14 simplified state diagram mrs sref srex pden pdex act aref pdex pden bst read write write writeap writeap read readap readap pre(pall) pre(pall) pre(pall) command input automatic sequence idle auto refresh pre - charge power - up power applied mode register set power down write with autopre - charge power down write read with autopre - charge bank active read self refresh
hy5du663222q rev. 0.9 / dec. 01 15 power-up sequence and device initialization ddr sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. power must first be applied to v dd , then to v ddq , and finally to v ref (and to the system v tt ). v tt must be applied after v ddq to avoid device latch-up, which may cause permanent damage to the device. v ref can be applied anytime after v ddq , but is expected to be nominally coincident with v tt . except for cke, inputs are not recognized as valid until after v ref is applied. cke is an sstl_2 input, but will detect an lvcmos low level after v dd is applied. maintaining an lvcmos low level on cke during power-up is required to guarantee that the dq and dqs outputs will be in the high-z state, where they will remain until driven in normal operation (by a read access). after all power supply and reference voltages are stable, and the clock is stable, the ddr sdram requires a 200us delay prior to applying an executable command. once the 200us delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharge all command should be applied. next a extended mode register set command should be issued for the extended mode register, to enable the dll, then a mode register set command should be issued for the mode register, to reset the dll, and to program the operating parameters. 200 clock cycles are required between the dll reset and any command. during the 200 cycles of ck, for dll locking, executable commands are disallowed (a deselect or nop command must be applied). after the 200 clock cycles, a precharge all command should be applied, placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. additionally, a mode register set command for the mode register with the reset dll bit deactivated (i.e. to program operating parameters without resetting the dll) must be performed. following these cycles, the ddr sdram is ready for normal operation. 1. apply power - v dd , v ddq , v tt , v ref in the following power up sequencing and attempt to maintain cke at lvc- mos low state. (all the other input pins may be undefined.) ? v dd and v ddq are driven from a single power converter output. ? v tt is limited to 1.44v (reflecting vddq(max)/2 + 50mv vref variation + 40mv vtt variation. ? v ref tracks v ddq /2. ? a minimum resistance of 42 ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the input current from the v tt supply into any pin. ? if the above criteria cannot be met by the system design, then the following sequencing and voltage relation- ship must be adhered to during power up. 2. start clock and maintain stable clock for a minimum of 200usec. 3. after stable power and clock, apply nop condition and take cke high. 4. issue extended mode register set (emrs) to enable dll. 5. issue mode register set (mrs) to reset dll and set device to idle state with bit a8=high. (an additional 200 cycles of clock are required for locking dll) 6. issue precharge commands for all banks of the device. votage description sequencing voltage relationship to avoid latch-up v ddq after or with v dd < v dd + 0.3v v tt after or with v ddq < v ddq + 0.3v v ref after or with v ddq < v ddq + 0.3v
hy5du663222q rev. 0.9 / dec. 01 16 7. issue 2 or more auto refresh commands. 8. issue a mode register set command to initialize the mode register with bit a8 = low. power-up sequence / clk clk vdd dqs dq ? s mrs aref pre nop mrs emrs pre nop code code code code code code code code code vddq vref cke cmd ba0,ba1 a8 addr dm(0~3) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tvtd t=200usec tmrd 200 cycles of ck* trp trfc power up vdd and ck stable precharge all emrs set mrs set reset dll (with a8=h) precharge all 2 or more auto refresh mrs set (with a8=l) *200 cycles of ck are required (for dll locking) before any executabl e command can be applied. vtt trp tis tih
hy5du663222q rev. 0.9 / dec. 01 17 mode register set (mrs) the mode register is used to store the various operating modes such as /cas latency, addressing mode, burst length, burst type, test mode, dll reset. the mode register is program via mrs command. this command is issued by the low signals of /ras, /cas, /cs, /we and ba0. this command can be issued only when all banks are in idle state and cke must be high at least one cycle before the mode register set command can be issued. two cycles are required to write the data in mode register. during the the mrs cycle, any command cannot be issued. once mode register field is determined, the information will be held until resetted by another mrs command. ba1 ba0 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 rfu dr tm cas latency bt burst length a2 a1 a0 burst length sequential interleave 0 0 0 reserved reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved a3 burst type 0 sequential 1 interleave a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved a7 test mode 0 normal 1 test a8 dll reset 0 no 1 yes ba0 mrs type 0 mrs 1 emrs
hy5du663222q rev. 0.9 / dec. 01 18 burst definition burst length & type read and write accesses to the ddr sdram are burst oriented, with the burst length being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write com- mand. burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. the block is uniquely selected by a1-ai when the burst length is set to two, by a2-ai when the burst length is set to four and by a3-ai when the burst length is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in burst definitionon table burst length starting address (a2,a1,a0) sequential interleave 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 0, 1, 2, 3, 4, 5, 6, 7 7, 6, 5, 4, 3, 2, 1, 0
hy5du663222q rev. 0.9 / dec. 01 19 cas latency the read latency or cas latency is the delay in clock cycles between the registration of a read command and the availability of the first burst of output data. the latency can be programmed 3 or 4 clocks. if a read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. reserved states should not be used as unknown operation or incompatibility with future versions may result. dll reset the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon return- ing to normal operation after having disabled the dll for the purpose of debug or evaluation. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before an any command can be issued. output driver impedance control the full drive strength for all outputs is specified to be sstl_2, class ii. hynix also supports a half strength driver option, intended for lighter load and/or point-to-point environments. selection of the half strength driver option will reduce the output drive strength by about 50% of that of the full strength driver.
hy5du663222q rev. 0.9 / dec. 01 20 extended mode register set (emrs) the extended mode register controls functions beyond those controlled by the mode register; these additional func- tions include dll enable/disable, output driver strength selection(optional). these functions are controlled via the bits shown below. the extended mode register is programmed via the mode register set command ( ba0=1 and ba1=0) and will retain the stored information until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. violating either of these requirements will result in unspecified operation. ba1 ba0 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 rfu* ds dll a0 dll enable 0 enable 1 diable ba0 mrs type 0 mrs 1 emrs a1 output driver impedance control 0 full 1 half * all bits in rfu address fields must be programmed to zero, all other states are reserved for future usage.
hy5du663222q rev. 0.9 / dec. 01 21 absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v ddq must not exceed the level of v dd . 2. v il (min) is acceptable -1.5v ac pulse width with 5ns of duration. 3. v ref is expected to be equal to 0.5*v ddq of the transmitting device, and to track variations in the dc level of the same. peak to peak noise on v ref may not exceed 2% of the dc value. dc characteristics i (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v in = 0 to 3.6v, all other pins are not tested under v in = 0v. 2. d out is disabled, v out = 0 to 2.7v parameter symbol rating unit ambient temperature t a 0 ~ 70 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd relative to v ss v dd -0.5 ~ 3.6 v voltage on v ddq relative to v ss v ddq -0.5 ~ 3.6 v output short circuit current i os 50 ma power dissipation p d 1 w soldering temperature time t solder 260 10 o c sec parameter symbol min typ. max unit note power supply voltage v dd 2.66 2.8 2.94 v power supply voltage v ddq 2.66 2.8 2.94 v 1 input high voltage v ih v ref + 0.15 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.15 v 2 termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v reference voltage v ref 0.49*v ddq 0.5*v ddq 0.51*v ddq v 3 parameter symbol min. max unit note input leakage current i li -5 5 ua 1 output leakage current i lo -5 5 ua 2 output high voltage v oh v tt + 0.76 - v i oh = -15.2ma output low voltage v ol - v tt - 0.76 v i ol = +15.2ma
hy5du663222q rev. 0.9 / dec. 01 22 dc characteristics ii (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. i dd1, idd4 and i dd5 depend on output loading and cycle rates. specified values are measured with the output open. 2. min. of t rfc (auto refresh row cycle time) is shown at ac characteristics. parameter symbol test condition speed unit note 5 55 6 7 operating current i dd1 burst length=2, one bank active t rc 3 t rc (min), i ol =0ma 280 270 260 240 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = min 10 ma precharge standby current in non power down mode i dd2n cke 3 v ih (min), /cs 3 v ih (min), t ck = min, input signals are changed one time during 2clks 60 ma active standby current in power down mode i dd3p cke v il (max), t ck = min 20 ma active standby current in non power down mode i dd3n cke 3 v ih (min), /cs 3 v ih (min), t ck = min, input signals are changed one time during 2clks 70 ma burst mode operating current i dd4 t ck 3 t ck (min), i ol = 0ma all banks active 470 440 410 370 ma 1 auto refresh current i dd5 t rc 3 t rfc (min), all banks active 320 ma 1,2 self refresh current i dd6 cke 0.2v 4 ma
hy5du663222q rev. 0.9 / dec. 01 23 ac operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. vid is the magnitude of the difference between the input level on ck and the input on ck. 2. the value of vix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. ac operating test conditions (ta=0 to 70 o c, voltage referenced to vss = 0v) parameter symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih(ac) v ref + 0.35 v input low (logic 0) voltage, dq, dqs and dm signals v il(ac) v ref - 0.35 v input differential voltage, ck and /ck inputs v id(ac) 0.7 v ddq + 0.6 v 1 input crossing point voltage, ck and /ck inputs v ix(ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v 2 parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.35 v ac input low level voltage (v il , max) v ref - 0.35 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t ) 50 w series resistor (r s ) 25 w output load capacitance for access time measurement (c l ) 30 pf
hy5du663222q rev. 0.9 / dec. 01 24 ac characteristics (ac operating conditions unless otherwise noted) parameter symbol 5 55 6 7 unit note min max min max min max min max row cycle time t rc 60 - 60.5 - 60 - 63 - ns auto refresh row cycle time t rfc 70 - 71.5 - 72 - 77 - ns row active time t ras 40 120k 44 120k 42 120k 49 120k ns row address to column address delay t rcd 4 - 3 - 3 - 3 - ck row active to row active delay t rrd 2 - 2 - 2 - 2 - ck column address to column address delay t ccd 1 - 1 - 1 - 1 - ck row precharge time t rp 4 - 3 - 3 - 3 - ck last data-in to precharge delay time (write recovery time : twr) t dpl 2 - 2 - 2 - 2 - ck last data-in to read command t drl 1 - 1 - 1 - 1 - ck auto precharge write recovery + precharge time t dal 6 - 5 - 5 - 5 - ck system clock cycle time cl = 3 t ck 5 10 5.5 10 6 10 7 10 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew t ac -1.0 1.0 -1.0 1.0 -1.0 1.0 -1.1 1.1 ns dqs-out edge to clock edge skew t dqsck -1.0 1.0 -1.0 1.0 -1.0 1.0 -1.1 1.1 ns dqs-out edge to data-out edge skew t dqsq - 0.5 - 0.5 - 0.5 - 0.5 ns data-out hold time from dqs t qh t hpmin -t qhs - t hpmin -t qhs - t hpmin -t qhs - t hpmin -t qhs - ns 1,6 clock half period t hp t ch/l min - t ch/l min - t ch/l min - t ch/l min - ns 1,5 data hold skew factor t qhs - 0.75 - 0.75 - 0.75 - 0.75 ns 6 input setup time t is 1.1 - 1.1 - 1.1 - 1.1 - ns 2 input hold time t ih 1.1 - 1.1 - 1.1 - 1.1 - ns 2 write dqs high level width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 ck write dqs low level width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 ck clock to first rising edge of dqs-in t dqss 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 ck data-in setup time to dqs-in (dq & dm) t ds 0.5 - 0.5 - 0.5 - 0.5 - ns 3 data-in hold time to dqs-in (dq & dm) t dh 0.5 - 0.5 - 0.5 - 0.5 - ns 3 read dqs preamble time t rpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 ck
hy5du663222q rev. 0.9 / dec. 01 25 n ote : 1. this calculation accounts for tdqsq(max), the pulse width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the clock : a0~a10, ba0~ba1, cke, /cs, /ras, /cas, /we. 3. data latched at both rising and falling edges of data strobes(dqs) : dq, dm(0~3). 4. minimum of 200 cycles of stable input clocks after self refresh exit command, where cke is held high, is required to complete self refresh exit and lock the internal dll circuit of ddr sdram. 5. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i .e. this value can be greater than the minimum specification limits for tcl and tch). 6. thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tch, tcl). tqhs consists of tdqsqmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-chann el to n-channel variation of the output drivers. 7. dqs, dm and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal transitions through the dc region must be monotonic. read dqs postamble time t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 ck write dqs preamble setup time t wpres 0 - 0 - 0 - 0 - ns write dqs preamble hold time t wpreh 0.25 - 0.25 - 0.25 - 0.25 - ck write dqs postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 ck mode register set delay t mrd 2 - 2 - 2 - 2 - ck exit self refresh to any execute command t xsc 200 - 200 - 200 - 200 - ck 4 parameter symbol 5 55 6 7 unit note min max min max min max min max
hy5du663222q rev. 0.9 / dec. 01 26 capacitance (t a =25 o c, f=1mhz ) note : 1. v dd/ v ddq = min. to max., v o dc = v ddq /2, v o peak-to-peak = 0.2v 2. pins not under test are tied to gnd. 3. these values are guaranteed by design and are tested on a sample basis only. output load circuit parameter pin symbol min max unit input clock capacitance ck, /ck c ck 2.0 3.0 pf input capacitance all other input-only pins c in 2.0 3.0 pf input / output capacitanc dq, dqs, dm c io 4.0 5.0 pf v ref v tt v tt r t =50 w r t =50 w r s =25 w zo =50 w c l =30pf output
hy5du663222q rev. 0.9 / dec. 01 27 package information 20mm x 14mm 100pin low quad flat package 0.15(0.006) 0.05(0.002) 0.75(0.029) 0.50(0.020) 1.00(0.0394) ref 0.20(0.008) 0.09(0.004) 0~7 deg gauge line detail a 0.66(0.026) 0.45(0.018) 0.65 (0.026) typ detail a 22.10(0.870) 21.90(0.862) 20.10(0.791) 19.90(0.783) 14.10(0.555) 13.90(0.547) 16.10(0.634) 15.90(0.626) 0.38(0.015) 0.22(0.009) 1.60(0.063) 1.45(0.057) base plane seating plane unit:mm(inch) 0.080 (0.003) all dimension in mm (inches). notation is or typical. max min

▲Up To Search▲

Price & Availability of HY5DU663222Q-55

	To Download HY5DU663222Q-55 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .