View CFPRM_1926339.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CFPRM/d rev. 2, 07/2001 coldfire family programmers reference manual f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
?motorola inc., 2001. all rights reserved. coldfire is a registered trademark and digitaldna is a trademark of motorola, inc. i 2 c is a registered trademark of philips semiconductors motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation consequential or incidental damages. ?ypical?parameters which may be provided in motorola data sheets and/or specifications c an and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals must be validated for each customer application by customer? technical experts. motorola does not convey any license under its pate nt rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applic ation in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purch ase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its offi cers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motor ola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1?03?75?140 or 1?00?41?447 japan: motorola japan ltd.; sps, technical information center, 3?0?, minami?zabu. minato?u, tokyo 106?573 japan. 81??440?569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong. 852?6668334 technical information center: 1?00?21?274 home page: http://www.motorola.com/semiconductors document comments : fax (512) 9335-2625, attn: risc applications engineering world wide web addresses : http://www.motorola.com/powerpc http://www.motorola.com/netcomm http://www.motorola.com/coldfire f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1 2 3 4 5 7 8 10 11 6 ind introduction addressing capabilities instruction set summary integer user instructions mac user instructions emac user instructions fpu user instructions supervisor instructions exception processing pst/ddata encodings index 12 processor instruction summary a s-record output format 9 instruction format summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
introduction addressing capabilities instruction set summary integer user instructions mac user instructions emac user instructions fpu user instructions supervisor instructions exception processing pst/ddata encodings index processor instruction summary s-record output format instruction format summary 1 2 3 4 5 7 8 10 11 6 ind 12 a 9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
contents paragraph number title page number contents v chapter 1 introduction 1.1 integer unit user programming model .............................................................. 1-1 1.1.1 data registers (d0?7).................................................................................. 1-2 1.1.2 address registers (a0?7) ............................................................................ 1-2 1.1.3 program counter (pc) .................................................................................... 1-2 1.1.4 condition code register (ccr) ..................................................................... 1-2 1.2 floating-point unit user programming model................................................... 1-4 1.2.1 floating-point data registers (fp0?p7) ...................................................... 1-4 1.2.1.1 floating-point control register (fpcr) .................................................... 1-4 1.2.2 floating-point status register (fpsr) ........................................................... 1-5 1.2.3 floating-point instruction address register (fpiar).................................... 1-6 1.3 mac user programming model ........................................................................ 1-7 1.3.1 mac status register (macsr)..................................................................... 1-7 1.3.2 mac accumulator (acc).............................................................................. 1-8 1.3.3 mac mask register (mask)........................................................................ 1-8 1.4 emac user programming model ...................................................................... 1-8 1.4.1 mac status register (macsr)..................................................................... 1-8 1.4.2 mac accumulators (acc[0:3]) .................................................................... 1-9 1.4.3 accumulator extensions (accext01, accext23) ....................................... 1-11 1.4.4 mac mask register (mask)...................................................................... 1-11 1.5 supervisor programming model....................................................................... 1-11 1.5.1 status register (sr)...................................................................................... 1-12 1.5.2 supervisor/user stack pointers (a7 and other_a7)................................ 1-13 1.5.3 vector base register (vbr)......................................................................... 1-14 1.5.4 cache control register (cacr) .................................................................. 1-14 1.5.5 address space identifier (asid).................................................................. 1-14 1.5.6 access control registers (acr0?cr3).................................................... 1-14 1.5.7 mmu base address register (mmubar) ................................................. 1-14 1.5.8 ram base address registers (rambar0/rambar1) ........................... 1-15 1.5.9 rom base address registers (rombar0/rombar1) ........................... 1-15 1.5.10 module base address register (mbar) ..................................................... 1-15 1.6 integer data formats......................................................................................... 1-16 1.7 floating-point data formats............................................................................. 1-16 1.7.1 floating-point data types ............................................................................ 1-17 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
vi coldfire family programmers reference manual contents paragraph number title page number 1.7.1.1 normalized numbers................................................................................ 1-17 1.7.1.2 zeros ......................................................................................................... 1-17 1.7.1.3 infinities.................................................................................................... 1-17 1.7.1.4 not-a-number.......................................................................................... 1-18 1.7.1.5 denormalized numbers ............................................................................ 1-18 1.7.2 fpu data format and type summary ......................................................... 1-18 1.8 multiply accumulate data formats.................................................................. 1-20 1.9 organization of data in registers..................................................................... 1-20 1.9.1 organization of integer data formats in registers ...................................... 1-20 1.9.2 organization of integer data formats in memory ....................................... 1-22 chapter 2 addressing capabilities 2.1 instruction format............................................................................................... 2-1 2.2 effective addressing modes............................................................................... 2-2 2.2.1 data register direct mode ............................................................................. 2-3 2.2.2 address register direct mode........................................................................ 2-3 2.2.3 address register indirect mode ..................................................................... 2-3 2.2.4 address register indirect with postincrement mode ..................................... 2-4 2.2.5 address register indirect with predecrement mode ...................................... 2-4 2.2.6 address register indirect with displacement mode ...................................... 2-5 2.2.7 address register indirect with scaled index and 8-bit displacement mode 2-6 2.2.8 program counter indirect with displacement mode...................................... 2-6 2.2.9 program counter indirect with scaled index and 8-bit displacement mode 2-7 2.2.10 absolute short addressing mode................................................................... 2-8 2.2.11 absolute long addressing mode ................................................................... 2-9 2.2.12 immediate data............................................................................................... 2-9 2.2.13 effective addressing mode summary.......................................................... 2-10 2.3 stack.................................................................................................................. 2-10 chapter 3 instruction set summary 3.1 instruction summary........................................................................................... 3-1 3.1.1 data movement instructions........................................................................... 3-4 3.1.2 integer arithmetic instructions....................................................................... 3-5 3.1.3 logical instructions ........................................................................................ 3-7 3.1.4 shift instructions............................................................................................. 3-7 3.1.5 bit manipulation instructions ......................................................................... 3-8 3.1.6 program control instructions.......................................................................... 3-8 3.1.7 system control instructions.......................................................................... 3-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
contents paragraph number title page number contents vii 3.1.8 cache maintenance instructions................................................................... 3-10 3.1.9 floating point arithmetic instructions ......................................................... 3-11 3.2 instruction set additions .................................................................................. 3-12 chapter 4 integer user instructions chapter 5 multiply-accumulate unit (mac) user instructions chapter 6 enhanced multiply-accumulate unit (emac) user instructions chapter 7 floating-point unit (fpu) user instructions 7.1 floating-point status register (fpsr) ............................................................... 7-1 7.2 conditional testing............................................................................................. 7-3 7.3 instruction results when exceptions occur ....................................................... 7-6 7.4 instruction descriptions ...................................................................................... 7-7 chapter 8 supervisor (privileged) instructions chapter 9 instruction format summary 9.1 operation code map........................................................................................... 9-1 chapter 10 pst/ddata encodings 10.1 user instruction set........................................................................................... 10-1 10.2 supervisor instruction set................................................................................. 10-7 chapter 11 exception processing 11.1 overview........................................................................................................... 11-1 11.1.1 supervisor/user stack pointers (a7 and other_a7)................................ 11-4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
viii coldfire family programmers reference manual contents paragraph number title page number 11.1.2 exception stack frame definition................................................................ 11-4 11.1.3 processor exceptions .................................................................................... 11-5 11.1.4 floating-point arithmetic exceptions .......................................................... 11-9 11.1.5 branch/set on unordered (bsun) ............................................................. 11-11 11.1.6 input not-a-number (inan)..................................................................... 11-11 11.1.7 input denormalized number (ide)............................................................ 11-11 11.1.8 operand error (operr)............................................................................. 11-12 11.1.9 overflow (ovfl) ....................................................................................... 11-13 11.1.10 underflow (unfl) ..................................................................................... 11-13 11.1.11 divide-by-zero (dz) .................................................................................. 11-14 11.1.12 inexact result (inex) ................................................................................ 11-14 11.1.13 v4 changes to the exception processing model........................................ 11-15 chapter 12 processor instruction summary appendix a s-record output format a.1 s-record content............................................................................................... a-1 a.2 s-record types.................................................................................................. a-2 a.3 s-record creation.............................................................................................. a-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
illustrations figure number title page number illustrations ix 1-1 coldfire family user programming model ................................................................. 1-2 1-2 condition code register (ccr) ................................................................................... 1-3 1-3 coldfire family floating-point unit user programming model ................................. 1-4 1-4 floating-point control register (fpcr) ...................................................................... 1-4 1-5 floating-point status register (fpsr) ......................................................................... 1-5 1-6 mac unit programming model................................................................................... 1-7 1-7 mac status register (macsr)................................................................................... 1-7 1-8 emac programming model......................................................................................... 1-8 1-9 mac status register (macsr)................................................................................... 1-9 1-10 emac fractional alignment...................................................................................... 1-10 1-11 emac signed and unsigned integer alignment ....................................................... 1-10 1-12 accumulator 0 and 1 extensions (accext01)............................................................ 1-11 1-13 accumulator 2 and 3 extensions (accext01)............................................................ 1-11 1-14 supervisor programming model................................................................................. 1-12 1-15 status register (sr).................................................................................................... 1-1 3 1-16 vector base register (vbr)....................................................................................... 1-14 1-17 mmu base address register (mmubar) ............................................................... 1-15 1-18 module base address register (mbar) ................................................................... 1-16 1-19 normalized number format ....................................................................................... 1-17 1-20 zero format ................................................................................................................ 1-17 1-21 infinity format ............................................................................................................ 1-17 1-22 not-a-number format ................................................................................................ 1-18 1-23 denormalized number format ................................................................................... 1-18 1-24 two? complement, signed fractional equation....................................................... 1-20 1-25 organization of integer data format in data registers ............................................. 1-21 1-26 organization of addresses in address registers........................................................ 1-21 1-27 memory operand addressing..................................................................................... 1-22 1-28 memory organization for integer operands............................................................... 1-22 2-1 instruction word general format................................................................................. 2-1 2-2 instruction word specification formats....................................................................... 2-2 2-3 data register direct...................................................................................................... 2- 3 2-4 address register direct ................................................................................................ 2-3 2-5 address register indirect.............................................................................................. 2-4 2-6 address register indirect with postincrement.............................................................. 2-4 2-7 address register indirect with predecrement............................................................... 2-5 2-8 address register indirect with displacement............................................................... 2-5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
illustrations figure number title page number x coldfire family programmers reference manual 2-9 address register indirect with scaled index and 8-bit displacement......................... 2-6 2-10 program counter indirect with displacement .............................................................. 2-7 2-11 program counter indirect with scaled index and 8-bit displacement......................... 2-8 2-12 absolute short addressing ........................................................................................... 2-8 2-13 absolute long addressing ........................................................................................... 2-9 2-14 immediate data addressing.......................................................................................... 2-9 2-15 stack growth from high memory to low memory................................................... 2-11 2-16 stack growth from low memory to high memory................................................... 2-11 7-1 floating-point status register (fpsr) ......................................................................... 7-1 11-1 exception stack frame ............................................................................................... 11-5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
tables xi tables table number title page number 1-1 ccr bit descriptions ................................................................................................... 1-3 1-2 fpcr field descriptions .............................................................................................. 1-5 1-3 fpsr field descriptions............................................................................................... 1-5 1-4 macsr field descriptions .......................................................................................... 1-7 1-5 macsr field descriptions .......................................................................................... 1-9 1-6 implemented supervisor registers by device............................................................ 1-12 1-7 status field descriptions ............................................................................................ 1-13 1-8 mmu base address register field descriptions....................................................... 1-15 1-9 mbar field descriptions .......................................................................................... 1-16 1-10 integer data formats................................................................................................... 1-16 1-11 real format summary ................................................................................................ 1-19 2-1 instruction word format field definitions .................................................................. 2-2 2-2 immediate operand location ....................................................................................... 2-9 2-3 effective addressing modes and categories.............................................................. 2-10 3-1 notational conventions ................................................................................................ 3-2 3-2 data movement operation format ............................................................................... 3-5 3-3 integer arithmetic operation format ........................................................................... 3-6 3-4 logical operation format............................................................................................. 3-7 3-5 shift operation format ................................................................................................. 3-8 3-6 bit manipulation operation format.............................................................................. 3-8 3-7 program control operation format .............................................................................. 3-9 3-8 system control operation format .............................................................................. 3-10 3-9 cache maintenance operation format ....................................................................... 3-11 3-10 dyadic floating-point operation format ................................................................... 3-11 3-11 dyadic floating-point operations .............................................................................. 3-11 3-12 monadic floating-point operation format................................................................. 3-12 3-13 monadic floating-point operations............................................................................ 3-12 3-14 coldfire user instruction set summary..................................................................... 3-12 3-15 coldfire supervisor instruction set summary ........................................................... 3-17 3-16 coldfire isa_b additions summary......................................................................... 3-18 3-17 mac instruction set summary .................................................................................. 3-19 3-18 emac instruction set enhancements summary........................................................ 3-19 3-19 floating-point instruction set summary .................................................................... 3-20 7-1 fpsr field descriptions............................................................................................... 7-1 7-2 fpsr exc bits............................................................................................................. 7- 3 7-3 fpcc encodings........................................................................................................... 7-4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
xii coldfire family programmers reference manual tables table number title page number 7-4 floating-point conditional tests .................................................................................. 7-5 7-5 fpcr exc byte exception enabled/disabled results................................................ 7-6 7-6 data format encoding ................................................................................................. 7-8 8-1 state frames................................................................................................................ .. 8-3 8-2 state frames................................................................................................................ .. 8-5 8-3 coldfire cpu space assignments ............................................................................. 8-14 9-1 operation code map..................................................................................................... 9-1 10-1 pst/ddata specification for user-mode instructions............................................ 10-2 10-2 pst/ddata values for user-mode multiply-accumulate instructions .................. 10-5 10-3 pst/ddata values for user-mode floating-point instructions.............................. 10-6 10-4 data markers and fpu operand format specifiers ................................................... 10-7 10-5 pst/ddata specifications for supervisor-mode instructions ................................ 10-7 11-1 exception vector assignments................................................................................... 11-2 11-2 format/vector word................................................................................................... 11-5 11-3 exceptions................................................................................................................. .. 11-6 11-4 exception priorities..................................................................................................... 11 -9 11-5 bsun exception enabled/disabled results ............................................................ 11-11 11-6 inan exception enabled/disabled results ............................................................. 11-11 11-7 ide exception enabled/disabled results ................................................................ 11-12 11-8 possible operand errors ........................................................................................... 11-12 11-9 operr exception enabled/disabled results .......................................................... 11-12 11-10 ovfl exception enabled/disabled results............................................................. 11-13 11-11 unfl exception enabled/disabled results............................................................. 11-14 11-12 dz exception enabled/disabled results.................................................................. 11-14 11-13 inexact rounding mode values................................................................................ 11-14 11-14 inex exception enabled/disabled results.............................................................. 11-15 11-15 oep ex cycle operations........................................................................................ 11-16 12-1 standard products ....................................................................................................... 12- 1 12-2 coldfire instruction set and processor cross-reference........................................... 12-2 12-3 coldfire mac and emac instruction sets............................................................... 12-4 12-4 coldfire fpu instruction set ..................................................................................... 12-5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. introduction 1-1 chapter 1 introduction this manual contains detailed information about software instructions used by the version 2 (v2), version 3 (v3), and version 4 (v4) coldfire ? microprocessors. the coldfire family programming model consists of two register groups: user and supervisor. programs executing in the user mode use only the registers in the user group. system software executing in the supervisor mode can access all registers and use the control registers in the supervisor group to perform supervisor functions. the following paragraphs provide a brief description of the registers in the user and supervisor models as well as the data organization in the registers. 1.1 integer unit user programming model figure 1-1 illustrates the integer portion of the user programming model. it consists of the following registers: 16 general-purpose 32-bit registers (d0?7, a0?7) 32-bit program counter (pc) 8-bit condition code register (ccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-2 coldfire family programmers reference manual integer unit user programming model figure 1-1. coldfire family user programming model 1.1.1 data registers (d0?7) these registers are for bit, byte (8 bits), word (16 bits), and longword (32 bits) operations. they can also be used as index registers. 1.1.2 address registers (a0?7) these registers serve as software stack pointers, index registers, or base address registers. the base address registers can be used for word and longword operations. register a7 functions as a hardware stack pointer during stacking for subroutine calls and exception handling. 1.1.3 program counter (pc) the program counter (pc) contains the address of the instruction currently executing. during instruction execution and exception processing, the processor automatically increments the contents or places a new value in the pc. for some addressing modes, the pc can serve as a pointer for pc relative addressing. 1.1.4 condition code register (ccr) consisting of 5 bits, the condition code register (ccr)?he status registers lower byte?s the only portion of the sr available in the user mode. many integer instructions affect the ccr and indicate the instructions result. program and system control instructions also use certain combinations of these bits to control program and system ?w. 31 0 d0 data registers d1 d2 d3 d4 d5 d6 d7 31 0 a0 address registers a1 a2 a3 a4 a5 a6 a7 stack pointer pc program counter ccr condition code register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. introduction 1-3 integer unit user programming model the condition codes meet two criteria: 1. consistency across: instructions, meaning that all instructions that are special cases of more general instructions affect the condition codes in the same way; uses, meaning that conditional instructions test the condition codes similarly and provide the same results whether a compare, test, or move instruction sets the condition codes; and instances, meaning that all instances of an instruction affect the condition codes in the same way. 2. meaningful results with no change unless it provides useful information. bits [3:0] represent a condition of the result generated by an operation. bit 5, the extend bit, is an operand for multiprecision computations. version 3 processors have an additional bit in the ccr: bit 7, the branch prediction bit. the ccr is illustrated in figure 1-2. figure 1-2. condition code register (ccr) table 1-1 describes ccr bits. 76543210 p 1 ?nzvc 1 the p bit is implemented only on the v3 core. table 1-1. ccr bit descriptions bits field description 7 p branch prediction (version 3 only). alters the static prediction algorithm used by the branch acceleration logic in the instruction fetch pipeline on forward conditional branches. refer to a v3 core or device users manual for further information on this bit. reserved, should be cleared (versions 2 and 4). 6? reserved, should be cleared. 4 x extend. set to the value of the c-bit for arithmetic operations; otherwise not affected or set to a speci?d result. 3 n negative. set if the most signi?ant bit of the result is set; otherwise cleared. 2 z zero. set if the result equals zero; otherwise cleared. 1 v over?w. set if an arithmetic over?w occurs implying that the result cannot be represented in the operand size; otherwise cleared. 0 c carry. set if a carry out of the most signi?ant bit of the operand occurs for an addition, or if a borrow occurs in a subtraction; otherwise cleared. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-4 coldfire family programmers reference manual floating-point unit user programming model 1.2 floating-point unit user programming model the following paragraphs describe the registers for the optional coldfire ?ating-point unit. figure 1-3 illustrates the user programming model for the ?ating-point unit. it contains the following registers: 8 64-bit ?ating-point data registers (fp0?p7) 32-bit ?ating-point control register (fpcr) 32-bit ?ating-point status register (fpsr) 32-bit ?ating-point instruction address register (fpiar) figure 1-3. coldfire family floating-point unit user programming model 1.2.1 floating-point data registers (fp0?p7) floating-point data registers are analogous to the integer data registers for the 68k/coldfire family. the 64-bit ?ating-point data registers always contain numbers in double-precision format. all external operands, regardless of the source data format, are converted to double-precision values before being used in any calculation or being stored in a ?ating-point data register. a reset or a null-restore operation sets fp0?p7 to positive, nonsignaling not-a-numbers (nans). 1.2.1.1 floating-point control register (fpcr) the fpcr, figure 1-4, contains an exception enable byte (ee) and a mode control byte (mc). the user can read or write to fpcr using fmove or frestore. a processor reset or a restore operation of the null state clears the fpcr. when this register is cleared, the fpu never generates exceptions. figure 1-4. floating-point control register (fpcr) table 1-2 describes fpcr ?lds. 63 31 0 fp0 floating-point data registers fp1 fp2 fp3 fp4 fp5 fp6 fp7 fpcr floating-point control register fpsr floating-point status register fpiar floating-point instruction address register 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0 bsun inan operr ovfl unfl dz inex ide prec rnd exception enable byte (ee) mode control byte (mc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. introduction 1-5 floating-point unit user programming model 1.2.2 floating-point status register (fpsr) the fpsr, figure 1-5, contains a ?ating-point condition code byte (fpcc), a ?ating-point exception status byte (exc), and a ?ating-point accrued exception byte (aexc). the user can read or write all fpsr bits. execution of most ?ating-point instructions modi?s fpsr. fpsr is loaded by using fmove or frestore. a processor reset or a restore operation of the null state clears the fpsr. figure 1-5. floating-point status register (fpsr) table 1-3 describes fpsr ?lds. table 1-2. fpcr field descriptions bits field description 31?6 reserved, should be cleared. 15? ee exception enable byte. each ee bit corresponds to a ?ating-point exception class. the user can separately enable traps for each class of ?ating-point exceptions. 15 bsun branch set on unordered 14 inan input not-a-number 13 operr operand error 12 ovfl over?w 11 unfl under?w 10 dz divide by zero 9 inex inexact operation 8 ide input denormalized 7? mc mode control byte. controls fpu operating modes. 7 reserved, should be cleared. 6 prec rounding precision 5? rnd rounding mode 3? reserved, should be cleared. 31 28 27 26 25 24 23 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 n z i nan bsun inan operr ovfl unfl dz inex ide iop ovfl unfl dz inex table 1-3. fpsr field descriptions bits field description 31?4 fpcc floating-point condition code byte. contains four condition code bits that are set after completion of all arithmetic instructions involving the ?ating-point data registers. 31?8 reserved, should be cleared. 27 n negative fpcc exception status byte (exc) aexc byte f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-6 coldfire family programmers reference manual floating-point unit user programming model 1.2.3 floating-point instruction address register (fpiar) the coldfire operand execution pipeline can execute integer and ?ating-point instructions simultaneously. as a result, the pc value stacked by the processor in response to a ?ating-point exception trap may not point to the instruction that caused the exception. for those fpu instructions that can generate exception traps, the 32-bit fpiar is loaded with the instruction pc address before the fpu begins execution. in case of an fpu exception, the trap handler can use the fpiar contents to determine the instruction that generated the exception. fmove to/from the fpcr, fpsr, or fpiar and fmovem instructions cannot generate ?ating-point exceptions and so do not modify fpiar. a reset or a null-restore operation clears fpiar. 26 fppc (cont.) z zero 25 i in?ity 24 nan not-a-number 23?6 reserved, should be cleared. 15? exc exception status byte. contains a bit for each ?ating-point exception that might have occurred during the most recent arithmetic instruction or move operation. 15 bsun branch/set on unordered 14 inan input not-a-number 13 operr operand error 12 ovfl over?w 11 unfl under?w 10 dz divide by zero 9 inex inexact operation 8 ide input denormalization 7? aexc accrued exception byte. contains 5 exception bits the ieee 754 standard requires for exception-disabled operations. these exceptions are logical combinations of bits in the exc byte. aexc records all ?ating-point exceptions since the user last cleared aexc. 7 iop invalid operation 6 ovfl under?w 5 unfl divide by zero 4 dz inexact operation 3 inex input denormalization 2? reserved, should be cleared. table 1-3. fpsr field descriptions (continued) bits field description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. introduction 1-7 mac user programming model 1.3 mac user programming model the following paragraphs describe the registers for the optional coldfire mac unit. figure 1-6 illustrates the user programming model for the mac unit. it contains the following registers: 32-bit mac status register (macsr) 32-bit accumulator register (acc) 32-bit mac mask register (mask) figure 1-6. mac unit programming model 1.3.1 mac status register (macsr) the macsr, shown in figure 1-7, contains an operational mode ?ld and a set of ?gs. table 1-4 describes macsr ?lds. 31 0 macsr mac status register acc mac accumulator mask mac mask register 31 8 7 4 3 0 operational mode flags omc s/u f/i r/t n z v c figure 1-7. mac status register (macsr) table 1-4. macsr field descriptions bits field description 31-8 reserved, should be cleared. 7-4 omf operational mode ?ld. de?es the operating con?uration of the mac unit. 7 omc over?w/saturation mode 6 s/u signed/unsigned operations 5 f/i fraction/integer mode 4 r/t round/truncate mode 3? flags flags. contains indicator ?gs from the last mac instruction execution. 3 n negative 2 z zero 1 v over?w 0 c carry. this ?ld is always zero. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-8 coldfire family programmers reference manual emac user programming model 1.3.2 mac accumulator (acc) this 32-bit register contains the results of mac operations. 1.3.3 mac mask register (mask) the mask register (mask) is 32 bits of which only the low-order 16 bits are implemented. when mask is loaded, the low-order 16 bits of the source operand are loaded into the register. when it is stored, the upper 16 bits are forced to all ones. when used by an instruction, this register is anded with the speci?d operand address. thus, mask allows an operand address to be effectively constrained within a certain range de?ed by the 16-bit value. this feature minimizes the addressing support required for ?tering, convolution, or any routine that implements a data array as a circular queue using the (ay)+ addressing mode. for mac with load operations, the mask contents can optionally be included in all memory effective address calculations. 1.4 emac user programming model the following paragraphs describe the registers for the optional coldfire emac unit. figure 1-8 illustrates the user programming model for the emac unit. it contains the following registers: one 32-bit mac status register (macsr) including four indicator bits signaling product or accumulation over?w (one for each accumulator: pav0?av3) four 32-bit accumulators (accx = acc0, acc1, acc2, acc3) eight 8-bit accumulator extensions (two per accumulator), packaged as two 32-bit values for load and store operations (accext01, accext23) one 32-bit mask register (mask) figure 1-8. emac programming model 1.4.1 mac status register (macsr) figure 1-9 shows the emac macsr, which contains an operational mode ?ld and two sets of ?gs. 31 0 macsr mac status register acc0 mac accumulator 0 acc1 mac accumulator 1 acc2 mac accumulator 2 acc3 mac accumulator 3 accext01 extensions for acc0 and acc1 accext23 extensions for acc2 and acc3 mask mac mask register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. introduction 1-9 emac user programming model table 1-5 describes emac macsr ?lds. 1.4.2 mac accumulators (acc[0:3]) the emac implements four 48-bit accumulators. the 32-bit accx registers, along with the accumulator extension words, contain the accumulator data. figure 1-10 shows the data contained by the accumulator and accumulator extension words when the emac is operating in fractional mode. the upper 8 bits of the extended product are sign-extended from the 40-bit result taken from the product. 31 1211109 8 76543210 prod/acc over?w ?gs operational mode flags pav3 pav2 pav1 pav0 omc s/u f/i r/t n z v ev figure 1-9. mac status register (macsr) table 1-5. macsr field descriptions bits field description 31-12 reserved, should be cleared. 11-8 pav x product/accumulation over?w ?gs, one per accumulator 7-4 omf operational mode field. de?es the operating con?uration of the emac unit. 7 omc over?w/saturation mode 6 s/u signed/unsigned operations 5 f/i fraction/integer mode 4 r/t round/truncate mode 3? flags flags. contains indicator ?gs from the last mac instruction execution. 3 n negative 2 z zero 1 v over?w 0 c carry. this ?ld is always zero. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-10 coldfire family programmers reference manual emac user programming model figure 1-10. emac fractional alignment figure 1-11 shows the data contained by the accumulator and accumulator extension words when the emac is operating in signed or unsigned integer mode. in signed mode, the upper 8 bits of the extended product are sign extended from the 40-bit result taken from the product. in unsigned mode, the upper 8 bits of the extended product are all zeros. figure 1-11. emac signed and unsigned integer alignment x operand y operand x product extended product accumulator 32 upper extension byte [7:0] lower extension byte [7:0] accumulator [31:0] + 32 40 24 40 8 32 88 x operand y operand x product extended product accumulator 32 upper extension byte [7:0] lower extension byte [7:0] accumulator [31:0] + 32 24 32 32 8 8 32 8 8 8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. introduction 1-11 supervisor programming model 1.4.3 accumulator extensions (accext01, accext23) the 32-bit accumulator extension registers (accext01, accext23) allow the complete contents of the 48-bit accumulator to be saved and restored on context switches. figure 1-12 shows how the acc0 and acc1 data is stored when loaded into a register. refer to figure 1-10 and figure 1-11 for information on the data contained in the extension bytes. figure 1-13 shows how the acc2 and acc3 data is stored when loaded into a register. refer to figure 1-10 and figure 1-11 for information on the data contained in the extension bytes. 1.4.4 mac mask register (mask) only the low-order 16 bits of the 32-bit mask register (mask) are implemented. when mask is loaded, the low-order 16 bits of the source operand are loaded into the register. when it is stored, the upper 16 bits are forced to all ones. when used by an instruction, mask is anded with the speci?d operand address. thus, mask allows an operand address to be effectively constrained within a certain range de?ed by the 16-bit value. this feature minimizes the addressing support required for ?tering, convolution, or any routine that implements a data array as a circular queue using the (ay)+ addressing mode. for mac with load operations, the mask contents can optionally be included in all memory effective address calculations. 1.5 supervisor programming model system programmers use the supervisor programming model to implement operating system functions. all accesses that affect the control features of coldfire processors must be made in supervisor mode. the following paragraphs brie? describe the supervisor registers, which can be accessed only by privileged instructions. the supervisor programming model consists of the registers available to users as well as the registers listed in figure 1-14. 31 24 23 16 15 8 7 0 acc1 upper extension byte acc1 lower extension byte acc0 upper extension byte acc0 lower extension byte figure 1-12. accumulator 0 and 1 extensions (accext01) 31 24 23 16 15 8 7 0 acc3 upper extension byte acc3 lower extension byte acc2 upper extension byte acc2 lower extension byte figure 1-13. accumulator 2 and 3 extensions (accext01) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-12 coldfire family programmers reference manual supervisor programming model figure 1-14. supervisor programming model note that not all registers are implemented on every coldfire device; refer to table 1-6. future devices will implement registers that are not implemented on current devices. 1.5.1 status register (sr) the sr, shown in figure 1-15, stores the processor status, the interrupt priority mask, and other control bits. supervisor software can read or write the entire sr; user software can read or write only sr[7?], described in section 1.1.4, ?ondition code register (ccr). the control bits indicate processor states: trace mode (t), supervisor or user mode (s), and master or interrupt state (m). sr is set to 0x27 xx after reset. 31 19 15 0 (ccr) sr status register other_a7 supervisor a7 stack pointer must be zeros vbr vector base register cacr cache control register asid address space id register acr0 access control register 0 (data) acr1 access control register 1 (data) acr2 access control register 2 (instruction) acr3 access control register 3 (instruction) mmubar mmu base address register rombar0 rom base address register 0 rombar1 rom base address register 1 rambar0 ram base address register 0 rambar1 ram base address register 1 mbar module base address register table 1-6. implemented supervisor registers by device name 5202 5204 5206 5206e 5272 5307 5407 sr ????? other_a7 vbr ????? cacr ????? asid acr0 ????? acr1 ????? acr2 acr3 mmubar rombar0 rombar1 rambar0 ???? rambar1 mbar ???? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. introduction 1-13 supervisor programming model table 1-7 describes sr ?lds. 1.5.2 supervisor/user stack pointers (a7 and other_a7) the v2 and v3 architectures support a single stack pointer (a7). the initial value of a7 is loaded from the reset exception vector, address offset 0. the v4 architecture supports two independent stack pointer (a7) registers: the supervisor stack pointer (ssp) and the user stack pointer (usp). this support provides the required isolation between operating modes as dictated by the virtual memory management scheme provided by the memory management unit (mmu). (note that a device without an mmu, such as v2 and v3, has a single stack pointer.) the hardware implementation of these two programmable-visible 32-bit registers does not uniquely identify one as the ssp and the other as the usp. rather, the hardware uses one 32-bit register as the currently active a7 and the other as other_a7. thus, the register contents are a function of the processor operating mode, as shown in the following: if sr[s] = 1 then a7 = supervisor stack pointer other_a7 = user stack pointer else a7 = user stack pointer other_a7 = supervisor stack pointer 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 system byte condition code register (ccr) t s m i p 1 x n z v c 1 the p bit is implemented only on the v3 core. figure 1-15. status register (sr) table 1-7. status field descriptions bits name description 15 t trace enable. when t is set, the processor performs a trace exception after every instruction. 14 reserved, should be cleared. 13 s supervisor/user state. indicates whether the processor is in supervisor or user mode 12 m master/interrupt state. cleared by an interrupt exception. it can be set by software during execution of the rte or move to sr instructions so the os can emulate an interrupt stack pointer. 11 reserved, should be cleared. 10? i interrupt priority mask. de?es the current interrupt priority. interrupt requests are inhibited for all priority levels less than or equal to the current priority, except the edge-sensitive level-7 request, which cannot be masked. 7? ccr condition code register (see figure 1-2 and table 1-1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-14 coldfire family programmers reference manual supervisor programming model 1.5.3 vector base register (vbr) the vector base register contains the 1 mbyte-aligned base address of the exception vector table in memory. the displacement of an exception vector adds to the value in this register, which accesses the vector table. vbr[19?] are ?led with zeros. 1.5.4 cache control register (cacr) the cacr controls operation of both the instruction and data cache memory. it includes bits for enabling, freezing, and invalidating cache contents. it also includes bits for de?ing the default cache mode and write-protect ?lds. bit functions and positions may vary among coldfire processor implementations. refer to a speci? device or core users manual for further information. 1.5.5 address space identi?r (asid) only the low-order 8 bits of the 32-bit asid register are implemented. the asid value is an 8-bit identi?r assigned by the operating system to each process active in the system. it effectively serves as an extension to the 32-bit virtual address. thus, the virtual reference now becomes a 40-bit value: the 8-bit asid concatenated with the 32-bit virtual address. asid is only available if a device has an mmu. refer to a speci? device or core users manual for further information. 1.5.6 access control registers (acr0?cr3) the access control registers (acr[0:3]) de?e attributes for four user-de?ed memory regions. acr0 and acr1 control data memory space and acr2 and acr3 control instruction memory space. attributes include de?ition of cache mode, write protect, and buffer write enables. not all coldfire processors implement all four acrs. bit functions and positions may vary among coldfire processor implementations. refer to a speci? device or core users manual for further information. 1.5.7 mmu base address register (mmubar) mmubar, shown in figure 1-17, de?es a memory-mapped, privileged data-only space with the highest priority in effective address attribute calculation for the data internal memory bus (that is, the mmubar has priority over rambar0). if virtual mode is enabled, any normal mode access that does not hit in the mmubar, rambars, rombars, or acrs is considered a normal-mode, virtual address request and generates its access attributes from the mmu. mmubar is only available if a device has an mmu. 31 20 19 0 exception vector table base address figure 1-16. vector base register (vbr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. introduction 1-15 supervisor programming model refer to a speci? device or core users manual for further information. table 1-8 describes mmu base address register ?lds. 1.5.8 ram base address registers (rambar0/rambar1) rambar registers determine the base address of the internal sram modules and indicate the types of references mapped to each. each rambar includes a base address, write-protect bit, address space mask bits, and an enable bit. ram base address alignment is implementation speci?. a speci? coldfire processor may implement 2, 1, or 0 rambars. bit functions and positions can vary among coldfire processor implementations. refer to a speci? device or core users manual for further information. 1.5.9 rom base address registers (rombar0/rombar1) rombar registers determine the base address of the internal rom modules and indicate the types of references mapped to each. each rombar includes a base address, write-protect bit, address space mask bits, and an enable bit. rom base address alignment is implementation speci?. a speci? coldfire processor may implement 2, 1, or 0 rombars. bit functions and positions can vary among coldfire processor implementations. refer to a speci? device or core users manual for further information. 1.5.10 module base address register (mbar) the supervisor-level mbar, figure 1-18, speci?s the base address and allowable access types for all internal peripherals. mbar can be read or written through the debug module as a read/write register; only the debug module can read mbar. all internal peripheral registers occupy a single relocatable memory block along 4-kbyte boundaries. mbar masks speci? address spaces using the address space ?lds. refer to a speci? device or core users manual for further information. 31 16 15 1 0 ba ? figure 1-17. mmu base address register table 1-8. mmu base address register field descriptions bits name description 31?6 ba base address. de?es the base address for the 64-kbyte address space mapped to the mmu. 15? reserved, should be cleared. 0 v valid f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-16 coldfire family programmers reference manual integer data formats table 1-9 describes mbar ?lds. 1.6 integer data formats the operand data formats are supported by the integer unit, as listed in table 1-10. integer unit operands can reside in registers, memory, or instructions themselves. the operand size for each instruction is either explicitly encoded in the instruction or implicitly de?ed by the instruction operation. 1.7 floating-point data formats this section describes the optional fpus operand data formats. the fpu supports three signed integer formats (byte, word, and longword) that are identical to those supported by 31 1211 9876 543210 ba wp am c/i sc sd uc ud v figure 1-18. module base address register (mbar) table 1-9. mbar field descriptions bits field description 31?2 ba base address. de?es the base address for a 4-kbyte address range. 11? reserved, should be cleared. 8? amb attribute mask bits 8 wp write protect. mask bit for write cycles in the mbar-mapped register address range 7 reserved, should be cleared. 6 am alternate master mask 5 c/i mask cpu space and interrupt acknowledge cycles 4 sc setting masks supervisor code space in mbar address range 3 sd setting masks supervisor data space in mbar address range 2 uc setting masks user code space in mbar address range 1 ud setting masks user data space in mbar address range 0 v valid. determines whether mbar settings are valid. table 1-10. integer data formats operand data format size bit 1 bit byte integer 8 bits word integer 16 bits longword integer 32 bits attribute mask bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. introduction 1-17 floating-point data formats the integer unit. the fpu also supports single- and double-precision binary ?ating-point formats that fully comply with the ieee-754 standard. 1.7.1 floating-point data types each ?ating-point data format supports ?e unique data types: normalized numbers, zeros, in?ities, nans, and denormalized numbers. the normalized data type, figure 1-19, never uses the maximum or minimum exponent value for a given format. 1.7.1.1 normalized numbers normalized numbers include all positive or negative numbers with exponents between the maximum and minimum values. for single- and double-precision normalized numbers, the implied integer bit is one and the exponent can be zero. figure 1-19. normalized number format 1.7.1.2 zeros zeros can be positive or negative and represent real values, + 0.0 and ?0.0. see figure 1-20. figure 1-20. zero format 1.7.1.3 in?ities in?ities can be positive or negative and represent real values that exceed the over?w threshold. a results exponent greater than or equal to the maximum exponent value indicates an over?w for a given data format and operation. this over?w description ignores the effects of rounding and the user-selectable rounding models. for single- and double-precision in?ities, the fraction is a zero. see figure 1-21. figure 1-21. infinity format min < exponent < max fraction = any bit pattern sign of mantissa, 0 or 1 exponent = 0 fraction = 0 sign of mantissa, 0 or 1 exponent = maximum fraction = 0 sign of mantissa, 0 or 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-18 coldfire family programmers reference manual floating-point data formats 1.7.1.4 not-a-number when created by the fpu, nans represent the results of operations having no mathematical interpretation, such as in?ity divided by in?ity. operations using a nan operand as an input return a nan result. user-created nans can protect against uninitialized variables and arrays or can represent user-de?ed data types. see figure 1-22. figure 1-22. not-a-number format if an input operand to an operation is a nan, the result is an fpu-created default nan. when the fpu creates a nan, the nan always contains the same bit pattern in the mantissa: all mantissa bits are ones and the sign bit is zero. when the user creates a nan, any nonzero bit pattern can be stored in the mantissa and the sign bit. 1.7.1.5 denormalized numbers denormalized numbers represent real values near the under?w threshold. denormalized numbers can be positive or negative. for denormalized numbers in single- and double-precision, the implied integer bit is a zero. see figure 1-23. figure 1-23. denormalized number format traditionally, the detection of under?w causes ?ating-point number systems to perform a ?sh-to-zero. the ieee-754 standard implements gradual under?w: the result mantissa is shifted right (denormalized) while the result exponent is incremented until reaching the minimum value. if all the mantissa bits of the result are shifted off to the right during this denormalization, the result becomes zero. denormalized numbers are not supported directly in the hardware of this implementation but can be handled in software if needed (software for the input denorm exception could be written to handle denormalized input operands, and software for the under?w exception could create denormalized numbers). if the input denorm exception is disabled, all denormalized numbers are treated as zeros. 1.7.2 fpu data format and type summary table 1-11 summarizes the data type speci?ations for byte, word, longword, single-, and double-precision data formats. exponent = maximum fraction = any nonzero bit pattern sign of mantissa, 0 or 1 exponent = 0 fraction = any nonzero bit pattern sign of mantissa, 0 or 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. introduction 1-19 floating-point data formats table 1-11. real format summary parameter single-precision double-precision data format field size in bits sign (s) 1 1 biased exponent (e) 8 11 fraction (f) 23 52 total 32 64 interpretation of sign positive fraction s = 0 s = 0 negative fraction s = 1 s = 1 normalized numbers bias of biased exponent +127 (0x7f) +1023 (0x3ff) range of biased exponent 0 < e < 255 (0xff) 0 < e < 2047 (0x7ff) range of fraction zero or nonzero zero or nonzero mantissa 1.f 1.f relation to representation of real numbers (?) s 2 e?27 1.f (?) s 2 e?023 1.f denormalized numbers biased exponent format minimum 0 (0x00) 0 (0x000) bias of biased exponent +126 (0x7e) +1022 (0x3fe) range of fraction nonzero nonzero mantissa 0.f 0.f relation to representation of real numbers (?) s 2 ?26 0.f (?) s 2 ?022 0.f signed zeros biased exponent format minimum 0 (0x00) 0 (0x00) mantissa 0.f = 0.0 0.f = 0.0 signed in?ities biased exponent format maximum 255 (0xff) 2047 (0x7ff) mantissa 0.f = 0.0 0.f = 0.0 nans sign don? care 0 or 1 biased exponent format maximum 255 (0xff) 255 (0x7ff) fraction nonzero nonzero se f 31 30 23 22 0 se f 63 62 52 51 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-20 coldfire family programmers reference manual multiply accumulate data formats 1.8 multiply accumulate data formats the mac and emac units support 16- or 32-bit input operands of the following formats: twos complement signed integers: in this format, an n-bit operand value lies in the range -2 (n-1) < operand < 2 (n-1) - 1. the binary point is right of the lsb. unsigned integers: in this format, an n-bit operand value lies in the range 0 < operand < 2 n - 1. the binary point is right of the lsb. twos complement, signed fractionals: in an n-bit number, the ?st bit is the sign bit. the remaining bits signify the ?st n-1 bits after the binary point. given an n-bit number, a n-1 a n-2 a n-3 ... a 2 a 1 a 0 , its value is given by the equation in figure 1-24. figure 1-24. two? complement, signed fractional equation this format can represent numbers in the range -1 < operand < 1 - 2 (n-1) . for words and longwords, the largest negative number that can be represented is -1, whose internal representation is 0x8000 and 0x8000_0000, respectively. the largest positive word is 0x7fff or (1 - 2 -15 ); the most positive longword is 0x7fff_ffff or (1 - 2 -31 ). 1.9 organization of data in registers this section describes data organization within the data, address, and control registers. 1.9.1 organization of integer data formats in registers each integer data register is 32 bits wide. byte and word operands occupy the lower 8- and 16-bit portions of integer data registers, respectively. longword operands occupy entire data registers. a data register that is either a source or destination operand only uses or representation of fraction nonzero bit pattern created by user fraction when created by fpu xxxxx?xxx 11111?111 xxxxx?xxx 11111?111 approximate ranges maximum positive normalized 3.4 10 38 1.8 x 10 308 minimum positive normalized 1.2 10 ?8 2.2 x 10 ?08 minimum positive denormalized 1.4 10 ?5 4.9 x 10 ?24 table 1-11. real format summary (continued) parameter single-precision double-precision value 1 a n1 ? () ? i1n + () ai ? i0 = n2 + = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 1. introduction 1-21 organization of data in registers changes the appropriate lower 8 or 16 bits (in byte or word operations, respectively). the remaining high-order portion does not change and is unused and unchanged. the address of the least signi?ant bit (lsb) of a longword integer is zero, and the most signi?ant bit (msb) is 31. figure 1-25 illustrates the organization of integer data in data registers. because address registers and stack pointers are 32 bits wide, address registers cannot be used for byte-size operands. when an address register is a source operand, either the low-order word or the entire longword operand is used, depending on the operation size. when an address register is the destination operand, the entire register becomes affected, despite the operation size. if the source operand is a word size, it is sign-extended to 32 bits and then used in the operation to an address-register destination. address registers are primarily for addresses and address computation support. the instruction set explains how to add to, compare, and move the contents of address registers. figure 1-26 illustrates the organization of addresses in address registers. control registers vary in size according to function. some control registers have unde?ed bits reserved for future de?ition by motorola. those particular bits read as zeros and must be written as zeros for future compatibility. all operations to the sr and ccr are word-size operations. for all ccr operations, the upper byte is read as all zeros and is ignored when written, despite privilege mode. the write-only movec instruction writes to the system control registers (vbr, cacr, etc.). 31 30 1 0 msb lsb bit (0 bit number 31) 31 8 7 6 1 0 not used msb low order byte lsb byte (8 bits) 31 16 15 14 1 0 not used msb lower order word lsb word (16 bits) 31 30 1 0 msb longword lsb longword (32 bits) figure 1-25. organization of integer data format in data registers 31 16 15 0 sign-extended 16-bit address operand 31 0 full 32-bit address operand figure 1-26. organization of addresses in address registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1-22 coldfire family programmers reference manual organization of data in registers 1.9.2 organization of integer data formats in memory the byte-addressable organization of memory allows lower addresses to correspond to higher order bytes. the address n of a longword data item corresponds to the address of the msb of the highest order word. the lower order word is located at address n + 2, leaving the lsb at address n + 3 (see figure 1-27). the lowest address (nearest 0x00000000) is the location of the msb, with each successive lsb located at the next address (n + 1, n + 2, etc.). the highest address (nearest 0xffffffff) is the location of the lsb. figure 1-28 illustrates the organization of data formats in memory. a base address that selects one byte in memory?he base byte?peci?s a bit number that selects one bit, the bit operand, in the base byte. the msb of the byte is 7. 31 24 23 16 15 8 7 0 longword 0x0000_0000 word 0x0000_0000 word 0x0000_0002 byte 0x0000_0000 byte 0x0000_0001 byte 0x0000_0002 byte 0x0000_0003 longword 0x0000_0004 word 0x0000_0004 word 0x0000_0006 byte 0x0000_0004 byte 0x0000_0005 byte 0x0000_0006 byte 0x0000_0007 ... ... ... longword 0xffff_fffc word 0xffff_fffc word 0xffff_fffe byte 0xffff_fffc byte 0xffff_fffd byte 0xffff_fffe byte 0xffff_ffff figure 1-27. memory operand addressing 7 0 7 0 7 0 7 0 byte n-1 7 6 5 43 2 1 0 byte n+1 byte n+2 bit data base address bit number 7 0 7 0 7 0 7 0 byte n-1 msb byte n lsb byte n+1 byte n+2 byte data address 7 0 15 0 7 0 7 0 byte n-1 msb word integer lsb byte n+2 byte n+3 word data address 7 0 31 0 7 0 byte n-1 msb longword integer lsb byte n+4 longword data address figure 1-28. memory organization for integer operands f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. addressing capabilities 2-1 chapter 2 addressing capabilities most operations compute a source operand and destination operand and store the result in the destination location. single-operand operations compute a destination operand and store the result in the destination location. external microprocessor references to memory are either program references that refer to program space or data references that refer to data space. they access either instruction words or operands (data items) for an instruction. program space is the section of memory that contains the program instructions and any immediate data operands residing in the instruction stream. data space is the section of memory that contains the program data. the program-counter relative addressing modes can be classi?d as data references. 2.1 instruction format coldfire family instructions consist of 1 to 3 words. figure 2-1 illustrates the general composition of an instruction. the ?st word of the instruction, called the operation word or opword, speci?s the length of the instruction, the effective addressing mode, and the operation to be performed. the remaining words further specify the instruction and operands. these words can be conditional predicates, immediate operands, extensions to the effective addressing mode speci?d in the operation word, branch displacements, bit number or special register speci?ations, trap operands, argument counts, or ?ating-point command words. the coldfire architecture instruction word length is limited to 3 sizes: 16, 32, or 48 bits. figure 2-1. instruction word general format an instruction speci?s the function to be performed with an operation code and de?es the location of every operand. the operation word format is the basic instruction word (see figure 2-2). the encoding of the mode ?ld selects the addressing mode. the register ?ld contains the general register number or a value that selects the addressing mode when the operation word (one word, speci?s operation and modes) extension word (if any) extension word (if any) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-2 coldfire family programmers reference manual effective addressing modes mode ?ld = 111. some indexed or indirect addressing modes use a combination of the operation word followed by an extension word. figure 2-2 illustrates two formats used in an instruction word; table 2-1 lists the ?ld de?itions. 2.2 effective addressing modes besides the operation code that speci?s the function to be performed, an instruction de?es the location of every operand for the function. instructions specify an operand location in one of the three following ways: a register ?ld within an instruction can specify the register to be used. an instructions effective address ?ld can contain addressing mode information. operation word format 1514131211109876543210 xxxxxxxxxx eff ective address mode register extension word format 1514131211109876543210 d/a register w/l scale 0 displacement figure 2-2. instruction word specification formats table 2-1 de?es instruction word formats. table 2-1. instruction word format field definitions field de?ition instruction mode addressing mode (see table 2-3) register general register number (see table 2-3) extensions d/a index register type 0 = d n 1 = a n w/l word/longword index size 0 = address error exception 1 = longword scale scale factor 00 = 1 01 = 2 10 = 4 11 = 8 (supported only if fpu is present) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. addressing capabilities 2-3 effective addressing modes the instructions de?ition can imply the use of a speci? register. other ?lds within the instruction specify whether the register selected is an address or data register and how the register is to be used. an instructions addressing mode speci?s the value of an operand, a register that contains the operand, or how to derive the effective address of an operand in memory. each addressing mode has an assembler syntax. some instructions imply the addressing mode for an operand. these instructions include the appropriate ?lds for operands that use only one addressing mode. 2.2.1 data register direct mode in the data register direct mode, the effective address ?ld speci?s the data register containing the operand. figure 2-3. data register direct 2.2.2 address register direct mode in the address register direct mode, the effective address ?ld speci?s the address register containing the operand. figure 2-4. address register direct 2.2.3 address register indirect mode in the address register indirect mode, the operand is in memory. the effective address ?ld speci?s the address register containing the address of the operand in memory. operand data register generation assembler syntax ea mode field ea register field number of extension words ea = dn dn 000 register number 0 operand address register generation assembler syntax ea mode field ea register field number of extension words ea = an an 001 register number 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-4 coldfire family programmers reference manual effective addressing modes figure 2-5. address register indirect 2.2.4 address register indirect with postincrement mode in the address register indirect with postincrement mode, the operand is in memory. the effective address ?ld speci?s the address register containing the address of the operand in memory. after the operand address is used, it is incremented by one, two, or four, depending on the size of the operand (i.e., byte, word, or longword, respectively). note that the stack pointer (a7) is treated exactly like any other address register. figure 2-6. address register indirect with postincrement 2.2.5 address register indirect with predecrement mode in the address register indirect with predecrement mode, the operand is in memory. the effective address ?ld speci?s the address register containing the address of the operand in memory. before the operand address is used, it is decremented by one, two, or four depending on the operand size (i.e., byte, word, or longword, respectively). note that the stack pointer (a7) is treated just like the other address registers. operand operand pointer 31 0 address register memory points to generation assembler syntax ea mode field ea register field number of extension words ea = (an) (an) 010 register number 0 operand contents contents size + 31 0 31 0 address register operand length operand pointer memory points to generation assembler syntax ea mode field ea register field number of extension words ea = (an); an = an + size (an)+ 011 register number 0 (1, 2, or 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. addressing capabilities 2-5 effective addressing modes figure 2-7. address register indirect with predecrement 2.2.6 address register indirect with displacement mode in the address register indirect with displacement mode, the operand is in memory. the operand address in memory consists of the sum of the address in the address register, which the effective address speci?s, and the sign-extended 16-bit displacement integer in the extension word. displacements are always sign-extended to 32 bits prior to being used in effective address calculations. figure 2-8. address register indirect with displacement operand contents contents size 31 0 31 0 address register operand length operand pointer memory points to generation assembler syntax ea mode field ea register field number of extension words ea = (an) - size; an = an - size; ?an) 100 register number 0 (1, 2, or 4) operand contents contents sign-extension integer + 31 0 31 0 31 0 15 address register displacement operand pointer memory points to generation assembler syntax ea mode field ea register field number of extension words ea = (an) + d 16 (d 16 ,an) 101 register number 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-6 coldfire family programmers reference manual effective addressing modes 2.2.7 address register indirect with scaled index and 8-bit displacement mode this addressing mode requires one extension word that contains an index register indicator, possibly scaled, and an 8-bit displacement. the index register indicator includes size and scale information. in this mode, the operand is in memory. the operand address is the sum of the address register contents; the sign-extended displacement value in the extension words low-order 8 bits; and the scaled index registers sign-extended contents. users must specify the address register, the displacement, the scale factor and the index register in this mode. figure 2-9. address register indirect with scaled index and 8-bit displacement 2.2.8 program counter indirect with displacement mode in this mode, the operand is in memory. the address of the operand is the sum of the address in the program counter (pc) and the sign-extended 16-bit displacement integer in the extension word. the value in the pc is the address of the extension word (pc+2). this is a program reference allowed only for reads. operand contents contents sign-extended value sign-extension integer + + scale value x 31 0 31 0 31 0 31 0 7 address register displacement index register scale operand pointer memory points to generation assembler syntax ea mode field ea register field number of extension words ea = (an) + ((xi) * scalefactor)) + sign-extended d 8 (d 8 ,an,xi,size*scale) 110 register number 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. addressing capabilities 2-7 effective addressing modes figure 2-10. program counter indirect with displacement 2.2.9 program counter indirect with scaled index and 8-bit displacement mode this mode is similar to the mode described in section 2.2.7, address register indirect with scaled index and 8-bit displacement mode,?except the pc is the base register. the operand is in memory. the operand address is the sum of the address in the pc, the sign-extended displacement integer in the extension words lower 8 bits, and the sized, scaled, and sign-extended index operand. the value in the pc is the address of the extension word (pc + 2). this is a program reference allowed only for reads. users must include the displacement, the scale, and the index register when specifying this addressing mode. operand contents contents sign-extension integer + 31 0 31 0 31 0 15 program counter displacement operand pointer memory points to generation assembler syntax ea mode field ea register field number of extension words ea = (pc) + d 16 (d 16 ,pc) 111 010 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-8 coldfire family programmers reference manual effective addressing modes figure 2-11. program counter indirect with scaled index and 8-bit displacement 2.2.10 absolute short addressing mode in this addressing mode, the operand is in memory, and the address of the operand is in the extension word. the 16-bit address is sign-extended to 32 bits before it is used. figure 2-12. absolute short addressing operand contents contents sign-extended value sign-extension integer + + scale value x 31 0 31 0 31 0 31 0 7 program counter displacement index register scale operand pointer memory points to generation assembler syntax ea mode field ea register field number of extension words ea = (pc) + ((xi) * scalefactor)) + sign-extended d 8 (d 8 ,pc,xi,size*scale) 111 011 1 operand contents sign-extension integer 31 0 31 0 31 0 15 extension word operand pointer memory points to generation assembler syntax ea mode field ea register field number of extension words ea given (xxx).w 111 000 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. addressing capabilities 2-9 effective addressing modes 2.2.11 absolute long addressing mode in this addressing mode, the operand is in memory, and the operand address occupies the two extension words following the instruction word in memory. the ?st extension word contains the high-order part of the address; the second contains the low-order part of the address. figure 2-13. absolute long addressing 2.2.12 immediate data in this addressing mode, the operand is in 1 or 2 extension words. table 2-2 lists the location of the operand within the instruction word format. the immediate data format is as follows: figure 2-14. immediate data addressing table 2-2. immediate operand location operation length location byte low-order byte of the extension word word entire extension word longword high-order word of the operand is in the ?st extension word; the low-order word is in the second extension word. operand contents address low 31 0 0 15 second extension word operand pointer memory points to generation assembler syntax ea mode field ea register field number of extension words ea given (xxx).l 111 001 2 address high 0 15 first extension word generation assembler syntax ea mode field ea register field number of extension words operand given # 111 100 1 or 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-10 coldfire family programmers reference manual stack 2.2.13 effective addressing mode summary effective addressing modes are grouped according to the mode use. data-addressing modes refer to data operands. memory-addressing modes refer to memory operands. alterable addressing modes refer to alterable (writable) operands. control-addressing modes refer to memory operands without an associated size. these categories sometimes combine to form new categories that are more restrictive. two combined classi?ations are alterable memory (addressing modes that are both alterable and memory addresses) and data alterable (addressing modes that are both alterable and data). table 2-3 lists a summary of effective addressing modes and their categories. 2.3 stack address register a7 stacks exception frames, subroutine calls and returns, temporary variable storage, and parameter passing and is affected by instructions such as the link, unlk, rte, and pea. to maximize performance, a7 must be longword-aligned at all times. therefore, when modifying a7, be sure to do so in multiples of 4 to maintain alignment. to further ensure alignment of a7 during exception handling, the coldfire architecture implements a self-aligning stack when processing exceptions. users can employ other address registers to implement other stacks using the address register indirect with postincrement and predecrement addressing modes. with an address register, users can implement a stack that ?ls either from high memory to low memory or vice versa. users should keep in mind these important directives: table 2-3. effective addressing modes and categories addressing modes syntax mode field reg. field data memory control alterable register direct data address dn an 000 001 reg. no. reg. no. x x x register indirect address address with postincrement address with predecrement address with displacement (an) (an)+ ?an) (d 16 ,an) 010 011 100 101 reg. no. reg. no. reg. no. reg. no. x x x x x x x x x x x x x x address register indirect with scaled index and 8-bit displacement (d 8 ,an,xi*sf) 110 reg. no. x x x x program counter indirect with displacement (d 16 ,pc) 111 010 x x x program counter indirect with scaled index and 8-bit displacement (d 8 ,pc,xi*sf) 111 011 x x x absolute data addressing short long (xxx).w (xxx).l 111 111 000 001 x x x x x x immediate # 111 100 x x f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 2. addressing capabilities 2-11 stack use the predecrement mode to decrement the register before using its contents as the pointer to the stack. use the postincrement mode to increment the register after using its contents as the pointer to the stack. maintain the stack pointer correctly when byte, word, and longword items mix in these stacks. to implement stack growth from high memory to low memory, use ?an) to push data on the stack and (an)+ to pull data from the stack. for this type of stack, after either a push or a pull operation, the address register points to the top item on the stack. figure 2-15. stack growth from high memory to low memory to implement stack growth from low memory to high memory, use (an)+ to push data on the stack and ?an) to pull data from the stack. after either a push or pull operation, the address register points to the next available space on the stack. figure 2-16. stack growth from low memory to high memory bottom of stack low memory (free) top of stack high memory an bottom of stack low memory top of stack (free) high memory an f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2-12 coldfire family programmers reference manual stack f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 3. instruction set summary 3-1 chapter 3 instruction set summary this section brie? describes the coldfire family instruction set, using motorolas assembly language syntax and notation. it includes instruction set details such as notation and format. 3.1 instruction summary instructions form a set of tools that perform the following types of operations: data movement program control integer arithmetic system control logical operations cache maintenance shift operations floating-point arithmetic bit manipulation the following paragraphs detail the instruction for each type of operation. table 3-1 lists the notations used throughout this manual. in the operand syntax statements of the instruction de?itions, the operand on the right is the destination operand. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-2 coldfire family programmers reference manual instruction summary table 3-1. notational conventions single- and double operand operations + arithmetic addition or postincrement indicator arithmetic subtraction or predecrement indicator * arithmetic multiplication / arithmetic division ~ invert; operand is logically complemented. & logical and | logical or ^ logical exclusive or source operand is moved to destination operand. two operands are exchanged. any double-operand operation. tested operand is compared to zero, and the condition codes are set appropriately. sign-extended all bits of the upper portion are made equal to the high-order bit of the lower portion. other operations if then else test the condition. if true, the operations after ?hen are performed. if the condition is false and the optional ?lse" clause is present, the operations after ?lse" are performed. if the condition is false and else is omitted, the instruction performs no operation. refer to the bcc instruction description as an example. register speci?ations a n any address register n (example: a3 is address register 3) ax, ay destination and source address registers, respectively d n any data register n (example: d5 is data register 5) dx, dy destination and source data registers, respectively dw data register containing a remainder rc control register r n any address or data register rx, ry any destination and source registers, respectively xi index register, can be any address or data register; all 32-bits are used. sub?lds and quali?rs # immediate data following the instruction word(s). ( ) identi?s an indirect address in a register. d n displacement value, n bits wide (example: d 16 is a 16-bit displacement). sz size of operation: byte (b), word (w), longword (l) lsb, msb least signi?ant bit, most signi?ant bit lsw, msw least signi?ant word, most signi?ant word sf scale factor for an index register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 3. instruction set summary 3-3 instruction summary register names ccr condition code register (lower byte of status register) pc program counter sr status register usp user stack pointer ic, dc, bc instruction, data, or both caches (uni?d cache uses bc) condition codes * general case c carry bit in ccr cc condition codes from ccr n negative bit in ccr v over?w bit in ccr x extend bit in ccr z zero bit in ccr not affected or applicable miscellaneous x, y destination and source effective address, respectively assembly program label #list list of registers, for example d3?0 mac operations acc, accx mac accumulator register, a speci? emac accumulator register accx, accy destination and source accumulators, respectively accext01 four extension bytes associated with emac accumulators 0 and 1 accext23 four extension bytes associated with emac accumulators 2 and 3 ev extension over?w ?g in macsr macsr mac status register mask mac mask register pavx product/accumulation over?w ?gs in macsr rxsf a register containing a mac operand that is to be scaled rw destination register for a mac with load operation table 3-1. notational conventions (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-4 coldfire family programmers reference manual instruction summary 3.1.1 data movement instructions the move and fmove instructions with their associated addressing modes are the basic means of transferring and storing addresses and data. move instructions transfer byte, word, and longword operands from memory to memory, memory to register, register to memory, and register to register. movea instructions transfer word and longword operands and ensure that only valid address manipulations are executed. in addition to the general move instructions, there are several special data movement instructions: mov3q, movem, moveq, mvs, mvz, lea, pea, link, and unlk. mov3q, mvs, and mvz are isa_b additions to the instruction set. the fmove instructions move operands into, out of, and between ?ating-point data registers. fmove also moves operands to and from the fpcr, fpiar, and fpsr. for operands moved into a ?ating-point data register, fsmove and fdmove explicitly select single- and double-precision rounding of the result. fmovem moves any combination of ?ating-point data registers. table 3-2 lists the general format of these integer and ?ating-point data movement instructions. floating-point operations fmt format of operation: byte (b), word (w), longword (l), single-precision (s), double-precision(d) +inf positive in?ity -inf negative in?ity fpx, fpy destination and source ?ating-point data registers, respectively fpcr floating-point control register fpiar floating-point instruction address register fpsr floating-point status register nan not-a-number table 3-1. notational conventions (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 3. instruction set summary 3-5 instruction summary 3.1.2 integer arithmetic instructions the integer arithmetic operations include 5 basic operations: add, sub, mul, div, and rem. they also include cmp, clr, and neg. the instruction set includes add, cmp, and sub instructions for both address and data operations. the clr instruction applies to all sizes of data operands. signed and unsigned mul, div, and rem instructions include: word multiply to produce a longword product longword multiply to produce a longword product longword divided by a word with a word quotient and word remainder longword divided by a longword with a longword quotient longword divided by a longword with a longword remainder (rem) table 3-2. data movement operation format instruction operand syntax operand size operation fdmove fpy,fpx d source destination; round destination to double fmove y,fpx fpy,x fpy,fpx fpcr,x y,fpcr b,w,l,s,d b,w,l,s,d d l l source destination fpcr can be any ?ating-point control register: fpcr, fpiar, fpsr fmovem #list,x y,#list d listed registers destination source listed registers fsmove y,fpx b,w,l,s,d source destination; round destination to single lea y,ax l y ax link ay,# w sp ?4 sp; ay (sp); sp ay, sp + d n sp mov3q 1 1 supported starting with v4 #,x l immediate data destination movclr 2 2 emac instruction accy,rx l accumulator destination, 0 accumulator move 3 move from ccr move to ccr 3 additional addressing modes supported starting with v4 y,x maccr,dx y,maccr ccr,dx y,ccr b,w,l l l w w source destination where maccr can be any mac control register: accx, accext01, accext23, macsr, mask movea y,ax w,l l source destination movem #list,x y,#list l listed registers destination source listed registers moveq #,dx b l immediate data destination mvs 1 y,dx b,w source with sign extension destination mvz 1 y,dx b,w source with zero ?l destination pea y l sp ?4 sp; y (sp) unlk ax none ax sp; (sp) ax; sp + 4 sp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-6 coldfire family programmers reference manual instruction summary a set of extended instructions provides multiprecision and mixed-size arithmetic: addx, subx, ext, and negx. for devices with the optional mac or emac unit, mac and msac instructions are available. refer to table 3-3 for a summary of the integer arithmetic operations. in table 3-3, x refers to the x-bit in the ccr. table 3-3. integer arithmetic operation format instruction operand syntax operand size operation add adda dy,x y,dx y,ax l l l source + destination destination addi addq #,dx #,x l l immediate data + destination destination addx dy,dx l source + destination + ccr[x] destination clr x b, w, l 0 destination cmp cmpa y,dx y,ax b, w, l 1 w, l 2 destination ?source ccr cmpi #,dx b, w, l 1 destination ?immediate data ccr divs/divu 3 y,dx w, l destination / source destination (signed or unsigned) ext extb dx dx dx b w w l b l sign-extended destination destination mac ry,rxsf,accx 4 ry,rxsf,y,rw,accx 4 w, l w, l accx + (ry * rx){<<|>>}sf accx accx + (ry * rx){<<|>>}sf accx; (y(&mask)) rw msac ry,rxsf,accx 4 ry,rxsf,y,rw,accx 4 w, l w, l accx - (ry * rx){<<|>>}sf accx accx - (ry * rx){<<|>>}sf accx; (y(&mask)) rw muls/mulu y,dx w * w l l * l l source * destination destination (signed or unsigned) neg dx l 0 ?destination destination negx dx l 0 ?destination ?ccr[x] destination rems/remu 3 y,dw:dx l destination / source remainder (signed or unsigned) sats 5 dx l if ccr[v] == 1; then if dx[31] == 0; then dx[31:0] = 0x80000000; else dx[31:0] = 0x7fffffff; else dx[31:0] is unchanged sub suba y,dx dy,x y,ax l l l destination - source destination f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 3. instruction set summary 3-7 instruction summary 3.1.3 logical instructions the instructions and, or, eor, and not perform logical operations with longword integer data operands. a similar set of immediate instructions (andi, ori, and eori) provides these logical operations with longword immediate data. table 3-4 summarizes the logical operations. 3.1.4 shift instructions the asr, asl, lsr, and lsl instructions provide shift operations in both directions. all shift operations can be performed only on registers. register shift operations shift longwords. the shift count can be speci?d in the instruction operation word (to shift from 1 to 8 places) or in a register (modulo 64 shift count). the swap instruction exchanges the 16-bit halves of a register. table 3-5 is a summary of the shift operations. in table 3-5, c and x refer to the c-bit and x-bit in the ccr. subi subq #,dx #,x l l destination ?immediate data destination subx dy,dx l destination ?source ?ccr[x] destination 1 byte and word supported starting with v4 2 word supported starting with v4 3 supported starting with the 5206e 4 the accumulator does not need to be speci?d on the original mac unit 5 supported starting with v4 table 3-4. logical operation format instruction operand syntax operand size operation and y,dx dy,x l l source & destination destination andi #, dx l immediate data & destination destination eor dy,x l source ^ destination destination eori #,dx l immediate data ^ destination destination not dx l ~ destination destination or y,dx dy,x l l source | destination destination ori #,dx l immediate data | destination destination table 3-3. integer arithmetic operation format (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-8 coldfire family programmers reference manual instruction summary 3.1.5 bit manipulation instructions btst, bset, bclr, and bchg are bit manipulation instructions. all bit manipulation operations can be performed on either registers or memory. the bit number is speci?d either as immediate data or in the contents of a data register. register operands are 32 bits long, and memory operands are 8 bits long. table 3-6 summarizes bit manipulation operations. 3.1.6 program control instructions a set of subroutine call-and-return instructions and conditional and unconditional branch instructions perform program control operations. also included are test operand instructions (tst and ftst), which set the integer or ?ating-point condition codes for use by other program and system control instructions. nop forces synchronization of the internal pipelines. tpf is a no-operation instruction that does not force pipeline synchronization. table 3-7 summarizes these instructions. table 3-5. shift operation format instruction operand syntax operand size operation asl dy,dx #,dx l l ccr[x,c] (dx << dy) 0 ccr[x,c] (dx << #) 0 asr dy,dx #,dx l l msb (dx >> dy) ccr[x,c] msb (dx >> #) ccr[x,c] lsl dy,dx #,dx l l ccr[x,c] (dx << dy) 0 ccr[x,c] (dx << #) 0 lsr dy,dx #,dx l l 0 (dx >> dy) ccr[x,c] 0 (dx >> #) ccr[x,c] swap dx w msw of dx ? lsw of dx table 3-6. bit manipulation operation format instruction operand syntax operand size operation bchg dy,x #,x b, l b, l ~ ( of destination) ccr[z] of destination bclr dy,x #,x b, l b, l ~ ( of destination) ccr[z]; 0 of destination bset dy,x #,x b, l b, l ~ ( of destination) ccr[z]; 1 of destination btst dy,x #,x b, l b, l ~ ( of destination) ccr[z] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 3. instruction set summary 3-9 instruction summary letters cc in the integer instruction mnemonics bcc and scc specify testing one of the following conditions: for the de?ition of cc for fbcc, refer to section 7.2, ?onditional testing. table 3-7. program control operation format instruction operand syntax operand size operation conditional bcc b, w, l 1 1 longword supported starting with v4 if condition true, then pc + d n pc fbcc w, l if condition true, then pc + d n pc scc dx b if condition true, then 1s destination; else 0s destination unconditional bra b, w, l 1 pc + d n pc bsr b, w, l 1 sp ?4 sp; nextpc (sp); pc + d n pc fnop none none pc + 2 pc (fpu pipeline synchronized) jmp y none source address pc jsr y none sp ?4 sp; nextpc (sp); source pc nop none none pc + 2 pc (integer pipeline synchronized) tpf none # # none w l pc + 2 pc pc + 4 pc pc + 6 pc (pipeline not synchronized) returns rts none none (sp) pc; sp + 4 sp test operand ta s 2 2 supported starting with v4 x b destination tested ccr; 1 bit 7 of destination ftst y b, w, l, s, d source operand tested fpcc tst y b, w, l source operand tested ccr cc?arry clear ge?reater than or equal ls?ower or same pl?lus cs?arry set gt?reater than lt?ess than t?lways true 1 1 not applicable to the bcc instructions. eq?qual hi?igher mi?inus vc?ver?w clear f?ever true 1 le?ess than or equal ne?ot equal vs?ver?w set f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-10 coldfire family programmers reference manual instruction summary 3.1.7 system control instructions this type of instruction includes privileged and trapping instructions as well as instructions that use or modify the ccr. fsave and frestore save and restore the nonuser visible portion of the fpu during context switches. table 3-8 summarizes these instructions. 3.1.8 cache maintenance instructions the cache instructions provide maintenance functions for managing the caches. cpushl is used to push a speci? cache line, and possibly invalidate it. intouch can be used to load speci? data into the cache. both of these instructions are privileged instructions. table 3-9 summarizes these instructions. table 3-8. system control operation format instruction operand syntax operand size operation privileged frestore y none fpu state frame internal fpu state fsave x none internal fpu state fpu state frame halt none none halt processor core (synchronizes pipeline) move from sr sr,dx w sr destination move from usp 1 1 supported starting with v4 on devices containing an mmu. usp,dx l usp destination move to sr y,sr w source sr; dy or # source only (synchronizes pipeline) move to usp 1 ay,usp l source usp movec ry,rc l ry rc (synchronizes pipeline) rte none none 2 (sp) sr; 4 (sp) pc; sp + 8 sp adjust stack according to format (synchronizes pipeline) stop # none immediate data sr; stop (synchronizes pipeline) wdebug y l addressed debug wdmreg command executed (synchronizes pipeline) debug functions pulse none none set pst = 0x4 wddata y b, w, l source ddata port trap generating illegal none none sp ?4 sp; pc (sp) pc; sp ?2 sp; sr ( sp); sp ?2 sp; vector offset ( sp); (vbr + 0x10) pc trap # none 1 s bit of sr; sp ?4 sp; nextpc (sp); sp ?2 sp; sr (sp) sp ?2 sp; format/offset (sp) (vbr + 0x80 +4*n) pc, where n is the trap number f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 3. instruction set summary 3-11 instruction summary 3.1.9 floating-point arithmetic instructions the ?ating-point instructions are organized into two categories: dyadic (requiring two operands) and monadic (requiring one operand). the dyadic ?ating-point instructions provide several arithmetic functions such as fadd and fsub. for these operations, the ?st operand can be located in memory, an integer data register, or a ?ating-point data register. the second operand is always located in a ?ating-point data register. the results of the operation are stored in the register speci?d as the second operand. all fpu arithmetic operations support all data formats. results are rounded to either single- or double-precision format. table 3-10 gives the general format for these dyadic instructions. table 3-11 lists the available operations. the monadic ?ating-point instructions provide several arithmetic functions requiring one input operand such as fabs. unlike the integer counterparts to these functions (e.g., neg), a source and a destination can be speci?d. the operation is performed on the source operand and the result is stored in the destination, which is always a ?ating-point data register. all data formats are supported. table 3-12 gives the general format for these monadic instructions. table 3-13 lists the available operations. table 3-9. cache maintenance operation format instruction operand syntax operand size operation cpushl ic,(ax) dc,(ax) bc,(ax) none if data is valid and modi?d, push cache line; invalidate line if programmed in cacr (synchronizes pipeline) intouch 1 1 supported starting with v4 ay none instruction fetch touch at (ay) (synchronizes pipeline) table 3-10. dyadic floating-point operation format instruction operand syntax operand size operation f y,fpx fpy,fpx b, w, l, s, d fpx source fpx table 3-11. dyadic floating-point operations instruction (f) operation fadd, fsadd, fdadd add fcmp compare fdiv, fsdiv, fddiv divide fmul, fsmul, fdmul multiply fsub, fssub, fdsub subtract f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-12 coldfire family programmers reference manual instruction set additions 3.2 instruction set additions this section contains tables which summarize the baseline instruction set as well as the instructions that are added through isa_b and the optional mac, emac, and floating-point units. table 3-14 shows the entire user instruction set in alphabetical order. table 3-15 shows the entire supervisor instruction set in alphabetical order. in these tables, the isa column has the following de?itions: isa_a: part of the original coldfire instruction set architecture isa_b: added with v4. isa_b also contains all isa_a instructions. mac: part of the original coldfire mac instruction set emac: additional mac instructions included in the emac fpu: floating-point unit instructions table 3-12. monadic floating-point operation format instruction operand syntax operand size operation f y,fpx fpy,fpx fpx b, w, l, s, d source fpx fpx fpx table 3-13. monadic floating-point operations instruction (f) operation fabs, fsabs, fdabs absolute value fint extract integer part fintrz extract integer part, rounded to zero fneg, fsneg, fdneg negate fsqrt, fssqrt, fdsqrt square root table 3-14. coldfire user instruction set summary instruction operand syntax operand size operation isa add adda dy,x y,dx y,ax l l l source + destination destination isa_a addi addq #,dx #,x l l immediate data + destination destination isa_a addx dy,dx l source + destination + ccr[x] destination isa_a and y,dx dy,x l l source & destination destination isa_a andi #, dx l immediate data & destination destination isa_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 3. instruction set summary 3-13 instruction set additions asl dy,dx #,dx l l ccr[x,c] (dx << dy) 0 ccr[x,c] (dx << #) 0 isa_a asr dy,dx #,dx l l msb (dx >> dy) ccr[x,c] msb (dx >> #) ccr[x,c isa_a bcc b, w, l 1 if condition true, then pc + d n pc isa_a bchg dy,x #,x b, l b, l ~ ( of destination) ccr[z] of destination isa_a bclr dy,x #,x b, l b, l ~ ( of destination) ccr[z]; 0 of destination isa_a bra b, w, l 1 pc + d n pc isa_a bset dy,x #,x b, l b, l ~ ( of destination) ccr[z]; 1 of destination isa_a bsr b, w, l 1 sp ?4 sp; nextpc (sp); pc + d n pc isa_a btst dy,x #,x b, l b, l ~ ( of destination) ccr[z] isa_a clr x b, w, l 0 destination isa_a cmp cmpa y,dx y,ax b, w, l 2 w, l 3 destination ?source ccr isa_a cmpi #,dx b, w, l 1 destination ?immediate data ccr isa_a divs/divu 4 y,dx w, l destination / source destination (signed or unsigned) isa_a eor dy,x l source ^ destination destination isa_a eori #,dx l immediate data ^ destination destination isa_a ext extb dx dx dx b w w l b l sign-extended destination destination isa_a fabs y,fpx fpy,fpx fpx b,w,l,s,d d d absolute value of source fpx absolute value of fpx fpx fpu fadd y,fpx fpy,fpx b,w,l,s,d d source + fpx fpx fpu fbcc w, l if condition true, then pc + d n pc fpu fcmp y,fpx fpy,fpx b,w,l,s,d d fpx - source fpu fdabs y,fpx fpy,fpx fpx b,w,l,s,d d d absolute value of source fpx; round destination to double absolute value of fpx fpx; round destination to double fpu fdadd y,fpx fpy,fpx b,w,l,s,d d source + fpx fpx; round destination to double fpu fddiv y,fpx fpy,fpx b,w,l,s,d d fpx / source fpx; round destination to double fpu table 3-14. coldfire user instruction set summary (continued) instruction operand syntax operand size operation isa f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-14 coldfire family programmers reference manual instruction set additions fdiv y,fpx fpy,fpx b,w,l,s,d d fpx / source fpx fpu fdmove fpy,fpx d source destination; round destination to double fpu fdmul y,fpx fpy,fpx b,w,l,s,d d source * fpx fpx; round destination to double fpu fdneg y,fpx fpy,fpx fpx b,w,l,s,d d d - (source) fpx; round destination to double - (fpx) fpx; round destination to double fpu fdsqrt y,fpx fpy,fpx fpx b,w,l,s,d d d square root of source fpx; round destination to double square root of fpx fpx; round destination to double fpu fdsub y,fpx fpy,fpx b,w,l,s,d d fpx - source fpx; round destination to double fpu fint y,fpx fpy,fpx fpx b,w,l,s,d d d integer part of source fpx integer part of fpx fpx fpu fintrz y,fpx fpy,fpx fpx b,w,l,s,d d d integer part of source fpx; round to zero integer part of fpx fpx; round to zero fpu fmove y,fpx fpy,x fpy,fpx fpcr,x y,fpcr b,w,l,s,d b,w,l,s,d d l l source destination fpcr can be any ?ating-point control register: fpcr, fpiar, fpsr fpu fmovem #list,x y,#list d listed registers destination source listed registers fpu fmul y,fpx fpy,fpx b,w,l,s,d d source * fpx fpx fpu fneg y,fpx fpy,fpx fpx b,w,l,s,d d d - (source) fpx - (fpx) fpx fpu fnop none none pc + 2 pc (fpu pipeline synchronized) fpu fsabs y,fpx fpy,fpx fpx b,w,l,s,d d d absolute value of source fpx; round destination to single absolute value of fpx fpx; round destination to single fpu fsadd y,fpx fpy,fpx b,w,l,s,d source + fpx fpx; round destination to single fpu fsdiv y,fpx fpy,fpx b,w,l,s,d d fpx / source fpx; round destination to single fpu fsmove y,fpx b,w,l,s,d source destination; round destination to single fpu fsmul y,fpx fpy,fpx b,w,l,s,d d source * fpx fpx; round destination to single fpu table 3-14. coldfire user instruction set summary (continued) instruction operand syntax operand size operation isa f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 3. instruction set summary 3-15 instruction set additions fsneg y,fpx fpy,fpx fpx b,w,l,s,d d d - (source) fpx; round destination to single - (fpx) fpx; round destination to single fpu fsqrt y,fpx fpy,fpx fpx b,w,l,s,d d d square root of source fpx square root of fpx fpx fpu fssqrt y,fpx fpy,fpx fpx b,w,l,s,d d d square root of source fpx; round destination to single square root of fpx fpx; round destination to single fpu fssub y,fpx fpy,fpx b,w,l,s,d d fpx - source fpx; round destination to single fpu fsub y,fpx fpy,fpx b,w,l,s,d d fpx - source fpx fpu ftst y b, w, l, s, d source operand tested fpcc fpu illegal none none sp ?4 sp; pc (sp) pc; sp ?2 sp; sr ( sp); sp ?2 sp; vector offset ( sp); (vbr + 0x10) pc isa_a jmp y none source address pc isa_a jsr y none sp ?4 sp; nextpc (sp); source pc isa_a lea y,ax l y ax isa_a link ay,# w sp ?4 sp; ay (sp); sp ay, sp + d n sp isa_a lsl dy,dx #,dx l l ccr[x,c] (dx << dy) 0 ccr[x,c] (dx << #) 0 isa_a lsr dy,dx #,dx l l 0 (dx >> dy) ccr[x,c] 0 (dx >> #) ccr[x,c] isa_a mac ry,rxsf,accx ry,rxsf,y,rw, accx w, l w, l accx + (ry * rx){<<|>>}sf accx accx + (ry * rx){<<|>>}sf accx; (y(&mask)) rw mac mov3q #,x l immediate data destination isa_b movclr accy,rx l accumulator destination, 0 accumulator emac move move from ccr move to ccr y,x maccr,dx y,maccr ccr,dx y,ccr b,w,l l l w w source destination where maccr can be any mac control register: accx, accext01, accext23, macsr, mask isa_a mac mac isa_a isa_a movea y,ax w,l l source destination isa_a movem #list,x y,#list l listed registers destination source listed registers isa_a moveq #,dx b l immediate data destination isa_a msac ry,rxsf,accx ry,rxsf,y,rw, accx w, l w, l accx - (ry * rx){<<|>>}sf accx accx - (ry * rx){<<|>>}sf accx; (y(&mask)) rw mac table 3-14. coldfire user instruction set summary (continued) instruction operand syntax operand size operation isa f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-16 coldfire family programmers reference manual instruction set additions muls/mulu y,dx w * w l l * l l source * destination destination (signed or unsigned) isa_a mvs y,dx b,w source with sign extension destination isa_b mvz y,dx b,w source with zero ?l destination isa_b neg dx l 0 ?destination destination isa_a negx dx l 0 ?destination ?ccr[x] destination isa_a nop none none pc + 2 pc (integer pipeline synchronized) isa_a not dx l ~ destination destination isa_a or y,dx dy,x l l source | destination destination isa_a ori #,dx l immediate data | destination destination isa_a pea y l sp ?4 sp; y (sp) isa_a pulse none none set pst = 0x4 isa_a rems/remu 4 y,dw:dx l destination / source remainder (signed or unsigned) isa_a rts none none (sp) pc; sp + 4 sp isa_a sats dx l if ccr[v] == 1; then if dx[31] == 0; then dx[31:0] = 0x80000000; else dx[31:0] = 0x7fffffff; else dx[31:0] is unchanged isa_b scc dx b if condition true, then 1s destination; else 0s destination isa_a sub suba y,dx dy,x y,ax l l l destination - source destination isa_a subi subq #,dx #,x l l destination ?immediate data destination isa_a subx dy,dx l destination ?source ?ccr[x] destination isa_a swap dx w msw of dx ? lsw of dx isa_a tas x b destination tested ccr; 1 bit 7 of destination isa_b tpf none # # none w l pc + 2 pc pc + 4 pc pc + 6 pc isa_a trap # none 1 s bit of sr; sp ?4 sp; nextpc (sp); sp ?2 sp; sr (sp) sp ?2 sp; format/offset (sp) (vbr + 0x80 +4*n) pc, where n is the trap number isa_a tst y b, w, l source operand tested ccr isa_a table 3-14. coldfire user instruction set summary (continued) instruction operand syntax operand size operation isa f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 3. instruction set summary 3-17 instruction set additions unlk ax none ax sp; (sp) ax; sp + 4 sp isa_a wddata y b, w, l source ddata port isa_a 1 longword supported starting with v4 2 byte and word supported starting with v4 3 word supported starting with v4 4 supported starting with the 5206e table 3-15. coldfire supervisor instruction set summary instruction operand syntax operand size operation isa cpushl ic,(ax) dc,(ax) bc,(ax) none if data is valid and modi?d, push cache line; invalidate line if programmed in cacr (synchronizes pipeline) isa_a frestore y none fpu state frame internal fpu state fpu fsave x none internal fpu state fpu state frame fpu halt none none halt processor core isa_a intouch ay none instruction fetch touch at (ay) isa_b move from sr sr,dx w sr destination isa_a move from usp 1 1 supported starting with v4 on devices containing an mmu. usp,dx l usp destination isa_b move to sr y,sr w source sr; dy or # source only isa_a move to usp 1 ay,usp l source usp isa_b movec ry,rc l ry rc isa_a rte none none 2 (sp) sr; 4 (sp) pc; sp + 8 sp adjust stack according to format isa_a stop # none immediate data sr; stop isa_a wdebug y l addressed debug wdmreg command executed isa_a table 3-14. coldfire user instruction set summary (continued) instruction operand syntax operand size operation isa f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-18 coldfire family programmers reference manual instruction set additions table 3-16 summarizes the additional instructions for the isa_b instruction set. table 3-16. coldfire isa_b additions summary instruction operand syntax operand size operation super/ user bcc b, w, l 1 1 longword supported starting with v4 if condition true, then pc + d n pc user bra b, w, l 1 pc + d n pc user bsr b, w, l 1 sp ?4 sp; pc (sp); pc + d n pc user cmp cmpa y,dx y,ax b, w, l 2 w, l 3 2 byte and word supported starting with v4 3 word supported starting with v4 destination ?source cc user cmpi #,dx b, w, l 1 destination ?immediate data cc user cpushl ic,(ax) dc,(ax) bc,(ax) none if data is valid and modi?d, push cache line; invalidate line if programmed in cacr super intouch ax none instruction fetch touch at (ax) super mov3q #,x l immediate data destination user move 4 4 additional addressing modes supported starting with v4 y,x b,w,l source destination user move from usp 5 5 supported starting with v4 on devices containing an mmu. usp,dx l usp destination super move to usp 5 ay,usp l source usp super movea y,ax w,l l source destination user mvs y,dx b,w source with sign extension destination user mvz y,dx b,w source with zero ?l destination user sats dx l if ccr[v] == 1; then if dx[31] == 0; then dx[31:0] = 0x80000000; else dx[31:0] = 0x7fffffff; else dx[31:0] is unchanged user tas x b destination tested condition codes; 1 bit 7 of destination user f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 3. instruction set summary 3-19 instruction set additions table 3-17 summarizes the instruction set supported by the original mac unit. table 3-18 summarizes the changes to the instruction set due to the enhancements in the emac unit. table 3-17. mac instruction set summary instruction operand syntax operand size operation super/ user mac ry,rxsf,acc ry,rxsf,y,rw, acc w, l w, l acc + (ry * rx){<<|>>}sf acc acc + (ry * rx){<<|>>}sf acc; (y(&mask)) rw user move maccr,dx y,maccr l l source destination where maccr can be any mac control register: acc, macsr, mask user msac ry,rxsf,acc ry,rxsf,y,rw, acc w, l w, l acc - (ry * rx){<<|>>}sf acc acc - (ry * rx){<<|>>}sf acc; (y(&mask)) rw user table 3-18. emac instruction set enhancements summary instruction operand syntax operand size operation super/ user mac 1 1 the emac has 4 accumulators ry,rxsf,accx ry,rxsf,y,rw, accx w, l w, l accx + (ry * rx){<<|>>}sf accx accx + (ry * rx){<<|>>}sf accx; (y(&mask)) rw user movclr accy,rx l accumulator destination, 0 accumulator user move maccr,dx y,maccr l l source destination where maccr can be any mac control register: accx, accext01, accext23, macsr, mask user msac ry,rxsf,accx ry,rxsf,y,rw, accx w, l w, l accx - (ry * rx){<<|>>}sf accx accx - (ry * rx){<<|>>}sf accx; (y(&mask)) rw user f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-20 coldfire family programmers reference manual instruction set additions table 3-19 summarizes the instruction set supported by the ?ating-point unit. table 3-19. floating-point instruction set summary instruction operand syntax operand size operation super/ user fabs y,fpx fpy,fpx fpx b,w,l,s,d d d absolute value of source fpx absolute value of fpx fpx user fadd y,fpx fpy,fpx b,w,l,s,d d source + fpx fpx user fbcc w, l if condition true, then pc + d n pc user fcmp y,fpx fpy,fpx b,w,l,s,d d fpx - source user fdabs y,fpx fpy,fpx fpx b,w,l,s,d d d absolute value of source fpx; round destination to double absolute value of fpx fpx; round destination to double user fdadd y,fpx fpy,fpx b,w,l,s,d d source + fpx fpx; round destination to double user fddiv y,fpx fpy,fpx b,w,l,s,d d fpx / source fpx; round destination to double user fdiv y,fpx fpy,fpx b,w,l,s,d d fpx / source fpx user fdmove fpy,fpx d source destination; round destination to double user fdmul y,fpx fpy,fpx b,w,l,s,d d source * fpx fpx; round destination to double user fdneg y,fpx fpy,fpx fpx b,w,l,s,d d d - (source) fpx; round destination to double - (fpx) fpx; round destination to double user fdsqrt y,fpx fpy,fpx fpx b,w,l,s,d d d square root of source fpx; round destination to double square root of fpx fpx; round destination to double user fdsub y,fpx fpy,fpx b,w,l,s,d d fpx - source fpx; round destination to double user fint y,fpx fpy,fpx fpx b,w,l,s,d d d integer part of source fpx integer part of fpx fpx user fintrz y,fpx fpy,fpx fpx b,w,l,s,d d d integer part of source fpx; round to zero integer part of fpx fpx; round to zero user fmove y,fpx fpy,x fpy,fpx fpcr,x y,fpcr b,w,l,s,d b,w,l,s,d d l l source destination fpcr can be any ?ating-point control register: fpcr, fpiar, fpsr user fmovem #list,x y,#list d listed registers destination source listed registers user f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 3. instruction set summary 3-21 instruction set additions fmul y,fpx fpy,fpx b,w,l,s,d d source * fpx fpx user fneg y,fpx fpy,fpx fpx b,w,l,s,d d d - (source) fpx - (fpx) fpx user fnop none none pc + 2 pc (fpu pipeline synchronized) user frestore y none fpu state frame internal fpu state super fsabs y,fpx fpy,fpx fpx b,w,l,s,d d d absolute value of source fpx; round destination to single absolute value of fpx fpx; round destination to single user fsadd y,fpx fpy,fpx b,w,l,s,d d source + fpx fpx; round destination to single user fsave x none internal fpu state fpu state frame super fsdiv y,fpx fpy,fpx b,w,l,s,d d fpx / source fpx; round destination to single user fsmove y,fpx b,w,l,s,d source destination; round destination to single user fsmul y,fpx fpy,fpx b,w,l,s,d d source * fpx fpx; round destination to single user fsneg y,fpx fpy,fpx fpx b,w,l,s,d d d - (source) fpx; round destination to single - (fpx) fpx; round destination to single user fsqrt y,fpx fpy,fpx fpx b,w,l,s,d d d square root of source fpx square root of fpx fpx user fssqrt y,fpx fpy,fpx fpx b,w,l,s,d d d square root of source fpx; round destination to single square root of fpx fpx; round destination to single user fssub y,fpx fpy,fpx b,w,l,s,d d fpx - source fpx; round destination to single user fsub y,fpx fpy,fpx b,w,l,s,d d fpx - source fpx user ftst y b, w, l, s, d source operand tested fpcc user table 3-19. floating-point instruction set summary instruction operand syntax operand size operation super/ user f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
3-22 coldfire family programmers reference manual instruction set additions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-1 chapter 4 integer user instructions this section describes the integer user instructions for the coldfire family. a detailed discussion of each instruction description is arranged in alphabetical order by instruction mnemonic. not all instructions are supported by all coldfire processors. divs/u and rems/u are supported starting with the 5206e. the original coldfire instruction set architecture, isa_a, is supported by v2 and v3 cores. the v4 core supports isa_b, which encompasses all of isa_a, extends the functionality of some isa_a instructions, and adds several new instructions. these extensions can be identi?d by a table which appears at the end of each instruction description where there are isa_b differences. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-2 coldfire family programmers reference manual add add add (all coldfire processors) operation: source + destination destination assembler syntax: add.l y,dx add.l dy,x attributes: size = longword description: adds the source operand to the destination operand using binary addition and stores the result in the destination location. the size of the operation may only be speci?d as a longword. the mode of the instruction indicates which operand is the source and which is the destination as well as the operand size. the dx mode is used when the destination is a data register; the destination x mode is invalid for a data register. in addition, adda is used when the destination is an address register. addi and addq are used when the source is immediate data. instruction fields: register ?ld?peci?s the data register. opmode ?ld: condition codes: x n z v c x set the same as the carry bit n set if the result is negative; cleared otherwise z set if the result is zero; cleared otherwise v set if an over?w is generated; cleared otherwise c set if an carry is generated; cleared otherwise ????? instruction format: 1514131211109876543210 1101 register opmode effective address mode register byte word longword operation 010 y + dx dx 110 dy + x x f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-3 add add add instruction fields (continued): effective address ?ld?etermines addressing mode for the source operand y, use addressing modes listed in the following table: for the destination operand x, use addressing modes listed in the following table: addressing mode mode register addressing mode mode register dy 000 reg. number:dy (xxx).w 111 000 ay 001 reg. number:ay (xxx).l 111 001 (ay) 010 reg. number:ay # 111 100 (ay) + 011 reg. number:ay ?(ay) 100 reg. number:ay (d 16 ,ay) 101 reg. number:ay (d 16 ,pc) 111 010 (d 8 ,ay,xi) 110 reg. number:ay (d 8 ,pc,xi) 111 011 addressing mode mode register addressing mode mode register dx (xxx).w 111 000 ax (xxx).l 111 001 (ax) 010 reg. number:ax # (ax) + 011 reg. number:ax ?(ax) 100 reg. number:ax (d 16 ,ax) 101 reg. number:ax (d 16 ,pc) (d 8 ,ax,xi) 110 reg. number:ax (d 8 ,pc,xi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-4 coldfire family programmers reference manual adda add address adda (all coldfire processors) operation: source + destination destination assembler syntax: adda.l y,ax attributes: size = longword description: operates similarly to add, but is used when the destination register is an address register rather than a data register. adds the source operand to the destination address register and stores the result in the address register. the size of the operation is speci?d as a longword. condition codes: not affected instruction fields: destination register ?ld?peci?s the destination register, ax. source effective address ?ld?speci?s the source operand; use addressing modes listed in the following table: instruction format: 1514131211109876543210 1101 destination register, ax 1 1 1 source effective address mode register addressing mode mode register addressing mode mode register dy 000 reg. number:dy (xxx).w 111 000 ay 001 reg. number:ay (xxx).l 111 001 (ay) 010 reg. number:ay # 111 100 (ay) + 011 reg. number:ay ?(ay) 100 reg. number:ay (d 16 ,ay) 101 reg. number:ay (d 16 ,pc) 111 010 (d 8 ,ay,xi) 110 reg. number:ay (d 8 ,pc,xi) 111 011 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-5 addi add immediate addi (all coldfire processors) operation: immediate data + destination destination assembler syntax : addi.l #,dx attributes: size = longword description: operates similarly to add, but is used when the source operand is immediate data. adds the immediate data to the destination operand and stores the result in the destination data register, dx. the size of the operation is speci?d as longword. the size of the immediate data is speci?d as a longword. note that the immediate data is contained in the two extension words, with the ?st extension word, bits [15:0], containing the upper word, and the second extension word, bits [15:0], containing the lower word. instruction fields: destination register ?ld - speci?s the destination data register, dx. condition codes: x n z v c x set the same as the carry bit n set if the result is negative; cleared otherwise z set if the result is zero; cleared otherwise v set if an over?w is generated; cleared otherwise c set if an carry is generated; cleared otherwise ????? instruction format: 1514131211109876543210 0000011010000 register, dx upper word of immediate data lower word of immediate data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-6 coldfire family programmers reference manual addq add quick addq (all coldfire processors) operation: immediate data + destination destination assembler syntax: addq.l #,x attributes: size = longword description: operates similarly to add, but is used when the source operand is immediate data ranging in value from 1 to 8. adds the immediate value to the operand at the destination location. the size of the operation is speci?d as longword. the immediate data is zero-?led to a longword before being added to the destination. when adding to address registers, the condition codes are not altered. instruction fields: data ?ld? bits of immediate data representing 8 values (0 ?7), with 1-7 representing values of 1-7 respectively and 0 representing a value of 8. destination effective address ?ld?peci?s the destination location, x; use only those alterable addressing modes listed in the following table: condition codes: x n z v c x set the same as the carry bit n set if the result is negative; cleared otherwise z set if the result is zero; cleared otherwise v set if an over?w is generated; cleared otherwise c set if an carry is generated; cleared otherwise ????? instruction format: 1514131211109876543210 0101 data 0 1 0 destination effective address mode register addressing mode mode register addressing mode mode register dx 000 reg. number:dx (xxx).w 111 000 ax 001 reg. number:ax (xxx).l 111 001 (ax) 010 reg. number:ax # (ax) + 011 reg. number:ax ?(ax) 100 reg. number:ax (d 16 ,ax) 101 reg. number:ax (d 16 ,pc) (d 8 ,ax,xi) 110 reg. number:ax (d 8 ,pc,xi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-7 addx add extended addx (all coldfire processors) operation: source + destination + ccr[x] destination assembler syntax: addx.l dy,dx attributes: size = longword description: adds the source operand and ccr[x] to the destination operand and stores the result in the destination location. the size of the operation is speci?d as a longword. normally ccr[z] is set explicitly via programming before the start of an addx operation to allow successful testing for zero results upon completion of multiple-precision operations. instruction fields: register dx ?ld?peci?s the destination data register, dx. register dy ?ld?peci?s the source data register, dy. condition codes: x n z v c x set the same as the carry bit n set if the result is negative; cleared otherwise z cleared if the result is non-zero; unchanged otherwise v set if an over?w is generated; cleared otherwise c set if an carry is generated; cleared otherwise ????? instruction format: 1514131211109876543210 1101 register, dx 110000 register, dy f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-8 coldfire family programmers reference manual and and logical and (all coldfire processors) operation: source & destination destination assembler syntax: and.l y,dx and.l dy,x attributes: size = longword description: performs an and operation of the source operand with the destination operand and stores the result in the destination location. the size of the operation is speci?d as a longword. address register contents may not be used as an operand. the dx mode is used when the destination is a data register; the destination mode is invalid for a data register. andi is used when the source is immediate data. instruction fields: register ?ld?peci?s any of the 8 data registers. opmode ?ld: condition codes: x n z v c x not affected n set if the msb of the result is set; cleared otherwise z set if the result is zero; cleared otherwise v always cleared c always cleared ?? 00 instruction format: 1514131211109876543210 1100 data register opmode effective address mode register byte word longword operation 010 y & dx dx 110 dy & x x f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-9 and and logical and instruction fields (continued): effective address ?ld?etermines addressing mode. for the source operand y, use addressing modes listed in the following table: for the destination operand x, use addressing modes listed in the following table: addressing mode mode register addressing mode mode register dy 000 reg. number:dy (xxx).w 111 000 ay (xxx).l 111 001 (ay) 010 reg. number:ay # 111 100 (ay) + 011 reg. number:ay ?(ay) 100 reg. number:ay (d 16 ,ay) 101 reg. number:ay (d 16 ,pc) 111 010 (d 8 ,ay,xi) 110 reg. number:ay (d 8 ,pc,xi) 111 011 addressing mode mode register addressing mode mode register dx (xxx).w 111 000 ax (xxx).l 111 001 (ax) 010 reg. number:ax # (ax) + 011 reg. number:ax ?(ax) 100 reg. number:ax (d 16 ,ax) 101 reg. number:ax (d 16 ,pc) (d 8 ,ax,xi) 110 reg. number:ax (d 8 ,pc,xi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-10 coldfire family programmers reference manual andi and immediate andi (all coldfire processors) operation: immediate data & destination destination assembler syntax: andi.l #,dx attributes: size = longword description: performs an and operation of the immediate data with the destination operand and stores the result in the destination data register, dx. the size of the operation is speci?d as a longword. the size of the immediate data is speci?d as a longword. note that the immediate data is contained in the two extension words, with the ?st extension word, bits [15:0], containing the upper word, and the second extension word, bits [15:0], containing the lower word. instruction fields: destination register ?ld - speci?s the destination data register, dx. condition codes: x n z v c x not affected n set if the msb of the result is set; cleared otherwise z set if the result is zero; cleared otherwise v always cleared c always cleared ?? 00 instruction format: 1514131211109876543210 0000001010000 destination register, dx upper word of immediate data lower word of immediate data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-11 asl, asr arithmetic shift asl, asr (all coldfire processors) operation: destination shifted by count destination assembler syntax: asd.l dy,dx asd.l #,dx where d is direction, l or r attributes: size = longword description: arithmetically shifts the bits of the destination operand, dx, in the direction (l or r) speci?d. the size of the operand is a longword. ccr[c] receives the last bit shifted out of the operand. the shift count is the number of bit positions to shift the destination register and may be speci?d in two different ways: 1. immediate?he shift count is speci?d in the instruction (shift range is 1 ?8). 2. register?he shift count is the value in the data register, dy, speci?d in the instruction (modulo 64). for asl, the operand is shifted left; the shift count equals the number of positions shifted. bits shifted out of the high-order bit go to both the carry and the extend bits; zeros are shifted into the low-order bit. the over?w bit is always zero. . . for asr, the operand is shifted right; the number of positions shifted equals the shift count. bits shifted out of the low-order bit go to both the carry and the extend bits; the sign bit (msb) is shifted into the high-order bit. ccr[c] ccr[c] ccr[x] 0 operand asl: ccr[c] ccr[c] ccr[x] msb operand asr: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-12 coldfire family programmers reference manual asl, asr arithmetic shift asl, asr note that ccr[v] is always cleared by asl and asr, unlike on the 68k family processors. instruction fields: count or register ?ld?peci?s shift count or register, dy, that contains the shift count: if i/r = 0, this ?ld contains the shift count; values 1 ?7 represent counts of 1 ? 7; a value of zero represents a count of 8. if i/r = 1, this ?ld speci?s the data register, dy, that contains the shift count (modulo 64). dr ?ld?peci?s the direction of the shift: 0 shift right 1 shift left i/r ?ld if i/r = 0, speci?s immediate shift count if i/r = 1, speci?s register shift count register ?ld?peci?s a data register, dx, to be shifted. condition codes: x n z v c x set according to the last bit shifted out of the operand; unaffected for a shift count of zero n set if the msb of the result is set; cleared otherwise z set if the result is zero; cleared otherwise v always cleared c set according to the last bit shifted out of the operand; cleared for a shift count of zero ??? 0 ? instruction format: 1514131211109876543210 1110 count or register, dy dr 1 0 i/r 0 0 register, dx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-13 bcc branch conditionally bcc (all coldfire processors; .l supported starting with v4) operation: if condition true then pc + d n pc assembler syntax: bcc.sz attributes: size = byte, word, longword (longword supported starting with v4) description: if the condition is true, execution continues at (pc) + displacement. branches can be forward, with a positive displacement, or backward, with a negative displacement. pc holds the address of the instruction word for the bcc instruction, plus two. the displacement is a twos-complement integer that represents the relative distance in bytes from the current pc to the destination pc. if the 8-bit displacement ?ld is 0, a 16-bit displacement (the word after the instruction) is used. if the 8-bit displacement ?ld is 0xff, the 32-bit displacement (longword after the instruction) is used. a branch to the next immediate instruction uses 16-bit displacement because the 8-bit displacement ?ld is 0x00. condition code speci?s one of the following tests, where c, n, v, and z stand for the condition code bits ccr[c], ccr[n], ccr[v] and ccr[z], respectively: condition codes: not affected code condition encod- ing test code condition encod- ing test cc(hs) carry clear 0100 c ls lower or same 0011 c | z cs(lo) carry set 0101 c lt less than 1101 n & v | n & v eq equal 0111 z mi minus 1011 n ge greater or equal 1100 n & v | n & v ne not equal 0110 z gt greater than 1110 n & v & z | n & v & z pl plus 1010 n hi high 0010 c & z vc over?w clear 1000 v le less or equal 1111 z | n & v | n & v vs over?w set 1001 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-14 coldfire family programmers reference manual bcc branch conditionally bcc instruction fields: condition ?ld?inary encoding for one of the conditions listed in the table. 8-bit displacement ?ld?wos complement integer specifying the number of bytes between the branch and the next instruction to be executed if the condition is met. 16-bit displacement ?ld?sed when the 8-bit displacement contains 0x00. 32-bit displacement ?ld?sed when the 8-bit displacement contains 0xff. instruction format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0110 condition 8-bit displacement 16-bit displacement if 8-bit displacement = 0x00 32-bit displacement if 8-bit displacement = 0xff bcc v2, v3 core (isa_a) v4 core (isa_b) opcode present yes yes operand sizes supported b,w b,w,l f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-15 bchg test a bit and change bchg (all coldfire processors) operation: ~ ( of destination) ccr[z]; ~ ( of destination) of destination assembler syntax: bchg.sz dy,x bchg.sz #,x attributes: size = byte, longword description: tests a bit in the destination operand and sets ccr[z] appropriately, then inverts the speci?d bit in the destination. when the destination is a data register, any of the 32 bits can be speci?d by the modulo 32-bit number. when the destination is a memory location, the operation is a byte operation and the bit number is modulo 8. in all cases, bit zero refers to the least signi?ant bit. the bit number for this operation may be speci?d in either of two ways: 1. immediate?it number is speci?d in a second word of the instruction. 2. register?peci?d data register contains the bit number. bit number static, speci?d as immediate data: condition codes: x n z v c x not affected n not affected z set if the bit tested is zero; cleared otherwise v not affected c not affected ? 1514131211109876543210 instruction format: 0000100001 destination effective address mode register 00000000 bit number f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-16 coldfire family programmers reference manual bchg test a bit and change bchg instruction fields: destination effective address ?ld?peci?s the destination location x; use only those data alterable addressing modes listed in the following table. note that longword is allowed only for the dx mode, all others are byte only. bit number ?ld?peci?s the bit number. bit number dynamic, speci?d in a register: instruction fields: data register ?ld?peci?s the data register, dy, that contains the bit number. destination effective address ?ld?peci?s the destination location, x; use only those data alterable addressing modes listed in the following table. note that longword is allowed only for the dx mode, all others are byte only. addressing mode mode register addressing mode mode register dx 000 reg. number:dx (xxx).w ax (xxx).l (ax) 010 reg. number:ax # (ax) + 011 reg. number:ax ?(ax) 100 reg. number:ax (d 16 ,ax) 101 reg. number:ax (d 16 ,pc) (d 8 ,ax,xi) (d 8 ,pc,xi) instruction format: 1514131211109876543210 0000 data register, dy 1 0 1 destination effective address mode register addressing mode mode register addressing mode mode register dx 000 reg. number:dx (xxx).w 111 000 ax (xxx).l 111 001 (ax) 010 reg. number:ax # (ax) + 011 reg. number:ax ?(ax) 100 reg. number:ax (d 16 ,ax) 101 reg. number:ax (d 16 ,pc) (d 8 ,ax,xi) 110 reg. number:ax (d 8 ,pc,xi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-17 bclr test a bit and clear bclr (all coldfire processors) operation: ~ ( of destination) ccr[z]; 0 of destination assembler syntax: bclr.sz dy,x bclr.sz #,x attributes: size = byte, longword description: tests a bit in the destination operand and sets ccr[z] appropriately, then clears the speci?d bit in the destination. when a data register is the destination, any of the 32 bits can be speci?d by a modulo 32-bit number. when a memory location is the destination, the operation is a byte operation and the bit number is modulo 8. in all cases, bit zero refers to the least signi?ant bit. the bit number for this operation can be speci?d in either of two ways: 1. immediate?it number is speci?d in a second word of the instruction. 2. register?peci?d data register contains the bit number. bit number static, speci?d as immediate data: condition codes: x n z v c x not affected n not affected z set if the bit tested is zero; cleared otherwise v not affected c not affected ? instruction format: 1514131211109876543210 0000100010 destination effective address mode register 00000000 bit number f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-18 coldfire family programmers reference manual bclr test a bit and clear bclr instruction fields: destination effective address ?ld?peci?s the destination location x; use only those data alterable addressing modes listed in the following table. note that longword is allowed only for the dx mode, all others are byte only. bit number ?ld?peci?s the bit number. bit number dynamic, speci?d in a register: instruction fields: data register ?ld?peci?s the data register, dy, that contains the bit number. destination effective address ?ld?peci?s the destination location, x; use only those data alterable addressing modes listed in the following table. note that longword is allowed only for the dx mode, all others are byte only. addressing mode mode register addressing mode mode register dx 000 reg. number:dx (xxx).w ax (xxx).l (ax) 010 reg. number:ax # (ax) + 011 reg. number:ax ?(ax) 100 reg. number:ax (d 16 ,ax) 101 reg. number:ax (d 16 ,pc) (d 8 ,ax,xi) (d 8 ,pc,xi) instruction format: 1514131211109876543210 0000 data register, dy 1 1 0 destination effective address mode register addressing mode mode register addressing mode mode register dx 000 reg. number:dx (xxx).w 111 000 ax (xxx).l 111 001 (ax) 010 reg. number:ax # (ax) + 011 reg. number:ax ?(ax) 100 reg. number:ax (d 16 ,ax) 101 reg. number:ax (d 16 ,pc) (d 8 ,ax,xi) 110 reg. number:ax (d 8 ,pc,xi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-19 bra branch always bra (all coldfire processors; .l supported starting with v4) operation: pc + d n pc assembler syntax: bra.sz attributes: size = byte, word, longword (longword supported starting with v4) description: program execution continues at location (pc) + displacement. branches can be forward with a positive displacement, or backward with a negative displacement. the pc contains the address of the instruction word of the bra instruction plus two. the displacement is a twos complement integer that represents the relative distance in bytes from the current pc to the destination pc. if the 8-bit displacement ?ld in the instruction word is 0, a 16-bit displacement (the word immediately following the instruction) is used. if the 8-bit displacement ?ld in the instruction word is all ones (0xff), the 32-bit displacement (longword immediately following the instruction) is used. a branch to the next immediate instruction automatically uses the 16-bit displacement format because the 8-bit displacement ?ld contains 0x00 (zero offset). condition codes: not affected instruction fields: 8-bit displacement ?ld?wos complement integer specifying the number of bytes between the branch instruction and the next instruction to be executed. 16-bit displacement ?ld?sed for displacement when the 8-bit displacement contains 0x00. 32-bit displacement ?ld?sed for displacement when the 8-bit displacement contains 0xff. instruction format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01100000 8-bit displacement 16-bit displacement if 8-bit displacement = 0x00 32-bit displacement if 8-bit displacement = 0xff bra v2, v3 core (isa_a) v4 core (isa_b) opcode present yes yes operand sizes supported b,w b,w,l f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-20 coldfire family programmers reference manual bset test a bit and set bset (all coldfire processors) operation: ~ ( of destination) ccr[z]; 1 of destination assembler syntax: bset.sz dy,x bset.sz #,x attributes: size = byte, longword description: tests a bit in the destination operand and sets ccr[z] appropriately, then sets the speci?d bit in the destination operand. when a data register is the destination, any of the 32 bits can be speci?d by a modulo 32-bit number. when a memory location is the destination, the operation is a byte operation and the bit number is modulo 8. in all cases, bit 0 refers to the least signi?ant bit. the bit number for this operation can be speci?d in either of two ways: 1. immediate?it number is speci?d in the second word of the instruction. 2. register?peci?d data register contains the bit number. bit number static, speci?d as immediate data: condition codes: x n z v c x not affected n not affected z set if the bit tested is zero; cleared otherwise v not affected c not affected ? 1514131211109876543210 instruction format: 0000100011 destination effective address mode register 00000000 bit number f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-21 bset test a bit and set bset instruction fields: destination effective address ?ld?peci?s the destination location x; use only those data alterable addressing modes listed in the following table. note that longword is allowed only for the dx mode; all others are byte only. bit number ?ld?peci?s the bit number. bit number dynamic, speci?d in a register: instruction fields: data register ?ld?peci?s the data register, dy, that contains the bit number. destination effective address ?ld?peci?s the destination location, x; use only those data alterable addressing modes listed in the following table. note that longword is allowed only for the dx mode, all others are byte only. addressing mode mode register addressing mode mode register dx 000 reg. number:dx (xxx).w ax (xxx).l (ax) 010 reg. number:ax # (ax) + 011 reg. number:ax ?(ax) 100 reg. number:ax (d 16 ,ax) 101 reg. number:ax (d 16 ,pc) (d 8 ,ax,xi) (d 8 ,pc,xi) instruction format: 1514131211109876543210 0000 data register, dy 1 1 1 destination effective address mode register addressing mode mode register addressing mode mode register dx 000 reg. number:dx (xxx).w 111 000 ax (xxx).l 111 001 (ax) 010 reg. number:ax # (ax) + 011 reg. number:ax ?(ax) 100 reg. number:ax (d 16 ,ax) 101 reg. number:ax (d 16 ,pc) (d 8 ,ax,xi) 110 reg. number:ax (d 8 ,pc,xi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-22 coldfire family programmers reference manual bsr branch to subroutine bsr (all coldfire processors; .l supported starting with v4) operation: sp ?4 sp; nextpc (sp); pc + d n pc assembler syntax: bsr.sz attributes: size = byte, word, longword (longword supported starting with v4) description: pushes the longword address of the instruction immediately following the bsr instruction onto the system stack. branches can be forward with a positive displacement, or backward with a negative displacement.the pc contains the address of the instruction word, plus two. program execution then continues at location (pc) + displacement. the displacement is a twos complement integer that represents the relative distance in bytes from the current pc to the destination pc. if the 8-bit displacement ?ld in the instruction word is 0, a 16-bit displacement (the word immediately following the instruction) is used. if the 8-bit displacement ?ld in the instruction word is all ones (0xff), the 32-bit displacement (longword immediately following the instruction) is used. a branch to the next immediate instruction automatically uses the 16-bit displacement format because the 8-bit displacement ?ld contains 0x00 (zero offset). condition codes: not affected instruction fields: 8-bit displacement ?ld?wos complement integer specifying the number of bytes between the branch instruction and the next instruction to be executed. 16-bit displacement ?ld?sed for displacement when the 8-bit displacement contains 0x00. 32-bit displacement ?ld?sed for displacement when the 8-bit displacement contains 0xff. instruction format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01100001 8-bit displacement 16-bit displacement if 8-bit displacement = 0x00 32-bit displacement if 8-bit displacement = 0xff bsr v2, v3 core (isa_a) v4 core (isa_b) opcode present yes yes operand sizes supported b,w b,w,l f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-23 btst test a bit btst (all coldfire processors) operation: ~ ( of destination) ccr[z] assembler syntax: btst.sz dy,x btst.sz #,x attributes: size = byte, longword description: tests a bit in the destination operand and sets ccr[z] appropriately. when a data register is the destination, any of the 32 bits can be speci?d by a modulo 32 bit number. when a memory location is the destination, the operation is a byte operation and the bit number is modulo 8. in all cases, bit 0 refers to the least signi?ant bit. the bit number for this operation can be speci?d in either of two ways: 1. immediate?it number is speci?d in a second word of the instruction. 2. register?peci?d data register contains the bit number. bit number static, speci?d as immediate data: instruction fields: destination effective address ?ld?peci?s the destination location x; use only those data alterable addressing modes listed in the following table. note that longword is allowed only for the dx mode, all others are byte only. condition codes: x n z v c x not affected n not affected z set if the bit tested is zero; cleared otherwise v not affected c not affected ? instruction format: 1514131211109876543210 0000100000 destination effective address mode register 00000000 bit number addressing mode mode register addressing mode mode register dx 000 reg. number:dx (xxx).w ax (xxx).l (ax) 010 reg. number:ax # (ax) + 011 reg. number:ax ?(ax) 100 reg. number:ax (d 16 ,ax) 101 reg. number:ax (d 16 ,pc) (d 8 ,ax,xi) (d 8 ,pc,xi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-24 coldfire family programmers reference manual btst test a bit btst instruction fields (continued): bit number ?ld?peci?s the bit number. bit number dynamic, speci?d in a register: instruction fields: data register ?ld?peci?s the data register, dy, that contains the bit number. destination effective address ?ld?peci?s the destination location, x; use only those data alterable addressing modes listed in the following table. note that longword is allowed only for the dx mode, all others are byte only. instruction format: 1514131211109876543210 0000 data register, dy 1 0 0 destination effective address mode register addressing mode mode register addressing mode mode register dx 000 reg. number:dx (xxx).w 111 000 ax (xxx).l 111 001 (ax) 010 reg. number:ax # 111 100 (ax) + 011 reg. number:ax ?(ax) 100 reg. number:ax (d 16 ,ax) 101 reg. number:ax (d 16 ,pc) 111 010 (d 8 ,ax,xi) 110 reg. number:ax (d 8 ,pc,xi) 111 011 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-25 clr clear an operand clr (all coldfire processors) operation: 0 destination assembler syntax: clr.sz x attributes: size = byte, word, longword description: clears the destination operand to 0. the size of the operation may be speci?d as byte, word, or longword. instruction fields: size ?ld?peci?s the size of the operation 00 byte operation 01 word operation 10 longword operation 11 reserved effective address ?ld?peci?s the destination location, x; use only those data alterable addressing modes listed in the following table: condition codes: x n z v c x not affected n always cleared z always set v always cleared c always cleared 0100 instruction format: 1514131211109876543210 01000010 size destination effective address mode register addressing mode mode register addressing mode mode register dx 000 reg. number:dx (xxx).w 111 000 ax (xxx).l 111 001 (ax) 010 reg. number:ax # (ax) + 011 reg. number:ax ?(ax) 100 reg. number:ax (d 16 ,ax) 101 reg. number:ax (d 16 ,pc) (d 8 ,ax,xi) 110 reg. number:ax (d 8 ,pc,xi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-26 coldfire family programmers reference manual cmp compare cmp (all coldfire processors; .b and .w supported starting with v4) operation: destination ?source cc assembler syntax: cmp.sz y,dx attributes: size = byte, word, longword (byte, word supported starting with v4) description: subtracts the source operand from the destination operand in the data register and sets condition codes according to the result; the data register is unchanged. the operation size may be a byte, word, or longword. cmpa is used when the destination is an address register; cmpi is used when the source is immediate data. instruction fields: register ?ld?peci?s the destination register, dx. opmode ?ld: source effective address ?ld?speci?s the source operand, y; use addressing modes listed in the following table: condition codes: x n z v c x not affected n set if the result is negative; cleared otherwise z set if the result is zero; cleared otherwise v set if an over?w occurs; cleared otherwise c set if a borrow occurs; cleared otherwise ???? instruction format: 1514131211109876543210 1011 destination register, dx opmode source effective address mode register byte word longword operation 000 001 010 dx - y addressing mode mode register addressing mode mode register dy 000 reg. number:dy (xxx).w 111 000 ay 001 reg. number:ay (xxx).l 111 001 (ay) 010 reg. number:ay # 111 100 (ay) + 011 reg. number:ay ?(ay) 100 reg. number:ay (d 16 ,ay) 101 reg. number:ay (d 16 ,pc) 111 010 (d 8 ,ay,xi) 110 reg. number:ay (d 8 ,pc,xi) 111 011 cmp v2, v3 core (isa_a) v4 core (isa_b) opcode present yes yes operand sizes supported l b,w,l f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-27 cmpa compare address cmpa (all coldfire processors; .w supported starting with v4) operation: destination ?source cc assembler syntax: cmpa.sz y, ax attributes: size = word, longword (word supported starting with v4) description: operates similarly to cmp, but is used when the destination register is an address register rather than a data register. the operation size can be word or longword. word-length source operands are sign-extended to 32 bits for comparison. instruction fields: address register ?ld?peci?s the destination register, ax. opmode ?ld: source effective address ?ld speci?s the source operand, y; use addressing modes in the following table: condition codes: x n z v c x not affected n set if the result is negative; cleared otherwise z set if the result is zero; cleared otherwise v set if an over?w occurs; cleared otherwise c set if a borrow occurs; cleared otherwise ???? instruction format: 1514131211109876543210 1011 address register, ax opmode source effective address mode register byte word longword operation 011 111 ax - y addressing mode mode register addressing mode mode register dy 000 reg. number:dy (xxx).w 111 000 ay 001 reg. number:ay (xxx).l 111 001 (ay) 010 reg. number:ay # 111 100 (ay) + 011 reg. number:ay ?(ay) 100 reg. number:ay (d 16 ,ay) 101 reg. number:ay (d 16 ,pc) 111 010 (d 8 ,ay,xi) 110 reg. number:ay (d 8 ,pc,xi) 111 011 cmpa v2, v3 core (isa_a) v4 core (isa_b) opcode present yes yes operand sizes supported l w,l f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-28 coldfire family programmers reference manual cmpi compare immediate cmpi (all coldfire processors; .b and .w supported starting with v4) operation: destination ?immediate data cc assembler syntax: cmpi.sz #,dx attributes: size = byte, word, longword (byte, word supported starting with v4) description: operates similarly to cmp, but is used when the source operand is immediate data. the operation size can be byte, word, or longword. the size of the immediate data matches the operation size. note that if size = byte, the immediate data is contained in bits [7:0] of the single extension word. if size = word, the immediate data is contained in the single extension word, bits [15:0]. if size = longword, the immediate data is contained in the two extension words, with the ?st extension word, bits [15:0], containing the upper word, and the second extension word, bits [15:0], containing the lower word. instruction fields: register ?ld?peci?s the destination register, dx. size ?ld?peci?s the size of the operation 00 byte operation 01 word operation 10 longword operation 11 reserved condition codes: x n z v c x not affected n set if the result is negative; cleared otherwise z set if the result is zero; cleared otherwise v set if an over?w occurs; cleared otherwise c set if a borrow occurs; cleared otherwise ???? instruction format: 1514131211109876543210 00001100 size 000 register, dx upper word of immediate data lower word of immediate data cmpi v2, v3 core (isa_a) v4 core (isa_b) opcode present yes yes operand sizes supported l b,w,l f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-29 divs signed divide divs (all coldfire processors starting with mcf5206e) operation: destination/source destination assembler syntax: divs.w y,dx 32-bit dx/16-bit y (16r:16q) in dx divs.l y,dx 32-bit dx/32-bit y 32q in dx where q indicates the quotient, and r indicates the remainder attributes: size = word, longword description: divide the signed destination operand by the signed source and store the signed result in the destination. for a word-sized operation, the destination operand is a longword and the source is a word; the 16-bit quotient is in the lower word and the 16-bit remainder is in the upper word of the destination. note that the sign of the remainder is the same as the sign of the dividend. for a longword-sized operation, the destination and source operands are both longwords; the 32-bit quotient is stored in the destination. to determine the remainder on a longword-sized operation, use the rems instruction. an attempt to divide by zero results in a divide-by-zero exception and no registers are affected. the resulting exception stack frame points to the offending divide opcode. if over?w is detected, the destination register is unaffected. an over?w occurs if the quotient is larger than a 16-bit (.w) or 32-bit (.l) signed integer. condition codes: x n z v c x not affected n cleared if over?w is detected; otherwise set if the quotient is negative, cleared if positive z cleared if over?w is detected; otherwise set if the quotient is zero, cleared if nonzero v set if an over?w occurs; cleared otherwise c always cleared ??? 0 instruction format: (word) 1514131211109876543210 1000 register, dx 1 1 1 source effective address mode register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4-30 coldfire family programmers reference manual divs signed divide divs instruction fields (word): register ?ld?peci?s the destination register, dx. source effective address ?ld speci?s the source operand, y; use addressing modes in the following table: instruction fields (longword): register ?ld?peci?s the destination register, dx. note that this ?ld appears twice in the instruction format. source effective address ?ld?speci?s the source operand, y; use addressing modes in the following table: addressing mode mode register addressing mode mode register dy 000 reg. number:dy (xxx).w 111 000 ay (xxx).l 111 001 (ay) 010 reg. number:ay # 111 100 (ay) + 011 reg. number:ay ?(ay) 100 reg. number:ay (d 16 ,ay) 101 reg. number:ay (d 16 ,pc) 111 010 (d 8 ,ay,xi) 110 reg. number:ay (d 8 ,pc,xi) 111 011 instruction format: (longword) 1514131211109876543210 0100110001 source effective address mode register 0 register, dx 100000000 register, dx addressing mode mode register addressing mode mode register dy 000 reg. number:dy (xxx).w ay (xxx).l (ay) 010 reg. number:ay # (ay) + 011 reg. number:ay ?(ay) 100 reg. number:ay (d 16 ,ay) 101 reg. number:ay (d 16 ,pc) (d 8 ,ay,xi) (d 8 ,pc,xi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
chapter 4. integer user instructions 4-31 divu unsigned divide divu (all coldfire processors starting with mcf5206e) operation: destination/source destination assembler syntax: divu.w y,dx 32-bit dx/16-bit y (16r:16q) in dx divu.l y,dx 32-bit dx/32-bit

▲Up To Search▲

Price & Availability of CFPRM

	To Download CFPRM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .