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frequency generator for integrated core logic with 133-mhz fsb W229B cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07223 rev. *a revised december 21, 2002 features ? maximized emi suppression using cypress?s spread spectrum technology low jitter and tightly controlled clock skew highly integrated device providing clocks required for cpu, core logic, and sdram two copies of cpu clock thirteen copies of sdram clock eight copies of pci clock one copy of synchronous apic clock three copies of 66-mhz outputs two copies of 48-mhz outputs one copy of selectable 24- or 48-mhz clock one copy of double strength 14.31818-mhz reference clock power-down control smbus interface for turning off unused clocks key specifications cpu, sdram outputs cycle-to-cycle jitter: ............. 250 ps apic, 48-mhz, 3v66, pci outputs cycle-to-cycle jitter:................................................... 500 ps cpu, 3v66 output skew: ........................................... 175 ps sdram, apic, 48-mhz output skew: ....................... 250 ps pci output skew: ....................................................... 500 ps cpu to sdram skew (@ 133 mhz) ....................... 0.5 ns cpu to sdram skew (@ 100 mhz) ................. 4.5 to 5.5 ns cpu to 3v66 skew (@ 66 mhz)........................ 7.0 to 8.0 ns 3v66 to pci skew (3v66 lead) .......................... 1.5 to 3.5 ns pci to apic skew..................................................... 0.5 ns table 1. frequency selections fs4 fs3 fs2 fs1 fs0 cpu sdram 3v66 pci apic ss 0 0 0 0 0 75.3 113.0 75.3 37.6 18.8 off 0 0 0 0 1 95.0 95.0 63.3 31.6 15.8 ? 0.6% 0 0 0 1 0 129.0 129.0 86.0 43.0 21.5 off 0 0 0 1 1 150.0 113.0 75.3 37.6 18.8 off 0 0 1 0 0 150.0 150.0 75.0 37.5 18.7 off 0 0 1 0 1 110.0 110.0 73.0 36.6 18.3 off 0 0 1 1 0 140.0 140.0 70.0 35.0 17.5 off 0 0 1 1 1 144.0 108.0 72.0 36.0 18.0 off 0 1 0 0 0 68.3 102.5 68.3 34.1 17.0 off 0 1 0 0 1 105.0 105.0 70.0 35.0 17.5 off 0 1 0 1 0 138.0 138.0 69.0 34.5 17.0 off 0 1 0 1 1 140.0 105.0 70.0 35.0 17.5 off 0 1 1 0 0 66.8 100.2 66.8 33.4 16.7 0.45% 0 1 1 0 1 100.2 100.2 66.8 33.4 16.7 0.45% 0 1 1 1 0 133.6 133.6 66.8 33.4 16.7 0.45% 0 1 1 1 1 133.6 100.2 66.8 33.4 16.7 0.45% 1 0 0 0 0 157.3 118.0 78.6 39.3 19.6 off 1 0 0 0 1 160.0 120.0 80.0 40.0 20.0 off 1 0 0 1 0 146.6 110.0 73.3 36.6 18.3 off 1 0 0 1 1 122.0 91.5 61.0 30.5 15.2 ? 0.6% 1 0 1 0 0 127.0 127.0 84.6 42.3 21.1 off 1 0 1 0 1 122.0 122.0 81.3 40.6 20.3 ? 0.6% 1 0 1 1 0 117.0 117.0 78.0 39.0 19.5 off 1 0 1 1 1 114.0 114.0 76.0 38.0 19.0 off 1 1 0 0 0 80.0 120.0 80.0 40.0 20.0 off 1 1 0 0 1 78.0 117.0 78.0 39.0 19.5 off 1 1 0 1 0 166.0 124.5 83.0 41.5 20.7 off 1 1 0 1 1 133.6 133.6 89.0 44.5 22.2 off 1 1 1 0 0 66.6 100.0 66.6 33.3 16.6 ? 0.6% 1 1 1 0 1 100.0 100.0 66.6 33.3 16.6 ? 0.6% 1 1 1 1 0 133.3 133.3 66.6 33.3 16.6 ? 0.6% 1 1 1 1 1 133.3 100.0 66.6 33.3 16.6 ? 0.6% block diagram pin configuration note: 1. internal pull-down or pull-up resistors present on inputs marked with * or ^, respectively. design should not rely solely on internal pull-up or pull-down resistor to set i/o pins high or low, respectively. [1] vddq3 vddq2 pci1/fs1* xtal pll ref freq pll 1 x2 x1 ref2x/fs3* pci3:7 48mhz_1/fs4* si0/24_48 mhz#* pll2 osc vddq3 i 2 c sdata logic sclk 3v66_0:2 cpu0:1 apic divider, delay, and phase control logic 3 vddq3 2 sdram0:12 13 pwrdwn# pci0/fs0* pci2/fs2* /2 (fs0:4*) 5 48mhz_0 gnd vddq3 ref2x/fs3* x1 x2 vddq3 3v66_0 3v66_1 3v66_2 gnd pci0/fs0* pci1/fs1* pci2/fs2* gnd pci3 pci4 vddq3 pci5 pci6 pci7 gnd 48mhz_0 48mhz_1/fs4* sio/24_48mhz#* W229B vddq2 apic gnd vddq2 cpu0 cpu1 gnd sdram0 sdram1 sdram2 vddq3 gnd sdram3 sdram4 sdram5 sdram6 vddq3 gnd sdram7 sdram8 sdram9 sdram10 vddq3 gnd 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 32 31 30 29 vddq3 sdata gnd vdd3 sdram11 sdram12 pwrdwn# ^ sclk
W229B document #: 38-07223 rev. *a page 2 of 17 i pin definitions pin name pin no. pin type pin description ref2x/fs3* 3 i/o reference clock with 2x drive/frequency select 3: 3.3v 14.318-mhz clock out- put. this pin also serves as the select strap to determine device operating frequency as described in table 1 . x1 4 i crystal input: this pin has dual functions. it can be used as an external 14.318- mhz crystal connection or as an external reference frequency input. x2 5 i crystal output: an input connection for an external 14.318-mhz crystal connec- tion. if using an external reference, this pin must be left unconnected. pci0/fs0* 11 i/o pci clock 0/frequency selection 0: 3.3v 33-mhz pci clock outputs. this pin also serves as the select strap to determine device operating frequency as described in table 1 . pci1/fs1* 12 i/o pci clock 1/frequency selection 1: 3.3v 33-mhz pci clock outputs. this pin also serves as the select strap to determine device operating frequency as described in table 1 . pci2/fs2* 13 i/o pci clock 2/frequency selection 2: 3.3v 33-mhz pci clock outputs. this pin also serves as the select strap to determine device operating frequency as described in table 1 . pci3:7 15, 16, 18, 19, 20 o pci clock 3 through 7: 3.3v 33-mhz pci clock outputs. pci0:7 can be individually turned off via smbus interface. 3v66_0:2 7, 8, 9 o 66-mhz clock output: 3.3v output clocks. the operating frequency is controlled by fs0:4 (see table 1 ). 48mhz_0 22 o 48-mhz clock output : 3.3v fixed 48-mhz, non-spread spectrum clock output. 48mhz_1/ fs4* 23 i/o 48-mhz clock output/frequency selection 4: 3.3v fixed 48-mhz, non-spread spectrum clock output. this pin also serves as the select strap to determine device operating frequency as described in table 1 . sio/ 24_48mhz#* 24 i/o clock output for super i/o: this is the input clock for a super i/o (sio) device. during power up, it also serves as a selection strap. if it is sampled high, the output frequency for sio is 24 mhz. if the input is sampled low, the output is 48 mhz. pwrdwn# 30 i power down control: lvttl-compatible input that places the device in power- down mode when held low. cpu0:1 52, 51 o cpu clock outputs: clock outputs for the host bus interface. output frequencies depending on the configuration of fs0:4. voltage swing is set by vddq2. sdram0:12, 49, 48, 47, 44, 43, 42, 41, 38, 37, 36, 35, 32, 31 o sdram clock outputs: 3.3v outputs for sdram and chipset. the operating fre- quency is controlled by fs0:4 (see table 1 ). apic 55 o synchronous apic clock outputs: clock outputs running synchronous with the pci clock outputs. voltage swing set by vddq2. sdata 26 i/o data pin for smbus circuitry. sclk 29 i clock pin for smbus circuitry. vddq3 2, 6, 17, 25, 34, 40, 46 p 3.3v power connection: power supply for sdram output buffers, pci output buff- ers, reference output buffers and 48-mhz output buffers. connect to 3.3v. vdd3 28 p 3.3v power connection: power supply for pll core. vddq2 53, 56 p 2.5v power connection: power supply for ioapic and cpu output buffers. con- nect to 2.5v or 3.3v. gnd 1, 10, 14, 21, 27, 33, 39, 45, 50, 54 g ground connections: connect all ground pins to the common system ground plane.
W229B document #: 38-07223 rev. *a page 3 of 17 overview the W229B is a highly integrated frequency timing generator, supplying all the required clock sources for an intel ? architec- ture platform using graphics integrated core logic. functional description i/o pin operation pin # 3, 11, 12, 13, 23, and 24 are dual-purpose l/o pins. upon power-up the pin acts as a logic input. an external 10-k ? strap- ping resistor should be used. figure 1 shows a suggested method for strapping resistor connections. after 2 ms, the pin becomes an output. assuming the power supply has stabilized by then, the specified output frequency is delivered on the pins. if the power supply has not yet reached full value, output frequency initially may be below tar- get but will increase to target once supply voltage has stabi- lized. in either case, a short output clock cycle may be pro- duced from the cpu clock outputs when the outputs are enabled. offsets among clock signal groups figure 2 , figure 3 , and figure 4 represent the phase relation- ship among the different groups of clock outputs from W229B when it is providing a 66-mhz cpu clock, a 100-mhz cpu clock, and a 133-mhz cpu clock, respectively. it should be noted that when cpu clock is operating at 100 mhz, cpu clock output is 180 degrees out of phase with sdram clock outputs. power down control W229B provides one pwrdwn# signal to place the device in low-power mode. in low-power mode, the plls are turned off and all clock outputs are driven low. power-on reset timer output three-state data latch hold qd W229B clock load output buffer 10 k ? output low output strapping resistor series termination resistor figure 1. input logic selection through resistor load option. cpu 66-mhz sdram 100-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz apic 0 ns figure 2. group offset waveforms (66-mhz cpu clock, 100-mhz sdram clock). 40 ns 30 ns 20 ns 10 ns sdram 100 period cpu 100 period hub-pc
W229B document #: 38-07223 rev. *a page 4 of 17 cpu 100-mhz sdram 100-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz apic 0 ns figure 3. group offset waveforms (100-mhz cpu clock/100-mhz sdram clock). 40 ns 30 ns 20 ns 10 ns sdram 100 period cpu 100 period hub-pc cpu 133-mhz sdram 100-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz dot 48-mhz cycle repeats apic 33-mhz figure 4. group offset waveforms (133-mhz cpu/100-mhz sdram). 0 ns 40 ns 30 ns 20 ns 10 ns
W229B document #: 38-07223 rev. *a page 5 of 17 notes: 2. once the pwrdwn# signal is sampled low for two consecutive rising edges of cpu, clocks of interest will be held low on the ne xt high-to-low transition. 3. pwrdwn# is an asynchronous input and metastable conditions could exist. this signal is synchronized inside W229B. 4. the shaded sections on the sdram, ref, and usb clocks indicate ? don ? t care ? states. 5. diagrams shown with respect to 100 mhz. similar operation when cpu is 66 mhz. cpu 100-mhz sdram 133-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz dot 48-mhz apic 33-mhz cycle repeat figure 5. group offset waveform (133-mhz cpu/133-mhz sdram). 0 ns 40 ns 30 ns 20 ns 10 ns 1 2 center 0ns 25ns 50ns 75ns vco internal cpu 100mhz 3v66 66mhz pci 33mhz apic 33mhz pwrdwn sdram 100mhz ref 14.318mhz usb 48mhz figure 6. W229B pwrdwn# timing diagram [2, 3, 4, 5] .
W229B document #: 38-07223 rev. *a page 6 of 17 table 2. W229B maximum allowed current W229B condition max 2.5v supply consumption max discrete cap loads, vddq2 = 2.625v all static inputs = vddq3 or vss max 3.3v supply consumption max discrete cap loads vddq3 = 3.465v all static inputs = vddq3 or vss full active 66 mhz fsel4:0 = 01100 (pwrdwn# =1) 70 ma 280 ma full active 100 mhz fsel4:0 = 11101 (pwrdwn# = 1) 100 ma 280 ma full active 133 mhz fsel4:0 = 11110 (pwrdwn# = 1) 50 ma 400 ma
W229B document #: 38-07223 rev. *a page 7 of 17 spread spectrum frequency timing generator the device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. by increasing the bandwidth of the fundamental and its harmonics, the am- plitudes of the radiated electromagnetic emissions are re- duced. this effect is depicted in figure 7 . as shown in figure 7 , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. the equation for the reduction is db = 6.5 + 9*log 10 (p) + 9*log 10 (f) where p is the percentage of deviation and f is the frequency in mhz where the reduction is measured. the output clock is modulated with a waveform depicted in figure 8 . this waveform, as discussed in ? spread spectrum clock generation for the reduction of radiated emissions ? by bush, fessler, and hardin, produces the maximum reduction in the amplitude of radiated electromagnetic emissions. the deviation selected for this chip is 0.45% or -0.6% of the se- lected frequency. figure 7 details the cypress spreading pat- tern. cypress does offer options with more spread and greater emi reduction. contact your local sales representative for de- tails on these devices. ssftg typical clock frequency span (mhz) center spread amplitude (db) spread spectrum enabled emi reduction spread spectrum non- frequency span (mhz) down spread amplitude (db) figure 7. clock harmonic with and without sscg modulation frequency domain representa- tion. max. min. 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% frequency figure 8. typical modulation profile.
W229B document #: 38-07223 rev. *a page 8 of 17 serial data interface the W229B features a two-pin, serial data interface that can be used to configure internal register settings that control par- ticular device functions. data protocol the clock driver serial protocol accepts only block writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. indexed bytes are not allowed. a block write begins with a slave address and a write condition. after the command code the core logic issues a byte count which describes how many more bytes will follow in the mes- sage. if the host had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. the byte count may not be 0. a block write command is allowed to transfer a maximum of 32 data bytes. the slave receiver ad- dress for W229B is 11010010. figure 9 shows an example of a block write. the command code and the byte count bytes are required as the first two bytes of any transfer. W229B expects a command code of 0000 0000. the byte count byte is the number of ad- ditional bytes required for the transfer, not counting the com- mand code and byte count bytes. additionally, the byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. table 3 shows an example of a possible byte count value. a transfer is considered valid after the acknowledge bit corre- sponding to the byte count is read by the controller. the com- mand code and byte count bytes are ignored by the W229B. however, these bytes must be included in the data write se- quence to maintain proper byte allocation. notes: 6. the acknowledgment bit is returned by the slave/receiver (W229B). 7. bytes 6 and 7 are not defined for W229B. 1 bit 7 bits 1 1 8 bits 1 start bit slave address r/w ack command code ack byte count = n ack data byte 1 ack data byte 2 ack ... data byte n ack stop 1 bit 8 bits 1 8 bits 1 8 bits 1 1 figure 9. an example of a block write [6] . table 3. example of possible byte count value byte count byte notes msb lsb 0000 0000 not allowed. must have at least one byte. 0000 0001 data for functional and frequency select register (currently byte 0 in spec) 0000 0010 reads first two bytes of data. (byte 0 then byte 1) 0000 0011 reads first three bytes (byte 0, 1, 2 in order) 0000 0100 reads first four bytes (byte 0, 1, 2, 3 in order) 0000 0101 reads first five bytes (byte 0, 1, 2, 3, 4 in order) [7] 0000 0110 reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order) [7] 0000 0111 reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order) 0010 0000 max. byte count supported = 32 table 4. serial data interface control functions summary control function description common application output disable any individual clock output(s) can be disabled. disabled outputs are actively held low. unused outputs are disabled to reduce emi and sys- tem power. examples are clock outputs to unused pci slots. (reserved) reserved function for future device revision or pro- duction device testing. no user application. register bit must be written as 0.
W229B document #: 38-07223 rev. *a page 9 of 17 W229B serial configuration map 1. the serial bits will be read by the clock driver in the following order: byte 0 - bits 7, 6, 5, 4, 3, 2, 1, 0 byte 1 - bits 7, 6, 5, 4, 3, 2, 1, 0 byte n - bits 7, 6, 5, 4, 3, 2, 1, 0 2. all unused register bits (reserved and n/a) should be writ- ten to a ? 0 ? level. 3. all register bits labeled ? initialize to 0" must be written to zero during initialization. failure to do so may result in high- er than normal operating current. the controller will read back the written value. note: 8. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. byte 0: control register (1 = enable, 0 = disable) [8] bit pin# name default pin function bit 7 - reserved 0 reserved bit 6 - reserved 0 reserved bit 5 - reserved 0 reserved bit 4 - reserved 0 reserved bit 3 - reserved 0 reserved bit 2 24 sio/24_48 mhz 1 (active/inactive) bit 1 22, 23 48 mhz 1 (active/inactive) bit 0 - reserved 0 reserved byte 1: control register (1 = enable, 0 = disable) [8] bit pin# name default pin description bit 7 38 sdram7 1 (active/inactive) bit 6 41 sdram6 1 (active/inactive) bit 5 42 sdram5 1 (active/inactive) bit 4 43 sdram4 1 (active/inactive) bit 3 44 sdram3 1 (active/inactive) bit 2 47 sdram2 1 (active/inactive) bit 1 48 sdram1 1 (active/inactive) bit 0 49 sdram0 1 (active/inactive) byte 2: control register (1 = enable, 0 = disable) [8] bit pin# name default pin description bit 7 20 pci7 1 (active/inactive) bit 6 19 pci6 1 (active/inactive) bit 5 18 pci5 1 (active/inactive) bit 4 16 pci4 1 (active/inactive) bit 3 15 pci3 1 (active/inactive) bit 2 13 pci2 1 (active/inactive) bit 1 12 pci1 1 (active/inactive) bit 0 11 pci0 1 (active/inactive)
W229B document #: 38-07223 rev. *a page 10 of 17 byte 3: reserved register (1 = enable, 0 = disable) bit pin# name default pin description bit 7 - reserved 0 reserved bit 6 - reserved 0 reserved bit 5 - reserved 0 reserved bit 4 - reserved 0 reserved bit 3 55 apic 1 (active/inactive) bit 2 - reserved 0 reserved bit 1 - reserved 0 reserved bit 0 - reserved 0 reserved byte 4: reserved register (1 = enable, 0 = disable) bit pin# name default pin function bit 7 - sel3 0 see table 5 bit 6 - sel2 0 see table 5 bit 5 - sel1 0 see table 5 bit 4 - sel0 0 see table 5 bit 3 - fs(0:4) override 0 0 = select operating frequency by fs(0:4) strapping 1 = select operating frequency by sel(0:4) bit settings bit 2 - sel4 0 see table 5 bit 1 - reserved 0 reserved bit 0 - test mode 0 0 = normal 1 = three-stated byte 5: reserved register (1 = enable, 0 = disable) bit pin# name default pin description bit 7 9 3v66_2 1 (active/inactive) bit 6 8 3v66_1 1 (active/inactive) bit 5 7 3v66_0 1 (active/inactive) bit 4 31 sdram12 1 (active/inactive) bit 3 32 sdram11 1 (active/inactive) bit 2 35 sdram10 1 (active/inactive) bit 1 36 sdram9 1 (active/inactive) bit 0 37 sdram8 1 (active/inactive) byte 6: reserved register (1 = enable, 0 = disable) bit pin# name default pin description bit 7 - reserved 0 reserved bit 6 - reserved 0 reserved bit 5 - reserved 0 reserved bit 4 - reserved 0 reserved bit 3 - reserved 0 reserved bit 2 - reserved 0 reserved bit 1 - reserved 0 reserved
W229B document #: 38-07223 rev. *a page 11 of 17 bit 0 - reserved 0 reserved table 5. additional frequency selections through serial data interface data bytes input conditions output frequency data byte 4, bit 3 = 1 cpu sdram 3v66 pci apic spread spectrum bit 2 sel_4 bit 7 sel_3 bit 6 sel_2 bit 5 sel_1 bit 4 sel_0 0 0 0 0 0 75.3 113.0 75.3 37.6 18.8 off 0 0 0 0 1 95.0 95.0 63.3 31.6 15.8 ? 0.6% 0 0 0 1 0 129.0 129.0 86.0 43.0 21.5 off 0 0 0 1 1 150.0 113.0 75.3 37.6 18.8 off 0 0 1 0 0 150.0 150.0 75.0 37.5 18.7 off 0 0 1 0 1 110.0 110.0 73.0 36.6 18.3 off 0 0 1 1 0 140.0 140.0 70.0 35.0 17.5 off 0 0 1 1 1 144.0 108.0 72.0 36.0 18.0 off 0 1 0 0 0 68.3 102.5 68.3 34.1 17.0 off 0 1 0 0 1 105.0 105.0 70.0 35.0 17.5 off 0 1 0 1 0 138.0 138.0 69.0 34.5 17.0 off 0 1 0 1 1 140.0 105.0 70.0 35.0 17.5 off 0 1 1 0 0 66.8 100.2 66.8 33.4 16.7 0.45% 0 1 1 0 1 100.2 100.2 66.8 33.4 16.7 0.45% 0 1 1 1 0 133.6 133.6 66.8 33.4 16.7 0.45% 0 1 1 1 1 133.6 100.2 66.8 33.4 16.7 0.45% 1 0 0 0 0 157.3 118.0 78.6 39.3 19.6 off 1 0 0 0 1 160.0 120.0 80.0 40.0 20.0 off 1 0 0 1 0 146.6 110.0 73.3 36.6 18.3 off 1 0 0 1 1 122.0 91.5 61.0 30.5 15.2 ? 0.6% 1 0 1 0 0 127.0 127.0 84.6 42.3 21.1 off 1 0 1 0 1 122.0 122.0 81.3 40.6 20.3 ? 0.6% 1 0 1 1 0 117.0 117.0 78.0 39.0 19.5 off 1 0 1 1 1 114.0 114.0 76.0 38.0 19.0 off 1 1 0 0 0 80.0 120.0 80.0 40.0 20.0 off 1 1 0 0 1 78.0 117.0 78.0 39.0 19.5 off 1 1 0 1 0 166.0 124.5 83.0 41.5 20.7 off 1 1 0 1 1 133.6 133.6 89.0 44.5 22.2 off 1 1 1 0 0 66.6 100.0 66.6 33.3 16.6 ? 0.6% 1 1 1 0 1 100.0 100.0 66.6 33.3 16.6 ? 0.6% 1 1 1 1 0 133.3 133.3 66.6 33.3 16.6 ? 0.6% 1 1 1 1 1 133.3 100.0 66.6 33.3 16.6 ? 0.6% byte 6: reserved register (1 = enable, 0 = disable) bit pin# name default pin description
W229B document #: 38-07223 rev. *a page 12 of 17 dc electrical characteristics [9] dc parameters must be sustainable under steady state (dc) conditions. note: 9. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. 10. input leakage current does not include inputs with pull-up or pull-down resistors. absolute maximum dc power supply parameter description min. max. unit v ddq3 3.3v core supply voltage ? 0.5 4.6 v v ddq2 2.5v i/o supply voltage ? 0.5 3.6 v t s storage temperature ? 65 150 c absolute maximum dc i/o parameter description min. max. unit v i/o3 3.3v core supply voltage ? 0.5 4.6 v v i/o3 2.5v i/o supply voltage ? 0.5 3.6 v esd prot. input esd protection 2000 v dc operating requirements parameter description condition min. max. unit v dd3 3.3v core supply voltage 3.3v5% 3.135 3.465 v v ddq3 3.3v i/o supply voltage 3.3v5% 3.135 3.465 v v ddq2 2.5v i/o supply voltage 2.5v5% 2.375 2.625 v v dd3 = 3.3v5% v ih3 3.3v input high voltage v dd3 2.0 v dd + 0.3 v v il3 3.3v input low voltage v ss ? 0.3 0.8 v i il input leakage current [9] 0 W229B document #: 38-07223 rev. *a page 13 of 17 ac electrical characteristics [9] t a = 0 c to +70 c, v ddq3 = 3.3v5%, v ddq2 = 2.5v5% f xtl = 14.31818 mhz notes: 11. period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5v clocks and at 1.5v for 3.3v clocks. 12. t high is measured at 2.0v for 2.5v outputs, 2.4v for 3.3v outputs. 13. t low is measured at 0.4v for all outputs. 14. the time specified is measured from when v ddq3 achieves its nominal operating level (typical condition v ddq3 = 3.3v) until the frequency output is stable and operating within specification. 15. t rise and t fall are measured as a transition through the threshold region v ol = 0.4v and v oh = 2.0v (1 ma) jedec specification for 2.5v outputs, and v ol = 0.4v and v oh = 2.4v for 3.3v outputs. parameter description 66.6-mhz host 100-mhz host 133-mhz host unit notes min. max. min. max. min. max. t period host/cpuclk period 15.0 15.5 10.0 10.5 7.5 8.0 ns 11 t high host/cpuclk high time 5.2 n/a 3.0 n/a 1.87 n/a ns 14 t low host/cpuclk low time 5.0 n/a 2.8 n/a 1.67 n/a ns t rise host/cpuclk rise time 0.4 1.6 0.4 1.6 0.4 1.6 ns 15 t fall host/cpuclk fall time 0.4 1.6 0.4 1.6 0.4 1.6 ns 15 t period sdram clk period 10.0 10.5 10.0 10.5 10.0 10.5 ns 11 t high sdram clk high time 3.0 n/a 3.0 n/a 3.0 n/a ns 14 t low sdram clk low time 2.8 n/a 2.8 n/a 2.8 n/a ns t rise sdram clk rise time 0.4 1.6 0.4 1.6 0.4 1.6 ns 15 t fall sdram clk fall time 0.4 1.6 0.4 1.6 0.4 1.6 ns 15 t period apic 33-mhz clk period 30.0 n/a 30.0 n/a 30.0 n/a ns 11 t high apic 33-mhz clk high time 12.0 n/a 12.0 n/a 12.0 n/a ns 14 t low apic 33-mhz clk low time 12.0 n/a 12.0 n/a 12.0 n/a ns t rise apic clk rise time 0.4 1.6 0.4 1.6 0.4 1.6 ns 15 t fall apic clk fall time 0.4 1.6 0.4 1.6 0.4 1.6 ns 15 t period 3v66 clk period 15.0 16.0 15.0 16.0 15.0 16.0 ns 11, 13 t high 3v66 clk high time 5.25 n/a 5.25 n/a 5.25 n/a ns 14 t low 3v66 clk low time 5.05 n/a 5.05 n/a 5.05 n/a ns t rise 3v66 clk rise time 0.5 2.0 0.5 2.0 0.5 2.0 ns 15 t fall 3v66 clk fall time 0.5 2.0 0.5 2.0 0.5 2.0 ns 15 t period pci clk period 30.0 n/a 30.0 n/a 30.0 n/a ns 11, 12 t high pci clk high time 12.0 n/a 12.0 n/a 12.0 n/a ns 14 t low pci clk low time 12.0 n/a 12.0 n/a 12.0 n/a ns t rise pci clk rise time 0.5 2.0 0.5 2.0 0.5 2.0 ns 15 t fall pci clk fall time 0.5 2.0 0.5 2.0 0.5 2.0 ns 15 tp zl , tp zh output enable delay (all outputs) 1.0 10.0 1.0 10.0 1.0 10.0 ns tp lz , tp zh output disable delay (all outputs) 1.0 10.0 1.0 10.0 1.0 10.0 ns t stable all clock stabilization from power-up 33 3ms
W229B document #: 38-07223 rev. *a page 14 of 17 intel is a registered trademark of intel corporation. group skew and jitter limits output group pin-pin skew max. cycle-cycle jitter duty cycle nom v dd skew, jitter measure point cpu 175 ps 250 ps 45/55 2.5v 1.25v sdram 250 ps 250 ps 45/55 3.3v 1.5v apic 250 ps 500 ps 45/55 2.5v 1.25v 48mhz 250 ps 500 ps 45/55 3.3v 1.5v 3v66 175 ps 500 ps 45/55 3.3v 1.5v pci 500 ps 500 ps 45/55 3.3v 1.5v ref n/a 1000 ps 45/55 3.3v 1.5v clock output wave 2.5v clocking 3.3v clocking test point test load t period duty cycle t high 2.0 1.25 0.4 t low t rise t fall t low t rise t fall t period duty cycle t high 2.4 1.5 0.4 output buffer interface interface figure 10. output buffer. ordering information ordering code package name package type W229B h 56-pin ssop (300 mils)
W229B document #: 38-07223 rev. *a page 15 of 17 layout example 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 6 7 13 19 20 24 g = via to gnd plane layer v =via to respective supply plane layer note: 1) each supply plane or strip should have a ferrite bead and capacitors. g +2.5v supply 1 2 3 4 5 8 9 11 12 14 15 16 17 22 23 21 25 26 27 28 40 39 18 41 10 31 30 29 36 35 34 33 32 37 38 c7 c8 fb +3.3v supply c4 c1 & c3 = 10 ? 22 f c2 & c4 = 0.005 f 10 f fb c1 c2 fb = vishay dale ilb1206 - 300 (300 ? @ 100 mhz) or tdk acb2012l120 0.005 f g g g g vddq2 vddq3 c3 c5 = 10 f c6 = 0.1 f g 10 ? vddq3 c5 c6 g v g v g v g v g v g v g v g v g v W229B core vddq3 g g g g g g g g g g g g g g g g g g g 10 f 0.005 f *note 3 r1 *note 4 2) bypass capacitors are 0.1 f ceramic unless otherwise stated. 3) c7 and c8 can be used to correct the crystal oscillaotr frequency if the crystal used is specified for more then 4) if an on-board video controler uses 48 mhz then use r1 and c5 to reduce long-term jitter on the 48 mhz clock. g vddq3, as shown, or to +3.3v supply. r1 can connect t o 18 pf cload.
W229B document #: 38-07223 rev. *a page 16 of 17 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 56-pin shrink small outline package (ssop, 300 mils)
W229B document #: 38-07223 rev. *a page 17 of 17 document title: W229B frequency generator for integrated core logic with 133-mhz fsb document number: 38-07223 rev. ecn no. issue date orig. of change description of change ** 110488 10/21/01 szv change from spec number: 38-00889 to 38-07223 *a 122840 12/21/02 rbi added power up requirements to recommended operating conditions

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