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functional block diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 lrck bck s0 dv dd 64/32 dgnd nc av ss 1 av ss 2 agnd apd vinr vinr+ refr wck data clock s1 dgnd dv dd av ss 1 av dd 2 av dd 1 agnd vinl vinl+ refl voltage reference serial output interface single-stage, 4k-tap fir decimation filter d a c digital chip analog chip reset single-stage, 4k-tap fir decimation filter d a c d a c d a c rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a high performance 16-/18-bit sd stereo adcs ad1878/AD1879* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features fully differential dual channel analog inputs 103 db signal-to-noise (AD1879 typ) C98 db thd+n (AD1879 typ) 0.001 db passband ripple and 115 db stopband attenuation fifth-order, 64 times oversampling sd modulator single stage, linear phase decimator 256 3 f s input clock applications digital tape recorders professional, dcc, and dat a/v digital amplifiers cd-r sound reinforcement product overview the AD1879 is a two-channel, 18-bit oversampling adc based on ?d technology and intended primarily for digital audio appli- cations. the ad1878 is identical to the 18-bit AD1879 except that it outputs 16-bit data words. statements in this data sheet should be read as applying to both parts unless otherwise noted. each input channel of these adcs is fully differential. each data conversion channel consists of a fifth order one-bit noise shaping modulator and a digital decimation filter. an on-chip voltage reference provides a voltage source to both channels sta- ble over temperature and time. digital output data from both channels is time-multiplexed to a single, flexible serial interface. the ad1878/AD1879 accepts a 256 f s input master clock. input signals are sampled at 64 f s on switched-capacitors, eliminating external sample-and-hold amplifiers and minimizing the requirements for antialias filtering at the input. with simpli- fied antialiasing, linear phase can be preserved across the passband. the ad1878/AD1879s proprietary fifth-order differential switch ed-capacitor modulator architecture shapes the one-bit comparators quantization noise out of the audio passband. the high order of the modulator randomizes the modulator output, reducing idle tones in the ad1878/AD1879 to very low levels. the ad1878/AD1879s differential architecture provides in- creased dynamic range and excellent common-mode rejection characteristics. because its modulator is single-bit, ad1878/ AD1879 is inherently monotonic and has no mechanism for producing differential linearity errors. the digital decimation filters are single-stage, 4095-tap finite impulse response filters for filtering the modulators high fre- quency quantization noise and reducing the 64 f s single-bit output data rate to a f s word rate. they provide linear * protected by u.s. patent numbers 5055843, 5126653, and others pending. phase and a narrow transition band that permits the digitization of 20 khz signals while preventing aliasing into the passband even when using a 44.1 khz sampling frequency. passband ripple is less the 0.001 db, and stopband attenuation exceeds 115 db. the f lexible serial output port produces data in twos-complement, msb-first format. input and output signals are to ttl and cmos-compatible logic levels. the port is configured by pin selections. the ad1878/AD1879 can operate in either master or slave mode. each 16-/18-bit output word of a stereo pair can be formatted within a 32-bit field as either right-justified, i 2 s- compatible, or at user-selected positions. the output can also be truncated to 16-bits by formatting into a 16-bit field. the ad1878/AD1879 consists of two integrated circuits in a single ceramic 28-pin dip package. the modulators and refer- ence are fabricated in a bicmos process; the decimator and output port, in a 1.0 m m cmos process. separating these func- tions reduces digital crosstalk to the analog circuitry. analog and digital supply connections are separated to further isolate the analog circuitry from the digital supplies. the ad1878/AD1879 operates from 5 v power supplies over the temperature range of C25 c to +70 c.
rev. 0 ad1878/AD1879Cspecifications C2C test conditions unless otherwise noted supply voltages 5v ambient temperature 25 c input clock (f clock ) 12.288 mhz input signal 974 hz C0.5 db full scale all minimums and maximums tested except as noted. analog performance min typ max units AD1879 resolution 18 bits ad1878 resolution 16 bits clock input frequency range clock input (f clock ) 0.01 12.288 14.286 mhz modulator sample rate (f clock /4) 0.0025 3.072 3.5715 mhz output word rate (f s = f clock /256) 0.039 48 55.8 khz AD1879 dynamic range (0 khz to 20 khz, C60 db input) stereo mode (no a-weight filter) 100 103 db mono mode 1 (no a-weight filter) 106 db stereo mode (with a-weight filter) 105 db AD1879 trimmed 2 signal to (noise + distortion) full scale 93 98 db C20 db 83 db AD1879 untrimmed 3 signal to (noise + distortion) full scale 91 96 db C20 db 83 db AD1879 trimmed 2 signal to total harmonic distortion full scale 98 db C20 db 100 db ad1878 dynamic range (0 khz to 20 khz, C60 db 1.0936 khz input dithered with a C10 db 21.873 khz sine wave) stereo mode (no a-weight filter) 95 97 db ad1878 trimmed 2 signal to (noise + distortion) full scale 93 95 db C20 db 77 db ad1878 untrimmed 3 signal to (noise + distortion) full scale 91 94 db C20 db 77 db ad1878 trimmed 2 signal to total harmonic distortion full scale 98 db C20 db 100 db analog inputs differential input range 4 5.985 6.3 6.615 v input impedance at each input pin 7.0 k w dc accuracy gain error 1 5% interchannel gain mismatch 0.05 0.15 db gain drift 150 ppm/ c AD1879 midscale offset error 200 750 18-bit lsbs ad1878 midscale offset error 50 200 16-bit lsbs midscale drift 13 ppm/ c voltage reference 2.4 2.86 3.2 v crosstalk (eiaj method) 100 105 db interchannel phase deviation 0.001 degrees notes 1 both channels connected together for mono operations as described below in how to extend snr. 2 differential gain imbalance manually trimmed to eliminate second harmonic. see applications issues below. 3 test performed without part-to-part trimming. 4 the differential input range is twice the range seen at each input pin. the input range corresponds to the full-scale digital output range. specifications subject to change without notice.
ad1878/AD1879 digital inputs min max units v ih v v il 0.8 v i ih @ v ih = 5 v 10 m a i il @ v il = 0 v 10 m a v oh @ i oh = 360 m a 4.0 v v ol @ i ol = 1.6 ma 0.5 v digital timing min typ max units clock period (t clock = 1/f clock ) 0.07 100 m s lo pulse width 35 ns hi pulse width 35 ns bck pulse width 2 clock periods 64-bit frame l r ck pulse width 32 bck periods 32-bit frame l r ck pulse width 16 bck periods wck pulse width 1 bck periods t rset reset setup to clock rising 5 ns t rhld reset hold from clock rising 20 ns t rsls reset pulse width 4 10 m s clock periods t wset wck to clock rising 5 ns t whld wck hold from clock rising 20 ns t dlyck clock to bck/wck/l r ck delay 65 ns (master mode) t set bck/l r ck to clock falling 5 ns (slave mode) t hld bck/l r ck hold from clock falling 20 ns (slave mode) t dlyd, msb clock falling to msb data delay 65 ns t dlyd clock rising to data delay, except msb 70 ns power min typ max units supplies voltage, dv dd /av dd 1/av dd 2 4.75 5 5.25 v voltage, av ss 1/av ss 2 C5.25 C5 C4.75 v current, av dd 1/av ss 17392ma current, av dd 1/av ss 1power down 13 23 ma current, av dd 2/av ss 2 8 10 ma current, dv dd 64 70 ma dissipation operation 1,130 1,370 mw operationanalog supplies 810 1,020 mw operationdigital supplies 320 350 mw power down (all supplies) 530 680 mw power supply rejection 1 khz 300 mv p-p signal at analog supply pins 102 dbfs passbandany 300 mv p-p signal 92 dbfs stopbandany 300 mv p-p signal 105 dbfs temperature range min typ max units specifications guaranteed +25 c functionality guaranteed C25 +70 c storage C60 +100 c rev. 0 C3C
ad1878/AD1879 rev. 0 C4C absolute maximum ratings min typ max units dv dd to dgnd and av dd 1/av dd 2 to agnd 0 6 v av ss 1/av ss 2 to agnd C6 0 v av ss 2 to av ss 1 C0.3 v digital inputs to dgnd C0.3 dv dd + 0.3 v analog inputs av ss 1 C 0.3 av dd 1 + 0.3 v agnd to dgnd C0.3 0.3 v reference voltage indefinite short circuit to ground soldering +300 c 10 sec digital filter characteristics min typ max units decimation factor 64 passband ripple 0.001 db stopband 1 attenuation 115 db 48 khz f s (12.288 mhz clock) passband 0 21.7 khz stopband 26.2 3,045 khz 44.1 khz f s (11.2896 mhz clock) passband 0 20.0 khz stopband 24.1 2,798 khz 32 khz f s (8.192 mhz clock) passband 0 14.5 khz stopband 17.5 2,030 khz other f s passband 0 0.4535 f s stopband 0.5458 63.4542 f s group delay ([4096/2]/[64 f s ]) 32/f s group delay variation 0 m s note 1 stopband repeats itself at multiples of 64 f s, where f s is the output word rate. thus the digital filter will attenuate to 115 db across the frequency spectrum except for a range 0.5458 f s wide at multiples of 64 f s . specifications subject to change without notice. ordering guide package package model temperature description option ad1878jd C25 c to +70 c ceramic dip d-28 AD1879jd C25 c to +70 c ceramic dip d-28 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1878/AD1879 features proprietary esd protection circuitry, permanent dam- age may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad1878/AD1879 rev. 0 C5C definitions dynamic range the ratio of a full-scale output signal to the integrated output noise in the passband (0 khz to 20 khz), expressed in decibels (db). dynamic range is measured with a C60 db input signal and is equal to (s/[thd+n]) + 60 db. signal to (noise + distortion) the ratio of the root-mean-square (rms) value of the fundamen- tal input signal to the rms sum of all spectral components in the passband, expressed in decibels (db). signal to total harmonic distortion (thd) the ratio of the rms sum of all harmonically related spectral components in the passband to the fundamental input signal, expressed either as a percentage (%) or in decibels (db). passband the region of the frequency spectrum unaffected by the attenu- ation of the digital decimators filter. passband ripple the peak-to-peak variation in amplitude response from equal amplitude input signal frequencies within the passband, ex- pressed in decibels. stopband the region of the frequency spectrum attenuated by the digi- tal decimators filter to the degree specified by stopband attenuation. gain error with a near full-scale input, the ratio of actual output to ex- pected output, expressed as a percentage. interchannel gain mismatch with near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels. gain drift change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per c. midscale offset error output response to a midscale input (i.e., zero volts dc), ex- pressed in least-significant bits (lsbs). midscale drift change in midscale offset error with a change in temperature, expressed as parts-per-million (ppm) of full scale per c. crosstalk ratio of response on one channel with a grounded input to a full-scale 1 khz sine-wave input on the other channel, expressed in decibels. interchannel phase deviation difference in input sampling times between stereo channels, ex- pressed as a phase difference in degrees between 1 khz inputs. power supply rejection with analog inputs grounded, energy at the output when a 300 mv p-p signal is applied to power supply pins, expressed in decibels of full scale. group delay intuitively, the time interval required for an input pulse to ap- pear at the converters output, expressed in milliseconds (ms). more precisely, the derivative of radian phase with respect to radian frequency at a given frequency. group delay variation the difference in group delays at different input frequencies. specified as the difference between largest and the smallest group delays in the passband, expressed in microseconds ( m s). ad1878/AD1879 pin list pin input/output pin name description 1 1 i/o l r ck left/right clock 1 2 i/o bck bit clock 1 3 i s0 mode select 0 1 4 i 64/ 32 bit rate select 1 5i dv dd +5 v digital supply 1 6 i dgnd digital ground 1 7 n/c no connection; do not connect 1 8i av ss 1 C5 v analog supply 1 9i av ss 2 C5 v analog logic supply 10 i agnd analog ground 11 i apd analog power down 12 i vinrC right inverting input 13 i vinr+ right noninverting input 14 i/o refr right reference capacitor 15 i/o refl left reference capacitor 16 i vinl+ left noninverting input 17 i vinlC left inverting input 18 i agnd analog ground 19 i av dd 1 +5 v analog supply 20 i av dd 2 +5 v analog logic supply 21 i av ss 1 C5 v analog supply 22 i dv dd +5 v digital supply 23 i dgnd digital ground 24 i reset reset 25 i s1 mode select 1 26 i clock master clock input 27 o data serial data output 28 i/o wck word clock theory of operation ?d modulator noise-shaping the stereo, differential analog modulators of the ad1878/ AD1879 employ a proprietary feedforward and feedback archi- tecture that passes input signals in the audio band with a unity transfer function yet simultaneously shape the quantization noise generated by the one-bit comparator out of the audio band. see figure 1. without the ?d architecture, this quantiza- tion noise would be spread uniformly from dc to one-half the oversampling frequency, 64 f s . (regardless of architecture, 64 times oversampling by itself significantly reduces the quanti- zation noise in the audio band if the input is properly dithered. however, the noise reduction is only [log 2 64] 3 db = 18 db.) pin 1 0.580 (14.73) 0.485 (12.32) 1 14 15 2 8 0.625 (15.87) 0.600 (15.24) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.125 (3.18) 0.250 (6.35) max 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) bsc 0.200 (5.05) 0.125 (3.18) 0.070 (1.77) max 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min seating plane 1.565 (39.70) 1.380 (35.10) figure 1. ad1878/AD1879 modulator noise-shaper (one channel)
ad1878/AD1879 rev. 0 C6C the ad1878/AD1879s patented ?d architectures shape the quantization noise-transfer function in a nonuniform manner. through careful design, this transfer function can be specified to high-pass filter the quantization noise out of the audio band into higher frequency regions. see figure 27. the analog devices ad1878/AD1879 also incorporates feedback resonators from the third integrators output to the second integrators input and from the fifth integrators output to the fourth integrators input. these resonators do not affect the signal transfer function but allow flexible placement of zeros in the noise transfer function. for the ad1878/AD1879, these zeros were placed near the high frequency end of the audio passband, reducing the quantization noise in a region where it otherwise would have been increasing. oversampling by 64 simplifies the implementation of a high per- formance audio analog-to-digital conversion system. antialias requirements are minimal; a single pole of filtering will usually suffice to eliminate inputs near f s and its higher multiples. a fifth-order architecture was chosen both to strongly shape the noise out of the audio band and to help break up the idle tones produced in all ?d architectures. these architectures have a ten- dency to generate periodic patterns with a constant dc input, a response that looks like a tone in the frequency domain. these idle tones have a direct frequency dependence on the input dc offset and indirect dependence on temperature and time as it affects dc offset. the human ear operates effectively like a spec- trum analyzer and can be sensitive to tones below the integrated noise floor, depending on frequency and level. the ad1878/ AD1879 suppresses idle tones typically 110 db or better below full-scale input levels. previously it was thought that higher-order modulators could not be designed to be globally stable. however, the ad1878/ AD1879s modulator was designed, simulated, and exhaustively tested to remain stable for any input within a wide tolerance of its rated input range. the ad1878/AD1879 was designed to reset itself should it ever be overdriven and go unstable. it will reset itself within 5 m s at a 48 khz sampling frequency. any such reset events will be invisible to the user since overdriving the in- puts will produce a clipped waveform at the output. the ad1878/AD1879 modulator architecture has been imple- mented using switched-capacitors. a systems benefit is that ex- ternal sample-and-hold amplifiers are unnecessary since the capacitors perform the sample-and-hold function coefficient weights are created out of varying capacitor sizes. the dominant noise source in this design is kt/c noise, and the input capaci- tors are accordingly very large to achieve the ad1878/AD1879s performance levels. (each 6 db improvement in dynamic range requires a quadrupling of input capacitor size, as well as an increase in size of the op amps to drive them.) this ad1878/ AD1879 thermal noise has been c ontrolled to properly dither the input to an 18-bit level. (note that 16-bit results from either the ad1878 or AD1879 will be underdithered.) with capacitors of adequate size and op amps of adequate drive, a well-designed switched-capacitor modulator will be relatively insensitive to jitter on the sampling clock. the key issue is whether the capacitors have had sufficient time to charge or discharge during the clock period. a properly designed switched capacitor modulator should be no more sensitive to clock jitter than are traditional nonoversampled adcs. this contrasts with continuous-time modulators, which are very sensitive to the exact location of sampling clock edges. see figures 20C23 for illustrations of the ad1878/AD1879s typical analog performance resulting from this design. signal- to-noise+distortion is shown under a range of conditions. note the very good linearity performance of the ad1878/AD1879 as a consequence of its single-bit ?d architecture in figure 24. the common-mode rejection (figure 25) graph illustrates the benefits of the ad1878/AD1879s differential architecture. the excellent channel separation shown in figure 26 is the result of careful chip design and layout. the relatively small change in gain over temperature (figure 31) results from a robust refer- ence design. the output of the ad1878/AD1879 modulators is a stereo bitstream at 64 f s (3.072 mhz for f s = 48 khz). spectral analysis of these bits would show that they contain a high qual- ity replica of the input in the audio band and an enormous amount of quantization noise at higher frequencies. the input signal can be recreated directly if these bits are fed into a prop- erly designed analog low-pass filter. digital filter characteristics the digital decimator accepts the modulators stereo bitstream and simultaneously performs two operations on it. first, the decimator low-pass filters the quantization noise that the modu- lator shaped to high frequencies and filters any other out-of- audio-band input signals. second, it reduces the data rate to an output word rate equal to f s . the high frequency bitstream is reduced to stereo 16-/18-bit words at 48 khz (or other desired f s ). the one-bit quantization noise, other high-frequency com- ponents of the bitstream, and analog signals in the stopband are attenuated by at least 115 db. the ad 1878/AD1879 decimator implements a symmetric fi nite impulse response (fir) filter, resulting in its linear phase re- sponse. this filter achieves a narrow transition band (0.0923 f s ), high stopband attenuation (> 115 db), and low passband ripple (< 0.001 db). the narrow transition band allows the unattenuated digitization of 20 khz input signals with f s as low as 44.1 khz. the stopband attenuation is sufficient to eliminate modulator quantization noise from affecting the output. low passband ripple prevents the digital filter from coloring the audio signal. for this level of performance, 4095 22-bit coeffic- ients (taps) were required in each channel of this filter. the ad1878/AD1879s decimator employs a proprietary single- stage, multiplier-free structure developed in conjunction with ensoniq corporation. see figures 28 and 29 for the digital filters characteristics. the output from the decimator is available as a single serial output, multiplexed between left and right channels. note that the digital filter itself is operating at 64 f s . as a consequence, nyquist images of the passband, transition band, and stopband will be repeated in the frequency spectrum at multiples of 64 f s . thus the digital filter will attenuate to 115 db across the frequency spectrum except for a window 0.5458 f s wide centered at multiples of 64 f s . any input signals, clock noise, or digital noise in these frequency windows will not be attenuated to the full 115 db. if the high frequency signals or noise appear within the passband images within these windows, they will not be digitally attenuated at all.
ad1878/AD1879 rev. 0 C7C sample delay the sample delay or group delay of the ad1878/AD1879 is dominated by the processing time of the digital decimation fil- ter. fir filters convolve a vector representing time samples of the input with an equal-sized vector of coefficients. after each convolution, the input vector is updated by adding a new sample at one end of the pipeline and eliminating the oldest input sample at the other. for an fir filter, the time at which a step input appears at the output will be approximately when that step input is halfway through the input sample vector pipeline. the input sample vector is updated every 64 f s . thus, the sample delay will be given by the equation, group delay = (4096 4 2) /(64 f s ) = 32 / f s for the most common sample rates this can be summarized as: f s group delay 48 khz 667 m s 44.1 khz 725 m s 32 khz 1000 m s due to the linear phase properties of fir filters, the group delay variation, or differences in group delay at different frequencies is zero. operating features voltage reference the ad1878/AD1879 includes a +3 v on-board reference which determines the ad1878/AD1879s input range. this ref- erence is buffered to both channels of the ad1878/AD1879s modulator, providing a well-matched reference to minimize interchannel gain mismatch. the reference should be bypassed with 10 m f tantalum capacitors as shown in figure 2. the inter- nal reference can be overpowered by applying an external refer- ence at the refr (pin 14) and refl (pin 15) pins, allowing multiple ad1878/AD1879s to be calibrated to the same gain. note that the reference pins still must be bypassed as shown. sample clock an external master clock supplied to clock (pin 26) drives the ad1878/AD1879 modulator, decimator, and digital inter- face. as with any analog-to-digital conversion system, the sam- pling clock must be low jitter to prevent conversion errors. the input clock operates at 256 f s . the clock is divided down to obtain the 64 f s clock required for the modulator. the out- put word rate will be at f s itself. this relationship is illustrated for popular sample rates below: AD1879 modulator output word clock input sample rate rate 12.288 mhz 3.072 mhz 48 khz 11.2896 mhz 2.822 mhz 44.1 khz 8.192 mhz 2.048 mhz 32 khz the ad1878/AD1879 serial interface supports both master and slave modes. note that even in slave mode it is presumed that the serial interface clocks are derived from the master clock input, clock. slave mode does not support asynchronous data transfers, since asynchronous data transfers would compro- mise the performance of any high performance converter. the ad1878/AD1879 decimator makes use of dynamic logic to minimize die area. there is, therefore, a minimum clock fre- quency that the ad1878/AD1879 will support specified in specifications above. operation of the ad1878/AD1879 at lower frequencies will cause the device to consume excessive power and may damage the converter. reset the active lo reset pin (pin 24) allows initializing the AD1879. this is of value only for synchronizing multiple ad1878/AD1879s in master modewck output. unless you are interested in synchronizing multiple ad1878/AD1879s, we recommend tying reset hi. the reset function is useful for nothing else. in fact, there is a maximum specification on reset lo; excessive power consumption may occur with loss of reliability if left lo too long due to the dynamic logic on the chip. figure 14 illustrates the timing parameters for reset to accomplish synchronization of multiple master modeword clock output adcs. (this sequence is not necessary for syn- chronizing multiple ad1878/AD1879s in other modes. see synchronizing multiple ad1878/AD1879s below.) note that reset first has to be lo for at least four clock periods (three clocks plus t rset plus t rhld , to be more precise). then reset must be hi for a minimum of one clock and a maximum of two clocks. then reset must he lo for at least another four clocks. from the time when reset goes hi again, exactly 127 clocks will occur before l r ck goes lo. analog power down the ad1878/AD1879 features a power-down mode that reduces current to the analog modulator. it is controlled by the active hi apd (pin 11). the power savings are specified in specifications. the converter is still alive in the power- down state but will not produce valid results for all audio-band inputs. power consumption can be further reduced by slowing down the master clock input to the minimum clock frequency, f clock , specified for the ad1878/AD1879. applications issues recommended input structure the ad1878/AD1879 input structure is fully differential for improved common-mode rejection properties and increased dynamic range. since each input pin sees 3 v swings, each channels input signal effectively swings 6 v, i.e., across a 12 v range. in most cases, a single-ended-to-differential input circuit is required. shown in figure 2 is our recommended circuit, based on extensive experimentation. note that to maximize signal swing, the op amps in this circuit are powered by 12 v or greater supplies. the ad1878/AD1879 itself requires 5 v supplies. if 5 v supplies are not already available in your sys- tem, figure 3 illustrates our recommended circuit for generat- ing these supplies.
ad1878/AD1879 rev. 0 C8C right input ne5532 or op-275 100pf .1? 5.76k w 100pf v cc v ss 249k w 100k w 249k w v ss .1? .0047 ? npo .01? npo .01? npo ne5532 or op-275 vinr vinr+ vinl+ vinl 12 13 16 17 refr refl 10? 14 .1? ad1878/79 left input 100pf 100pf v cc .1? .0047 ? npo .01? npo ne5532 or op-275 .1? v cc v ss .1? .01? npo 10? 15 5.62k w 5.62k w 5.62k w 5.62k w 5.49k w 51 w 51 w 200 w 249k w 5.62k w 100k w 5.36k w 200 w 51 w 51 w 5.62k w 5.62k w 5.62k w 249k w 5.90k w figure 2. ad1878/AD1879 recommended input structure v cc agnd v ss v dd dgnd 0.1? 22? 7805 in out gnd +5v analog ?v analog +5v digital +12v < v cc < +18v ?2v > v ss > ?18v 0.1? 22? 0.1? 22? 7905 in out gnd 0.1? 10? 0.1? 10? figure 3. ad1878/AD1879 recommended power condi- tioning circuit (if 5 v supplies are not already available) the trim potentiometers shown in figure 2 connecting the minus (C) inputs of the driving op amps permit trimming out dc offset, if desired. note that the driving op amp feedback resistors are all slightly different values. these values produce a slight differential gain imbalance and were derived empirically to minimize second harmonic distortion on average and produce the best overall thd without part-by-part trimming. replacing one of these feedback resistors in each channel with a trim potentiometer allows trimming the differential gain imbalance for part-by-part optimal performance. we have done this in the lab by parallel- ing 100 k w trim potentiometers around the 5.49 k w and 5.36 k w input feedback resistors for the v in plus (+) signals that can be found in figure 2. by trimming gain imbalance, sec- ond harmonic distortion can always be eliminated. in specifi- cati ons, a distinction is drawn between trimmed and untrimmed signal-to (noise + distortion) and trimmed and untrimmed total harmonic distortion. the untrimmed specifications are tested to the input structure shown in figure 2. the trimmed specifica- tions are based on a part-by-part trim of this differential gain to eliminate the second harmonic. the input circuit of figure 2 could be implemented with a single pair of operational amplifiers per channel, one inverting and one noninverting. the recommended architecture shown in figure 2 using three inverting op amps per channel provides iso- lation of the op amp inputs from charge dumped back from the ad1878/AD1879s input capacitors when these large capacitors switch. the performance from a two op amp per channel input structure is not quite as good as the structure recommended, but it is close and may be adequate in many applications. layout and decoupling considerations obtaining the best possible performance from a state-of-the-art data converter like the ad1878/AD1879 requires close atten- tion to board layout. from extensive experimentation, we have discovered principles that produce typical values of 103 db dy- namic range and 98 db s/(thd+n) in your system. schematics of our ad1878/AD1879 evaluation boa rd, which implements these recommendations, are available from analog devices. the principles and their rationales are listed below in descend- ing order of importance. the first two pertain to bypassing and are illustrated in figure 4. ad1878/ 79 av ss 1 av ss 1 av dd 1 agnd agnd 10? ?v analog +5v analog 10? 0.1? +5v digital 10? 0.1? +5v digital av ss 2 av dd 2 dv dd dgnd dgnd dv dd ?v analog +5v analog +5v digital oscillator 0.1? 26 clkin 10? 10? 821 19 10 18 9205 6 23 22 figure 4. ad1878/AD1879 recommended bypassing and oscillator circuits ? the digital bypassing of the ad1878/AD1879 is the most critical item on the board layout. there are two pairs of digi- tal supply pins of the part, each pair on opposite sides (pins 5 and 6 and pins 22 and 23). the user should tie a bypass ca- pacitor set (0.1 m f ceramic and 10 m f tantalum) on each pair of supply pins as close to the pins as possible. the traces between these package pins and the capacitors should be as short and as wide as possible. this will prevent digital supply current transients from being inductively transmitted to the inputs of the part. ? the analog input bypassing is the second most critical item. use 0.01 m f npo ceramic capacitors from each input pin to the analog ground plane, with a clear ground path from the bypass capacitor to the agnd pin on the same side of the package (pins 10 and 18). the trace between this package pin and the capacitor should be as short and as wide as pos- sible. a 0.0047 m f npo ceramic capacitor should be placed
ad1878/AD1879 rev. 0 C9C between each set of input pins (12 to 13, and 17 to 16) to complete the input bypassing. this input bypassing mini- mizes the rf transmission and reception capability of the ad1878/AD1879 inputs. ? for best performance, do not use a socket with the ad1878/ AD1879. if you must socket the part, use pin clips to keep the part flush with the board, thus keeping bypassing as close to the chip as possible. ? the ad1878/AD1879 should be placed on a split ground plane as illustrated in figure 5. the digital ground plane should be placed under the top end of the package and the analog ground plane should be placed under the bottom end of the package as shown in figure 5. the split should be be- tween pins 7 and 8 and between pins 21 and 22. the ground planes should be tied together at one spot under- neath the center of the package. this ground plane tech- nique also minimizes rf transmission and reception. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 lrck bck s0 dv dd 64/32 dgnd nc av ss 1 av ss 2 agnd apd vinr vinr+ refr wck data clk s1 dgnd dv dd av ss 1 av dd 2 av dd 1 agnd vinl vinl+ refl reset digital ground plane analog ground plane figure 5. ad1878/AD1879 recommended ground plane ? each reference pin (14 and 15) should be bypassed with a resistor and a capacitor. one end of the resistor should be placed as close to the package pin as possible, and the trace to it from the reference pin should be as short and as wide as possible. keep this trace away from input pin traces! cou- pling between input and reference traces will cause second harmonic distortion. the resistor is used to reduce the high frequency coupling into the references from the board. ? wherever possible, minimize the capacitive load on digital outputs of the part. this will reduce the digital spike cur- rents drawn from the digital supply pins. how to extend snr a cost-effective method of improving the dynamic range and snr of an analog-to-digital conversion system is to use mul- tiple AD1879 channels in parallel with a common analog input. (the same technique would work with the ad1878. however, this would be of little value since using a single AD1879 would be more effective.) this technique makes use of the fact that the noise in independent modulator channels is uncorrelated. thus every doubling of the number of AD1879 channels used will im- prove system dynamic range by 3 db. the digital outputs from the corresponding decimator channels have to be arithmetically averaged to obtain the improved results in the correct data for- mat. a digital processor, either general-purpose or dsp, can easily perform the averaging operation. shown below in figure 6 is a circuit for obtaining a 3 db im- provement in dynamic range by using both channels of a single AD1879 with a mono input. the minus (C) output from the in- put buffer is sent to both right and left minus AD1879 inputs; the plus (+) output from the input buffer is sent to both right and left plus AD1879 inputs. a stereo implementation would require using two AD1879s and using the full recommended in- put structure shown above in figure 2. note that a single digital processor would likely be able to handle the averaging require- ments for both left and right channels. pin 1 0.580 (14.73) 0.485 (12.32) 1 14 15 2 8 0.625 (15.87) 0.600 (15.24) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.125 (3.18) 0.250 (6.35) max 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) bsc 0.200 (5.05) 0.125 (3.18) 0.070 (1.77) max 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min seating plane 1.565 (39.70) 1.380 (35.10) figure 6. increasing dynamic range by using two AD1879 channels digital interface modes of operation the ad1878/AD1879s flexible serial output port produces data in twos-complement, msb-first format. output signals are to ttl/cmos logic levels. the port is configured by pin selec- tions. the AD1879 can operate in either master or slave modes. each 16-/18-bit output word of a stereo pair can be formatted within a 32-bit field as right-justified, as i 2 s-compatible, or at user-selected positions. the two 32-bit fields constitute a 64-bit frame (64-bit mode). the output can also be truncated to 16 bits and formatted in a 16-bit field with two 16-bit fields in a 32-bit frame (32-bit mode). the various mode options are pin-programmed with the s0 mode select pin (3), the s1 mode select pin (25), and the 64/32 bit rate select pin (4). the function of these pins is summarized: serial port operation mode 64/ 32 s0 s1 64-bit master modeword clock output 1 0 0 64-bit master modeword clock input 1 1 0 64-bit slave mode 1 1 1 reserved 1 0 1 32-bit master modeword clock out hi 0 0 0 32-bit master modeword clock ignored 0 1 0 32-bit slave mode 0 1 1 reserved 0 0 1 serial port data timing sequences in the master modes, the bit clock (bck) and left/right clock (l r ck) are always outputs, generated internally in the ad 1878/ AD1879 from the master clock (clock) input. the word clock (wck) may either be an internally generated output or a user-supplied input, depending on the pin-programmed mode selected.
ad1878/AD1879 rev. 0 C10C in the slave modes, the bit clock (bck), the word clock (wck), and the left/right clock (l r ck) are user-supplied in- puts. note that, for performance reasons, the ad1878/AD1879 does not support asynchronous operation; these clocks must be externally derived from the master clock (clock). the func- tional sequence of the signals in the slave modes is identical to the master modes with word clock input, and they share the same sequence timing diagrams. in 64-bit master mode with word clock output, the 16-/18-bit words are right-justified in 32-bit fields as shown in figures 7 and 8. the wck output goes hi approximately with the falling edge of the bck output, indicating that the msb on data will be externally valid at the next bck rising edge. the l r ck out- put discriminates the left from the right output fields. in 64-bit frame modes with word clock (wck) is an input, the 16-/18-bit words can be placed in user-defined locations within 32-bit fields. this is true in both master and slave modes. the options are illustrated in figures 9, 10, 11, and 12. for all op- tions, the first occurrence in a 32-bit field when the word clock (wck) is hi on a bit clock (bck) falling edge will cause the beginning of data transmission. the msb on data will be valid at the next bck rising edge. again, the l r ck output dis- criminates the left from the right output fields. figure 9 illustrates the general case for 64-bit frame modes with word clock input where the msb is valid on the rising edge of the nth bit clock (bck). figures 10 and 11 illustrate the limits. if wck is still lo at the falling edge of the 14th bit clock (bck) for the AD1879 or 16th bit clock (bck) for the ad1878, t hen the msb of the current word will be output anyway, valid at the ris- ing edge of the 15th bit clock (bck) in the field for the AD1879, 17th for the ad1878. this limit insures that all 16/18 bits will be output within the current field. the effect is to right-justify the data. 32 1 2 31415161718 29 32 1 2 3 14 15 16 17 18 1 msb msb? msb? msb? left data zeros lsb? lsb lsb msb msb? msb? msb? right data 30 31 zeros lsb? lsb? 29 32 lsb? lsb 30 31 lsb? lsb? bck output wck output lrck output previous data data output figure 7. AD1879 64-bit output timing with wck as output (master mode only) 32 bck output 1 2 31415161718 29 32 1 2 3 14 15 16 17 18 1 wck output 30 31 lrck output 29 32 30 31 msb msb? left data zeros lsb? lsb previous data right data zeros data output lsb lsb? lsb? msb msb? lsb? lsb lsb? lsb? figure 8. ad1878 64-bit frame output timing with wck as output (master mode only) lsb-2 lsb 32 bck i/o 1 n? n n+1 31 32 wck input AD1879 data output msb? zeros lsb? lrck i/o n+14 n+17 n+15 n+16 lsb? 1 n? n n+1 31 32 1 msb msb? zeros zeros lsb lsb? lsb-2 lsb? ad1878 data output msb msb? zeros lsb? lsb msb msb? zeros zeros lsb? lsb n+14 n+17 n+15 n+16 right data right data left data left data msb figure 9. ad1878/AD1879 64-bit frame output timing with wck as input: wck transitions hi before 16th bck (ad1878)/14th bck (AD1879) (master mode or slave mode)
ad1878/AD1879 rev. 0 C11C msb wck input 32 1 2 3 14151617181920 31 32 1 2 3 14 15 16 17 18 19 20 31 32 1 msb? msb? msb? zeros lsb? lsb zeros lsb lsb lsb? bck i/o lrck i/o ad1878 data output msb msb? msb? msb? left data previous data right data figure 10. ad1878 64-bit frame output timing with wck as input: wck held lo until 16th bck (master mode or slave mode) wck input 32 1 2 3 14151617181920 31 32 1 2 3 14 15 16 17 18 19 20 31 32 1 msb msb? msb? msb? msb? msb? zeros lsb? lsb previous data msb msb? msb? msb? msb? msb? zeros lsb lsb lsb? bck i/o lrck i/o AD1879 data output left data right data figure 11. AD1879 64-bit frame output timing with wck as input: wck held lo until 14th bck (master mode or slave mode) lsb-2 lsb-2 wck input 32 1 2 3 1617 1819 20 21 22 31 32 zeros bck i/o lrck i/o 1 2 3 31 32 right data 1 AD1879 data output msb msb? zeros lsb? lsb? lsb ad1878 data output msb msb? zeros lsb? lsb zeros zeros msb msb? zeros lsb? lsb? lsb msb msb? zeros lsb? lsb zeros right data 16 17 18 19 20 21 22 left data left data figure 12. ad1878/AD1879 64-bit output frame timing with wck as input: wck hl during 1st bck (master mode or slave mode) 16 1 2 3456 15 16 left data msb msb? msb? msb? msb? msb? lsb? bck i/o lrck i/o 1 2 3456 right data msb msb? msb? msb? msb? msb? 15 16 1 lsb? lsb? lsb? AD1879 data output ad1878 data output left data msb msb? msb? msb? msb? msb? lsb-1 right data msb msb? msb? msb? msb? msb? lsb lsb-1 lsb figure 13. ad1878/AD1879 32-bit output frame timing (master mode or slave mode) at the other limit, if the word clock (wck) is hi during the first bit clock (bck) of the field, then the msb of the output word will be valid on the rising edge of the 2nd bit clock (bck) as shown in figure 12. the effect is to delay the msb for one bit clock cycle into the field, making the output data compatible at the data format level with the i 2 s data format. in 64-bit frame modes with word clock (wck) as an input, the relative placement of the word clock (wck) input can vary from 32-bit field to 32-bit field, even within the same 64-bit frame. for example, within a single 64-bit frame the left word could be right-justified (by keeping wck lo) and the right word could be in an i 2 s-compatible data format (by having wck hi at the beginning of the second field).
ad1878/AD1879 rev. 0 C12C delayed from a master clock input (clock) rising edge by t dlyck as shown in figure 15. the msb of the data output will be delayed from a falling edge of master clock (clock) by t dlyd,msb . subsequent bits of the data output in contrast will be delayed from a rising edge of master clock (clock) by t dlyd . (the msb is valid one-half clock period less than the subsequent bits.) for master modes with word clock (wck) inputs, bit clock (bck) and left/ right clock (l r ck) will be delayed from a master clock input (clock) rising edge by t dlyck as shown in figure 16, the same delay as with word clock output modes. the word clock (wck) input, however, now has a setup time requirement, t wset , to the rising edge of master clock (clock at w) and a corresponding hold time, t whld , from the rising of the third rising edge of clock (w+3) after the setup edge. see figure 16. as in the master modeword clock output case, the msb of the data output will be delayed from a fall- ing edge of master clock (clock) by t dlyd,msb . subsequent bits of the data output in contrast will be delayed from a ris- ing edge of master clock (clock) by t dlyd . for slave modes, bit clock (bck) and left/right clock (l r ck) will be inputs with setup time, t set , and hold time t hld , requirements to the falling edges of clock as shown in fig- ure 17. note that both edges of bck and of l r ck have setup and hold time requirements. note also that l r ck is setup to the fall ing edge of the l clock, coincident with the clock edge to which a falling edge of bck is setup (b+3). l r cks hold time requirements are relative to the falling edge of the l + 31 clock edge. also available with the ad1878/AD1879 is a 32-bit frame mode where the 1879s 18-bit output is truncated to 16-bit words and for both parts the output packed tightly into two 16-bit fields in the 32-bit frame as shown in figure 13. note that the bit clock (bck) and data transmission (data) are operating at one-half the rate as they would in the 64-bit frame modes. the distinction between master and slave modes still holds in the 32-bit frame modes, though the word clock (wck) becomes ir- relevant. if 32-bit master mode with word clock out hi is selected, the word clock (wck) will stay in a constant hi state. if 32-bit master mode with word clock ignored is selected, the word clock pin (wck) will be three-stated and any input to it is ignored as meaningless. (however, such an input should be tied off to hi or lo and not left to float.) in both 32-bit master modes, the left/right clock (l r ck) will be an output, indicating the difference between the left word/field and right word/field. in 32-bit slave mode, the left/right clock (l r ck) is an input. timing parameters the ad1878/AD1879 uses its master clock, clock to resyn- chronize all inputs and outputs. the discussion above presumed that most timing parameters are relative to the bit clock, bck. this is approximately true and provides an accurate model of the sequence of timing events. however, to be more precise, we have to specify all setup and hold times relative to clock. these are illustrated in figures 15, 16, and 17. for master modes with word clock (wck) output, bit clock (bck), left/right clock (l r ck), and word clock (wck) will be t rset clock input reset t rhld t rpls min 4 clks for synch min 1 clk max 2 clks for synch min 4 clks for synch 1 2 3 4 126 127 128 lrck output bck output figure 14. ad1878/AD1879 reset clock timing for synchronizing master mode wck output data output bck output (64? s ) clock input lrck & wck outputs t dlyd,msb previous new msb msb? 14 15 1 16 msb? 17 t dlyd t dlyd t dlyck t dlyck t dlyck t dlyck zeros figure 15. ad1878/AD1879 master mode clock timing: wck output
ad1878/AD1879 rev. 0 C13C data output bck output (64? s ) clock input lrck output wck input previous new 1 t dlyck t wset t whld t dlyd,msb msb msb? msb? t dlyd t dlyd t dlyck t dlyck t dlyck zeros w+1 w+2 w+3 w figure 16. ad1878/AD1879 master mode clock timing: wck input data output bck input (64? s ) clock input lrck input wck input t hld t set l+1 l w+1 w+2 w+3 w t wset t whld t dlyd,msb msb msb? msb? t dlyd t dlyd t set t set t hld b+1 b+2 b b+3 l+30 l+31 t hld zeros figure 17. ad1878/AD1879 slave mode timing for slave modes, the word clock (wck) input has the same setup time requirement, t wset , to the rising edge of master clock (clock at w ) as in figure 16 and a corresponding hold time, t whld , from the rising edge of clock (w+3) after the setup edge. the msb of the data output will be delayed from a falling edge of master clock (clock) by t dlyd,msb . subsequent bits of the data output in contrast will be delayed from a rising edge of master clock (clock) by t dlyd . synchronizing multiple ad1878/AD1879s multiple ad1878/AD1879s can be synchronized either by making all ad1878/AD1879s serial port slaves or by making one AD1879 the serial port master and all other AD1879s slaves. these two options are illustrated in figure 18. as a third alternative, it is possible to synchronize multiple mas- ters all in master modeword clock output mode. see the reset discussion above in the operating features section for timing considerations. ad1878/AD1879 to dsp56001 interface the 18-bit ad1878/AD1879 can be interfaced quite simply to the dsp56001 digital signal processor. figure 19 illustrates one me thod of connection. in this implementation, the ad1878/ AD1879 is configured to operate in 64-bit master mode with word clock output. thus, the ad1878/AD1879 is the master of the serial interface. the ad1878/AD1879 operates indepen- dently from the ds m ps clock. the dsp56001 serial port is configured to operate in synchronous mode with the ad1878/ AD1879 connected to its synchronous serial interface (ssi) port. clock source #1 AD1879 master mode clk data bck wck lrck #2 AD1879 slave mode clk data bck wck lrck #n AD1879 slave mode clk data bck wck lrck clock source #1 AD1879 slave mode clk data bck wck lrck #2 AD1879 slave mode clk data bck wck lrck #n AD1879 slave mode clk data bck wck lrck figure 18. synchronizing multiple ad1878/AD1879s
ad1878/AD1879 rev. 0 C14C data bck wck lrck AD1879 srd sck sc2 sc1 dsp56001 figure 19. AD1879 to dsp56001 interface to configure the dsp56001 for proper operation, the cra register must he programmed for a 24-bit receive data register (rx). the crb register must be programmed with the follow- ing conditions: receiver enabled, normal mode, continuous clock, word length frame synch, msb first, sck an input, sc1 an input and sc2 an input. the pcc register must be pro- grammed to set the sck, sc1, sc2, and srd pins of port c to operate as a serial interface rather than in general-purpose parallel i/o mode. when ssi detects the rising edge of the ad1878/AD1879s word clock (wck), the next 24-bits on the ad1878/AD1879s data pin will be clocked into the dsp56001s ssi receive shift register on the falling edges of the inverted bit-clock (bck) signal. this data is then transferred to the rx register. the 16-/18-bit word from the AD1879 will be located in bits 8 through 23/21 of the rx register. bits 0 through 7 will be zero-filled. the user may poll bit 7 (rdf) of the ssi status register (ssisr) to detect when the data has been transferred to rx. alternatively, the rie bit can be set, allowing an inter- rupt to occur when the data has been transferred. to differentiate left and right data, the sc1 pin of the ssi is an input and is connected to the l r ck of the ad1878/AD1879. after a data word is transferred to the rx register, the software reads the if1 bit in the ssisr, which contains the left/right in- formation. in order to use the sc1 pin as indicated, the ssi must operate in synchronous mode. an dsp56001 assembly code fragment for this approach (with polling) is shown in table i. table i. dsp56001 assembly code for ad1878/AD1879 data transfer poll jclr #7,x:$ffee,poll :l oop until rx reg. has data movep x:$ffef,al: :transfer adc to al register jset #i:x:$ffee,left :if lrck=1, save left else move a1,x:$c000 :store right channel jmp poll :wait for next input left move a1,y:$c000 :store left channel jump poll if the ssi is set up for asynchronous operation, the sc0 and sc1 pins are unavailable for left/right detection. if asynchro- nous operation is essential, left/right information can be ob- tained by synchronizing the ad1878/AD1879 with a software reset. coming out of reset, the ad1878/AD1879 will transmit left channel data first. a flag maintained in software can main- tain the synchronization. ad1878/AD1879 performance graphs 0 ?40 24k ?0 ?20 2k ?00 0 ?0 ?0 ?0 22k 20k 18k 16k 14k 12k 10k 8k 6k 4k frequency ?hz dbfs figure 20. AD1879 s/(thd+n)1 khz tone at C0.5 dbfs (4k-point fft) 0 ?40 24k ?0 ?20 2k ?00 0 ?0 ?0 ?0 22k 20k 18k 16k 14k 12k 10k 8k 6k 4k frequency ?hz dbfs figure 21. AD1879 s/(thd+n)1 khz tone at C10 dbfs (4k-point fft) 0 ?40 24k ?0 ?20 2k ?00 0 ?0 ?0 ?0 22k 20k 18k 16k 14k 12k 10k 8k 6k 4k frequency ?hz dbfs figure 22. AD1879 s/(thd+n)1 khz tone at C60 dbfs (4k-point fft)
ad1878/AD1879 rev. 0 C15C 0 ?40 24k ?0 ?20 2k ?00 0 ?0 ?0 ?0 22k 20k 18k 16k 14k 12k 10k 8k 6k 4k dbfs frequency ?hz figure 23. AD1879 s/(thd+n)10 khz tone at C10 dbfs (4k-point fft) 1.0 ?.0 0 ?.4 ?.8 ?00 ?.6 ?20 0.2 ?.2 0.0 0.4 0.6 0.8 ?0 ?0 ?0 ?0 amplitude ?dbfs dbfs figure 24. AD1879 linearity test10 khz tone fade to noise ?4 ?8 ?0 100 100k 10k 1k 20 ?0 ?2 ?6 ?4 ?8 ?0 ?2 ?6 ?4 ?6 ?8 frequency ?hz dbfs figure 25. ad1878/AD1879 common-mode rejection ratio0 khz to 20 khz ?00 ?20 ?40 100 10k 20 ?30 ?10 ?15 ?25 ?35 ?05 1k frequency ?hz 20k dbfs figure 26. ad1878/AD1879 channel separation0 khz to 20 khz 1e? 1e? 1e? 1e1 1e2 1m 1e5 1e4 1k 1e? 1u 1e? 1m frequency ?hz volts per root ?hz figure 27. ad1878/AD1879 modulator noise transfer function0 mhz to 1 mhz 10 ?0 ?50 1e1 1e2 1m 1e5 1e4 1k ?0 ?0 ?0 ?30 ?10 ?0 frequency ?hz dbfs figure 28. ad1878/AD1879 digital filter signal transfer function0 mhz to 1 mhz
ad1878/AD1879 rev. 0 C16C c1843C18C10/93 printed in u.s.a. 0 ?30 26.5 ?00 ?20 22.0 ?10 21.5 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 25.5 26.0 25.0 24.5 24.0 23.5 23.0 22.5 frequency ?khz decibels figure 29. ad1878/AD1879 digital filter signal transfer function transition band: 21.5 khz to 26.5 khz 1.012 0.997 ?0 ?0 130 110 90 70 50 30 10 temperature ?? gain 1.011 1.010 1.009 1.008 1.007 1.006 1.005 1.004 1.003 1.002 1.001 1.000 0.999 0.998 figure 30. ad1878/AD1879 typical gain over temperature C30 c to +130 c outline dimensions dimensions shown in inches and (mm). d-28 28-lead side brazed ceramic dip 0.610 (15.49) 0.500 (12.70) 14 0.100 (2.54) max 15 pin 1 1 0.005 (0.13) min 28 0.225 (5.72) max 0.200 (5.08) 0.125 (3.18) 0.026 (0.66) 0.014 (0.36) 1.490 (37.85) max 0.110 (2.79) 0.090 (2.29) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min seating plane 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20)

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