1/94 block diagram receives both power and signal across the isolation boundary 9 to 15 volt high level gate drive under-voltage lockout programmable over-current shutdown and restart output enable function the uc1725 and its com panion chip, the uc1724, provide all the nec - essary features to drive an isolated mosfet transistor from a ttl in - put signal. a unique modulation scheme is used to transmit both power and signals across an isolation boundary with a minimum of external components. protection circuitry, including under-voltage lockout, over-current shut - down, and gate voltage clamping provide fault protection for the mos - fet. high level gate drive is guaranteed to be greater than 9 volts and less than 15 volts under all conditions. uses include isolated off-line full bridge and half bridge drives for driv - ing motors, switches, and any other load requiring full electrical isola - tion. the uc1725 is characterized for operation over the full military tem - perature range of -55c to +125c while the uc2725 and uc3725 are characterized for -25c to +85c and 0c to +70c respectively. uc1725 uc2725 uc3725 isolated high side fet driver features description udg-92051-1
connection diagrams dil-8 (top view) j or n package uc1725 uc2725 uc3725 package pin function function pin n/c 1 i sense 2 n/c 3-5 timing 6 enable 7 n/c 8-9 input a 11 n/c 12-14 input b 15 gnd 16 v cc 17 n/c 18-19 output 20 plcc-20 (top view) q package absolute maximum ratings supply voltage (pin 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30v power inputs (pins 7 & 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30v output current, source or sink (pin 2) dc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5a pulse (0.5 us) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0a enable and current limit inputs (pins 4 & 6). . . . . . . . -0.3 to 6v power dissipation at t a 25c (dil-8) . . . . . . . . . . . . . . . . 1w power dissipation at t a 25c (so-14) . . . . . . . . . . . . 725mw lead temperature (soldering, 10 seconds) . . . . . . . . . . 300c note 1: unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the speci- fied terminals (pin numbers refer to dil-8 package). note 2: see unitrode integrated circuits databook for information regarding thermal specifications and limitations of packages. parameter test conditions min typ max units power input section (pins 7 & 8) forward diode drop, schottky rectifier i f = 50ma .55 .7 v i f = 500ma 1.1 1.5 v current limit section (pin 4) input bias current v pin4 = ov -1 -10 m a threshold voltage 0.4 0.5 0.6 v delay to outputs v pin4 = 0 to 1v 100 250 ns timing section (pin 5) output off time 27 30 33 m s upper mono threshold 6.3 7.0 7.7 v lower mono threshold 1.9 2.0 2.3 v hysteresis amplifier (pins 7 & 8) input open circuit voltage inputs (pins 7 & 8), open circuited, t a = 25c 7.0 vcc/2 8.0 v input impedance t a = 25c 23 28 33 k w hysteresis 26.5 2 * vcc 30.5 v delay to outputs v pin7 - v pin8 = v cc + 1v 100 300 ns electrical characteristics: (unless otherwise stated, these specifications apply for -55 c t a +125 c for uc1725; -25 c t a +85 c for uc2725; 0 c t a +70 c for uc3725; v cc (pin 3) = 0 to 15v, r t =10k, c t =2.2nf, t a =t j , pin numbers refer to dil-8 package.) soic-16 (top view) dw package dil-16 (top view) je or ne package 2
parameter test conditions min typ max units enable section ( pin 6) high level input voltage 2.1 1.4 v low level input voltage 1.4 .8 v input bias current -250 -500 m a output section output low level i out = 20ma 0.35 0.5 v i out = 200ma 0.6 2.5 v output high level i out = -20ma 13 13.5 v i out = -200ma 12 13.4 v v cc = 30v, iout = -20ma 14 15 v rise/fall time c t = 1nf 30 60 ns under voltage lockout uvlo low saturation 20ma, v cc = 8v 0.8 1.5 v start-up threshold 11.2 12 12.6 v threshold hysteresis .75 1.0 1.12 v total standby current supply current 12 16 ma uc1725 uc2725 uc3725 electrical characteristics (cont.) (unless otherwise stated, these specifications apply for -55 c t a +125 c for uc1725; -25 c t a +85 c for uc2725; 0 c t a +70 c for uc3725; v cc (pin 3) = 0 to 15v, rt=10k, c t =2.2nf, t a =t j, pin numbers refer to dil-8 package.) inputs: figure 1 shows the rectification and detection scheme used in the uc1725 to derive both power and signal information from the input waveform. vcc is gener- ated by peak detecting the input signal via the internal bridge rectifier and storing on a small external capacitor, c1. note that this capacitor is also used to bypass high pulse currents in the output stage, and therefore should be placed direclty between pins 1 and 3 using minimal lead lengths. signal detection is performed by the internal hysteresis comparator which senses the polarity of the input signal as shown in figure 2. this is accomplished by setting (resetting) the comparator only if the input signal ex- ceeds vcc (-vcc). in some cases it may be necessary to add a damping resistor across the transformer secondary to minimize ringing and eliminate false triggering of the hysteresis amplifier as shown in figure 3. application and operation information figure 1 - input stage figure 2 - input waveform (dil-8 pin 7 - pin 8) figure 3 - signal detection udg-92047 udg-92048 udg-92049 3
uc1725 uc2725 uc3725 current limit and timing: current sensing and shutdown can be implemented directly at the output us- ing the scheme shown in figure 4. alternatively, a current transformer can be used in place of r sense . a small rc filter in series with the input (pin 4) is generally needed to eliminate the leading edge current spike caused by parasitic circuit capacitances being charged during turn on. due to the speed of the current sense circuit, it is very important to ground c f directly to gnd as shown to eliminate false triggering of the one shot caused by ground drops. one shot timing is easily programmed using an external capacitor and resistor as shown in figure 4. this, in turn, controls the output off time according to the formula: t off = 1.28 rc . if current limit feature is not required, simply ground pin 4 and leave pin 5 open. output: gate drive to the power fet is provided by a totem pole output stage capable of sourcing and sinking currents in excess of 1 amp. the undervoltage lockout circuit guarantees that the high level output will never be less than 9 volts. in addition, during undervoltage lock- out, the output stage will actively sink current to eliminate the need for an external gate to source resistor. high level output is also clamped to 15 volts. under high ca- pacitive loading however, the output may overshoot 2 to 3 volts, due to the drivers inabitlity to switch from full to zero output current instantaneously. in a practical circuit this is not normally a concern. a few ohms of series gate resistance is normally required to prevent parasitic oscil- lations, and will also eliminate overshoot at the gate. enable: an enable pin is provided as a fast, digital in- put that can be used in a number of applications to di- rectly switch the output. figure 6 shows a simple means of providing a fast, high voltage translation by using a small signal, high voltage transistor in a cascode configu- ration. note that the uc1725 is still used to provide power, drive and protection circuitry for the power fet. figure 4 - current limit udg-92050 figure 5 - output circuit figure 6 - using enable pin as a high speed input path udg-92052 udg-92053 unitrode integrated circuits 7 continental blvd. merrimack, nh 03054 tel. (603) 424-2410 fax (603) 424-3460 4
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated
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