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rev. 4671c?dab?06/04 features 8.5 v supply voltage voltage regulator for stable operating conditions microprocessor-controlled via a simple two-wire bus two addresses selectable gain-controlled rf amplifier with two inputs, selectable via a simple two-wire bus control balanced rf amplifier inputs gain-controlled rf mixer four-pin voltage-controlled oscillator saw filter driver with differential low-impedance output agc voltage generation for rf section, available at charge-pump output (can also be used to control a pin diode attenuator) gain-controlled if amplifier balanced if amplifier inputs selectable gain-controlled if mixer single-ended if output agc voltage generation for if section, available at charge-pump output separate differential input for the if agc block all agc time constants adjustable agc thresholds programmable via a simple two-wire bus three agc charge pump currents selectable (zero, low, high) reference oscillator programmable 9-bit reference divider programmable 15-bit counter 1:2048 to 1:32767 effectively tristate phase detector with programmable charge pump superior phase-noise performance deactivation of tuning output programmable three switching outputs (open collector) three d/a converters (resolution: 8 bits) lock status indication (open collector) electrostatic sensitive device. observe precautions for handling. description the u2731b is a monolithically integrat ed digital audio broadcasting one-chip front end circuit manufactured using atmel?s advanced uhf5s technology. its functionality covers a gain-controlled rf amplifier with two selectable rf inputs, a gain-controlled rf mixer, a vco which provides the lo signal for the rf mixers, either directly or after passing a frequency divider, a saw filter driver, an agc block for the rf section, a gain-controlled if amplifier, an if mixer which can also be bypassed, an agc block for the if section and a fractional-n frequency synthesizer. the frequency synthesizer controls the vco to synthesize frequencies in the range of 70 mhz to 500 mhz in a 16-khz raster; within certain limits the reference divider factor is fully programmable. the lock status of the phase detector is indicated at a special output pin; three switch- ing outputs can be addressed. a reference signal which is generated by an on-chip reference oscillator is available at an output pin. this reference signal is also used to generate the lo signal for the if mixer, ei ther by doubling the frequency or by using the reference frequency itself. three d/a converters at a resolution of 8 bits provide a digitally controllable output voltage. the thresholds inside the agc blocks can be digi- tally controlled by means of on-chip 4-bit d/a converters. all functions of this ic are controlled via a simple two-wire bus. dab one-chip front end u2731b
2 u2731b 4671c?dab?06/04 figure 1. block diagram programmable 13-bit counter n/n+1 fractional-n control reference counter 15-bit latch 9-bit latch 4-bit latch switches mux mux 3-bit latch tristate phase detector programmable charge pump 8-bit latch 8-bit latch 8-bit latch osci 42 osco 43 fref 5 simple two-wire bus interface/control d/a d/a d/a vd 40 lock detector 4-bit latch plck 41 pd 39 d/a x1/x2 1/ 2 c1vco 32 b2vco b1vco c2vco 33 34 35 vco rfa1 rfa2 12 13 rfb1 rfb2 14 15 th1 th2 19 18 23 24 28 saw1 saw2 ifin1 ifin2 cpif th3 if agcin2 26 if agcin1 27 sli 21 wagc 22 ifout 29 10, 11, 17, 30, 31,36, 37 vs 20, 25, 38 1 scl 44 adr 2 sda 6 swc 4 swb 3 swa 7 cao 8 cco 9 cbo v agc v agc d/a d/a 4-bit latch 4-bit latch 4-bit latch cprf 16 gnd
3 u2731b 4671c?dab?06/04 pin configuration figure 2. pinning 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 adr osco osci vd pd vs gnd gnd c2vc b2vco c1vc gnd gnd ifout cpif ifagcin1 ifagcin2 vs ifin1 ifin2 sda swa swb fref swc cao cbo gnd rfa1 rfb2 cprf gnd saw1 saw2 vs sli wagc rfb1 scl plck b1vco rfa2 gnd cco
4 u2731b 4671c?dab?06/04 pin description pin symbol function 1 scl clock (simple two-wire bus) 2 sda data (simple two-wire bus) 3 swa switching output (open collector) 4 swb switching output (open collector) 5 fref reference frequency output (for u2731b) 6 swc switching output (open collector) 7 cao output of d/a converter a 8 cco output of d/a converter b 9 cbo output of d/a converter c 10 gnd ground 11 gnd ground 12 rfa1 input 1 of rf amplifier a (differential) 13 rfa2 input 2 of rf amplifier a (differential) 14 rfb1 input 1 of rf amplifier b (differential) 15 rfb2 input 2 of rf amplifier b (differential) 16 cprf charge-pump output (rf agc block) 17 gnd ground 18 saw1 saw driver output 1 (differential) 19 saw2 saw driver output 2 (differential) 20 vs supply voltage rf part 21 sli agc mode selection (charge-pump current high) 22 wagc agc mode selection (charge-pump current off) 23 ifin2 input 2 of if amplifier (differential) 24 ifin1 input 1 of if amplifier (differential) 25 vs supply voltage if part 26 ifagcin2 input 2 of if agc block (differential) 27 ifagcin1 input 1 of if agc block (differential) 28 cpif charge-pump output (if agc block) 29 ifout if output (single ended) 30 gnd ground 31 gnd ground 32 c1vc collector 1 of vco 33 b2vco base 2 of vco 34 b1vco base 1 of vco 35 c2vc collector 2 of vco 36 gnd ground 37 gnd ground 38 vs supply voltage pll 39 pd tri-state charge pump output 40 vd active filter output
5 u2731b 4671c?dab?06/04 functional description the u2731b represents a monolithically integrated front end ic designed for applica- tions in dab receivers. it covers rf and if signal processing, the pll section and also supporting functions such as d/a converters or switching outputs. two rf input ports offer the possibility of handling various input signals such as a down- converted l-band signal or band ii and band iii rf signals. the high dynamic range of the rf inputs and the use of a gain-controlled amplifier and a gain-controlled mixer in the rf section offer the possibility of handling even strong rf input signals. the lo signal of the first mixer stage is derived from an on-chip vco. the vco frequency is either divided by two or directly fed to the mixer. in this way band ii and band iii can be covered easily. in the if section, it can be selected if the first if signal is down-converted to a second, lower if or if it is simply amplified to appear at the if output. if the down-conversion option is chosen, it can be selected if the lo signal of the if mixer is directly derived from the reference signal of the pll, or if it is generated by doubling its frequency. the amplifiers in the if section are gain-controlled in similar fashion to the rf section. the rf and the if part also contain agc functional blocks which generate the agc control voltages. the agc thresholds can be defined by means of three on-chip 4-bit d/a converters. the frequency of the vco is locked to a reference frequency by an on-chip fractional-n pll circuit which guarantees a superior phase-noise performance. the reference frequency is generated by an on-chip crystal oscillator which can also be overdriven by an external signal. starting from a minimum value, the reference scaling factor is freely programmable. three switching outputs can be used for various switching tasks on the front end board. three 8-bit d/a converters providing an output voltage between 0 and 8.5 v are used to improve the tuning voltages of the tuned preselectors which are derived from the tuning voltage of the vco. 41 plck lock-indicating output (open collector) 42 osci input of reference oscillator/buffer 43 osco output of reference oscillator/buffer 44 adr address selection (simple two-wire bus) pin description (continued) pin symbol function
6 u2731b 4671c?dab?06/04 rf part rf gain-controlled amplifier in order to support two different channels, two identical input buffers with balanced inputs (rfa1, rfa2; rfb1, rfb2) are integrated. by setting the two-wire bus bits m0 and m1 (see section ?simple two-wire bus functions? on page 11), the active buffer can be selected. the buffers are followed by a gain-controlled amplifier whose output signal is fed to a gain-controlled mixer. the rf amplifiers are capable of handling input signals up to a typical power of -6 dbm without causing third-order intermodulation com- ponents stronger than -40 dbc. rf gain-controlled mixer, vco and lo divider the purpose of the rf mixer is to down-convert the incoming signal (band ii, band iii) to an if frequency which is typically 38.912 mhz. this if signal is fed to an agc voltage- generation block (which is described in the following section) and an output buffer stage. this driver stage has a low output impedanc e and is capable of driving a saw filter directly via its differential output pins saw1, saw2. the mixer's lo signal is generated by a balanced voltage-controlled oscillator whose frequency is stabilized by a frac- tional-n phase-locked loop. an example circuit of the vco is shown in figure 12 on page 23. the oscillator's tank is applied to the pins b1vc, c1vc, b2vc, c2vc as shown in the application circuit in figure 8 on page 20. before the vco's signal is fed to the rf mixer, it has to pass an lo divi der block where the vco frequency is either divided by 1 or 2. the setting of this divider is defined by means of the two-wire bus bits m0 and m1 as indicated in the section ?simple two-wire bus functions? on page 11. this feature offers the possibility of covering both band ii and band iii by tuning the vco frequency in the range between 200 mhz to 300 mhz. rf agc voltage-generation block in this functional block, the output signal of the rf mixer is amplified, weakly bandpass filtered (transition range: x8 mhz to x80 mhz), rectified and finally lowpass filtered. the voltage derived in this power-measurement process is compared to a voltage threshold (th1) which can be digitally controlled by an on-chip 4-bit d/a converter. the setting of this converter is defined by means of the two-wire bus bits tai (i = 1, 2, 3, 4). depending on the result of this comparison, a charge pump feeds a positive or negative current to pin cprf in order to charge or discharge an external capacitor. the voltage of this external capacitor can be used to control the gain of an external preamplifier or attenua- tor stage. furthermore, it is also used to generate the internal control voltages of an rf amplifier and mixer. for this purpose, the voltage at pin cprf is compared to a voltage threshold (th2) which is also controlled by an on-chip 4-bit d/a converter whose setting is fixed by the two-wire bus bits tbi (i =1, 2, 3, 4). by means of the input pins wagc and sli the current of the rf agc charge pump can be selected according to the following table: table 1. current of charge pump the function can be seen in figure 11 on page 22. wagc sli charge-pump current/a high x off low low 50 a (slow mode) low high 190 a (fast mode)
7 u2731b 4671c?dab?06/04 if part if gain-controlled amplifier the signal applied to the balanced input pins ifin1, ifin2 is amplified by a gain-con- trolled if amplifier. the gain-control signal is generated by an if agc voltage- generation block which is described in the next section. to avoid offset problems, the output of the gain-controlled amplifier is fed to an amplifier/mixer combination by ac coupling. if gain-controlled amplifier/mixer combination depending on the setting of the two-wire bus bits m2, m3, the output signal of the gain- controlled if amplifier is either mixed down to a lower, second if or, after passing an output buffer stage, amplified before it appears at the single-ended output pin ifout. if the down-conversion option is chosen this circuit still offers two possibilities concerning the synthesis of the if mixers lo signal. this lo signal is derived from the pll's on- chip reference oscillator. by means of the two-wire bus bits m2, m3, it can be decided whether the reference frequency is doubled before it is given to the mixer's lo port, or if it is used directly. the gain-control voltage of the amplifier/mixer combination is similar to the gain-controlled if amplifier generated by an internal gain-control circuit. if agc voltage-generation block the purpose of this gain-control circuit in the if part is to measure the power of the incoming signal at the balanc ed input pins ifagcin1, ifagcin2, to compare it with a certain power level and to generate a control voltage for the if gain-controlled amplifiers and mixer. this architecture offers the possibility of ensuring an optimal use of the dynamic range of the a/d converter which transforms the output signal at pin ifout from the analog to the digital domain despite possible insertion losses of (anti-aliasing) filters which are arranged in front of the converter. such a constellation is indicated in the application circuit in figure 8 on page 20. the incoming signal at the balanced input pins ifagc1, ifagc2 passes a power-mea- surement process similar to that described in the section ?rf agc voltage-generation block? on page 6. for flexibility reasons, no bandpass filtering is implemented. the volt- age derived in this process is compared to a voltage threshold (th3) which is defined by an on-chip 4-bit d/a converter. the setting of this converter is defined by the two-wire bus bits tci (i = 1, 2, 3, 4). depending on the result of this comparison, a charge pump feeds a positive or negative current to pin cpif in order to charge or discharge an exter- nal capacitor. by means of the pins wagc and sli the current of this charge pump can be selected according to the following table: table 2. current of charge pump the function can be seen in figure 12 on page 23. wagc sli charge-pump current/a high x off low low 50 a (slow mode) low high 190 a (fast mode)
8 u2731b 4671c?dab?06/04 pll part the purpose of the pll part is to perform a phase lock of the voltage-controlled rf oscillator to an on-chip crystal reference oscillator. this is achieved by means of a spe- cial phase-noise-shaping technique based on the fractional-n principle which is already used in atmel's u2733b frequency synthesizer series. it concentrates the phase detec- tor's phase-noise contribution to the spec trum of the controlled vco at frequency positions where it does not impair the quality of the received dab signal. a special prop- erty of the transmission technique which is used in dab is that the phase-noise- weighting function which measures the influe nce of the lo's phase noise to the phase information of the coded signal in a dab receiver has zeros, i.e., if phase noise is con- centrated in the position of such zeros as discrete lines, the dab signal is not impaired as long as these lines do not exceed a se t limit. for dab mode i, this phase-noise- weighting function is shown in figure 3. figure 3. phase-noise-weighting function it is important to realize that this function shows zeros in all distances from the center line which are multiples of the carrier spacing. the technique of concentrating the phase noise in the positions of such zeros is patent protected. reference oscillator an on-chip crystal oscillator generates the reference signal which is fed to the reference divider. as already described in the section ?if gain-controlled amplifier/mixer combi- nation? on page 7, the lo signal for the mixer in the if section is derived. by applying a crystal to the pins osci, osco, see figure 8 on page 20, this oscillator generates a highly stable reference signal. if an external reference signal is available, the oscillator can be used as an input buffer. in such an application, see figure 9 on page 21, the reference signal has to be applied to the pin osci and the pin osco must be left open. reference divider starting from a minimum value, the scaling factor sfref of the 9-bit reference divider is freely programmable by means of the two-wire bus bits ri (i = 0, ..., 8) according to 0,00 0,20 0,40 0,60 0,80 1,00 1,20 1,40 1,60 1,80 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 df/hz pnwf sf ref r i 2 i =
9 u2731b 4671c?dab?06/04 if, for example, a frequency raster of 16 khz is requested, the scaling factor of the refer- ence divider has to be specified in such a way that the division process results in an output frequency which is four times higher than the desired frequency raster, i.e., the comparison frequency of the phase detector equals four times the frequency raster. by changing the division ratio of the main divider from n to n+1 in an appropriate way (fractional-n technique), this frequency raster is interpolated to deliver a frequency spacing of 16 khz. so effectively a reference scaling divide factor is achieved. by setting, the two-wire bus bit t, a test signal representing the divided input signal can be monitored at the switching output swa. main divider the main divider consists of a fully programmable 13-bit divider which defines a division ratio n. the applied division ratio is either n or n+1 according to the control of a special control unit. on average, the scaling factors sf = n + k/4 can be selected where k = 0, 1, 2 or 3. in this way, vco frequencies f vco = 4 (n+k/4) f ref /(4 sf ref ) can be synthesized starting from a reference frequency fref. if we define sf eff = 4 n + k and sf ref,eff =4 sf ref (previous section), then f vco = sf eff f ref /sf ref,eff , where sf eff is defined by 15 bits. in the following, this circuit is described in terms of sf eff and sf ref,eff . sf eff has to be pro- grammed via the two-wire bus interface. an effective scaling factor from 2048 to 32767 can be selected by means of the two-wire bus bits ni (i = 0, ..., 14) according to by setting the two-wire bus bit t, a test signal representing the divided input signal can be monitored at the switching output swc. when the supply voltage is switched on, both the reference divider and the programma- ble divider are kept in reset state until a complete scaling factor is written onto the chip. changes in the setting of the programmable divider become active when the corre- sponding two-wire bus transmission is co mpleted. an internal synchronization procedure ensures that such changes do not become active while the charge pump is sourcing or sinking current at its output pin. this behavior allows a smooth tuning of the output frequency without restricting the controlled vco's frequency spectrum. phase comparator and charge pump the tri-state phase detector causes the charge pump to source or to sink current at the output pin pd depending on the phase relation of its input signals which are provided by the reference and the main divider respectively. four different values of this current can be selected by means of the two-wire bus bits i50 and i100. by use of this option, changes of the loop characteristics due to the variation of the vco gain as a function of the tuning voltage can be reduced. the charge-pump current can be switched off using the two-wire bus bit tri. a change in the setting of the charge pump current becomes active when the corresponding two-wire bus transmission is completed. as described for the setting of the scaling factor of the programmable divider, an internal synchronization procedure ensures that such changes do not become active while the charge pump is sourcing or sinking current at its output pin. this behavior allows a change in the charge pump current without restricting the controlled vco's frequency spectrum. sf ref,eff 4r i 2 i = sf eff n i 2 i =
10 u2731b 4671c?dab?06/04 a high-gain amplifier (output pin: vd), which is implemented in order to construct a loop filter, as shown in the application circuit, c an be switched off by means of the two-wire bus bit os. an internal lock detector checks if the phase difference of the input signals of the phase detector is smaller than approximately 250 ns in seven subsequent comparisons. if phase lock is detected, the open collector output pin plck is set to h (logical value). it should be noted that the output current of this pin must be limited by external circuitry as it is not limited internally. if the two-wire bus bit tri is set to h, the lock detector function is deactivated and the logical value of the plck output is undefined. switching outputs three switching outputs controlled by the two-wire bus bits swa, swb, swc can be used for any switching task on the front-end board. the currents of these outputs are not limited internally. they have to be limited by an external circuit. d/a converters three d/a converters, a, b and c, offer the possibility of generating three output volt- ages at a resolution of 8 bits. these voltages appear at the output pins cao, cbo and cco. the converters are controlled via the two-wire bus interface by means of the con- trol bits ca0, ..., ca7, cb0, ..., cb7 and cc0, ..., cc7 respectively as described in the section ?two-wire bus instruction codes?. the output voltages are defined as where vm = 4.25 v nominally. due to the rail-to-rail outputs of these converters, almost the full voltage range from 0 to 8.5 v can be used. a common application of these converters is the digital synthesis of cont rol signals for the tuning of preselectors. the output pins cau, cbo and cco must be blocked externally with capacitors (100 nf) as shown in the application circuit (see figure 8 on page 20). v cao v m 128 --------- - caj j = 0 7 2 j = v cbo v m 128 --------- - cbj j = 0 7 2 j = v cco v m 128 --------- - ccj j = 0 7 2 j =
11 u2731b 4671c?dab?06/04 simple two-wire bus interface via its two-wire bus interface, various functions can be controlled by a microprocessor. these functions are outlined in the followi ng table ?simple two-wire bus instruction codes? on page 11 and in the section ?simple two-wire bus functions? on page 11. the programming information is stored in a set of internal registers. by means of the pin adr, two different two-wire bus addresses can be selected as described in the section ?electrical characteristics?. in figure 6 on page 19, the two-wire bus timing parameters are explained, figure 7 on page 20 shows a typical two-wire bus pulse diagram. simple two-wire bus functions table 3. simple two-wire bus instruction codes description msb lsb address 1 1 0 0 0 as1 0 0 a byte 1 0 0 x x x n 14 n 13 n 12 a byte 2 x x n 11 n 10 n 9 n 8 n 7 n 6 a byte 3 x x n 5 n 4 n 3 n 2 n 1 n 0 b byte 1 0 1 x r 8 ta3 ta2 ta1 ta0 b byte 2 r 7 r 6 r 5 r 4 tb3 tb2 tb1 tb0 b byte 3 r 3 r 2 r 1 r 0 tc3 tc2 tc1 tc0 c byte 1 1 0 x x x x x x c byte 2 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 c byte 3 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 d byte 1 1 1 0 os t tri i100 i50 d byte 2 swa swb swc x m3 m2 m1 m0 d byte 3 cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 as1 defines the two-wire bus address n i deffective scaling factor (sfeff) of the main divider r i scaling factor (sf ref,eff ) of the reference divider sf ref,eff = 4 r i 2 i tai define the setting of a 4-bit d/a converter controlling the threshold, th1, of the rf agc to adjust the controlled output power tbi define the setting of a 4-bit d/a converter controlling the threshold, th2, which determines the activation voltage for the internal rf agc tci define the setting of a 4-bit d/a converter controlling the threshold, th3, of the if agc to adjust the output power cai, cbi, cci define the setting of the three d/a converters a, b and c (i = 0, ..., 7) os os = high switches off the tuning output t for t = high, reference signals describing the output frequencies of the reference divider and programmable divider are monitored at swa (reference divider) and swc (programmable divider). tri tri = high switches off the charge pump sf eff n i 2 i =
12 u2731b 4671c?dab?06/04 i50 and i100 define the charge pump current: table 4. current of charge pump mi defines the operation mode: table 5. mode selection note: sw = high switches on the output current ( = a, b, c) simple two-wire bus data transfer format: start - adr - ack - - stop the consists of a sequence of a bytes, b bytes, c bytes and d bytes each followed by ack. always a triplet of these bytes (a, b, c or d) has to be completed before a new triplet is started. if no new triplet is started the transmission can be finished before the current triplet is finished. examples: start - adr - ack - db1 - ack - db2 - ack - db3 - ack - cb1 - ack - cb2 - ack - cb3 - ack - ab1 - ack - ab2 - ack - ab3 - ack - bb1 - ack - bb2 - ack - bb3 - ack - stop start - adr - ack - cb1 - ack - cb2 - ack - stop however: start - adr - ack - db1 - ack - cb1 -ack - stop is not allowed. description: i50 i100 charge-pump current (nominal)/a low low 50 high low 100 low high 150 high high 200 m3 m2 m1 m0 mode low low x x f lo,ifmix = f ref low high x x f lo,ifmix = 2 f ref high high x x if mixer switched off x x low low rf mixer a active, f lo,rfmix = f vco x x high low rf mixer b active, f lo,rfmix = f vco x x high high rf mixer b active, f lo,rfmix = f vco /2 start start condition stop stop condition ack acknowledge adr address byte bi byte i ( = a, b, c, d; i = 1, 2, 3)
13 u2731b 4671c?dab?06/04 simple two-wire bus timing the values of the periods shown are specified in the table ?electrical characteristics? on page 15. more detailed information can be taken from the ?application note 1.0 (two- wire bus description)?. please note, that due to the two-wire bus specification, the msb of a byte is transmitted first, the lsb last. figure 4. two-wire bus timing figure 5. typical pulse diagram t buf t r t f t hdstat t hdsta t low t hddat t high t sudat t susta t sustp sda scl stop start start stop sda a byte 3 ack c byte 1 ack c byte 2 ack stop scl address byte ack a byte 1 a byte 2 ack start ack sda scl
14 u2731b 4671c?dab?06/04 absolute maximum ratings parameters symbol min. max. unit supply voltage v s -0.3 +9.5 v junction temperature t j 150 c storage temperature t stg -40 +150 c differential input rf amplifier, pins 12 and 13 v rfa1,2 500 mv rms pins 14 and 15 v rfb1,2 500 mv rms externally applied voltage at rf charge pump output, pin 16 v cprf 0.5 6.75 v pin 28 v cpif 0.5 6.25 v wagc input voltage, pin 22 v wagc -0.3 5.5 v sli input voltage, pin 21 v sli -0.3 5.5 v differential base input vco, pins 33 and 34 v bivc 500 mv rms differential input if amplifier, pins 23 and 24 v ifin 500 mv rms differential input if agc block, pins 26 and 27 v ifagcin 500 mv rms reference input voltage (ac), pin 42 v osci 1v pp two-wire bus input/output voltage, pins 1 and 2 scl, sda -0.3 5.5 v sda output current, pin 2 sda 5 ma address select voltage, pin 44 adr -0.3 5.5 v switch output voltage; pins 3, 4 and 6 sw -0.3 9.5 v switch output current sw 4ma plck output voltage, pin 41 plck -0.3 5.5 v plck output current, pin 41 plck 0.5 ma thermal resistance parameters symbol value unit junction ambient (soldered on application board) r thja 40 k/w operating range parameters symbol value unit supply voltage v s 8.0 to 9.35 v ambient temperature range t amb -40 to +85 c
15 u2731b 4671c?dab?06/04 electrical characteristics test conditions (unless otherwise specified): v s = 8.5 v, t amb = 25c no. parameters test conditions pin symbol min. typ. max. unit type* 1 overall characteristics 20, 25, 38 1.1 supply voltage v s 8.0 8.5 9.35 v 1.2 minimum supply current v(cprf) = v(cpif) < 0.8 v m3 = m2 = high m1 = m0 = low tai = tci = 0000; tbi = 1000 swa = swb = swc = low tri = low; plck = low i100 = i50 = low; v(adr) = open sli = low; wagc = high i s,min 74 ma b 1.3 maximum supply current 3.4v 200 ? , tai = 0000 18, 19 -7 dbm d 2.9 agc threshold (th1) tai = ?1000? tai = ?1111? tai = ?0000? output power, differential controlled by two-wire bus bits tai; rl (saw1, saw2) = 200 ? 18, 19 p th,rf 50 90 160 10 120 mv rms a b b *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. the phase detector?s phase-noise contribution to the vco?s frequency spectrum is determined by the operating frequency of the phase detector divided by 4 according to the fractional-n technique (regularly: 16 khz).
16 u2731b 4671c?dab?06/04 2.10 agc threshold (th2) (internal agc) upper limit (tbi = 1111) lower limit (tbi = 0000) controlled by two-wire bus bits tbi; p in,max = -25 dbm 16 v int agc,rf 1.0 5.1 1.5 1.8 v v b a 2.11 output impedance single ended; f(saw1) = 39 mhz 18 (19) z out,saw 30 ? 3 vco 3.1 phase noise ? f = 10 khz l(f) -88 dbc/hz d 3.2 phase noise f lo 100 400 mhz d 4 if part 4.1 voltage gain ifin2 blocked (see figure 9 on page 21) f lo,ifmix = f ref or f lo,ifmix = 2 f ref 24 29 g v, t o t 42 44 48 db a 4.2 voltage gain ifin2 blocked (see figure 9 on page 21) if mixer switched off 24 29 g v, t o t 45 47 51 db a 4.3 agc range if 42 44 48 db a 4.4 noise figure (double side band) ifin2 blocked 24 29 nf dsb 11 db d 4.5 maximum input power level ifin2 blocked, 3rd order intermodulation distance 40 dbc; rl(ifout) = 1 k; tci = 0000; r 10 = 4.7 k, r 11 = 1.8 k 24 p in,max -20 dbm c 4.6 input frequency range 23, 24 f in,ifin 10 60 mhz d 4.7 input impedance ifin2 blocked, f if,ifin = 38.912 mhz 23, 24 z in,ifin 600 - j1000 ? d 4.8 output frequency range single ended 29 f out,ifo 1 45 mhz d 4.9 output impedance single ended f out,ifo (3 mhz) f out,ifo (20 mhz) f out,ifo (38.9 mhz) 29 z out,ifout 20 + j50 65 + j35 58 - j25 ? ? ? d 5 rf agc unit 5.1 positive charge pump current, fast mode v wagc = low v sli = high 16 icprf pos,fm 145 180 220 a a 5.2 negative charge pump current, fast mode v wagc = low v sli = high 16 icprf neg,fm -220 -180 -145 a a 5.3 positive charge pump current, slow mode v wagc = low v sli = low 16 icprf pos,sm 30 40 52 a a 5.4 negative charge pump current, fast mode v wagc = low v sli = low 16 icprf neg,fm -52 -40 -30 a a 5.5 minimum gain control voltage vagc min 0.75 v c electrical characteristics (continued) test conditions (unless otherwise specified): v s = 8.5 v, t amb = 25c no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. the phase detector?s phase-noise contribution to the vco?s frequency spectrum is determined by the operating frequency of the phase detector divided by 4 according to the fractional-n technique (regularly: 16 khz).
17 u2731b 4671c?dab?06/04 5.6 maximum gain control voltage vagc max 6.6 v c 6 if agc unit 6.1 positive charge pump current, fast mode v wagc = low v sli = high 28 icpif pos,fm 145 180 220 a a 6.2 negative charge pump current, fast mode v wagc = low v sli = high 28 icpif neg, fm -220 -180 -145 a a 6.3 positive charge pump current, slow mode v wagc = low v sli = low 28 icpif pos, sm 30 40 52 a a 6.4 negative charge pump current, slow mode v wagc = low v sli = low 28 icpif neg, sm -52 -40 -30 a a 6.5 window agc mode charge pump current v wagc = high 28 icpif wagc -4 0 +4 a a 6.6 minimum gain control voltage 28 vagcif min 0.75 v c 6.7 maximum gain control voltage 28 vagcif max 5.9 v c 6.8 control voltage for activated wagc wagc = high 22 vwagc high 2.0 v a 6.9 control voltage for deactivated wagc wagc = low 22 vwagc low 0.7 v a 6.10 control voltage for activated sli sli = high 21 vsli high 2.0 v a 6.11 control voltage for deactivated sli sli = low 21 vsli low 0.7 a 7 pll part 7.1 effective scaling factor of programmable divider sf eff 2048 32766 d 7.2 effective scaling factor of reference divider sf ref,eff 144 2047 d 7.3 tuning step 16 khz d 8 ref input 42 8.1 input frequency range internal oscillator overdriven f ref 5 30 mhz b 8.2 input sensitivity internal oscillator overdriven v ref,min 50 mv rms a 8.3 maximum input signal internal oscillator overdriven v ref,max 300 mv rms d 8.4 input impedance single ended z ref 2 || 2.5 k ? /pf d 9 ref output 5 9.1 output voltage 1.5 k ? || 2.5 pf load v out,ref 65 100 mv rms a electrical characteristics (continued) test conditions (unless otherwise specified): v s = 8.5 v, t amb = 25c no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. the phase detector?s phase-noise contribution to the vco?s frequency spectrum is determined by the operating frequency of the phase detector divided by 4 according to the fractional-n technique (regularly: 16 khz).
18 u2731b 4671c?dab?06/04 10 phase detector 39 10.1 charge-pump current i100 = high, i50 = high 160 200 240 a a 10.2 i100 = high, i50 = low 120 150 180 a a 10.3 i100 = low, i50 = high 80 100 120 a a 10.4 i100 = low, i50 = low 35 50 65 a a 10.5 high impedance mode tri = high i pd,tri -100 100 na a 10.6 effective phase noise (1) i pd = 203 ma l pd -159 dbc/ hz c 11 lock indication 41 11.1 leakage current v plck = 5.5 v i plck,l 10 a a 11.2 saturation voltage i plck = 0.25 ma v plck,sat 0.5 v a 12 switches 3, 4, 6 12.1 leakage current i sw,l 10 a a 12.2 saturation voltage i sw = 0.25 ma v sw,sat 0.5 v a 13 address selection 44 13.1 as1 = 0 0 0.1 v s c 13.2 as1 = 1 0.4 v s 0.6 v s c 14 d/a converters 7, 8, 9 14.1 output voltage c 7 = high c 0 to c 6 = low = a, b, c v m 4.05 4.25 4.45 v a 14.2 variation of v m v s = 8.00 to 9.35 v ? v m,vs -50 50 mv a 14.3 variation of v m t amb = -40 to +85 c ? v m,temp 20 mv c 14.4 accuracy vc n-n v m /128 n = 24 ... 232, = a, b, c ? v c n -70 70 mv a 14.5 maximum output current i caomax i cbomax i ccomax 20 a c 15 simple two-wire bus 1, 2 15.1 input voltage scl/sda high 3 5.5 v d 15.2 input voltage scl/sda low 1.5 v d 15.3 output voltage sda (open collector) i sda = 2 ma, sda = low 0.4 v d 15.4 scl clock frequency 0.1 100 khz d 15.5 rise time (scl, sda) t r 1 s d 15.6 fall time (scl; sda) t f 300 s d 15.7 time before new transmission can start t buf 4.7 s d electrical characteristics (continued) test conditions (unless otherwise specified): v s = 8.5 v, t amb = 25c no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. the phase detector?s phase-noise contribution to the vco?s frequency spectrum is determined by the operating frequency of the phase detector divided by 4 according to the fractional-n technique (regularly: 16 khz). i pd4 i pd3 i pd2 i pd1
19 u2731b 4671c?dab?06/04 figure 6. application circuit 15.8 scl high period t high 4 s d 15.9 scl low period t low 4.7 s d 15.10 hold time start t hdsta 4 s d 15.11 setup time start t susta 4.7 s d 15.12 setup time stop t sustp 4.7 s d 15.13 hold time data t hddat 0 s d 15.14 setup time data t sudat 250 ns d electrical characteristics (continued) test conditions (unless otherwise specified): v s = 8.5 v, t amb = 25c no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. the phase detector?s phase-noise contribution to the vco?s frequency spectrum is determined by the operating frequency of the phase detector divided by 4 according to the fractional-n technique (regularly: 16 khz). address select voltage 3.3 44 43 42 41 40 39 38 37 36 35 12345678910 u2731b 34 33 32 31 30 29 28 27 26 25 11 12 13 14 15 16 17 18 19 20 24 23 21 22 68p 2.2k 22k 8.5v 33p 18p 10n 100p 4.7p 2.2p 2.2p 4.7p 2.2k 3.3n 47nh 2.2p 27p bb545 3.3n 33k 33k 1.2n 8.5v 51k 4.7k microcontroller saw filter 8.5v vagcif antialiasing filter 4.7k 1.8k wagc micro- controller 220n 1n scl sda switches 100n 100n 100n rfa rfb vagcrf 3.3 ad-converter sli 8.5v 8.5v u2730b-n pre- selector 4.7k 100p 100p bc846b 10n miro crystal 16.384 mhz cxat-t1 10n 10n 10n 10n s+m x6922m 680nh 10n 10n 1n 1n 1n 1n 76k 76k 76k 9k 9k 9k
20 u2731b 4671c?dab?06/04 application circuits of the reference oscillator figure 7. oscillator operation figure 8. oscillator overdriven osci osco 33p 68p 18p reference divider osci osco reference divider 1n reference signal 50
21 u2731b 4671c?dab?06/04 figure 9. measurement circuit for electrical characteristics address select voltage 3.3 44 43 42 41 40 39 38 37 36 35 12345678910 u2731b 34 33 32 31 30 29 28 27 26 25 11 12 13 14 15 16 17 18 19 20 24 23 21 22 10n 2.2k 22k 8.5v 100p 4.7p 2.2p 2.2p 4.7p 2.2k 3.3n 47nh 2.2p 27p bb545 3.3n 33k 8.5v 51k 4.7k microcontroller 8.5v vagcif 1.8k wagc micro- controller 220n 1n scl sda switches 100n 100n 100n rfa rfb vagcrf 3.3 sli 8.5v 8.5v u2730b-n pre- selector ref in 4.7k 1k 4.7k 50 ifad ifin 50 50 o1sa 51 100 10n 33k 1.2n 100p bc846b 10n 47n 10n 10n 100p 10n 10n 10n 10n 1n 1n 1n 1n 76k 76k 76k 9k 9k 9k
22 u2731b 4671c?dab?06/04 figure 10. rfagc voltage-generation block circuit figure 11. ifagc voltage-generation block circuit wagc buf_in agc_bp agc_rect r agc_comp charge pump cprf agcrf voltage agc_thresh v ref c agc saw1 saw2 d/a ida tai d/a tbi ida v ref sli vagc,int agc_tp ifagc1 ifagc2 vagc r agc_thresh v ref d/a ida charge pump sli wagc ifamp ifmx tci antialiasing filter r2 ifad r1 a/d converter agcif cprf
23 u2731b 4671c?dab?06/04 figure 12. vco circuit phase-noise performance (example: sf eff = 16899, sf ref,eff = 1120, f ref = 17.92 mhz, i pd = 200 ma, spectrum analysis: hp7000) figure 13. phase-noise over frequency c1vc b2vc b1vc c2vc v bias v s v tune center 270.384 mhz span 10.00 khz rb 100 hz vb 100 hz st 3.050 sec < -70 dbc/hz 10.00 db/div center 270.384 mhz span 200.0 khz 10.00 db/div rb 1.00 khz vb 1.00 khz st 600.0 msec
24 u2731b 4671c?dab?06/04 package information ordering information extended type number package remarks u2731b?nfn sso44 tube u2731b?nfng1 sso44 taped and reeled technical drawings according to din specifications package sso44 dimensions in mm 0.25 0.10 0.3 0.8 18.05 17.80 16.8 2.35 9.15 8.65 7.50 7.30 10.50 10.20 0.25 44 23 1 22
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