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www.fairchildsemi.com features no potentiometer required direct interface to scr supply voltage derived from ac line?6v shunt adjustable sensitivity grounded neutral fault detection meets ul943 standards 450 m a quiescent current ideal for 120v or 220v systems description the lm1851 is a controller for ac outlet ground fault interrupters. these devices detect hazardous grounding con- ditions (example: a pool of water and electrical equipment connected to opposite phases of the ac line) in consumer and industrial environments. the output of the ic triggers an external scr, which in turn opens a relay circuit breaker to prevent a harmful or lethal shock. full advantage of the u.s. ul943 timing speci?ation is taken to ensure maximum immunity to false triggering due to line noise. a special feature is found in circuitry that rapidly resets the integrating timing capacitor in the event that noise pulses introduce unwanted charging currents. also, ?p-?p is included that ensures ?ing of even a slow circuit breaker relay on either half-cycle of the line voltage when external full wave recti?ation is used. the application circuit can be con?ured to detect both normal faults (hot wire to ground) and grounded neutral faults. block diagram 65-1851-01 +v s timing capacitor sensitivity set resistor i th sense amplifier output i th for i f > 0 3i th for i f = 0 i th = i f q2 q1 latch d3 i 2 q3 q4 a1 d1 i f ground non-inverting input 10v inverting input scr trigger q5 d2 +v s lm1851 ground fault interrupter rev. 1.0.0
lm1851 product specification 2 functional description the voltage at the supply pin is clamped to +26v by the internal shunt regulator d3. this shunt regulator also generates an arti?ial ground voltage for the noninverting input of a1 (shown as a +10v source). a1, q1, and q2 act a a current mirror for fault current signals (which are derived from an external transformer). when a fault signal is present, the mirrored current charges the external timing capacitor until its voltage exceeds the latch trigger threshold (typically 17.5v). when then this threshold is exceeded, the latch engages and q3 turns off, allowing i 2 to drive the scr connected to pin 1. extra circuitry in the feedback path of a1 works with the switched current source i 1 to remove any charge on c t induced by noise in the transformer. if no fault current is present, then i 1 discharges c t with a current equal to 3 i th , where i th is the value of current set by the external r set resistor. if fault signals are present at the input of a1 (which is held at virtual ground, +10v), one of the two current mirrors in the feedback path of a1 (q4 and q5) will become active, depending on which half-cycle the fault occurs. this action will raise the voltage at v s , switching i 1 to a value equal to i th , and reducing the discharge rate of c t to better allow fault currents to charge it. notice that i th discharges c t during both half-cycles of the line, while i f only charges c t during the half-cycle in which i f exits pin 2 (since q1 will only carry fault current in one direction). thus, during one half-cycle, i f -i th charges c t , while during the other half-cycle i th discharges it. pin assignments scr trigger 65-1851-02 ?input + input ground +v s c t r set amp out 1 2 3 4 8 7 6 5 de?ition of terms normal fault an unintentional electrical path, r b , between the load termi- nal of the hot line and the ground, as shown by the dashed lines in figure1. figure 1. normal fault grounded neutral fault an unintentional electrical path between the load terminal of the neutral line and the ground, as shown by the dashed lines in figure 2. figure 2. grounded neutral fault hot gfi neutral line hot r load r b neutral r g 65-1851-03 hot gfi neutral line hot r load r in neutral r g 65-1851-05
product specification lm1851 3 normal fault plus grounded neutral fault the combination of the normal fault and the grounded neutral fault, as shown by the dashed lines in figure 3. figure 3. normal fault plus grounded neutral fault absolute maximum ratings thermal characteristics parameter conditions min max units supply current 19 ma power dissipation 570 mw operating temperature -40 70 c lead soldering temperature soic, 10 seconds 260 c dip, 60 seconds 300 c parameter conditions min max units maximum junction temperature 125 c maximum p d t a < 50 c dip 468 mw soic 300 thermal resistance, q ja dip 160 c/w soic 240 for ta > 50 c, derate at dip 6.25 mw/ c soic 4.17 hot gfi neutral line hot r load r b neutral r g 65-1851-04 r n
lm1851 product specification 4 dc electrical characteristics (t a = +25 c, i shunt = 5 ma) notes: 1. this external applied current is in addition to the internal ?utput drive current?source. ac electrical characteristics (t a = +25 c, i shunt = 5 ma) notes: 1. average of 10 trials. 2. required ul sensitivity tolerance is such that external trimming of lm1851 sensitivity is necessary. parameters test conditions min typ max units power supply shunt regulator voltage pin 8, average value 22 26 30 v latch trigger voltage pin 7 15 17.5 20 v sensitivity set voltage pin 8 to pin 6 6 7 8.2 v output drive current pin 1 with fault 0.5 1 2.4 ma output saturation voltage pin 1 without fault 100 240 mv output saturation resistance pin 1 without fault 100 w output external current sinking capability 1 pin 1 without fault, v pin1 held to 0.3v 25 ma noise integration sink current ratio pin 7, ratio of discharge currents between no fault fault and fault conditions 2.0 2.8 3.6 m a/ m a parameters conditions min typ max units normal fault current sensitivity 2 see figure 9 3 5 7 ma normal fault trip time 1 500 w fault, see figure 10 18 ms normal fault with grounded 500 w normal fault 18 ms neutral fault trip time 1 2 w neutral, see figure 10
product specification lm1851 5 typical performance characteristics (t a = +25 c) figure 4. average trip time vs. fault current figure 5. normal fault current threshold vs. r set figure 6. output drive current vs. output voltage figure 7. pin 1 saturation voltage vs. external load current, i l 65-1851-07 100k 1m 10m 100 10 1 r set ( w ) fault current on line [ma(rms)] 7v i f (rms)* x (0.91) sense transformer 1000:1 r set = 65-1851-06 0.01 0.1 1 1000 100 10 0 trip time (seconds) fault current (ma) circuit of figure 10 ul943 normal fault 10 65-1851-08 1000 100 10 0 output voltage @ v pin1 (v) output drive current @ pin 1 ( a) 35 30 25 20 15 10 5 0 a 5 ma 31v 1 ma 8 1 4 v pin1 65-1851-09 0.1 1 10 100 10 1 0.1 0.01 external load current (ma) pin 1 saturation voltage (v) a 5 ma 31v i l 1 ma 8 1 4
lm1851 product specification 6 applications discussion a typical ground fault interrupter circuit is shown in figure 10. it is designed to operate on 120 vac line voltage with 5 ma normal fault sensitivity. a full-wave recti?r bridge and a 15k/2w resistor are used to supply the dc power required by the ic. a 1 m f capacitor at pin 8 is used to ?ter the ripple of the supply voltage and is also connected across the scr to allow ?ing of the scr on either half-cycle. when a fault causes the scr to trigger, the circuit breaker is energized and line voltage is removed from the load. at this time no fault current ?ws and the c t discharge cur- rent increases from i th to 3i th (see block diagram). this quickly resets both the timing capacitor and the output latch. the circuit breaker can be reset and the line voltage again supplied to the load, assuming the fault has been removed. a 1000:1 sense transformer is used to detect the normal fault. the fault current, which is basically the difference current between the got and neutral lines, is stepped down by 1000 and fed into the input pin of the operational ampli?r through a 10 m f capacitor. the 0.0033 m f capacitor between pin 2 and pin 3 and the 200 pf between pins 3 and 4 are added to obtain better noise immunity. the normal fault sen- sitivity is determined by the timing capacitor discharging current, i th . i th can be calculated by: (1) at the decision point, the average fault current just equals the threshold current, i th . (2) where i f (rms) is the rms input fault current to the opera- tional ampli?r and the factor of 2 is due to the fact that i f charges the timing capacitor only during one half-cycle, while i th discharges the capacitor continuously. the factor 0.91 converts the rms value to an average value. combining equations (1) and (2) we have: (3) for example, to obtain 5 ma(rms) sensitivity for the circuit in figure 7 we have: (4) i th 7v r set ------------- 2 ? = i th i f rms () 2 ------------------- 0.91 = r set 7v i f rms () 0.91 ------------------------------------ = r set 7v 5 ma 0.91 1000 ----------------------------- - ------------------------------ 1.5m w = = the correct value for r set can also be determined from the characteristic curve that plots equation (3). note that this is an approximate calculation; the exact value of r set depends on the speci? sense transformer used and lm1851 toler- ances. inasmuch as ul943 speci?s a sensitivity ?indow? of 4 ma to 6ma, provision should be made to adjust r set with a potentiometer. independent of setting sensitivity, the desired integration time can be obtained through proper selection of the timing capacitor, c t . due to the large number of variables involved, proper selection of c t is best done empirically. the follow- ing design example should only be used as a guideline. assume the goal is to meet ul943 timing requirements. also assume that worst case timing occurs during gfi start- up (s1 closure) with both a heavy normal fault and a 2 w grounded neutral fault present. this situation is shown dia- grammatically in figure 8. figure 8. ul943 speci?s 25 ms average trip time under these condi- tions. calculation of c t based upon charging currents due to normal fault only is as follows: 1. start with a 25 ms speci?ation. subtract 3 ms gfi turn-on time (15k and 1 m f). subtract 8 ms potential loss of one half-cycle due to fault current sense of half- cycles only. 2. subtract 4 ms time required to open a sluggish circuit breaker. 3. this gives a total 10 ms maximum integration time that could be allowed. 4. to generate 8 ms value of integration time that accom- modates component tolerances and other variables: (5) 65-1851-12 line neutral hot s1 gfi hot neutral r b 500 i r b 500 (0.2)i (0.8)i r n 0.4 c t 1t v ------------ =
product specification lm1851 7 where: t = integration time v = threshold voltage i = average fault current into ct (6) therefore: (7) i 120 v ac rms () r b ------------------------------------ - ? ?? rn rg rn + ----------------------- ? ?? = heavy fault current generated (swamps i th ) portion of fault current shunted around gfi 1 turn 1000 turns ------------------------- ? ?? 1 2 -- - ? ?? 0.91 () current division of input sense transformer ct charging on half- cycles only rms to average conversion c t 120 500 -------- - ? ?? 0.4 1.6 0.4 + -------------------- - ? ?? 1 1000 ----------- - ? ?? 1 2 -- - ? ?? 0.91 () 17.5 ----------------------------------------------------------------------------------------------------------------- - 0.008 = c t 0.01 m f = in practice, the actual value of c t will have to be modi?d to include the effects of the neutral loop upon the net charging current. the effect of neutral loop induced currents is dif? cult to quantize, but typically they sum with normal fault currents, thus allowing a larger value of c t . for ul943 requirements, 0.015 m f has been found to be the best compromise between timing and noise. for those gfi standards not requiring grounded neutral detection, a still larger value capacity can be used and better noise immunity obtained. the larger capacitor can be accommodated because r n and r g are not present, allowing the full fault current, i, to enter the gfi. in figure 10, grounded neutral detection is accomplished by feeding the neutral coil with 120 hz energy continuously and allowing some of the energy to couple into the sense trans- former during conditions of neutral fault. transformers may be obtained from magnetic metals, inc., 21st street and hayes street, camden, nj 08101 (609) 964-7842.
lm1851 product specification 8 application circuits figure 9. normal fault sensitivity test circuit figure 10. 120 hz neutral transformer application 65-1851-10 lm1851 timing cap -in +in scr trigger op amp output +v s r set gnd 2 3 6 4 7 1 5 8 0.047 f 100k i shunt a c t 0.002 300 mv 1.5m 31v 1k 800 hz 65-1851-11 lm1851 timing cap ?n +in scr trigger op amp output +v s r set gnd 2 3 6 4 7 1 5 8 r set* line sense coil 1.0 f tant 200 pf 10 f tant 0.01 c t 0.015 0.01/400v gnd/neutral coil 200:1 high coil mov hot neutral load 0.01/400v 5k/2w scr *adjust r set for desired sensitivity. 1000:1 0.0033 circuit breaker
product specification lm1851 9 schematic diagram 65-1851-13 q2 (6) q1 .5x q3 r1 13.1k r2 40k q4 q5 q6 q7 q8 q9 2.44x r4 20k q37 q38 2x q10 q11 q39 q36 q12 2.44x r5 320 r6 6k q13 q15 q16 r7 1.2k q14 q22 q23 q20 .5x q21 .5x r8 2k q30 q17 q18 .5x .5x r3 10k q19 r9 100k r10 110 (3) (2) r12 390 (5) q28 .7x .3x q29 2.44x .3x q24 d1 q26 q27 2.44x q25 r11 50k q33 .5x .5x n+ c2 8 pf q34 q35 q32 q31 r13 50k r14 5k q47 .5x q46 q45 r17 100k q44 q42 q41 q40 q54 (8) q54 3x q53 .2x q52 .8x (1) q56 q55 4.54x (4) q50 r16 17.33k q49 q48 r15 5.6k (7) .5x
lm1851 product specification 10 mechanical dimensions 8-lead plastic dip package a .210 5.33 symbol inches min. max. min. max. millimeters notes a1 .015 .38 .022 .56 b .014 .36 b1 .045 .070 1.14 1.78 d .348 .430 8.84 10.92 .300 .325 7.62 8.26 .240 .280 6.10 7.11 e e .430 10.92 .005 .13 4 a2 .115 .195 2.93 4.95 2 e1 .100 bsc 2.54 bsc 2 eb a2 .115 .160 2.92 4.06 l d1 8 ? 8 ? 5 n c .008 .015 .20 .38 notes: 1. 2. 3. 4. 5. dimensioning and tolerancing per ansi y14.5m-1982. "d" and "e1" do not include mold flashing. mold flash or protrusions shall not exceed .010 inch (0.25mm). terminal numbers are for reference only. "c" dimension does not include solder finish thickness. symbol "n" is the maximum number of terminals. d b1 e b e1 a1 a l 4 5 8 1 e eb c d1
product specification lm1851 11 mechanical dimensions (continued) 8-lead plastic soic package 85 14 d a a1 ?c ccc c lead coplanarity seating plane e b l h x 45 ? c a eh a .053 .069 1.35 1.75 symbol inches min. max. min. max. millimeters notes a1 .004 .010 0.10 0.25 .020 0.51 b .013 0.33 c .008 .010 0.20 0.25 e .150 .158 3.81 4.01 e .228 .244 5.79 6.20 .010 .020 0.25 0.50 h .050 bsc 1.27 bsc h l .016 .050 0.40 1.27 0 ? 8 ? 0 ? 8 ? 3 6 5 2 2 n8 8 a ccc .004 0.10 d .189 .197 4.80 5.00 notes: 1. 2. 3. 4. 5. 6. dimensioning and tolerancing per ansi y14.5m-1982. "d" and "e" do not include mold flash. mold flash or protrusions shall not exceed .010 inch (0.25mm). "l" is the length of terminal for soldering to a substrate. terminal numbers are shown for reference only. "c" dimension does not include solder finish thickness. symbol "n" is the maximum number of terminals.
lm1851 product specification 5/20/98 0.0m 001 stock#ds30001851 1998 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1 . life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2 . a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com o r dering in f ormation p a r t number p a c k age operatin g t emperature range lm1851an 8-lead plastic dip -40 c to +70 c RV4145M 8-lead plastic soic -40 c to +70 c

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