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128k x 32 flash memory puma 2f4006-70/90/12 issue 4.1 april 1999 pin definition block diagram 1 12 23 view from above 213 24 3 14 25 4 15 26 5 16 27 6 17 28 7 18 29 8 19 30 9 20 31 10 21 32 11 22 33 34 45 56 35 46 57 36 47 58 37 48 59 38 49 60 39 50 61 40 51 62 41 52 63 42 53 64 43 54 65 44 55 66 d8 we2 d15 d9 cs2 d14 d10 gnd d13 a14 d11 d12 a16 a10 oe a9 nc a15 we1 nc vcc d7 d0 cs1 d6 d1 nc d5 d2 d3 d4 d24 vcc d31 d25 cs4 d30 d26 we4 d29 a7 d27 d28 a12 a4 a1 nc a5 a2 a13 a6 a3 a8 we3 d23 d16 cs3 d22 d17 gnd d21 d18 d19 d20 a11 a0 pin functions a0~a16 address inputs d0~d31 data input/output cs1~4 chip select oe output enable we1~4 write enable v cc power (+5v) gnd ground oe we4 a0~a16 d16~23 d0~7 d8~15 d24~31 cs1 cs2 cs3 cs4 128k x 8 flash 128k x 8 flash 128k x 8 flash 128k x 8 flash we3 we2 we1 general description the puma 2f4006 is a 4,194,304 bit cmos 5.0v only flash memory in a 66 pin ceramic pga package, which is configurable as 8, 16, 32 bit wide output using four chip selects.flash memory combines the functionality of eeprom with on chip electrical write/erase logic, thus simplifying the external control circuitry. the puma 2f4006 incorporates automatic programming and erase functions, which allow up to 10,000 write/erase cycles (min). in addition, a sector erase function is available which can erase one 16k block of data randomly and more than one block simultaneously. the puma 2f4006 also features hardware sector protection, which enables both program and erase operations in any of the 32 sectors on the module. features ? very fast access times of 70ns/90ns/120ns. operating power (read) 660 mw (max) (program/erase) 1100 mw (max) standby power 2.2 mw (max) output configurable as 32 / 16 / 8 bit wide. automatic write/erase by embedded algorithm - end of write/erase indicated by data polling and toggle bit. flexible sector erase architecture - 16k byte sector size, with hardware protection of any number of sectors. single byte program of 14s (typical), sector pro gram time of 0.3 sec. (typical). module flash erase of 3 seconds (typical). erase/write cycle endurance 10,000 (minimum) can be screened in accordance with mil-std-883. elm road, west chirton, north shields, tyne & wear ne29 8se, england tel. +44 (0)191 2930500 fax. +44 (0) 191 2590997
2 puma 2f4006 - 70/90/12 issue 4.1 april 1999 dc electrical characteristics (t a = -55c to +125c,v cc =5v 10%) parameter symbol test condition min typ max unit input leakage current i li v in =0 to v cc , v cc = v cc max. --4a output leakage current i lo v out =0 to v cc ,v cc = v cc max. --4a standby supply current ttl i sb1 cs1~4=v ih ,v cc = v cc max. --4ma cmosi sb2 cs1~4=v cc +0.5 , v cc = v cc max. - - 400 a operating current read i cc1 cs1~4 = v il , oe = v ih - 120 ma program/erase i cc2 cs1~4 = v il , oe = v ih - 200 ma output lowvoltage v ol i ol =12ma , v cc = v cc min. - - 0.45 v output highvoltage v oh i oh =-2.5ma , v cc = v cc min. 2.4 - - v low vcc lock out voltage v lko 3.2 - - v a9 voltage for autoselect v id v cc =5.0v 11.5 - 12.5 v capacitance (t a =25 o c,f=1mhz) parameter symbol test condition typ max unit input capacitance: c in v in =0v 34 40 pf output capacitance: c out v out =0v 44 58 pf note: capacitance calculated not measured. recommended operating conditions parameter symbol min typ max unit dc logic supply voltage v cc 4.5 5.0 5.5 v input high voltage ttl v ih 2.0 - v cc +0.5 v cmos v ihc 0.7v cc -v cc +0.5 v input low voltage ttl v il -0.5 - 0.8 v cmos v ilc -0.5 - 0.8 v operating temperature t a 0-70 c t ai -40 - 85 c(- i suffix) t am -55 - 125 c(- m , mb suffix) absolute maximum ratings (1) unit voltage on any pin w.r.t. gnd (2) (except a9) -2.0 to +7 v supply voltage (2) -2.0 to +7 v voltage on a 9 w.r.t. gnd -2.0 to +14 v storage temperature -65 to +150 c notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operationof the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. (2) minimum dc voltage on any input or i/o pin is -0.5v. maximum dc voltage on output and i/o pins is vcc+0.5v. dur ing transitions voltage may overshoot by +/-2v for up to 20ns dc operating conditions
3 puma 2f4006 - 70/90/12 issue 4.1 april 1999 ac test conditions * input pulse levels : 0.0v to 3.0v * input rise and fall times : 5 ns * input and output timing reference levels : 1.5v * v cc = 5v +/- 10% * module tested in 32 bit mode 166 30pf i/o pin 1.76v ? operation cs1~4 oe we1~4 a o a 1 a 9 i /o auto-select manufacturer code l l h l l vid code auto select device code l l h h l vid code read l l h a0 a1 a9 dout standby h x x x x x high z output disable l h h x x x high z write l h l a0 a1 a9 din enable sector protect l vid l x x vid x verify sector protect l l h l h vid code operating modes the following modes are used to control the puma 2f4006 cs1~4 and we1~4 should be controlled by the user to configure the device for 8,16,or 32 bit operation.
4 puma 2f4006 - 70/90/12 issue 4.1 april 1999 -70 -90 -12 parameter symbol min max min max min max unit read cycle time t rc 70 - 90 - 120 - ns address to output delay t ac - 70 - 90 - 120 ns chip select to output t ce - 70 - 90 - 120 ns output enable to output t oe - 30 - 35 - 50 ns chip select to o/p high z t df -20-20-30ns output enable to output high z t df - 20 - 20 - 30 ns output hold time (from address, t oh 0-0-0-ns cs1~4 or oe whichever occurs first) ac operating conditions read -70 -90 -12 parameter symbol min max min max min max unit write cycle time t wc 70 - 90 - 120 - ns address setup time t as 0-0-0-ns address hold time t ah 45 - 45 - 50 - ns data setup time t ds 30 - 40 - 50 - ns data hold time t dh 0-0-0-ns output enable setup time t oes 0-0-0-ns output enable hold time t oeh 0-0-0-ns read recover before write t ghwl 0-0-0-ns cs1~4 setup time t cs 0-0-0-ns cs1~4 hold time t ch 0-0-0-ns write pulse width t wp 35 - 40 - 50 - ns write pulse width high t wph 20 - 20 - 20 - ns programming operation t whwh1 14 - 14 - 14 - s erase operation (1) t whwh2 3-3-3-s vcc setup time (4) t vcs 50 - 50 - 50 - s voltage transition time (2,4) t vlht 4-4-4- n s write pulse width (2) t wpp 10 - 10 - 10 - n s oe setup time to we1~4 active (2,4) t oesp 4-4-4- n s cs1~4 setup time to we1~4 active (3,4) t csp 4-4-4- n s write/ erase/ program notes: (1) this also includes the preprogramming time. (2) these timings are for sector protect/unprotect operations. (3) this timing is only for sector unprotect. (4) not 100% tested.
5 puma 2f4006 - 70/90/12 issue 4.1 april 1999 write/erase/program (alternate cs1~4 controlled writes) -70 -90 -12 parameter symbol min max min max min max unit write cycle time t wc 70 - 90 - 120 - ns address setup time t as 0-0-0-ns address hold time t ah 45 - 45 - 50 - ns programming operation t ds 30 - 40 - 50 - ns data hold time t dh 0-0-0-ns output enable setup time t oes 0-0-0-ns output enable hold time t oeh 0-0-0-ns read recover before write t ghel 0-0-0-ns we1~4 setup time t ws 0-0-0-ns we1~4 hold time t wh 0-0-0-ns cs1~4 pulse width t cp 35 - 40 - 50 - ns cs1~4 pulse width high t cph 20 - 20 - 20 - ns programming operation t whwh1 14 - 14 - 14 - s erase operation (1) t whwh2 3-3-3-s vcc setup time (2) t vcs 2-2-2- s notes: (1) this also includes the preprogramming time. (2) not 100% tested.
6 puma 2f4006 - 70/90/12 issue 4.1 april 1999 ac waveforms for read operation 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte/word address. 3. d 7 is the output of the complement of the data written to the device. d 7 and d 15 are used for 16 bit mode, whilst d 7 ,d 15 ,d 23 ,d 31 are used for 32 bit mode. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. notes: address cs1~4 oe data out high z t ce t oe t acc t df t oh t rc output valid address valid we1~4 high z address 5.0 v oe data cs1~4 we1~4 5555h pa pa data polling a0h pd d out d t t as t ah t ghwl t wp t wph t cs t dh t ds t whwh1 t rc t oe t df t ce t oh 7 wc ac programming waveforms
7 puma 2f4006 - 70/90/12 issue 4.1 april 1999 ac chip / sector erase waveforms notes 1. sa is the address for sector erase. addresses = don't care for chip erase. 2. the data must be repeated on both bytes of the data bus for 16 bit mode and on all four bytes for 32 bit mode. 5555h 2aaah 5555h 5555h 2aaah sa address cs1~4 oe we1~4 data vcc aah 55h 80h aah 5hh 10h/30h t as t ah t ghwl t wp t cs t wph t dh t ds t vcs * d 7 = valid data(the device has completed the embeded operation).for 16 and 32 bit modes d 7 ,d 15 and d 7 ,d 15 ,d 23 ,d 31 are used respectively. 8 bit mode is shown above. * oe cs1~4 we1~4 d7 = valid data d7 d7 t high z ch t oeh t ce t oe t oh t whwh 1 or 2 t df d0~7 valid data d0~6=inval id d0~6 high z t oe ac waveforms for data polling during embedded algorithm operations
8 puma 2f4006 - 70/90/12 issue 4.1 april 1999 sax = sector addr for intial sector say = sector addr for next sector * cs1~4 we1~4 oe t oe t oeh t oh data (d0~7) d0~7 valid d6=toggle d6=toggle d6 = stop toggling 01h a16 a15 a14 a0 a1 a9 oe we1~4 cs1~4 data sa x sa y 12v 5v 12v 5v t vlht t oesp t vlht t wpp t vlht t oe * d 6 stops toggling(the device has completed the embedded operation). d 6 ,d 14 and d 6 ,d 14 ,d 22 ,d 30 are used for 16 bit and 32 bit modes respectively. 8 bit mode shown above. ac waveforms for toggle bit during embedded algorithm operations ac waveforms for sector protection
9 puma 2f4006 - 70/90/12 issue 4.1 april 1999 a16 a15 a14 a0 a1 a9 oe we1~4 00h data execute auto select command sequence 5v 5v 12v 12v cs1~4 5v 12v sa 0 sa 1 a12 a7 a6 t vlht t vlht t vlht t vlht t t wpp t csp ac waveforms for sector unprotect
10 puma 2f4006 - 70/90/12 issue 4.1 april 1999 a.c waveforms - alternate cs1~4 controlled program operation timings address v cc oe data we1~4 cs1~4 5555h pa pa data polling a0h pd d out d7 t ds t wc t as t ah t ghel t cp t cph t ws t dh 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte/word address. 3. d 7 is the output of the complement of the data written to the device. d 7 and d 15 are used for 16 bit mode, whilst d 7 ,d 15 ,d 23 ,d 31 are used for 32 bit mode. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. notes:
11 puma 2f4006 - 70/90/12 issue 4.1 april 1999 1. address bit a 15 =x=don't care. write sequences may be initiated with a 15 in either state. 2. address bit a 16 =x=don't care for all address commands except for program address (pa) and sector address (sa). 3. ra=address of the memory location to be read. pa=address of memory location to be programmed. addresses are latched on the falling edge of the we1~4 pulse. sa=address of the sector to be erased. the combination of a 16 , a 15 and a 14 will uniquely select any sector in 32 bit mode. 4. rd=data read from location ra during read operation. pd=data to be programmed at location pa. data is latched on the falling edge of we1~4 the read or reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of memory content occurs during the power transition. refer to the ac read characteristics and waveforms for specific timing parameters. addr data addr data addr data addr data addr data addr data sequence req'd notes: read/reset 4 5555h aah 2aaah 55h 5555h f0h ra rd autoselect 4 5555h aah 2aaah 55h 5555h 90h 00h/01h 01h/20h byte program 4 5555h aah 2aaah 55h 5555h a0h pa pd chip erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h sector erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa 30h command cycles cycle device operations are selected by writing specific address and data sequences into the command register. the following table defines these register command sequences for 8 bit mode. for 16 and 32 bit mode, the data values in the table should be repeated on each byte of the data bus, when entering a command sequence. data to be stored should be entered normally as 16 or 32 bit. bus first bus second bus third bus forth bus fifth bus sixth bus write write cycle write cycle write cycle read/write write cycle write cycle command definitions read/reset command
12 puma 2f4006 - 70/90/12 issue 4.1 april 1999 device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the register is a latch used to store the commands along with the address and data information required to execute the command. the command register is written by bringing we1~4 to v il while cs1~4 is at v il and oe is at v ih .addresses are latched on the falling edge of we1~4 while data is latched on the rising edge. to activate this mode the programming equipment must force v id (11.5 to 12.5v) on address a 9 . two identifier bytes may then be sequenced from each die device outputs by toggling a 0 from v il to v ih . all addresses are dont care apart from a 1 & a 0 . all identifiers for manufacturer and device will exhibit odd parity with d 7 defined as the parity bit. the manufacturer and device codes may also be read via the command register, for instances when the puma 2f4006 is erased or programmed in a system without access to high voltage on a 9 . all identifiers for manufacturers and device will exhibit odd parity with the msb(d 7 /d 15 /d 23 /d 31 ) defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . read mode write standby mode the puma 2f4006 has two control functions which must be satisfied in order to obtain data at the outputs. cs1~4 is the power control and should be used for device selection oe is the output control and should be used to gate data to the output pins if the device is selected. two standby modes are available : cmos standby : cs1~4 held at vcc +/- 0.5v ttl standby : cs1~4 held at v ih in the standby mode the outputs are in a high impedance state independent of the oe input. if the device is deselected during erasure or programming the device will draw active current until the operation is completed. output disable with the oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the device and will identify the die manu- facturer and type. this mode is intended for use by programming equipment. this mode is functional over the full military temperature range. the autoselect codes are as follows : a 16 a 15 a 14 a 1 a 0 code d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 (hex) die manufacturer code x x x v il v il 01h 0 0 0 0 0 0 0 1 die device code x x x v il v ih 20h 0 0 1 0 0 0 0 0 sector protection sector address v ih v il 01h* 0 0 0 0 0 0 0 1 * outputs 01h at protected sector address. outputs 00h at unprotected sector address.for 16 & 32 bit d0-d7 is repeated on each by te of the data bus.
13 puma 2f4006 - 70/90/12 issue 4.1 april 1999 to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe. the sector adresses (a 16 , a 15 and a 14 ) should be set to the sector to be protected. programming of the protection circuitry begins on the falling edge of the we1~4 pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we1~4 pulse. (see sector address table) to verify programming of the protection equipment circuitry, the programming equipment must force v id on address pin a 9 with cs1~4 and oe at v il and we1~4 at v ih . reading the device at a particular sector address (a 16 , a 15 and a 14 ) will produce 01h at data outputs (d 0 -d 7 /d 0 -d 15 /d 0 -d 31 ) for a protected sector. otherwise the device will read 00h for unprotected sector. in this mode, the lower order addresses, except for a 0 and a 1 , are don't care. address location 02h is reserved to verify sector protection of the device. address pin a 1 must be held at v ih and a 0 at v il . address location 00h and 01h are reserved for autoselect codes. if a verify of the sector protection circuitry were done at these addresses, the device would output the manufacturer and device codes respectively a 16 a 15 a 14 address range sa 0 0 0 0 00000h-03fffh sa 1 0 0 1 04000h-07fffh sa 2 0 1 0 08000h-0bfffh sa 3 0 1 1 0c000h-0ffffh sa 4 1 0 0 10000h-13fffh sa 5 1 0 1 14000h-17fffh sa 6 1 1 0 18000h-1bfffh sa 7 1 1 1 1c000h-1ffffh it is also possible to determine if a sector is protected in the system by writing the autoselect command. performing a read operation at particular sector addresses (a 16 , a 15 and a 14 ) and with a 1 =v ih and a 0 =v il (other addresses are a don't care) will produce 01h data if those sectors are protected. otherwise the device will read 00h for an unprotected sector. (see sector protect/unprotect algorithms for more details.) the puma 2f4006 features hardware sector protection. this feature will disable both program and erase operations in any number of sectors (0 through 7). the sector protect feature is enabled using programming equipment at the users site. the device is shipped with all sectors unprotected. sector protection sector address table
14 puma 2f4006 - 70/90/12 issue 4.1 april 1999 the device is programmed on a byte/word-by-byte/word basis. programming is a four bus cycle operation. there are two "unlock" write cycle. these are followed by the program set-up command and data write cycles. the addresses are latched on the falling edge of cs1~4 or we1~4 (whichever first), the data is latched on the rising edge of cs1~4 or we1~4 (whichever first), and then programming begins. upon executing the embedded program algorithm command sequence the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the automatic programming operation is completed when the data on d 7 is equivalent to data written to this bit (see write operations status) at which time the device returns to read mode and addresses are no longer latched. data polling must be performed at the memory location which is being programmed. programming is allowed in any address sequence and across sector boundaries. beware that data "0" cannot be programmed back to a "1". attempting to do so will hang up the device, or result in an apparent success according to the data polling algorithm. however, a read from read/reset mode will show data is still "0". only an erase operation can convert "0"s to "1"s. flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the device resides in the target systems. prom programmers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally a desired system design practice. the device contains an autoselect operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. following the command write, a read cycle from address xxx0h retrieves the manufacture code of 01h. a read cycle from address xxx1h returns the device code 20h. a read cycle from address xxx2h returns information as to which sectors are protected. all manufacturer and device codes will exhibit odd paritywith the msb (d7) defined as the parity bit for 8 bit. d7 and d15 for 16 bit. d7, d15, d23 and d31 are used for 32 bit. to terminate the operation, it is necessary to write the read/reset command sequence into the register. chip erase is a six bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command. two more "unlock" write cycles are then followed by the chip erase command. chip erase doesn't require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. the systems is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we1~4 pulse in the command sequence and terminates when the data on d 7 ,d 15 ,d 23 ,d 31 are "1" (see written operation section) at which time the device returns to read the mode. autoselect command byte programming chip erase
15 puma 2f4006 - 70/90/12 issue 4.1 april 1999 the puma 2f4006 features data polling as a method to indicate to the host system that the embedded algorithms are in progress or completed. during the embedded programming algorithm, an attempt to read the device will produce complement data of the data last written to d 7 . upon completion of the embedded programming algorithm an attempt to read the device will produce the true data last written to d 7 . data polling is valid after the rising edge of the forth we1~4 pulse in the four write pulse sequence. for 16 and 32 bit modes, the data values for the sector erase command sequence should be repeated on each byte of the data bus. sector erase is a six bus cycle operation. there are two "unlock"write cycles. these are followed by writing the "set-up" command. two more "unlock" write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we1~4, while the command (data) is latched on the rising edge of we1~4. a time-out of 80 s from the rising edge of the last sector erase command will initiate the sector erase command(s). multiple sectors may be erased concurrently by writing the six bus cycle operations as desribed above. this sequence is followed with writes of the sector erase command (30h) to addresses in other sectors required to be concurrently erased. the time between writes must be less than 80 s, otherwise that command will not be accepted. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command(s). if another falling edge of we1~4 occurs within the 80 s time-out window , the timer is reset.(d 3, d 11, d 19, d 27, indicate if the timer window is still open on each 128k device on the module). loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 7). any command other than sector erase during this period will reset the device to read mode, ignoring the previous. sector erase doesn't require the user to program the device prior to erase. the device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the 100 s time-out from the rising edge of the we1~4 pulse for the last sector erase command pulse and terminates when the data on d 7, d 15, d 23 and d 31 are "1" ( see write operation status section) at which time the device returns to read mode. data polling must be preformed at an address within any of the sectors being erased. data polling - d 7, d 15, d 23, d 31 status d 7 d 6 d 5 d 3 d 2 -d 0 auto-programming d 7 toggle 0 0 erasing in auto erase 0 toggle 0 1 future use auto-programming d 7 toggle 1 0 hardware sequence flags :- time limits erasing in auto-erase 0 toggle 1 1 future use exceeded programming in auto erase 0 toggle 1 1 reserved for in progress programming in auto erase 0 toggle 0 1 reserved for sector erase write operation status
16 puma 2f4006 - 70/90/12 issue 4.1 april 1999 the puma 2f4006 also features the "toggle bit" as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read(oe toggling) data from the device will result in d 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, d 6 will stop toggling and valid data will be read on successive attempts. during programming, the toggle bit is valid after the rising edge of the forth we1~4 pulse in the four write pulse sequence. for chip erase, the toggle bit is valid after the sixth we1~4 pulse in the six write pulse sequence. for sector erase, the toggle bit is valid after the last rising edge of the sector erase we1~4 pulse. the toggle bit is active during the sector time-out. note: cs1~4 or oe toggling will toggle d 6 . for 16 and 32 bit modes d 14 ,d 22 and d 30 behave like d 6. during the embedded erase algorithm, d 7 will be "0" until the erase operation is completed. upon completion data at d 7 is "1". for chip erase, the data polling is valid after the rising edge of the sixth we1~4 pulse in the six write pulse sequence. for sector erase, data polling is valid after the last rising edge of the sector erase we1~4 pulse. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm, or sector erase time-out. for 16 and 32 bit modes d 15 ,d 23 and d 31 behave like d 7. if the device has exceeded the specified erase or program time and d 5 is "1", then d 4 will indicate at which step in the algorithm the device exceeded the limits. a "0" in d 4 indicates in programming, a "1" indicates an erase. d 5 will indicate if the program or erase time has exceeded the specified limits. under these conditions d 5 will produce "1", indicating the program or erase cycle was not successfully completed . data polling is the only operating function of the device under this condition. the cs1~4 circuit will partially power down the device under these conditions (to approximately 2ma). the oe and we1~4 pins will control the output disable functions . to reset the device, write reset command sequence to the device. this allows the system to continue to use the other active sectors in the device. if this failiure condition occurs during the sector erase operation, it specifies that a particular sector is bad and it may not be reused. however, other sectors are still functional and may be used for additional program or erase operations. the device must be reset to use other sectors. write the reset command sequence to the device, and then execute the program or erase command sequence. if this failure condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. if this failure condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused(other sectors are still functional and can be reused). the device must be reset to use other sectors. the d 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the system never reads valid data on the d 7 bit and d 6 never stops toggling. once the device has exceeded timing limits, the d 5 bit will indicate a "1". please note that this is not a device failure condition since the device was incorrectly used. the device must be reset to continue using the device.for 16 and 32 bit modes d 13 ,d 21 and d 29 behave like d 5. exceeding time limits - d 5, d 13, d 21, d 29 toggle bit - d 6, d 14, d 22, d 30 hardware sequence flag - d 4 , d 12, d 20, d 28
17 puma 2f4006 - 70/90/12 issue 4.1 april 1999 sectors of the puma 2f4006 may be hardware protected at the users factory. the protection circuitry will disable both program and erase functions for the protected sector(s). requests to program or erase a protected sector will be ignored by the device. the puma 2f4006 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically resets the internal state machine in the read mode. also, with its controls register architecture , alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power up and power down transitions or system noise. to avoid initiation of a write cycle during v cc power up and power down, a write cycle is locked out for v cc less than 3.2v (typically 3.7v). if v cc 18 puma 2f4006 - 70/90/12 issue 4.1 april 1999 note:aa h ,55 h , and a0 h above should be repeated on each byte of the data bus for 16 and 32 bit configurations, program data should be entered normally in 8,16 or 32 bit form. data poll device write program command sequence (see below) last address ? programming completed increment address 5555h/aah 2aaah/55h 5555h/a0h program address/program data no yes start program command sequence (address /command) yes embedded programming algorithm
19 puma 2f4006 - 70/90/12 issue 4.1 april 1999 note: all data above should be repeated on each byte of the data bus for 16 and 32 bit configurations. start write erase command sequence (see below) data poll or toggle bit successfully complete erasure completed chip erase command sequence (address/command): 5555h/aah 2aaah/55h 5555h/80h 5555h/aah 2aaah/55h 5555h/10h 5555h/aah 2aaah/55h 5555h/80h 5555h/aah 2aaah/55h sector address/30h sector address/30h sector address/30h } additional sector erase commands are optional individual sector/mulitiple sector erase command sequence (address/command): yes embedded erase algorithm
20 puma 2f4006 - 70/90/12 issue 4.1 april 1999 va = byte/word address for programming. = any of the sector address within the sector erase during sector erase operation. = xxxxh during chip erase note: 1. d 7 is rechecked even if d 5 = 1 because d 7 may change simultaneously with d 5 . 2. for 16 and 32 bit d 5 , d 7 ,d 13 , d 15 and d 5 , d 7 ,d 13 , d 15 ,d 21 , d 23 ,d 29 , d 31 are used respectively. bold =data polling bits. note: 1. d 6 is rechecked even if d 5 = 1 because d 6 may stop toggling at the same time as d 5 changing to "1". 2. for 16 and 32 bit d 5 , d 6 ,d 13 , d 14 and d 5 , d 6 ,d 13 , d 14 ,d 21 , d 22 ,d 29 , d 30 are used respectively. bold =toggle bits. start fail d7 = data ? d5 = 1 ? d7 = data ? pass no yes yes no no yes (note 1) read byte/ word addr=va read byte/ word addr=va start d6=toggle ? pass fail d5 = 1 ? d6=toggle ? no yes yes no yes no (note 1) read byte/ word addr = va read byte/ word addr = va data polling algorithm toggle bit algorithm
21 puma 2f4006 - 70/90/12 issue 4.1 april 1999 notes: sa0 = sector addr for intial sector sa7 = sector addr to last sector start protect all sectors plscnt = 1 set up sector unprotect mode set oe = cs1~4 = a9 = v activate we1~4 pulse time out 10ms set oe = cs1~4= v write autoselect command sequence set up sector addr sa0 set a1=1, a0=0 read data from device data =00h ? sector addr = sa7 ? write reset command sector unprotect completed increment sector addr write reset command plscnt =1000 ? device failed increment plscnt no no yes no yes id remove v from a9 a12 = a7 = v , a6 = v set vcc=5.0v set vcc=5.0v set vcc=4.25v id ih il il set vcc=5.0v sector unprotect algorithm
22 puma 2f4006 - 70/90/12 issue 4.1 april 1999 start set up sector addr (a16, a15, a14) plscnt = 1 oe = v a9=v ,cs1~4=v activate we1~4 pulse time out 100us power down oe we1~4 = v cs1~4 = oe =v a9 should remain v read from sector addr=sa, a0=0, a1=1 data =01h ? protect another sector write reset command sector protection complete device failed plscnt = 25 ? increment plscnt id no no yes yes yes no remove v from a9 id il il ih id id sector protection algorithm
23 puma 2f4006 - 70/90/12 issue 4.1 april 1999 module screening flow screen test method level visual and mechanical external visual 2017 condition b or manufacturers equivalent 100% temperature cycle 1010 condition c (10 cycles,-65 o c to +150 o c) 100% burn-in pre-burn-in electrical per applicable device specifications at t a =+25 o c 100% burn-in t a =+125 o c,160hrs minimum. 100% final electrical tests per applicable device specification static (dc) a) @ t a =+25 o c and power supply extremes 100% b) @ temperature and power supply extremes 100% functional a) @ t a =+25 o c and power supply extremes 100% b) @ temperature and power supply extremes 100% switching (ac) a) @ t a =+25 o c and power supply extremes 100% b) @ temperature and power supply extremes 100% percent defective allowable (pda) calculated at post-burn-in at t a =+25 o c 5% quality conformance per applicable device specification sample external visual 2009 per vendor or customer specification 100% military screening procedure module screening flow for high reliability product is in accordance with mil-std-883 method 5004 level b and is detailed below: 15.24 (0.60) typ 27.55 (1.085) square 4.83 (0.190) 4.32 (0.170) 1.40 (0.055) 1.52 (0.060) 27.05 (1.065) square 8.13 (0.320) max 1.27 (0.050) 0.64 (0.025) 2.54 (0.100) typ. 2.54 (0.100) typ. 1.02 (0.040) 0.53 (0.021) 0.38 (0.015) 1.14 (0.045) package details dimensions in mm(inches). puma 2 - 66 pin ceramic pga
24 puma 2f4006 - 70/90/12 issue 4.1 april 1999 ordering information puma 2f4006mb-70e e = 100,000 w/e cycles speed 70 = 70 ns 90 = 90 ns 12 = 120 ns temp. range/screening blank = commercial temp. i = industrial temp (-40 c to +85 c) m = military temp (-55 c to 125 c) mb = screened in accordance with mil-std-883. organisation 4006 = user configurable as 128k x 32, 256k x 16, or 512k x 8. technology f = flash memory package puma 2 = 66 pin ceramic pga. note : although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for aparticular purpose. our products are subject to a constant process of development. data may be changed without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director.

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