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ispgdx ? device datasheet june 2010 all devices discontinued! product change notification (pcn) #09-10 has been issued to discontinue all devices in this data sheet. the original datasheet pages have not been modi fied and do not reflect those changes. please refer to the table below for refe rence pcn and current product status. product line ordering part number product status reference pcn ispgdx80a-5t100 ispgdx80a ispgdx80a-7t100 ISPGDX120A-5Q160 ispgdx120a-7q160 ispgdx120a-5t176 ispgdx120a ispgdx120a-7t176 ispgdx160a-5b272 ispgdx160a-7b272 ispgdx160a-5q208 ispgdx160a ispgdx160a-7q208 discontinued pcn#09-10 5555 n.e. moore ct. z hillsboro, oregon 97124-6421 z phone (503) 268-8000 z fax (503) 268-8347 internet: http://www.latticesemi.com
ispgdx family in-system programmable generic digital crosspoint ispgdx_11 1 functional block diagram features in-system programmable generic digital crosspoint family advanced architecture addresses programmable pcb interconnect, bus interface integration and jumper/switch replacement ?three device options: 80 to 160 programmable i/o pins ??ny input to any output?routing ?fixed high or low output option for jumper/dip switch emulation ?space-saving tqfp, pqfp and bga packaging ?dedicated ieee 1149.1-compliant boundary scan test ?pci compliant output drive high performance e 2 cmos technology ?5v power supply ?5.0ns input-to-output/5.0ns clock-to-output delay ?low-power: 40ma quiescent icc ?balanced 24ma output buffers with programmable slew rate control ?schmitt trigger inputs for noise immunity ?electrically erasable and reprogrammable ?non-volatile e 2 cmos technology ?100% tested ispgdx offers the following advantages ?in-system programmable ?lattice isp or jtag programming interface ?only 5v power supply required ?change interconnects in seconds ?reprogram soldered devices flexible architecture ?combinatorial/latched/registered inputs or outputs ?individual i/o tri-state control with polarity control ?dedicated clock input pins (two or four) or programmable clocks from i/o pins (from 20 up to 40) ?up to 4:1 dynamic path selection ?programmable output pull-up resistors ?outputs tri-state during power-up (?ive insertion friendly) global routing pool (grp) i/o cells i/o pins b boundary scan control i/o cells isp control i/o pins a i/o pins c i/o pins d description the ispgdx architecture provides a family of fast, flexible programmable devices to address a variety of system- level digital signal routing and interface requirements including: multi-port multiprocessor interfaces ? ide data and address bus multiplexing (e.g. 4:1 high-speed bus mux) programmable control signal routing (e.g. interrupts, dmareqs, etc) board-level pcb signal routing for prototyping or programmable bus interfaces the ispgdx family consists of three members with 80, 120 and 160 programmable i/os. these devices are available in packages ranging from the 100-pin tqfp to the 208-pin pqfp. the devices feature fast operation, with input-to-output signal delays (tpd) of 5ns and clock- to-output delays of 5ns. the architecture of the devices consists of a series of programmable i/o cells interconnected by a global rout- copyright ?2002 lattice semiconductor corporation. all brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. november 2003 t el. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com all devices discontinued
2 specifications ispgdx family description (continued) ing pool (grp). all i/o pin inputs enter the grp directly or are registered or latched so they can be routed to the required i/o outputs. i/o pin inputs are defined as four sets (a,b,c,d) which have access to the four mux inputs found in each i/o cell. each output has individual, pro- grammable i/o tri-state control (oe), output latch clock (clk) and two multiplexer control (mux0 and mux1) inputs. polarity for these signals is programmable for each i/o cell. the mux0 and mux1 inputs control a fast 4:1 mux, allowing dynamic selection of up to four signal sources for a given output. oe, clk and mux0 and mux1 inputs can be driven directly from selected sets of i/o pins. optional dedicated clock input pins give mini- mum clock-to-output delays. through in-system programming, connections between i/o pins and architectural features (latched or registered inputs or outputs, output enable control, etc.) can be defined. in keeping with its data path application focus, the ispgdx devices contain no programmable logic arrays. all input pins include schmitt trigger buffers for noise immunity. these connections are programmed into the device using non-volatile e 2 cmos technology. non-volatile technology means the device configuration is saved even when the power is removed from the device. in addition, there are no pin-to-pin routing constraints for 1:1 or 1:n signal routing. that is, any i/o pin configured as an input can drive one or more i/o pins configured as outputs. the device pins also have the ability to set outputs to fixed high or low logic levels (jumper or dip switch mode). device outputs are specified for 24ma sink and source current and can be tied together in parallel for greater drive. programmable output slew rate can be defined independently for each i/o pin to reduce overall ground bounce and switching noise. all i/o pins are equipped with ieee1149.1-compliant boundary scan test circuitry for enhanced testability. in addition, in-system programming is supported through the test access port via a special set of private com- mands or through lattice? industry-standard isp protocol. the bscan/ ispen pin is used to make this selection. the ispgdx i/os are designed to withstand ?ive inser- tion?system environments. the i/o buffers are disabled during power-up and power-down cycles. when design- ing for ?ive insertion,?absolute maximum rating conditions for the vcc and i/o pins must still be met. for additional information, an application note about using lattice de- vices in hot swap environments can be downloaded from the lattice web site at www.latticesemi.com. table 1. ispgdx family members ispgdx device ispgdx80a ispgdx120a ispgdx160a i/o pins 80 120 160 i/o-oe inputs* 20 30 40 i/o-clk inputs* 20 30 40 i/o-muxsel1 inputs* 20 30 40 i/o-muxsel2 inputs* 20 30 40 bscan / isp interface 4 4 4 reset 111 power/gnd 12 25 33 pin count/package 100-pin tqfp 176-pin tqfp/ 160-pin pqfp 208-pin pqfp 272-ball bga * the clk, oe, mux0 and mux1 terminals on each i/o cell can each access 25% of the i/os. ** muxed with y1. toe 1** 1 1 dedicated clock pins 2 4 4 bscan / ispen 111 all devices discontinued
3 specifications ispgdx family architecture the ispgdx architecture is different from traditional pld architectures, in keeping with its unique application fo- cus. the block diagram is shown below. the programmable interconnect consists of a single global routing pool (grp). unlike isplsi devices, there are no programmable logic arrays on the device. control signals for oes, clocks and mux controls must come from designated sets of i/o pins. the polarity of these signals can be independently programmed in each i/o cell. each i/o cell drives a unique pin. the oe control for each i/o pin is independent and may be driven via the grp by one of the designated i/o pins (i/o-oe set). the i/o-oe set consists of 25% of the total i/o pins. boundary scan test is supported by dedicated registers at each i/o pin. the in-system programming process uses either a bound- ary scan based or lattice isp protocol. the programming protocol is selected by the bscan/ ispen pin as de- scribed later. the various i/o pin sets are also shown in the block diagram below. the a, b, c, and d i/o pins are grouped together with one group per side. i/o architecture each i/o cell contains a 4:1 dynamic mux controlled by two select lines called mux0 and mux1 as shown in figure 1. the four data inputs to the mux (called muxa, muxb, muxc and muxd) come from i/o signals found in the grp. each mux data input can access one quarter of the total i/os. for example, in a 160 i/o ispgdx, each data input can connect to one of 40 i/o pins. mux0 and mux1 can be driven by designated i/o pins called muxsel1 and muxsel2. each muxsel input covers 25% of the total i/o pins (e.g. 40 out of 160). mux0 and mux1 can be driven from either muxsel1 or muxsel2. the i/o cell also includes a programmable flow-through latch or register that can be placed in the input or output path and bypassed for combinatorial outputs. as shown in figure 1, when both register/latch control muxes select the ? path, the register/latch gets its inputs from the 4:1 mux and drives the i/o output. when selecting the ??path, the register/latch is directly driven by the i/o input while its output feeds the grp. the programmable polarity clock to the latch or register can be connected to any i/o in the i/o-clock set (one-quarter of total i/os) or to one of the dedicated clock input pins (y x ). use of the dedicated clock inputs gives minimum clock-to-output delays and minimizes delay variation with fanout. com- binatorial output mode may be implemented by a dedicated architecture bit and bypass mux. i/o cell output polarity can be programmed as active high or active low. figure 1. ispgdx i/o cell and grp detail (160 i/o device) i/o 0 i/o 1 i/o 78 i/o 79 80 i/o cells boundary scan cell bypass option i/o cell n register or latch i/o pin prog. pull-up programmable slew rate d a b clk reset q 4-to-1 mux 160 input grp inputs vertical outputs horizontal i/o 80 i/o 81 i/o 158 muxa muxb muxc muxd mux1 mux0 global reset i/o 159 ????? 80 i/o cells e 2 cmos programmable interconnect logic "1" 160 i/o inputs c r y0-y3 global clocks i/o mux operation mux1 mux0 data input selected 00 muxa 01 muxb 11 muxc 10 muxd all devices discontinued
4 specifications ispgdx family applications the ispgdx family architecture has been developed to deliver an in-system programmable signal routing solu- tion with high speed and high flexibility. the devices are targeted for three similar but distinct classes of end- system applications: programmable, random signal interconnect (prsi) this class includes pcb-level programmable signal rout- ing and may be used to provide arbitrary signal swapping between chips. it opens up the possibilities of program- mable system hardware. it is characterized by the need to provide a large number of 1:1 pin connections which are statically configured, i.e., the pin-to-pin paths do not need to change dynamically in response to control in- puts. programmable data path (pdp) this application area includes system data path trans- ceiver, mux and latch functions. with today? 32- and 64-bit microprocessor buses, but standard data path glue components still relegated primarily to eight bits, pcbs are frequently crammed with a dozen or more data path glue chips that use valuable real estate. many of these applications consist of ?n-board?bus and memory inter- faces that do not require the very high drive of standard glue functions but can benefit from higher integration. therefore, there is a need for a flexible means to inte- grate these on-board data path functions in an analogous way to programmable logic? solution to control logic integration. lattice? isplsi high-density plds make an ideal control logic complement to the ispgdx in-system programmable data path devices as shown below. programmable switch replacement (psr) includes solid-state replacement and integration of me- chanical dip switch and jumper functions. through in-system programming, pins of the ispgdx devices can be driven to high or low logic levels to emulate the traditional device outputs. psr functions do not require any input pin connections. these applications actually require somewhat different silicon features. prsi functions require that the device support arbitrary signal routing on-chip between any two pins with no routing restrictions. the routing connections are static (determined at programming time) and each input-to-output path operates independently. as a result, there is little need for dynamic signal controls (oe, clocks, etc.). because the ispgdx device will interface with control logic outputs from other components (such as isplsi) on the board (which frequently change late in the design process as control logic is finalized), there must be no restrictions on pin-to-pin signal routing for this type of application. pdp functions, on the other hand, require the ability to dynamically switch signal routing (muxing) as well as latch and tri-state output signals. as a result, the pro- grammable interconnect is used to define possible signal routes that are then selected dynamically by control signals from an external mpu or control logic. these functions are usually formulated early in the conceptual design of a product. the data path requirements are driven by the microprocessor, bus and memory architec- ture defined for the system. this part of the design is the earliest portion of the system design frozen, and will not usually change late in the design because the result would be total system and pcb redesign. as a result, the ability to accommodate arbitrary any pin-to-any pin re- routing is not a strong requirement as long as the designer has the ability to define his functions with a reasonable degree of freedom initially. as a result, the ispgdx architecture has been defined to support psr and prsi applications (including bidirec- tional paths) with no restrictions, while pdp applications (using dynamic muxing) are supported with a minimal number of restrictions as described below. in this way, speed and cost can be optimized and the devices can still support the system designer? needs. the following diagrams illustrate several ispgdx appli- cations. data path bus #1 control inputs (from p) address inputs (from p) control outputs system clock(s) data path bus #2 configuration (switch) outputs isp/jtag interface isplsi device ispgdx device state machines decoders buffers / registers buffers / registers figure 2. ispgdx complements lattice isplsi all devices discontinued
5 specifications ispgdx family figure 4. data bus byte swapper figure 5. four-port memory interface designing with the ispgdx as mentioned earlier, this architecture satisfies the prsi class of applications without restrictions: any i/o pin as a single input or bidirectional can drive any other i/o pin as output. for the case of pdp applications, the designer does have to take into consideration the limitations on pins that can be used as control (mux0, mux1, oe, clk) or data (muxa-d) inputs. the restrictions on control inputs are not likely to cause any major design issues because the input possibilities span 25% of the total pins. the muxa-d input partitioning requires that designers consciously assign pinouts so that mux inputs are in the appropriate, disjoint groups. for example, since the muxa group includes i/o0-19 (80 i/o device), it is not possible to use i/o0 and i/o9 in the same mux function. as previously discussed, data path functions will be assigned early in the design process and these restric- tions are reasonable in order to optimize speed and cost. user electronic signature the ispgdx family includes dedicated user electronic signature (ues) e 2 cmos storage to allow users to code design-specific information into the devices to identify particular manufacturing dates, code revisions, or the like. the ues information is accessible through the boundary scan or lattice isp programming port via a specific command. this information can be read even when the security cell is programmed. security bit the ispgdx family includes a security bit feature that prevents reading the device program once set. even when set, it does not inhibit reading the ues or device id code. it can be erased only via a device bulk erase. applications (cont.) control bus data bus a data bus b oea oeb i/oa d0-7 d8-15 d8-15 d0-7 i/ob xcvr oea oeb i/oa i/ob xcvr oea oeb i/oa i/ob xcvr oea oeb i/oa i/ob xcvr bus 4 bus 3 bus 2 bus 1 port #1 oe1 memory port oem sel0 sel1 to memory port #2 oe2 port #3 oe3 note: all oe and sel lines driven by external arbiter logic (not shown). port #4 oe4 4-to-1 16-bit mux bidirectional figure 3. address demultiplex/data buffering control bus muxed address data bus dq clk oea oeb i/oa i/ob address buffered data to memory / peripherals xcvr address latch all devices discontinued
6 specifications ispgdx family supply voltage commercial t a = 0 c to +70 c input low voltage input high voltage 5.25 0.8 vcc + 1 absolute maximum ratings 1 supply voltage v cc ................................. -0.5 to +7.0v input voltage applied ........................ -2.5 to v cc +1.0v off-state output voltage applied ..... -2.5 to v cc +1.0v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the ?bsolute maximum ratings?may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating conditions v v v parameter symbol min. max. units 4.75 0 2.0 v cc v il 1 v ih 1 1. typical 100mv of input hysteresis. c symbol table 2 - 0006 c parameter dedicated clock capacitance 10 units typical test conditions 1 2 8 i/o capacitance pf pf v = 5.0v, v = 2.0v v = 5.0v, v = 2.0v cc cc y i/o capacitance (t a =25 o c, f=1.0 mhz) parameter minimum maximum units ispgdx erase/reprogram cycles 10,000 cycles erase/reprogram specifications all devices discontinued
7 specifications ispgdx family switching test conditions output load conditions test condition r1 r2 cl a 160? 90? 35pf b 90? 35pf 160? 90? 35pf active high active low c 160? 90? 5pf 90? 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2 - 0004a output low voltage output high voltage input or i/o low leakage current input or i/o high leakage current ispen input low leakage current i/o active pull-up current output short circuit current quiescent power supply current dynamic power supply current per input switching v v a a a a ma ma ma/mhz i ol =24 ma i oh =-24 ma 0v v in v il (max.) 3.5v v in v cc 0v v in v il (max.) 0v v in v il v cc = 5v, v out = 0.5v, t a = 25?c v il = 0.5v, v ih = v cc one input toggling @ 50% duty cycle, outputs open. v ol v oh i il i ih i il-isp i il-pu i os 1 i ccq i cc 25 see note 3 2.4 -100 1. one output at a time for a maximum duration of one second. v = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. typical values are at v = 5v and t = 25 o c. 3. i / mhz = (0.0114 x i/o cell fanout) + 0.06 e.g. an input driving four i/o cells at 40 mhz results in a dynamic i of approximately ((0.0114 x 4) + 0.06) x 40 = 4.2 m a. symbol min. max. typ. 2 parameter condition units 0.55 -10 10 -150 -150 -250 40 input pulse levels gnd to 3.0v input rise and fall time 1.5ns 10% to 90% input timing reference levels 1.5v output timing reference levels 1.5v output load see figure at right 3-state levels are measured 0.5v from steady-state active level. cc a out dc electrical characteristics over recommended operating conditions + 5v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. cc cc all devices discontinued
8 specifications ispgdx family external timing parameters over recommended operating conditions ns ns mhz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 111 4.0 4.0 0.0 3.5 3.5 10.0 5.0 6.5 5 8.5 6.0 9.5 6.0 6.0 9.0 9.0 14.0 5.0 0.5 80.0 5.5 5.5 0.0 5.0 5.0 14.0 7.0 9.0 7.0 11.0 9.0 13.0 8.5 8.5 12.0 12.0 18.0 7.0 0.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a a a a a a b c b c a a data propagation delay from any i/o pin to any i/o pin data propagation delay from muxsel inputs to any output clock frequency with external feedback input latch or register setup time before any clk output latch or register mux data setup time before any clk latch or register hold time after any clk output latch or register clk (from y x ) to output delay input latch or register clk (from y x ) to output delay output latch or register clk (from i/o pin) to output delay input latch or register clock (from i/o pin) to output delay input to output enable input to output disable test oe output enable test oe output disable clock pulse duration, high clock pulse duration, low register reset delay from reset low reset pulse width output delay adder for output timings using slow slew rate output skew (tgco1 across chip) t pd t sel f max(ext) t su1 t su2 t h t gco1 t gco2 t co1 t co2 t en t dis t toeen t toedis t wh t wl t rst t rw t sl t sk description parameter test 1 cond. # ( ) 1 tsu2+tgco1 units -5 min. max. -7 min. max. 1. all timings measured with one output switching, fast output slew rate setting, except t sl . 2 8 010 420304 0506 070 i/o cell fanout ? grp delay (ns) 6 10 4 maximum ? grp delay vs. i/o cell fanout ispgdx timings are specified with a grp load (fanout) of four i/o cells. the figure at right shows the maximum ? grp delay with increased grp loads. these deltas apply to any signal path traversing the grp (muxa-d, oe, clk, muxsel0-1). global clock signals, which do not use the grp, have no fanout delay adder. all devices discontinued
9 specifications ispgdx family -5 -7 parameter # 2 description 1 min. max. min. max. units inputs t io 21 input buffer delay 0.7 1.3 ns grp t grp 22 grp delay 2.0 2.5 ns mux t muxd 23 i/o cell mux a/b/c/d data delay 1.0 1.4 ns t muxs 24 i/o cell mux a/b/c/d data select 2.5 3.4 ns register t iolat 25 i/o latch delay 1.6 2.2 ns t iosu 26 i/o register setup time before clock 1.6 1.8 ns t ioh 27 i/o register hold time after clock 2.4 3.6 ns t ioco 28 i/o register clock to output delay 1.6 2.2 ns t ior 29 i/o reset to output delay 0.7 1.0 ns data path t rfdbk 30 i/o register feedback delay 0.2 0.3 ns t iobp 31 i/o register bypass delay 0.4 0.6 ns t ioob 32 i/o register output buffer delay 0.1 0.7 ns t muxc (yx clk) 33 i/o register data input mux delay 1.1 1.2 ns t muxc (i/o clk) 34 i/o register data input mux delay 2.1 3.2 ns t iod (yx clk) 35 i/o register i/o input mux delay 4.1 5.1 ns t iod (i/o clk) 36 i/o register i/o input mux delay 5.1 7.1 ns outputs t ob 37 output buffer delay 0.9 1.3 ns t obs 38 output buffer delay, slow slew 5.9 8.3 ns t oen 39 i/o cell oe to output enabled 0.8 1.1 ns t oedis 40 i/o cell oe to output disabled 0.8 1.1 ns t goe 41 global output enable delay 2.5 3.6 ns t toe 42 test oe enable delay 8.2 10.9 ns clocks t cio 43 i/o clock delay 0.7 1.0 ns t gy0/1/2/3 44 clock delay, y0/1/2/3 2.4 2.8 ns global reset t gr 45 global reset to i/o register/latch 12.3 15.0 ns internal timing parameters 1 over recommended operating conditions 1. internal timing parameters are not tested and are for reference only. 2. refer to the timing model in this data sheet for further details. all devices discontinued
10 specifications ispgdx family ispgdx timing model i/o pin reset toe y0,1,2,3 tgy0/1/2/3 #44 mux0 mux1 tgrp #22 grp d c b a oe tgoe #41 tiobp #31 tioob #32 tmuxd #23 tmuxs #24 tiod #35, #36 tgr #45 0902/gdx tio #21 trfdbk #30 tmuxc #33, #34 tcio #43 tiolat #25 tiosu #26 tioh #27 tioco #28 tior #29 tob #37 tobs #38 toen #39 toedis #40 ttoe #42 clock dq switching waveforms clock width clk (i/o input) t wl t wh combinatorial i/o output valid input data (i/o input) t pd t sel valid input muxsel (i/o input) combinatorial output combinatorial i/o output oe (i/o input) t en t dis i/o output enable/disable data (i/o input) registered i/o output clk valid input t su1 t co2 t h t su2 t co1 1/ f max (external fdbk) t gco1 t gco2 registered output reset registered i/o output t rst reset t rw all devices discontinued
11 specifications ispgdx family isplever development system the isplever development system supports ispgdx design using a vhdl or verilog language syntax. from creation to in-system programming, the isplever sys- tem is an easy-to-use, self-contained design tool. features vhdl and verilog synthesis support available ispgdx design compiler - design rule checker - i/o connectivity checker - automatic compiler function industry standard jedec file for programming min/max timing report interfaces to popular timing simulators user electronic signature (ues) support detailed log and report files for easy design debug on-line help ? indows xp, windows 2000, windows 98 and windows nt compatible solaris and hp-ux versions available in-system programmability all necessary programming of the ispgdxv/va is done via four ttl level logic interface signals. these four signals are fed into the on-chip programming circuitry where a state machine controls the programming. on-chip programming can be accomplished using an ieee 1149.1 boundary scan protocol. the ieee 1149.1- compliant interface signals are test data in (tdi), test data out (tdo), test clock (tck) and test mode select (tms) control. the epen pin is also used to enable or disable the jtag port. the embedded controller port enable pin (epen) is used to enable the jtag tap controller and in that regard has similar functionality to a trst pin. when the pin is driven high, the jtag tap controller is enabled. this is also true when the pin is left unconnected, in which case the pin is pulled high by the permanent internal pullup. this allows isp programming and bscan testing to take place as specified by the instruction table. when the pin is driven low, the jtag tap controller is driven to a reset state asynchronously. it stays there while the pin is held low. after pulling the pin high the jtag controller becomes active. the intent of this fea- ture is to allow the jtag interface to be directly controlled by the data bus of an embedded controller (hence the name embedded port enable). the epen signal is used as a ?evice select?to prevent spurious programming and/or testing from occurring due to random bit patterns on the data bus. figure 9 illustrates the block diagram for the ispjtag interface. figure 5. isp device programming interface ispgdx 80a sdo sdi mode sclk ispen 5-wire programming interface ispgdx 120a ispgdx 160a bscan/ispen bscan/ispen bscan/ispen figure 6. ispjtag device programming interface ispgdx 80a tdo tdi tms tck ispjtag programming interface ispgdx 120a ispgdx 160a bscan/ispen bscan/ispen bscan/ispen vcc all devices discontinued
12 specifications ispgdx family table 3. i/o shift register order i/o shift reg order/ispgdx ispgdx80a sdi/tdi, i/o b10 .. b19, i/o c0 .. c19, i/o d0 .. d9, reset, y1/toe, y0, i/o b9 .. b0, i/o a19.. a0, i/o d19 .. d10, sdo/tdo ispgdx120a sdi/tdi, i/o b15 .. b29, i/o c0 .. c29, i/o d0 .. d14, toe, y2, y3, reset, y1, y0, i/o b14 .. b0, i/o a29.. a0, i/o d29 .. d15, sdo/tdo ispgdx160/a sdi/tdi, i/o b20 .. b39, i/o c0 .. c39, i/o d0 .. d19, toe, y2, y3, reset, y1, y0, i/o b19 .. b0, i/o a39.. a0, i/o d39 .. d20, sdo/tdo i/o shift register order device table 4. ispgdx device id codes gdx id codes 0000 0000 0010 0101 0001 0000 0100 0011 0000 0000 0010 0101 0011 0000 0100 0011 ispgdx80a ispgdx160/a 0111 0111 0000 0000 0010 0101 0010 0000 0100 0011 ispgdx120a 0111 1000 0111 1001 8-bit isp id 32-bit boundary scan idcode device boundary scan the ispgdxv/va devices provide ieee1149.1a test capability and isp programming through a standard boundary scan test access port (tap) interface. the boundary scan circuitry on the ispgdxv/va family operates independently of the programmed pattern. this allows customers using boundary scan test to have full test capability with only a single bsdl file. the ispgdxv/va devices are identified by the 32-bit jtag idcode register. the device id assignments are listed in table 4. the ispjtag programming is accomplished by execut- ing lattice private instructions under the boundary scan state machine. contact lattice technical support to obtain more de- tailed programming information. all devices discontinued
13 specifications ispgdx family 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 0 1 update-ir exit2-ir pause-ir exit1-ir shift-ir capture-ir select-ir-scan update-dr exit2-dr pause-dr exit1-dr shift-dr capture-dr select-dr-scan run-test/idle test-logic-reset tck tms or tdi tdo t su t h t co tsu = 0.1 s (min.) th = 0.1 s (min.) tco = 0.1 s (min.) figure 8. boundary scan state machine figure 7. boundary scan i/o register cell d q m u x d q d q d q d q m u x m u x m u x m u x normal function oe i/o pin extest update dr scanout (to next cell) clock dr scanin (from previous cell) shift dr normal function oe toe all devices discontinued
14 specifications ispgdx family toe 178 a12 reset 185 d10 y0, y1, y2, y3, 75, 76, 180, 181 v10, y10, c11, a11 bscan/ ispen 183 b10 tdi/sdi 81 y12 tck/sclk 80 u11 tms/mode 79 v11 tdo/sdo 78 w11 gnd 6, 15, 25, 35, 44, 54, 63, 77, 91, 100, 110, 119, 129, a1, d4, d8, d13, d17, h4, h17, j9, j10, j11, j12, 139, 148, 159, 168, 182, 195, 204 k9, k10, k11, k12, l9, l10, l11, l12, m9, m10, m11, m12, n4, n17, u4, u8, u13, u17 vcc 1, 17, 33, 49, 65, 89, 105, 121, 137, 153, 170, 184 d6, d11, d15, f4, f17, k4, l17, r4, r17, u6, u10, 193 u15 nc 1 73, 74, 156, 179 a2, a6, a7, a10, a15, a19, a20, b1, b2, b4, b11, b14, b18, b19, b20, c2, c3, c10, c18, d2, d3, d16, e2, e17, e19, h1, h3, h18, h20, k20, l1, n1, n3, n18, n20, t2, t4, t19, u5, u18, u19, v3, v14, v18, v19, w1, w2, w3, w7, w10, w14, w19, w20, y1, y2, y6, y9, y11, y18, y20 signal descriptions i/o input/output pins ?these are the general purpose bidirectional data pins. when used as outputs, each may be independently latched, registered or tristated. they can also each assume one other control function (oe, clk and muxsel as described in the text). toe test output enable pin ?this pin tristates all i/o pins when a logic low is driven. reset active low input pin ?resets all i/o register outputs when low. y0, y1, y2, y3 input pins ?dedicated clock input pins. each pin can drive any or all i/o cell registers. bscan/ ispen input pin ?when high, this pin enables the boundary scan test and programming interface. when low, this pin enables the lattice isp protocol for programming and tristates all i/o pins, except those used for the programming interface. tdi/sdi input/input pin ?serial data input during isp programming or boundary scan mode. tck/sclk input/input pin ?serial data clock during isp programming or boundary scan mode. tms/mode input/input pin ?control input during isp programming or boundary scan mode. tdo/sdo output/output pin ?serial data output during isp programming or boundary scan mode. gnd ground (gnd) vcc vcc ?supply voltage (5v). nc 1 no connect. signal name description 1. nc pins are not to be connected to any active signals, vcc or gnd. signal 208-pin pqfp 272-ball bga 1. nc pins are not to be connected to any active signals, vcc or gnd. signal locations: ispgdx160a all devices discontinued
15 specifications ispgdx family i/o locations: ispgdx160a i/o a0 2 e4 i/o a1 3 c1 i/o a2 4 d1 i/o a3 5 e3 i/o a4 7 e1 i/o a5 8 f3 i/o a6 9 g4 i/o a7 10 f2 i/o a8 11 f1 i/o a9 12 g3 i/o a10 13 g2 i/o a11 14 g1 i/o a12 16 h2 i/o a13 18 j4 i/o a14 19 j3 i/o a15 20 j2 i/o a16 21 j1 i/o a17 22 k2 i/o a18 23 k3 i/o a19 24 k1 i/o a20 26 l2 i/o a21 27 l3 i/o a22 28 l4 i/o a23 29 m1 i/o a24 30 m2 i/o a25 31 m3 i/o a26 32 m4 i/o a27 34 n2 i/o a28 36 p1 i/o a29 37 p2 i/o a30 38 r1 i/o a31 39 p3 i/o a32 40 r2 i/o a33 41 t1 i/o a34 42 p4 i/o a35 43 r3 i/o a36 45 u1 i/o a37 46 t3 i/o a38 47 u2 i/o a39 48 v1 i/o b0 50 u3 i/o b1 51 v2 i/o b2 52 w4 i/o b3 53 v4 i/o b4 55 y3 i/o b5 56 y4 i/o b6 57 v5 i/o b7 58 w5 i/o b8 59 y5 i/o b9 60 v6 i/o b10 61 u7 i/o b11 62 w6 i/o b12 64 v7 i/o b13 66 y7 i/o b14 67 v8 i/o b15 68 w8 i/o b16 69 y8 i/o b17 70 u9 i/o b18 71 v9 i/o b19 72 w9 i/o b20 82 w12 i/o b21 83 v12 i/o b22 84 u12 i/o b23 85 y13 i/o b24 86 w13 i/o b25 87 v13 i/o b26 88 y14 i/o b27 90 y15 i/o b28 92 w15 i/o b29 93 y16 i/o b30 94 u14 i/o b31 95 v15 i/o b32 96 w16 i/o b33 97 y17 i/o b34 98 v16 i/o b35 99 w17 i/o b36 101 u16 i/o b37 102 v17 i/o b38 103 w18 i/o b39 104 y19 i/o c0 106 t17 i/o c1 107 v20 i/o c2 108 u20 i/o c3 109 t18 i/o c4 111 t20 i/o c5 112 r18 i/o c6 113 p17 i/o c7 114 r19 i/o c8 115 r20 i/o c9 116 p18 i/o c10 117 p19 i/o c11 118 p20 i/o c12 120 n19 i/o c13 122 m17 i/o c14 123 m18 i/o c15 124 m19 i/o c16 125 m20 i/o c17 126 l19 i/o c18 127 l18 i/o c19 128 l20 i/o c20 130 k19 i/o c21 131 k18 i/o c22 132 k17 i/o c23 133 j20 i/o c24 134 j19 i/o c25 135 j18 i/o c26 136 j17 i/o c27 138 h19 i/o c28 140 g20 i/o c29 141 g19 i/o c30 142 f20 i/o c31 143 g18 i/o c32 144 f19 i/o c33 145 e20 i/o c34 146 g17 i/o c35 147 f18 i/o c36 149 d20 i/o c37 150 e18 i/o c38 151 d19 i/o c39 152 c20 i/o d0 154 d18 i/o d1 155 c19 i/o d2 157 b17 i/o d3 158 c17 i/o d4 160 a18 i/o d5 161 a17 i/o d6 162 c16 i/o d7 163 b16 i/o d8 164 a16 i/o d9 165 c15 i/o d10 166 d14 i/o d11 167 b15 i/o d12 169 c14 i/o d13 171 a14 i/o d14 172 c13 i/o d15 173 b13 i/o d16 174 a13 i/o d17 175 d12 i/o d18 176 c12 i/o d19 177 b12 i/o d20 186 a9 i/o d21 187 b9 i/o d22 188 c9 i/o d23 189 d9 i/o d24 190 a8 i/o d25 191 b8 i/o d26 192 c8 i/o d27 194 b7 i/o d28 196 c7 i/o d29 197 b6 i/o d30 198 a5 i/o d31 199 d7 i/o d32 200 c6 i/o d33 201 b5 i/o d34 202 a4 i/o d35 203 c5 i/o d36 205 a3 i/o d37 206 d5 i/o d38 207 c4 i/o d39 208 b3 208 272 signal pqfp bga 208 272 signal pqfp bga 208 272 signal pqfp bga 208 272 signal pqfp bga 208 272 signal pqfp bga all devices discontinued
16 specifications ispgdx family signal configuration: ispgdx160a ispgdx160a 272-ball bga signal diagram 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a nc 1 nc 1 i/o d4 i/o d5 i/o d8 nc 1 i/o d13 i/o d16 toe y3 nc 1 i/o d20 i/o d24 nc 1 nc 1 i/o d30 i/o d34 i/o d36 nc 1 gnd a b nc 1 nc 1 nc 1 i/o d2 i/o d7 i/o d11 nc 1 i/o d15 i/o d19 nc 1 bscan/ ispen i/o d21 i/o d25 i/o d27 i/o d29 i/o d33 nc 1 i/o d39 nc 1 nc 1 b c i/o c39 i/o d1 nc 1 i/o d3 i/o d6 i/o d9 i/o d12 i/o d14 i/o d18 y2 n c 1 i/o d22 i/o d26 i/o d28 i/o d32 i/o d35 i/o d38 nc 1 nc 1 i/o a1 c d i/o c36 i/o c38 i/o d0 gnd nc 1 vcc i/o d10 gnd i/o d17 vcc reset i/o d23 gnd i/o d31 vcc i/o d37 gnd nc 1 nc 1 i/o a2 d e i/o c33 nc 1 i/o c37 nc 1 i/o a0 i/o a3 nc 1 i/o a4 e f i/o c30 i/o c32 i/o c35 vcc ispgdx160a vcc i/o a5 i/o a7 i/o a8 f g i/o c28 i/o c29 i/o c31 i/o c34 bottom view i/o a6 i/o a9 i/o a10 i/o a11 g h nc 1 i/o c27 nc 1 gnd gnd nc 1 i/o a12 nc 1 h j i/o c23 i/o c24 i/o c25 i/o c26 gnd gnd gnd gnd i/o a13 i/o a14 i/o a15 i/o a16 j k nc 1 i/o c20 i/o c21 i/o c22 gnd gnd gnd gnd vcc i/o a18 i/o a17 i/o a19 k l i/o c19 i/o c17 i/o c18 vcc gnd gnd gnd gnd i/o a22 i/o a21 i/o a20 nc 1 l m i/o c16 i/o c15 i/o c14 i/o c13 gnd gnd gnd gnd i/o a26 i/o a25 i/o a24 i/o a23 m n nc 1 i/o c12 nc 1 gnd gnd nc 1 i/o a27 nc 1 n p i/o c11 i/o c10 i/o c9 i/o c6 i/o a34 i/o a31 i/o a29 i/o a28 p r i/o c8 i/o c7 i/o c5 vcc vcc i/o a35 i/o a32 i/o a30 r t i/o c4 nc 1 i/o c3 i/o c0 nc 1 i/o a37 nc 1 i/o a33 t u i/o c2 nc 1 nc 1 gnd i/o b36 vcc i/o b30 gnd i/o b22 tck/ sclk vcc i/o b17 gnd i/o b10 vcc nc 1 gnd i/o b0 i/o a38 i/o a36 u v i/o c1 nc 1 nc 1 i/o b37 i/o b34 i/o b31 nc 1 i/o b25 i/o b21 tms/ mode y0 i/o b18 i/o b14 i/o b12 i/o b9 i/o b6 i/o b3 nc 1 i/o b1 i/o a39 v w nc 1 nc 1 i/o b38 i/o b35 i/o b32 i/o b28 nc 1 i/o b24 i/o b20 tdo/ sdo nc 1 i/o b19 i/o b15 nc 1 i/o b11 i/o b7 i/o b2 nc 1 nc 1 nc 1 w y nc 1 i/o b39 nc 1 i/o b33 i/o b29 i/o b27 i/o b26 i/o b23 tdi/ sdi nc 1 y1 n c 1 i/o b16 i/o b13 nc 1 i/o b8 i/o b5 i/o b4 nc 1 nc 1 y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1. ncs are not to be connected to any active signals, vcc or gnd. note: ball a1 indicator dot on top side of package. all devices discontinued
17 specifications ispgdx family pin configuration: ispgdx160a ispgdx160a 208-pin pqfp (with heat spreader) pinout diagram ispgdx160a top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 vcc i/o a 0 i/o a 1 i/o a 2 i/o a 3 gnd i/o a 4 i/o a 5 i/o a 6 i/o a 7 i/o a 8 i/o a 9 i/o a 10 i/o a 11 gnd i/o a 12 vcc i/o a 13 i/o a 14 i/o a 15 i/o a 16 i/o a 17 i/o a 18 i/o a 19 gnd i/o a 20 i/o a 21 i/o a 22 i/o a 23 i/o a 24 i/o a 25 i/o a 26 vcc i/o a 27 gnd i/o a 28 i/o a 29 i/o a 30 i/o a 31 i/o a 32 i/o a 33 i/o a 34 i/o a 35 gnd i/o a 36 i/o a 37 i/o a 38 i/o a 39 vcc i/o b 0 i/o b 1 i/o b 2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 nc 1 i/o d1 i/o d 0 vcc i/o c 39 i/o c 38 i/o c 37 i/o c 36 gnd i/o c 35 i/o c 34 i/o c 33 i/o c 32 i/o c 31 i/o c 30 i/o c 29 i/o c 28 gnd i/o c 27 vcc i/o c 26 i/o c 25 i/o c 24 i/o c 23 i/o c 22 i/o c 21 i/o c 20 gnd i/o c 19 i/o c 18 i/o c 17 i/o c 16 i/o c 15 i/o c 14 i/o c 13 vcc i/o c 12 gnd i/o c 11 i/o c 10 i/o c 9 i/o c 8 i/o c 7 i/o c 6 i/o c 5 i/o c 4 gnd i/o c 3 i/o c 2 i/o c 1 i/o c 0 vcc data control muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 data control i/o b 3 gnd i/o b 4 i/o b 5 i/o b 6 i/o b 7 i/o b 8 i/o b 9 i/o b 10 i/o b 11 gnd i/o b 12 vcc i/o b 13 i/o b 14 i/o b 15 i/o b 16 i/o b 17 i/o b 18 i/o b 19 1 nc 1 nc y0 y1 gnd tdo/sdo tms/mode tck/sclk tdi/sdi i/o b 20 i/o b 21 i/o b 22 i/o b 23 i/o b 24 i/o b 25 i/o b 26 vcc i/o b 27 gnd i/o b 28 i/o b 29 i/o b 30 i/o b 31 i/o b 32 i/o b 33 i/o b 34 i/o b 35 gnd i/o b 36 i/o b 37 i/o b 38 i/o b 39 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk data control i/o d 39 i/o d 38 i/o d 37 i/o d 36 gnd i/o d 35 i/o d 34 i/o d 33 i/o d 32 i/o d 31 i/o d 30 i/o d 29 i/o d 28 gnd i/o d 27 vcc i/o d 26 i/o d 25 i/o d 24 i/o d 23 i/o d 22 i/o d 21 i/o d 20 reset vcc bscan/ispen gnd y3 y2 nc 1 toe i/o d 19 i/o d 18 i/o d 17 i/o d 16 i/o d 15 i/o d 14 i/o d 13 vcc i/o d 12 gnd i/o d 11 i/o d 10 i/o d 9 i/o d 8 i/o d 7 i/o d 6 i/o d 5 i/o d 4 gnd i/o d 3 i/o d 2 muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 data control 1. no connect pins (nc) are not to be connected to any active signal, vcc or gnd. all devices discontinued
18 specifications ispgdx family signal locations: ispgdx120a toe 150 136 reset 156 142 y0, y1, y2, y3, 63, 64, 152, 153 57, 58, 138, 139 bscan/ ispen 154 140 tdi/sdi 69 63 tck/sclk 68 62 tms/mode 67 61 tdo/sdo 66 60 gnd 8, 17, 27, 37, 50, 65, 77, 91, 101, 110, 120, 129, 6, 15, 25, 35, 44, 59, 71, 81, 91, 100, 110, 119, 130, 144, 161, 170 147, 156 vcc 3, 19, 35, 55, 79, 99, 115, 136, 155, 159 1, 17, 33, 49, 73, 89, 105, 122, 141, 145 nc 1 1, 2, 43, 44, 45, 46, 61, 62, 87, 88, 89, 90, 130, 131, 55, 56, 120, 137 132, 133, 134, 151, 175, 176 signal 176-pin tqfp 160-pin pqfp 1. nc pins are not to be connected to any active signals, vcc or gnd. i/o locations: ispgdx120a 176 160 signal tqfp pqfp i/o a0 4 2 i/o a1 5 3 i/o a2 6 4 i/o a3 7 5 i/o a4 9 7 i/o a5 10 8 i/o a6 11 9 i/o a7 12 10 i/o a8 13 11 i/o a9 14 12 i/o a10 15 13 i/o a11 16 14 i/o a12 18 16 i/o a13 20 18 i/o a14 21 19 i/o a15 22 20 i/o a16 23 21 i/o a17 24 22 i/o a18 25 23 i/o a19 26 24 i/o a20 28 26 i/o a21 29 27 i/o a22 30 28 i/o a23 31 29 i/o a24 32 30 i/o a25 33 31 i/o a26 34 32 i/o a27 36 34 i/o a28 38 36 i/o a29 39 37 i/o b0 40 38 i/o b1 41 39 i/o b2 42 40 i/o b3 47 41 i/o b4 48 42 i/o b5 49 43 i/o b6 51 45 i/o b7 52 46 i/o b8 53 47 i/o b9 54 48 i/o b10 56 50 i/o b11 57 51 i/o b12 58 52 i/o b13 59 53 i/o b14 60 54 i/o b15 70 64 i/o b16 71 65 i/o b17 72 66 i/o b18 73 67 i/o b19 74 68 i/o b20 75 69 i/o b21 76 70 i/o b22 78 72 i/o b23 80 74 i/o b24 81 75 i/o b25 82 76 i/o b26 83 77 i/o b27 84 78 i/o b28 85 79 i/o b29 86 80 i/o c0 92 82 i/o c1 93 83 i/o c2 94 84 i/o c3 95 85 i/o c4 96 86 i/o c5 97 87 i/o c6 98 88 i/o c7 100 90 i/o c8 102 92 i/o c9 103 93 i/o c10 104 94 i/o c11 105 95 i/o c12 106 96 i/o c13 107 97 i/o c14 108 98 i/o c15 109 99 i/o c16 111 101 i/o c17 112 102 i/o c18 113 103 i/o c19 114 104 i/o c20 116 106 i/o c21 117 107 i/o c22 118 108 i/o c23 119 109 i/o c24 121 111 i/o c25 122 112 i/o c26 123 113 i/o c27 124 114 i/o c28 125 115 i/o c29 126 116 i/o d0 127 117 i/o d1 128 118 i/o d2 135 121 i/o d3 137 123 i/o d4 138 124 i/o d5 139 125 i/o d6 140 126 i/o d7 141 127 i/o d8 142 128 i/o d9 143 129 i/o d10 145 131 i/o d11 146 132 i/o d12 147 133 i/o d13 148 134 i/o d14 149 135 i/o d15 157 143 i/o d16 158 144 i/o d17 160 146 i/o d18 162 148 i/o d19 163 149 i/o d20 164 150 i/o d21 165 151 i/o d22 166 152 i/o d23 167 153 i/o d24 168 154 i/o d25 169 155 i/o d26 171 157 i/o d27 172 158 i/o d28 173 159 i/o d29 174 160 176 160 signal tqfp pqfp 176 160 signal tqfp pqfp 176 160 signal tqfp pqfp 176 160 signal tqfp pqfp all devices discontinued
19 specifications ispgdx family pin configuration: ispgdx120a ispgdx120a 176-pin tqfp pinout diagram ispgdx120a top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 1 nc 1 nc vcc i/o a 0 i/o a 1 i/o a 2 i/o a 3 gnd i/o a 4 i/o a 5 i/o a 6 i/o a 7 i/o a 8 i/o a 9 i/o a 10 i/o a 11 gnd i/o a 12 vcc i/o a 13 i/o a 14 i/o a 15 i/o a 16 i/o a 17 i/o a 18 i/o a 19 gnd i/o a 20 i/o a 21 i/o a 22 i/o a 23 i/o a 24 i/o a 25 i/o a 26 vcc i/o a 27 gnd i/o a 28 i/o a 29 i/o b 0 i/o b1 i/o b 2 1 nc 1 nc clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk nc 1 nc 1 nc 1 gnd i/o d 1 i/o d 0 i/o c 29 i/o c 28 i/o c 27 i/o c 26 i/o c 25 i/o c 24 gnd i/o c 23 i/o c 22 i/o c 21 i/o c 20 vcc i/o c 19 i/o c 18 i/o c 17 i/o c 16 gnd i/o c 15 i/o c 14 i/o c 13 i/o c 12 i/o c 11 i/o c 10 i/o c 9 i/o c 8 gnd i/o c 7 vcc i/o c 6 i/o c 5 i/o c 4 i/o c 3 i/o c 2 i/o c 1 i/o c 0 gnd nc 1 nc 1 data control oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 data control 1 nc 1 nc i/o b 3 i/o b 4 i/o b 5 gnd i/o b 6 i/o b 7 i/o b 8 i/o b 9 vcc i/o b 10 i/o b 11 i/o b 12 i/o b 13 i/o b 14 1 nc 1 nc y0 y1 gnd tdo/sdo tms/mode tck/sclk tdi/sdi i/o b 15 i/o b 16 i/o b 17 i/o b 18 i/o b 19 i/o b 20 i/o b 21 gnd i/o b 22 vcc i/o b 23 i/o b 24 i/o b 25 i/o b 26 i/o b 27 i/o b 28 i/o b 29 1 nc 1 nc muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk data control nc 1 nc 1 i/o d 29 i/o d 28 i/o d 27 i/o d 26 gnd i/o d 25 i/o d 24 i/o d 23 i/o d 22 i/o d 21 i/o d 20 i/o d 19 i/o d 18 gnd i/o d 17 vcc i/o d 16 i/o d 15 reset vcc bscan/ispen 2 y3 y2 nc toe i/o d 14 i/o d 13 i/o d 12 i/o d 11 i/o d 10 gnd i/o d 9 i/o d 8 i/o d 7 i/o d 6 i/o d 5 i/o d 4 i/o d 3 vcc i/o d 2 nc 1 nc 1 muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk data control 1. nc pins are not to be connected to any active signals, vcc or gnd. all devices discontinued
20 specifications ispgdx family pin configuration: ispgdx120a ispgdx120a 160-pin pqfp pinout diagram ispgdx120a top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 vcc i/o a 0 i/o a 1 i/o a 2 i/o a 3 gnd i/o a 4 i/o a 5 i/o a 6 i/o a 7 i/o a 8 i/o a 9 i/o a 10 i/o a 11 gnd i/o a 12 vcc i/o a 13 i/o a 14 i/o a 15 i/o a 16 i/o a 17 i/o a 18 i/o a 19 gnd i/o a 20 i/o a 21 i/o a 22 i/o a 23 i/o a 24 i/o a 25 i/o a 26 vcc i/o a 27 gnd i/o a 28 i/o a 29 i/o b 0 i/o b1 i/o b 2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk nc 1 gnd i/o d 1 i/o d 0 i/o c 29 i/o c 28 i/o c 27 i/o c 26 i/o c 25 i/o c 24 gnd i/o c 23 i/o c 22 i/o c 21 i/o c 20 vcc i/o c 19 i/o c 18 i/o c 17 i/o c 16 gnd i/o c 15 i/o c 14 i/o c 13 i/o c 12 i/o c 11 i/o c 10 i/o c 9 i/o c 8 gnd i/o c 7 vcc i/o c 6 i/o c 5 i/o c 4 i/o c 3 i/o c 2 i/o c 1 i/o c 0 gnd data control oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 data control i/o b 3 i/o b 4 i/o b 5 gnd i/o b 6 i/o b 7 i/o b 8 i/o b 9 vcc i/o b 10 i/o b 11 i/o b 12 i/o b 13 i/o b 14 1 nc 1 nc y0 y1 gnd tdo/sdo tms/mode tck/sclk tdi/sdi i/o b 15 i/o b 16 i/o b 17 i/o b 18 i/o b 19 i/o b 20 i/o b 21 gnd i/o b 22 vcc i/o b 23 i/o b 24 i/o b 25 i/o b 26 i/o b 27 i/o b 28 i/o b 29 muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk data control i/o d 29 i/o d 28 i/o d 27 i/o d 26 gnd i/o d 25 i/o d 24 i/o d 23 i/o d 22 i/o d 21 i/o d 20 i/o d 19 i/o d 18 gnd i/o d 17 vcc i/o d 16 i/o d 15 reset vcc bscan/ispen y3 y2 nc 1 toe i/o d 14 i/o d 13 i/o d 12 i/o d 11 i/o d 10 gnd i/o d 9 i/o d 8 i/o d 7 i/o d 6 i/o d 5 i/o d 4 i/o d 3 vcc i/o d 2 muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk data control 1. nc pins are not to be connected to any active signals, vcc or gnd. all devices discontinued
21 specifications ispgdx family signal locations: ispgdx80a y1/toe 87 y0 38 reset 89 bscan/ ispen 35 tdi/sdi 39 tck/sclk 36 tms/mode 86 tdo/sdo 85 gnd 6, 18, 29, 45, 56, 68, 79, 95 vcc 12, 37, 62, 88 signal 100-pin tqfp i/o locations: ispgdx80a i/o a0 1 i/o a1 2 i/o a2 3 i/o a3 4 i/o a4 5 i/o a5 7 i/o a6 8 i/o a7 9 i/o a8 10 i/o a9 11 i/o a10 13 i/o a11 14 i/o a12 15 i/o a13 16 i/o a14 17 i/o a15 19 i/o a16 20 i/o a17 21 i/o a18 22 i/o a19 23 i/o b0 24 i/o b1 25 i/o b2 26 i/o b3 27 i/o b4 28 i/o b5 30 i/o b6 31 i/o b7 32 i/o b8 33 i/o b9 34 i/o b10 40 i/o b11 41 i/o b12 42 i/o b13 43 i/o b14 44 i/o b15 46 i/o b16 47 i/o b17 48 i/o b18 49 i/o b19 50 i/o c0 51 i/o c1 52 i/o c2 53 i/o c3 54 i/o c4 55 i/o c5 57 i/o c6 58 i/o c7 59 i/o c8 60 i/o c9 61 i/o c10 63 i/o c11 64 i/o c12 65 i/o c13 66 i/o c14 67 i/o c15 69 i/o c16 70 i/o c17 71 i/o c18 72 i/o c19 73 i/o d0 74 i/o d1 75 i/o d2 76 i/o d3 77 i/o d4 78 i/o d5 80 i/o d6 81 i/o d7 82 i/o d8 83 i/o d9 84 i/o d10 90 i/o d11 91 i/o d12 92 i/o d13 93 i/o d14 94 i/o d15 96 i/o d16 97 i/o d17 98 i/o d18 99 i/o d19 100 signal 100 tqfp signal 100 tqfp signal 100 tqfp signal 100 tqfp all devices discontinued
22 specifications ispgdx family pin configuration: ispgdx80a ispgdx80a 100-pin tqfp pinout diagram i/o a0 i/o a1 i/o a2 i/o a3 i/o a4 gnd i/o a5 i/o a6 i/o a7 i/o a8 i/o a9 vcc i/o a10 i/o a11 i/o a12 i/o a13 i/o a14 gnd i/o a15 i/o a16 i/o a17 i/o a18 i/o a19 i/o b0 i/o b1 i/o c19 i/o c18 i/o c17 i/o c16 i/o c15 gnd i/o c14 i/o c13 i/o c12 i/o c11 i/o c10 vcc i/o c9 i/o c8 i/o c7 i/o c6 i/o c5 gnd i/o c4 i/o c3 i/o c2 i/o c1 i/o c0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 58 ispgdx80a top view data control clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 1. pins have dual function capability. clk oe muxsel2 muxsel1 i/o d1 i/o d0 oe clk oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk data control muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 oe clk muxsel2 muxsel1 data control i/o d19 i/o d18 i/o d17 i/o d16 i/o d15 gnd i/o d14 i/o d13 i/o d12 i/o d11 i/o d10 vcc reset tms/mode 1 y1/toe 1 i/o d9 i/o d8 i/o d7 i/o d6 i/o d5 gnd i/o d4 i/o d3 i/o d2 i/o b2 i/o b3 i/o b4 gnd i/o b5 i/o b6 i/o b7 i/o b8 i/o b9 i/o b10 1 tdi/sdi i/o b11 i/o b12 i/o b13 i/o b14 gnd i/o b15 i/o b16 i/o b17 i/o b18 bscan/ispen 1 tck/sclk vcc y0 data muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 clk oe muxsel1 muxsel2 control i/o b19 tdo/sdo 1 all devices discontinued
23 specifications ispgdx family part number description ordering information table 2-0041/ispgdx 208-pin pqfp 176-pin tqfp 5 5 ispgdx160a-5q208 272-ball bga 5 ispgdx160a-5b272 160a 208-pin pqfp 7 ispgdx160a-7q208 272-ball bga 7 ispgdx160a-7b272 ispgdx120a-5t176 120 80 160-pin pqfp 5 ISPGDX120A-5Q160 176-pin tqfp 7 ispgdx120a-7t176 160-pin pqfp 7 ispgdx120a-7q160 100-pin tqfp 5 ispgdx80a-5t100 100-pin tqfp 7 ispgdx80a-7t100 i/o pins ordering number package tpd (ns) commercial device number 160a 120a 80a grade blank = commercial ispgdx xxxx x xxxx x speed 5 = 5ns tpd 7 = 7ns tpd package q208 = pqfp (with heat spreader) t176 = tqfp q160 = pqfp b272 = bga t100 = tqfp device family 0212/ispgdx all devices discontinued

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