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datasheet ax5051 v e rsi o n 1. 6
version 1.6 datasheet ax5051 2 document type datasheet document status document version version 1.6 product ax5051
tabl e of con t en ts 3 table of co ntents 1. overvi ew ....................................................................................................................... ............. 6 1. 1. f e at u r e s ....................................................................................................................... .................... 6 1. 2. ap p l ic at io ns ................................................................................................................... ................. 6 2. block diagr am .................................................................................................................. ......... 7 3. pin functi on descriptions ...................................................................................................... .... 8 3. 1. p i n o ut d r aw in g ................................................................................................................. .............. 9 4. specifi catio n s . ................................................................................................................ ......... 10 4. 1. ab s o lut e max i m u m r a t i ng s ....................................................................................................... .1 0 4. 2. d c c h a r act e r i st ic s ............................................................................................................. .......... 1 1 s u p p l i es ....................................................................................................................... ................... 1 1 l o g i c .......................................................................................................................... ..................... 1 2 4. 3. ac c h a r a c te r i st ic s ............................................................................................................. .......... 1 3 c r yst a l os cillat o r ............................................................................................................. .............. 1 3 r f f r e q u e n c y g e ne r a t i on s u bs yst e m ( s yn t h e s ize r ) ................................................................ 1 4 t r a n s m it t e r .................................................................................................................... .................. 1 5 r e c e iv e r ....................................................................................................................... .................. 1 6 s p i t i m i n g ..................................................................................................................... ................... 1 8 5. circuit descr i ption ............................................................................................................ ....... 19 5. 1. v o l t a g e r e gu l a t o r .............................................................................................................. ......... 2 0 5. 2. c r yst a l os cillat o r ............................................................................................................. .............. 2 0 5. 3. s y sc l k outp ut .................................................................................................................. ............ 2 1 5. 4. p o w e r - o n -r es et ( p o r ) a n d r e s e t_ n i n p u t ................................................................................ 2 1 5. 5. r f f r e q u e n c y g e ne r a t i on s u bs yst e m ....................................................................................... 2 1 v c o ............................................................................................................................ .................... 2 2 v c o au t o -ra n g i n g ............................................................................................................... ....... 2 2 l o o p f ilt e r a n d c h a r g e p u m p .................................................................................................... 22 versi o n 1. 6 datasheet a x 5051
tabl e of con t en ts 4 r e g i st e r s ...................................................................................................................... ................... 2 2 5. 6. r f i n put a n d o u t p ut st ag e ( a n t p / an t n ) ................................................................................ 2 3 l n a ............................................................................................................................ ...................... 2 3 i / q mi x e r ...................................................................................................................... ................... 2 3 p a ............................................................................................................................. ....................... 2 3 5. 7. an a l o g i f f ilte r ............................................................................................................... ............... 2 3 5. 8. d i g i t a l i f cha n ne l f i lt e r a n d d e m o du l a t o r ............................................................................... 2 3 r e g i st e r s ...................................................................................................................... ................... 2 4 5. 9. e n c o de r ........................................................................................................................ ................. 2 4 5. 10. f r a m in g a n d f i fo ............................................................................................................... .... 2 5 h d l c mo de ...................................................................................................................... ............. 2 6 r a w mo de ....................................................................................................................... .............. 2 6 r a w mo de w i t h p r e a m b l e mat c h ............................................................................................. 2 6 8 0 2 . 1 5 . 4 ( z i g b e e ) .............................................................................................................. ............. 2 7 5. 11. r x ag c a n d r s s i ................................................................................................................ .... 2 7 5. 12. mo du l a t o r ...................................................................................................................... .......... 2 8 5. 13. aut o mat i c fr e q u e n c y co nt r o l ( a f c ) .................................................................................. 2 8 5. 14. p w r m o d e r e g i st e r ............................................................................................................... .2 9 5. 15. s e r i a l pe r i p h e r a l i n t e r f a c e ( s p i ) ............................................................................................ 3 1 s p i t i m i n g ..................................................................................................................... ................... 3 1 6. register ban k descriptio n ...................................................................................................... .3 2 6. 1. c o nt r o l r e g i st e r ma p ........................................................................................................... ........ 3 3 7. application information ........................................................................................................ .. 37 7. 1. t y p i c a l ap p lic a t io n d i a g r a m .................................................................................................... .3 7 7. 2. ant e n n a i n t e r f a c e c i r c uit r y .................................................................................................... .... 3 8 s i n g l e -en d ed an t e nn a i n t e r f a c e ............................................................................................... 3 8 d i p o l e ant e n n a i n t e r f ace ....................................................................................................... .... 3 9 7. 3. v o l t a g e r e gu l a t o r .............................................................................................................. ......... 3 9 versi o n 1. 6 datasheet a x 5051
tabl e of con t en ts 5 8. qfn28 pac k age inf o rma t ion .................................................................................................. 40 8. 1. p a c k a g e out l ine qf n2 8 .......................................................................................................... ... 4 0 8. 2. qf n 2 8 s o l d e r in g p r o fil e ........................................................................................................ ....... 4 1 8. 3. qf n 2 8 r e c o m m e n de d pa d l a yo ut ......................................................................................... 4 2 8. 4. as s e m b l y p r o c e s s ............................................................................................................... .......... 4 2 st en c i l de s i g n & s o l d e r pa st e ap pl ic at io n ............................................................................... 4 2 9. life support applications ...................................................................................................... .. 44 10 . contact in fo rmation ............................................................................................................ .... 45 versi o n 1. 6 datasheet a x 5051
ov e r v i ew 6 1. overv i ew 1. 1 . features ? advan ced multi-chann e l single chip u h f tra n sceiver ? configurable for usage in 400- 470 mhz and 800-930 m h z srd bands ? wide variety of shaped modulations supported in rx and tx (ask , ps k , ms k, f s k) ? data rates fr om 38.4 to 200 kbps (fsk, m s k) a n d to 600 kb ps (ask, ps k) ? ultra fast sett ling rf fr equency synthesizer for low - power consumptio n ? variable ch annel filterin g from 40 k h z t o 60 0 k h z ? 80 2. 1 5 . 4 c o m patible ? rf carrier fre q uency and fsk deviation programmable in 1 hz steps ? fully integrat ed rf freque ncy synthesizer with vc o au to-ranging and band-width boost modes for fast locking ? few extern al comp o nents ? on chip c o mmunicatio n controller and flexible digital mod e m ? channel hopping up to 2000 hops/s ? sensitivit y d o wn t o ?104 dbm ? up to + 1 2 dbm programmable transmitter pow e r amplifier for long range opera t ion ? crystal oscill ator with programmable transcon ductance and programmable internal tuning capacitors for low cost crystals ? automati c frequency co ntrol (afc) ? spi micro- co ntroller interface ? fully integrated current/voltage references ? qfn28 pa ckage ? low po wer r ecei ver: 20 - 21 m a in high sensitivity mod e an d 17-18 ma in low po wer mode ? low power tr ansmitter 11 - 40 m a during transmit ? extend ed su pply voltage range 2. 3v - 3 . 6 v ? internal po wer-on-reset ? 32 bit rx/t x data fifo ? programma ble cycli c r e dundancy check (crc -ccitt, c r c - 16, crc - 32) ? optional spectral shaping using a self synchro n izing shift r e gister ? brown-out d e tection ? integrated rx/t x switching ? differentia l a n tenna pins 1. 2. a ppli c a t ions 40 0- 4 7 0 m h z and 8 00- 93 0 m h z d a t a t r ansmission and re cept ion in t h e short range devi ces ( s rd) b a nd. ? te lemet r ic appl icat io ns, se nsor readout ? toys ? w i reless a u d i o ? w i reless n e tworks ? w i reless u s b ? access co ntrol ? remo te k e y l ess en try ? ari b co mpat ible ? poin t i ng devices and k e y b oards ? act i v e rfid ? rfi d base stat ion t r ansmitt e r ? 43 3/ 86 8/ 91 5 m h z srd band sys t ems versi o n 1. 6 datasheet a x 5051
block diagra m 7 2. block diagram a x5051 4 ant p 5 ant n if f ilt er & ag c p g a s a gc crys t a l osci ll at o r ty p . 16 m h z f ou t rf frequency genera t i o n subsy s t e m f xta l c o m m u n i c a t io n c o nt r o lle r & seria l i n t e rface divid e r a d c mi x e r digi tal i f channe l fi l t er lna pa de- mo d u la t o r enco de r fr a m i n g fif o mo d u la t o r 13 syscl k 27 28 cl k 16n rss i chip configura t i o n 16 15 14 se l cl k mi so 17 mosi 24 v re g 20 vol t age reg u l a t o r por vdd_i o re se t_n 19 ir q 12 cl k 16p figure 1 fun c tio nal block diagram of the ax505 1 versi o n 1. 6 datasheet a x 5051
pin fun c t i on descrip t ion s 8 3. pin fu nct i o n de sc ri pt ion s symbol pin ( s ) type description nc 1 n no t to be co nn ec ted v dd 2 p pow e r suppl y, must b e suppl ie d w i t h reg u l a t e d v o l t age v r eg gn d 3 p g r o u n d an t p 4 a an t e n n a i n p u t / o u t p ut an t n 5 a an t e n n a i n p u t / o u t p ut gn d 6 p g r o u n d v dd 7 p pow e r suppl y, must b e suppl ie d w i t h reg u l a t e d v o l t age v r eg nc 8 n no t to be co nn ec ted ts t1 9 i mu s t b e co nn e c ted to g n d ts t2 1 0 i mu s t b e co nn e c ted to g n d gn d 1 1 p g r o u n d reset _ n 1 2 i o p ti o n a l r e s e t p i n i f t h is pin is not used i t mus t be conn ec ted to vdd_i o sysc l k 1 3 i / o defaul t func t i o n al it y: cryst a l osci ll at or ( o r di v i ded ) cl ock output can be pr og ra mme d to be us e d as a ge ne ra l purpose i / o pi n sel 14 i serial periphera l int e rface s e l e ct clk 15 i serial periphera l int e rfa c e cl oc k mi so 16 o serial periphera l int e rfa c e da ta ou t p u t mosi 17 i serial periphera l int e rfa c e da ta input ts t3 1 8 i mu s t b e co nn e c ted to g n d irq 1 9 i/ o de faul t funct i onal it y: t r a n smit and rece iv e inte rrup t can be pr og ra mme d to be us e d as a ge ne ra l purpose i / o pi n v dd_i o 20 p u n reg u l a te d pow e r suppl y n c 2 1 n no t c o nn ec ted gn d 2 2 p g r o u n d nc 2 3 n no t to be co nn ec ted v r e g 2 4 p r e g u la t e d out p u t v o lt a g e vdd pins mus t be connec t e d t o this supply v o l t ag e a 1f l o w esr c a pacitor t o g n d must b e con n ec ted to t h is pin nc 2 5 n no t to be co nn ec ted v dd 26 p pow e r suppl y, must b e suppl ie d w i t h reg u l a t e d v o l t age v r eg cl k16p 27 a cryst a l osci ll at or input / ou t p u t cl k16n 28 a cryst a l osci ll at or input / ou t p u t a = anal og signal i / o = d i gi ta l i n p u t/ o u tp u t s i g n a l i = dig i t a l input signal n = n o t to b e c o n n e c t ed o = d i gi ta l o u tp u t s i g n a l p = po w e r or grou n d all dig i t a l inputs are schmi tt t r ig ge r inpu t s , dig i t a l inpu t an d ou t p u t l e v e l s are lvcmo s /lvtt l c o mpa t ible an d 5 v to l e r a n t . th e c e n t r e p a d of th e q f n2 8 p a ck ag e s h oul d b e con n e c te d to gn d. versi o n 1. 6 datasheet a x 5051
pin fun c t i on descrip t ion s 9 3. 1 . pinout drawing clk16 n figure 2 : p i n o ut drawing (top v i ew) 22 23 2 5 2 4 26 27 28 clk16p vreg gnd vdd nc nc nc nc 21 1 20 vd d _ i o vd d 2 19 irq g nd 3 ax5051 18 tst3 4 an tp 17 mos i an tn 5 16 mis o 6 gnd clk 15 vd d 7 10 11 12 13 14 8 9 nc reset _ n gnd sysclk tst1 tst2 sel versi o n 1. 6 datasheet a x 5051
spe c ificat ions 10 4. specific a tions 4. 1. a b solu te maximu m ra ting s st re sses abov e t h ose l i st e d u n d e r absolu te maximu m r a t i ngs may cau s e p e r m an en t damage to th e de v i c e . this is a st re ss rat i ng onl y ; fu nct i onal operat ion of the dev i ce at t h ese or any ot he r condit ions abo v e t h o s e l i ste d in t h e ope r ational se ct ions of t h is sp e c ificat ion is no t impl ie d. expos u re t o abso lu te m a ximu m ra t i ng condi t io ns for e x te nde d pe riods may affe ct dev i c e r e l i a b il it y . symbol descr i pt ion condit ion min ma x unit v dd_i o s u p p l y v o l t ag e -0. 5 5. 5 v i d d s u p p l y curre nt 1 0 0 ma p to t t o t a l pow e r consumpt ion 800 m w p i a b so l u t e maxi mum input pow e r a t re ce iv e r input 1 5 d b m i i1 dc curr en t in to any pin e x ce pt an t p , an t n - 1 0 1 0 ma i i2 d c c u r r en t i n t o p i n s a n t p , an t n - 1 0 0 1 0 0 ma i o o u t p u t curr e n t 4 0 ma i n p u t v o lt a g e an t p , an t n pins - 0 . 5 5. 5 v v ia i n p u t v o l t a g e d i gi ta l p i n s - 0 .5 5 . 5 v v es e l e c t r os t a t i c ha ndl ing h b m - 2 0 0 0 2 0 0 0 v t amb o p era t i n g tem p era t ur e -4 0 8 5 c t st g s t ora g e te mp e r at ur e - 6 5 1 5 0 c t j j u n c t i o n t e mp e r a t ur e 1 5 0 c versi o n 1. 6 datasheet a x 5051
spe c ificat ions 11 4.2 . dc ch ara c t e ri sti c s supplies symbol descr i pt ion condit ion min . typ. ma x. unit t am b o p e r a t ional ambie n t te mpe r at ur e - 4 0 2 7 8 5 c rx opera t io n or t x op era t ion u p to 4 d b m o u tp u t p o we r 2. 3 3 . 0 3. 6 v vdd_i o i / o and v o l t age regul a t o r sup p ly vo lt a g e t x op era t ion up t o 12 d b m ou t p u t po w e r 2. 4 3 . 0 3. 6 v p o we r - d o wn m o d e p w rmod e=0x00 1 . 7 v vreg int e rnall y re g u late d suppl y vo lt a g e all ot he r p o w e r mode s 2. 1 2. 5 2. 8 v vreg dr o p t y p r e g u la t o r v o lt ag e d r o p rx opera t io n or t x op era t ion u p to 4 d b m o u tp u t p o we r 5 0 m v vreg dr o p max r e g u la t o r v o lt ag e d r o p at maximum inte r n al curre nt consump t ion tx mo de w i t h 1 2 dbm ou t p u t pow e r 3 0 0 m v i pdow n p o w e r-dow n cu rre nt p w rmod e = 0 x 0 0 0. 5 a 868 mhz, bit r a te 10 kbit /s 20 868 mhz, bit r a te 600 kbit /s 21 433 mhz, bit r a te 10 kbit /s 20 i rx - h s curren t co nsumpt ion r x hig h se nsi t iv it y mode: v c o_i=001; ref_ i = 011 433 mhz, bit r a te 600 kbit /s 21 ma 868 mhz, bit r a te 10 kbit /s 17 868 mhz, bit r a te 600 kbit /s 18 433 mhz, bit r a te 10 kbit /s 17 i rx - l p curren t co nsumpt ion r x l o w p o we r m o d e : v c o_i=001; ref_ i = 101 433 mhz, bit r a te 600 kbit /s 18 ma 868 mhz, 10 dbm 36 868 mhz, 4 dbm 23 868 mhz, 0 dbm 18 868 mhz, -12 dbm 11 433 mhz, 12 dbm 36 433 mhz, 6dbm 23 433 mhz, 2 dbm 19 i tx curren t co nsumpt ion tx v c o_i=001; ref_ i = 011; l o cu r s t = 1 433 mhz, -8 dbm 12 ma versi o n 1. 6 datasheet a x 5051
spe c ificat ions 12 log i c symbol descr i pt ion condit ion min . typ. ma x. unit d i g i ta l i n p u ts v t+ s c h m it t t r ig g e r low t o h i g h t h re shol d point 1. 9 v v t- s c h m i t t tr i g g e r h i gh to l o w t h re shol d point 1. 2 v v il input v o l t age, low 0. 8 v v ih i n p u t v o l t age, hig h 2. 0 v i l i n p u t l e akag e curre n t - 1 0 1 0 a digit a l output s i oh o u t p u t curr en t , h i g h v oh = 2. 4 v 4 ma i ol o u t p u t curr en t , l o w v ol = 0. 4 v 4 ma i oz tri - s t a t e ou tp u t l e ak ag e cur r en t -1 0 1 0 a versi o n 1. 6 datasheet a x 5051
spe c ificat ions 13 4. 3. a c chara c ter i s t ic s cryst a l osci llat o r symbol descr i pt ion condit ion min . typ. ma x. unit f xta l cryst a l fre q ue ncy n o te 1 16 mhz x t a l oscg m = 0 0 0 0 1 x t a l oscg m = 0 0 0 1 2 x t a l oscg m =0010 defaul t 3 x t a l oscg m =0011 4 x t a l oscg m =0100 5 x t a l oscg m =0101 6 x t a l oscg m =0110 6. 5 x t a l oscg m =0111 7 x t a l oscg m =1000 7. 5 x t a l oscg m =1001 8 x t a l oscg m =1010 8. 5 x t a l oscg m =1011 9 x t a l oscg m =1100 9. 5 x t a l oscg m =1101 10 x t a l oscg m =1110 10. 5 gm os c t r a n s c ondu c t a n ce oscil l a t o r x t a l oscg m =1111 11 ms x t a l ca p = 0 0 0 000 defaul t 2 pf c osc programmabl e t u ning capacitors at pins cl k16n and cl k16p x t a l ca p = 1 1 1 111 33 pf c osc - l s b programmabl e t u ning capacitors , incr emen t per ls b of xt al c a p 0. 5 pf f ext ex t e r n al c l ock i n put n o te 2 16 mhz ri n osc input dc impedanc e 10 k ? not e s 1. t o l e rances an d st ar t - up t i m e s depend on t he cry s t a l used. dep ending on t he rf fre q uency and channe l spacing t he i c must be c al i b r a t e d to t he exac t cry s t a l frequency using t he re ad ings of t he regis t er trkfreq 2 . i f a n ext e rna l c l o c k is used, it sho u l d b e in p u t v i a a n ac co up l i ng at p i n c l k 1 6 p w i t h t he o s ci l l a t o r p o w e red up a n d xt alc a p = 0000 00 versi o n 1. 6 datasheet a x 5051
spe c ificat ions 14 r f fr e q uen c y ge ner a t i on s u bs ys t e m ( s yn t h esi z er) symbol descr i pt ion condit ion min . typ. ma x. unit f re f r e fe r e nc e fr e q ue n c y 1 6 mhz f range_hi b a n d sel = 0 8 0 0 9 3 0 f range_lo w f r e q ue nc y r a ng e ba n d sel = 1 4 0 0 4 7 0 mhz f re so f r e q u e n c y resol u t i o n 1 h z bw 1 loop f i l t er c o nf i g ura t i o n : fl t= 0 1 char g e pump curre nt: p l lcpi=010 1 0 0 bw 2 loop f i l t er c o nf i g ura t i o n : fl t= 0 1 char g e pump curre nt: p l lcpi=001 5 0 bw 3 loop f i l t er c o nf i g ura t i o n : fl t= 1 1 char g e pump curre nt: p l lcpi=010 2 0 0 bw 4 sy nthesizer l o op band w i d t h v c o curr e n t: vco i =001 loop f i l t er c o nf i g ura t i o n : fl t= 1 0 char g e pump curre nt: p l lcpi=010 5 0 0 khz t set 1 loop f i l t er c o nf i g ura t i o n : fl t= 0 1 char g e pump curre nt: p l lcpi=010 1 5 t set 2 loop f i l t er c o nf i g ura t i o n : fl t= 0 1 char g e pump curre nt: p l lcpi=001 3 0 t set 3 loop f i l t er c o nf i g ura t i o n : fl t= 1 1 char g e pump curre nt: p l lcpi=010 7 t set 4 sy nthesizer sett l i ng t i m e for 1mhz s t ep as t y pically required for rx/ t x s w i t chin g v c o curr e n t: vco_ i = 001 loop f i l t er c o nf i g ura t i o n : fl t= 1 0 char g e pump curre nt: p l lcpi=010 3 s t st a r t 1 loop f i l t er c o nf i g ura t i o n : fl t= 0 1 char g e pump curre nt: p l lcpi=010 2 5 t st a r t 2 loop f i l t er c o nf i g ura t i o n : fl t= 0 1 char g e pump curre nt: p l lcpi=001 5 0 t st a r t 3 loop f i l t er c o nf i g ura t i o n : fl t= 1 1 char g e pump curre nt: p l lcpi=010 1 2 t st a r t 4 synthe size r s t art-up t i m e if cry s t a l oscill at or and refer e n c e ar e r u nning v c o curr e n t: vco_ i = 001 loop f i l t er c o nf i g ura t i o n : fl t= 1 0 char g e pump curre nt: p l lcpi=010 5 s 868 mhz, 50 khz from carrie r -85 868 mhz, 100 khz from carri e r -90 868 mhz, 300 khz from carri e r -100 pn 868 1 868 mhz, 2 mh z from carrie r -110 433 mhz, 50 khz from carrie r -90 433 mhz, 100 khz from carri e r -95 433 mhz, 300 khz from carri e r -105 pn 433 1 sy nthesizer pha s e noise loop f i l t er c o nf i g ura t i o n : f l t = 01 char ge pump curren t : pl l c pi =010 v c o curr e n t: vco_ i = 001 433 mhz, 2 mh z from carrie r -115 dbc/h z 868 mhz, 50 khz from carrie r -80 868 mhz, 100 khz from carri e r -90 868 mhz, 300 khz from carri e r -105 pn 868 2 868 mhz, 2 mh z from carrie r -115 433 mhz, 50 khz from carrie r -90 433 mhz, 100 khz from carri e r -95 433 mhz, 300 khz from carri e r -110 pn 433 2 sy nthesizer pha s e noise loop f i l t er c o nf i g ura t i o n : f l t = 01 char ge pump curren t : pl l c pi =001 v c o curr e n t: vco_ i = 001 433 mhz, 2 mh z from carrie r -122 dbc/h z versi o n 1. 6 datasheet a x 5051
spe c ificat ions 15 trans m itte r symbol descr i pt ion condit ion min . typ. ma x. unit a s k & psk 38. 4 600 sbr signal bit ra te f s k 3 8 . 4 2 0 0 kbps t x r n g = 0 0 0 0 - 4 0 t x r n g = 0 0 0 1 -7. 5 t x r n g = 0 0 1 0 - 2 t x r n g = 0 0 1 1 1. 5 t x r n g = 0 1 0 0 3. 5 t x r n g = 0 1 0 1 5. 5 t x r n g = 0 1 1 0 6. 5 t x r n g = 0 1 1 1 7. 5 t x r n g = 1 0 0 0 8. 5 t x r n g = 1 0 0 1 9. 5 t x r n g = 1 0 1 0 1 0 t x r n g = 1 0 1 1 10. 5 t x r n g = 1 1 0 0 1 1 t x r n g = 1 1 0 1 11. 5 t x r n g = 1 1 1 0 1 2 pt x 868 t r ansmi tte r po w e r @ 868 mh z lo c u r s t= 1 t x r n g = 1 1 1 1 12. 5 dbm pt x 433 t r ansmi tte r po w e r @ 433 mh z t x r n g=1111 13 dbm pt x 868- harm2 e m ission @ 2 nd harmonic -50 pt x 868- harm3 e m ission @ 3 rd h a rmonic no te 1 - 5 5 dbc not e s 1. addit i on al l o w - pass fi l t ering w a s app l ie d t o t he an t enna in t e rf ace, see sect i o n 7: a p p l icat i o n i n form at i o n. versi o n 1. 6 datasheet a x 5051
spe c ificat ions 16 receiver symbol descr i pt ion condit ion min . typ. ma x. unit a s k & psk 38. 4 600 sbr signal bit ra te f s k 3 8 . 4 2 0 0 kbps a s k 3 8 . 4 kbps -103 a s k 5 0 kbps -102 a s k 1 00kbps -100 a s k 2 00 kbps -97 f s k 38. 4 kbps -104 f s k 50 kbps -103 f s k 100kbps -101 f s k 200kbps -98 psk 200 kbps -100 psk 400 kbps -97 psk 600 kbps -95 is 868_ hs input se nsi t i v it y at b e r = 10 -3 for 868 mhz op e r a t ion hig h se nsi t iv it y mode: v c o_i=001; ref_ i = 011; rx i m i x = 01 no t e 6 802. 15. 4 ( z i g bee) -102 dbm a s k 3 8 . 4 kbps -101 a s k 5 0 kbps -100 a s k 1 00kbps -98 a s k 2 00 kbps -95 f s k 38. 4 kbps -102 f s k 50 kbps -101 f s k 100kbps -99 f s k 200kbps -95 psk 200 kbps -98 psk 400 kbps -95 psk 600 kbps -93 is 868_ ls input se nsi t i v it y at b e r = 10 -3 for 868 mhz op e r a t ion l o w p o we r m o d e : v c o_i=001; ref_ i = 101; rx i m i x = 01 no t e 6 802. 15. 4 ( z i g bee) -100 dbm i l maximum inpu t l e v e l -20 dbm cp 1db input re f e rre d compre ssion poi n t -35 iip3 input re f e rr e d ip3 2 t o ne s se para te d by 100 khz - 2 5 dbm rssi r rssi cont rol range 85 db rssi s 1 rssi st e p siz e b e f o re d i g i t a l c h a n ne l f i lt e r ; c a lc u l a t e d f r om r e g i st e r a g cco u n te r 0 . 6 2 5 d b rssi s 2 rssi st e p siz e behind di git a l chann e l fil t er; c a lc u l a t e d f r om r e g i st e r s a g cco u n te r , tr k a mp l 0 . 1 d b versi o n 1. 6 datasheet a x 5051
spe c ificat ions 17 symbol descr i pt ion condit ion min . typ. ma x. unit a d jace nt channe l suppre ssion 18 al t e rna t e channe l suppre ssion f s k 50 kbps, not e s 1 & 2 1 9 db a d jace nt channe l suppre ssion 16 al t e rna t e channe l suppre ssion f s k 100 kbps, not e s 1 & 3 3 0 db a d jace nt channe l suppre ssion 17 sel 868 al t e rna t e channe l suppre ssion psk 200 kbps, not e s 1 & 4 2 8 db bl ocking a t +/- 1mhz offset 38 bl ocking a t - 2 m hz offs et 40 bl ocking a t +/- 10mhz offset 60 blk 868 bl ocking a t +/- 100mhz offset 82 im r r 868 i m a g e r e je ct ion f s k 100 kbps, no t e 5 3 0 db not e s 1. i n t e rferer/channel @ ber = 10 -3 , channe l leve l is +10db above t he t y pi cal sensit ivi t y, t he in t e r f ering signal is a rando m dat a sig n a l ( e xcep t ps k200 ); bo t h c h ann e l an d int e r f erer are m o d u l a t e d w i t h ou t s h aping 2. fs k 50 kbps : 868 m h z, 2 00 kh z c h anne l s p ac ing, 25 k h z d e via t i o n, pr ogram m i ng as rec o m m en d e d in pr ogram m i ng m a nu a l 3. fsk 100 kb ps: 86 8 mhz, 400 khz c h annel s p ac ing, 5 0 khz d e via t ion , prog ramm ing as rec o mm en d e d in program m i ng m a nu a l 4. psk 200 kbps : 868 m h z, 400 khz c h annel s p ac ing, pr ogram m i n g as rec o mm en d e d i n program m i ng m a n u a l , int e r f ering signal is a c o nst a n t w a ve 5. channel /b l o cker @ ber = 10 -3 , channe l l e ve l is +10db above the t y pi cal sensit ivi t y, t he bl ocker signa l is a cons t a n t w a ve; ch anne l signa l is m o du l a t e d w i t h ou t s h aping, t he im age frequency l i es 2 m h z above t he w a n t ed signa l 6. s ens itivi t ies for the 43 3 m h z band are 1- 2 d b be tter t h an t h os e for the 868 m h z ban d versi o n 1. 6 datasheet a x 5051
spe c ificat ions 18 spi t i ming symbol descr i pt ion condit ion min . typ. ma x. unit t ss se l fal ling e d ge t o cl k rising e d g e 10 ns t s h cl k fall ing e d ge t o se l rising edge 10 ns t ssd se l fal ling e d ge t o mi so dri v ing 0 10 ns t ssz se l rising edge t o mi so hig h -z 0 10 ns ts m o s i s e tu p ti m e 1 0 n s th mosi ho l d t i me 10 ns t c o cl k fall ing e d ge t o mi so out p ut 10 ns t c k cl k pe riod n o te 1 50 ns t c l c l k low d u r a t i on 4 0 n s tch clk high dura t i on 40 ns not e s 1. for sp i acce ss d u ring pow e r-d o w n m o d e t he period shoul d be re l a xed t o 10 0ns. for a figu r e showing the spi t i mi ng para me ter s se e s e c t i o n 5. 15: serial periph era l in terf ac e (s p i ) . versi o n 1. 6 datasheet a x 5051
circui t d e scr i pt ion 19 5 . ci rc ui t de sc ri pt io n the a x 50 51 is a t r ue sing l e chip l o w- powe r cmos t r ansce i v e r primaril y for u s e in srd bands . the o n -chip t r ansce i v e r consist s of a full y in t e g r a t e d r f f r o n t- e n d w i th m o d u l a to r, a n d demod u la to r. base ban d data pro c essing is i m pl eme n t e d in an ad v a nce d and fl e x ible commu n icat ion co nt ro l l e r t h at e n abl e s u s e r frie ndl y commu n icat ion v i a the spi interface . a x 50 51 ca n be op era t e d f r om a 2. 3 v t o 3. 6 v power s u pp l y o v er a te mp era t ure r a nge of -4 0 o c t o 85 o c , i t c o n s u m e s 1 1 - 4 0 m a f o r t r a n s m i t t i n g , d e p e n d i n g o n t h e o u t p u t p o w e r , 2 0 - 2 1 m a f o r r e c e iv i n g i n h i g h s e ns it iv it y m o d e a n d 17 ? 18 ma f o r recei v ing in low power mode. the ax5 051 fe at u r es make i t an ideal int e rface for int e grat i o n int o v a ri ou s batt e r y powe re d s r d s o l u ti o n s s u c h a s ti c k e t i n g o r a s tr a n s c e i v e r f o r te l e m e tr i c a p p l i c a t i o n s e . g. i n s e n s o r s . a s primary appl icat ion, t h e t r ansce i v e r i s inte nd e d f o r u h f radio equipment in accordance wi t h the e u rope an te le co mmu n icat ion standard i n st i t ut e ( e tsi ) spe c ificat ion en 30 0 22 0 - 1 and the u s federal com m unica t ion s co m m ission ( f cc) standard cfr47, part 15. the use of a x 50 51 in accord anc e to f c c pa r 1 5 . 247, allo ws f o r i m pro v ed rang e i n the 91 5 m h z ba nd . a d d i t i ona lly a x 5 0 5 1 i s compa t i b l e wi th t h e lo w f r e q u e ncy s t an d a rd s of 802 . 15. 4 ( z igbee ) . the a x 50 51 send s a n d rec e i v es d a ta v i a t h e sp i port i n f r am es. thi s s t an d a rd opera t i o n mod e i s call ed fram e m o d e . pre and pos t amb l es as well as chec ksums can be genera ted aut o ma t i cally. i n terrupt s cont rol the da t a flow between a cont roller a n d the a x 50 51 . the ax5 051 be hav e s as a spi sl av e int e rface . configu r at ion of t h e ax 50 51 i s a l s o d o n e v i a th e sp i in terf ace. a x 50 51 s u p p o r t s a n y d a t a r a t e f r o m 3 8 . 4 k b p s t o 2 0 0 k b p s f o r f s k a n d m s k a n d f r o m 3 8 . 4 kbps for 6 00 kbps for ask and psk. to achi ev e opt i mu m performance f o r spe c ific dat a rate s and mod u la t i on sc he me s s e vera l regi s t er s e t t i n gs t o con f i g ure the ax 505 1 are n e c e ssary, th ey are ou tl i n ed i n t h e f o llo wi ng, f o r d e t a i l s s ee t h e a x 50 51 programming manua l . spreading a n d des p rea d ing is possi ble on all d a t a ra tes a n d mod u la ti on sch e mes . the n e t t r a n s f e r r a t e i s r e d u c e d b y a f a c t o r o f 1 5 i n t h i s c a s e . f o r z i g b e e e i t h e r 6 0 0 o r 3 0 0 k b p s m o d e s h a v e t o be c h o s en . the r e cei v er suppor t s m u l t i - c h an ne l opera t i o n fo r all da ta ra tes and modula tion sc he me s. versi o n 1. 6 datasheet a x 5051
circui t d e scr i pt ion 20 5. 1. v o ltage r e gula t o r the ax5 051 u s e s an on-chip v o lt ag e re gul a t o r t o cre a te a st able suppl y v o ltage for t h e i n te r n a l c i r c u i tr y a t p i n v r e g f r o m th e p r i m a r y s u p p l y v d d _ i o . a ll v d d pi n s o f th e d e vi c e m u s t be con n ec t e d t o v r eg. the an te nn a pi ns a n tp and a n tn mu s t b e dc bi ased t o v r eg. the i / o le ve l of the digital pi ns is v dd_i o . the v o ltage regula t o r r e quires a 1 f low esr cap a cit o r a t pin v r eg. in po we r-down mode the v o ltag e regu l a tor t y pi call y outputs 1 . 7 v at v r e g , if it is powe re d- up i t s outp ut ris e s t o t y pically 2. 5 v . at de v i ce power-up t h e reg u la tor is in power-down mode. the v o lt ag e regula tor must be power e d-up befo re recei v e or t r ansmi t opera t ions can be init iate d. this is handled aut o mat i call y wh en programmi ng th e d e vi ce mod e s v i a th e pwrmode reg i s t er . register vreg cont ains st atu s bi t s t h at can be re ad t o che c k if t h e re gul a t e d volt ag e is abo v e 1. 3 v or 2. 3 v , st i c ky versi o ns of t h e bi t s a r e pro v i d ed tha t c a n b e used t o d e t e c t low power events ( b rown-out d e tect io n). 5. 2 . cryst a l osci llat o r the o n - c hi p cry s t a l osc i lla t o r al low s t h e us e of an i n exp e nsi v e q u ar tz cry s t a l as th e rf g e n e r a ti o n s u b s y s t e m ? s ti m i n g r e f e r e n c e . a l t h ough a wider range of crystal frequencies can be hand l e d by t h e cryst a l oscill at or circu i t , it is re comme nd e d t o u s e 16 mhz as refe re nc e fre q ue ncy si nce this choi ce al l o ws all the t y pi cal srd band rf frequencies t o be g e nera t e d. the osci lla t o r circui t is en abled by pr ogramming th e pwrmode r e g i s t e r . a t p o w e r - u p i t i s n o t ena b l e d . to adjust the circui t?s c h arac terist ic s t o the qu ar t z c r yst a l b e in g u s e d w i t h out us in g addit i on al ex terna l co mpon en ts, both the tran s c ond u c t anc e and th e tu ni ng capaci tanc e of t h e cry s t a l oscilla tor ca n be progra mmed. the t r a n sco n ductance is programmed v i a re gister bi t s xtaloscgm[3: 0] in regist er xta l osc . the i n tegra t ed program m ab le tu ni n g capaci t o r b a n k m a ke s it p o ss ib le t o con n e ct t h e oscilla tor directly t o pins clk16n and clk16p wi t h out the need for external capa ci t o r s . it is programmed using bi t s xtalcap[5: 0] in register xtal cap . to sy nchroni z e the r e c e i v er f r e q u e n c y t o a carr ie r signal , t h e oscill at or f r e q u e ncy cou l d b e tu ned usi n g t h e ca pa ci t o r ban k howe ve r, the r e co mm end e d m e t h od t o i m pl em en t frequency s y nchroniza t i o n is t o mak e us e of t h e high resolut i on rf frequency gener a t i on sub- syst em t o get h e r wi t h t h e aut o m a t i c fre q u e nc y cont ro l, both are described fur t her down. a l terna t i v e l y a si ngle en d e d ref e r e n c e ( t xco, cxo) may be us ed . the cm os le v e l s sho u l d be ap pli e d to clk1 6p vi a an a c co up li ng wi th t h e cry s tal o s ci lla to r en ab led . versi o n 1. 6 datasheet a x 5051
circui t d e scr i pt ion 21 5. 3 . sy sclk output the s y scl k pin o u t p uts the refer e nce cloc k signal di v i ded by a pro g rammable inte ge r. div i sions fro m 1 t o 2048 are possi ble. for di v i d e r ra t i os > 1 the d u t y cy cle i s 50% . bi t s s y sc l k [3 :0 ] i n t h e pincf g 1 regist er set the di v i der rat i o. the sy s c lk o u tput can be disabled. ou tpu tting a frequ e ncy tha t is ide n t i cal t o th e if f r equ e ncy ( d ef au l t 1 m h z) on the s y s c lk pi n i s no t reco m m e n d e d d u r i ng recei v e opera t i o n, since i t r e q u i r es ex tensi v e d e cou p li ng on t h e pcb t o a v oi d i n terf er en ce. 5. 4. power - on-reset ( p or) and re set_n i n put a x 50 51 has an i n tegra t ed pow e r- o n - r es e t bloc k. no ex ter n al por ci r c ui t or si gn al a t th e reset _ n pi n i s req u i r ed , pri o r t o por the res e t _ n pi n i s d i sabl e d . aft e r por t h e ax5 051 c a n b e r e s e t i n tw o w a y s : 1. by spi acc e s s es: t h e bi t r s t i n the pwrmode regi ster is t o ggl ed. 2. v i a t h e res e t_n pi n: a low pu ls e i s appli e d a t t h e res e t_ n pi n. w i t h t h e ri si ng ed ge of reset _ n t h e d e v i c e goes i n t o i t s oper a t i o nal s t a t e . a f ter por or rese t a ll r e gi s t ers are s e t t o th ei r d e f a ul t v a l u es. if the r e set _ n pi n i s no t u s ed i t m u s t b e t i ed t o v d d_ io. 5.5 . rf freq uen c y generati on subsystem the rf f r eq ue ncy gen e ra t i on s u b s y s te m consi s t s of a fu lly inte grated synt he sizer , which mult ipl i es t h e re fe re nce fre q ue ncy from t h e cryst a l oscill at or to get t h e desired rf frequency. the ad vanc ed archi t ec ture of t h e sy n t h e si z e r en abl e s f r eq u e ncy resol u t i o n s of 1 hz, as wel l a s fas t s e ttli n g times of 5 ? 5 0 s de pe nd ing on t h e set t i n gs ( s e e se ct io n 4 . 3 : ac charact e rist ics). f a st set t l in g t i m e s me an fast st art - u p an d fa st rx/tx swi t ching , which e n able s l o w-powe r sys t em d e sign. for rec e i v e opera t i o n the rf f r eq u e ncy i s f e d t o th e mi x e r, f o r t r an s m i t op era t i o n t o th e powe r-amplifie r . the f r e q u e n c y mu s t be programm e d t o t h e d e si red carri er f r eq ue ncy . the rf f r eq u e ncy s h i f t by t h e i f freque ncy that is re qu ire d for rx ope r ation , is aut o mat i call y set whe n the re ce i v e r is ac t i v a ted a n d d o es no t need t o b e programm ed by th e u s er. the d e f a ul t if f r e q u e ncy i s 1 m h z. it ca n be program m ed t o o t h e r v a l u e s . changi ng the if f r equ e n c y and t h us th e cen t r e fre q ue ncy o f t h e digit a l channel filt er can be u s ed t o adapt the bl ocki ng pe rformance of the dev i ce t o spe c ific syst em re qu ireme n ts. th e s y nt he s i ze r l oop b a ndw i dt h can b e p r ogrammed, t h is serves t h r e e purposes: 1 . s t a r t- u p ti m e o p ti m i s a ti o n , s t a r t- u p i s f a s t e r f o r h i g h e r s y n t h e s i z e r lo o p b a n d w i d t h s 2. tx s p ec tr um op t i mi s a t i o n , phase- noi s e a t 3 0 0 kh z t o 1 m h z d i st a n c e f r om th e carri e r impro v es wi th lower synt hesiz e r loop bandwid t hs versi o n 1. 6 datasheet a x 5051
circui t d e scr i pt ion 22 3 . a d a p ta ti o n o f th e b a n d w i d t h to t h e d a ta - r a t e . f o r tr a n s m i s s i o n o f f s k a n d m s k i t i s req u i r ed t h a t th e sy n t h e s i zer band wi d t h m u st be in the ord e r of t h e da t a - r a t e. vc o an on-chip v c o conv e r t s t h e co nt ro l v o lt ag e gene rate d by the charge pu mp and l o op filt e r int o an output freque ncy. this fre q ue ncy is use d for t r ansmi t as well as for recei v e opera t ion. the f r eq u e n c y can be p r ogramm ed i n 1 hz s t ep s i n the freq registers. fo r opera t ion i n t h e 43 3 m h z ba nd, t h e ba n d sel bi t i n th e p lllo op r e gister must be programmed. vc o au t o - r an gi ng the a x 50 51 has an in teg r a t ed a u t o -r anging func t i on, which allo ws t o set the corr ec t v c o range for spe c ific fre q uency ge ne rat i on su bsyst e m set t i n gs aut o mat i call y. t y pical l y i t has t o be e x e c uted afte r powe r-u p . the funct i on is ini t iat e d by set t i n g t h e rng_ start bi t in the pl l r anging regi ster. the bi t i s r e a d abl e and a 0 i n d i ca t e s the end of t h e rangi n g pr ocess. the r n g e rr bi t i n d i ca te s t h e correc t exec u t i o n o f t h e a u t o - r a n gi ng. l o o p fi lt er an d ch ar ge pump the ax5 051 int e rnal l oop fil t e r configu r at ion t o g e the r wi t h t h e charge pu mp cu rrent set s t h e synt he size r l oop band wid t h. the l oop-filt e r has three configu r at i o ns t h at can be programmed v i a t h e register bi t s fl t[ 1: 0] i n regis t er pl ll oop , t h e charg e pump c u rrent ca n be progra mmed usin g regis t er bits pll c p i [ 1 : 0 ] also in regis t er pllloop . s y nt he s i z e r band wi d t hs are t y pi cal l y 50 - 50 0 khz d e pend i n g on the p lll oop sett i n gs , for det a ils see t h e sec t i o n 4. 3: a c charac t e ri s t i c s. reg i s t ers register bits purpose fl t[ 1 : 0 ] sy nthes i z er l o op f i l t er b a n d w i d th, r e co m m e nd ed us ag e i s to i n creas e th e b a nd w i d t h for faste r sett l i ng t i me, band w i dt h incre a se s of factor 2 and 5 are possibl e . p llcp i [2 :0 ] sy nthesizer c h a r ge pump current, r e c o mmend ed us ag e i s to decr eas e th e b a nd w i d t h ( a nd improv e the phas e - nois e) for l o w da ta-rate t r ansmissions. pl ll oop ba n d sel sw i t che s b e tw ee n 868 mh z / 915 mhz and 433 mhz bands freq programmin g o f t h e carri er frequency i ffr eqhi , i ffr e q lo p r ogram m i n g o f th e i f f r eq uen c y pl l r a n gi n g init iate v c o au t o -rang i ng and che c k re sul t s versi o n 1. 6 datasheet a x 5051
circui t d e scr i pt ion 23 5. 6 . rf input and out p ut stage ( antp/ a n tn ) the ax 505 1 u s e s f u ll y diffe re nt ial ant e nna pi ns. rx /tx swi t ching is handle d inte rnal l y , an ex terna l rx/tx swi t ch is not r e quired. lna the ln a ampl ifie s the di ffe re nt ial rf signal from the ant e nna and bu ffers it t o dri v e the i/q m i x e r . a n e x t e r n a l m a t c h i n g n e t w o r k i s u s e d to adapt the antenna impe dance t o the ic i m ped a nc e. a dc f eed t o the r e g u la te d su pp ly v o l t age v r eg mu s t be pro v i d e d at th e ante nna pins. for re commendat ions, see sect ion 7 : appl icat ion i n format io n. i/q mixer t h e r f s i g n a l f r o m t h e l n a i s m i x e d d o w n t o a n i f o f t y p i c a l l y 1 m h z . i - a n d q - i f s i g n a l s a r e bu ffe re d for the anal og if filt e r . pa in tx mod e the pa d r i v es t h e si gna l g e n e ra ted by t h e f r eq u e n c y gen e ra t i on su bsy s te m ou t t o the diffe re nt ial ante nna t e rminal s. the o u t p ut powe r of t h e pa is programme d v i a bi ts txrn g[ 3: 0] in t h e regi s t e r txpwr . ou tput po we r as we ll as harmonic co nte n t will depe nd o n th e ex terna l i m p e d a nc e s e en by th e pa , recomm end a t i ons ar e gi ven i n the s e c t i o n 7: appl icat ion informat ion. 5. 7 . a n alog i f filter the mixe r is fol l o we d by a compl e x band-pass i f filt e r , whi c h su ppresse s t h e down-mixe d image while the wante d signal is ampl ifie d. the ce nt re freque ncy of the fil te r is 1 mhz, wit h a passband widt h of 1 mhz. the rf fre q ue ncy ge ne rat i on su bsys t e m mu st b e p r ogramm e d in suc h a way tha t for all possible mo dula t i o n sch e mes th e i f frequency s p ec trum fits int o the p a s s b a n d of t h e an al og fil t e r . 5. 8 . di gi tal if ch ann e l fi lter an d dem o dulat o r the digit a l if channel filt e r and t h e demodula t o r e x t r act t h e data bit - stre am from t h e incoming i f signal. they mu s t b e pro g ramm ed t o m a t c h t h e m o d u l a t i o n s c h e m e a s w e l l a s the da t a -ra t e. i n accura te programming wi ll lead to lo ss o f s e n s i t i v i t y . the channel filter offers bandwid t hs o f 40 khz up to 600 khz. for detail e d inst ru ct ions how to prog ram t h e digit a l channe l fil t e r and the d e mod u l a t o r see th e a x 50 51 programmi ng manu al , an o v e r v i ew of the registe r s inv o lv e d is gi v e n in t h e f o llowi ng ta bl e. the regi s t er se tu ps ty pi cally m u st be done o n ce a t po wer-up of t h e dev i ce. versi o n 1. 6 datasheet a x 5051
circui t d e scr i pt ion 24 reg i s t ers register remarks ci cdec this re gis t er pr o g rams t h e ban d w i d t h o f th e d i gi ta l c h a n n e l f i l t er . d a ta r a te h i , d a ta r a te l o th es e r e gi s t ers s p eci f y th e r e c e i v er bi t r a te , r e l a ti v e to th e c h a n n e l f i l t er ba n d w i dt h. tm ggai n h i , tm ggai n lo t h e s e reg iste r s spe c ify t h e a g g r e ssi v e ne ss of t h e rece iv e r bit t i ming recov e ry. more agg r e ssi v e sett ing s all o w t h e re ce i v e r t o synchronize w i th shorte r p r eam b l e s , a t the exp e ns e of m o re ti m i n g ji tter and thus a hi gh er b i t err o r ra te at a g i v e n sig nal - t o -noise ra t i o. mod u la t i on this regis t er s e l e ct s the m o dul a tion to be us ed by t h e transmi tter and the re ce i v e r , i.e. w h et he r a s k, psk , f s k , msk or oq psk shoul d be use d . pha s eg a i n, fr eqga i n , f r eqgai n 2, ampl gai n th es e r e gi s t ers con t rol the b a n d w i d th of th e p h as e , f r eq u e nc y of f s et an d amplit ud e t r ac king l oops. rec o mmen d ed sett ing s are prov ide d in t h e prog ramming manual . ag c a t t ac k , ag c d e c ay th es e r e gi s t ers con t rol the a g c ( a u t om a t i c g a i n con t rol ) l o o p sl op es , an d thus th e s p e e d of g a i n adjus t m e n t s . th e f a s t er the b i t-ra te , th e f a s t er th e a g c l o op shoul d be . recomme nded sett ing s are prov ide d in t h e prog ramming ma nu al . txr a te th es e r e gi s t ers con t rol the b i t r a te of th e tra n s m i tter . fsk d e v th es e r e gi s t ers con t rol the f r eq uency d e v i ati o n of the trans m i tter i n fsk m o d e . th e re cei v er does no t exp l i c i t l y ne ed to k n o w the f r eq u e n c y dev i ati o n , onl y th e chann e l fil t er band w i d t h has to be set w i d e enough for t h e c o mpl e t e m o d u l a ti o n to p a s s . 5. 9 . encod e r the encod e r i s loca ted be tw ee n th e fra m i n g u n i t , t h e d e mod u la t o r and t h e m o d u la tor. it c a n o p ti o n a lly tr a n s f o r m t h e b i t- s t r e a m i n th e f o l l o w i n g w a y s : ? i t c a n inv e rt t h e b i t st re am . ? it can pe rform diffe re nt ial e n coding. this me ans t h at a ze ro is t r ansmi tte d as no chang e in the l e v e l , and a one is transmi t t e d as a chang e in the leve l . diffe re nt i a l encod i ng i s us ef u l f o r psk, becau s e ps k t r an smi ssi ons c a n be r e cei v ed ei ther a s t r ans m i tted or i n ver t ed, d u e t o t h e unc e r t ai n t y of the i n i t i a l pha s e . di ff eren t i a l e n coding / de coding remo v e s this unce rtaint y. ? it can p e rf orm manch e s t er enco ding. manches t er enc o ding ensur e s tha t th e m o d u la ti o n h a s n o d c c o n t e n t a n d e n o u g h tr a n s i ti o n s ( c h a n g e s f r o m 0 t o 1 a n d f r o m 1 to 0 ) f o r t h e d e m o d u la to r b i t t i m i n g r e c o v e r y to f u n c ti o n c o r r e c t ly , b u t d o e s s o a t a doubling of the da t a ra te. ? it c a n perfo r m spec t r al shaping. spec tral sha p ing re mo ves d c co n t en t of the bi t s t r e a m , e n s u r e s tr a n s i ti o n s f o r th e d e m o d u l a to r b i t ti m i n g r e c o ve r y , a n d m a k e s s u r e t h a t t h e tr a n s m i t t e d s p e c tr u m d o e s n o t h a ve discrete lin e s even if th e t r an smi t ted dat a is cyclic. i t do e s so without adding a d d i ti o n a l b i t s , i. e . w i th o u t c h a n g i n g th e da t a ra te. s p ectral s h a p ing uses a self synchronizing fe e d back shif t re giste r . the encoder is programmed using the register en cod i n g , det a ils and re comme nd at ions on usag e are gi ve n i n t h e ax 505 1 p r o g r a mm in g ma n u al . versi o n 1. 6 datasheet a x 5051
circui t d e scr i pt ion 25 5. 10. fra m ing a n d fi fo m o s t r a d i o s y s t e m s to d a y g r o u p da ta i n to p a cket s. the framing u n i t is re sponsible for con v er t i ng thes e pa ck e t s i n t o a bi t - s t ream sui t abl e f o r the mo d u la tor, and t o ex t r ac t p a cke t s from t h e cont inu o u s bi t - st ream arri v i ng from t h e demod u la to r. the framing u n i t su pport s fou r diffe re nt mod e s: ? hdlc ? raw ? raw wi t h prea mble ma tch ? 80 2. 15. 4 comp li an t the micro-cont roll e r co mmu n icates with t h e framing u n i t throu g h a 4 lev e l 10 bi t f i fo. the fi fo d e co uples micro-cont roll er t i ming from the radio ( m od ul ator and demod u l a to r) t i ming. the bo tto m 8 bi ts of t h e f i f o con t ai n t r ans m i t or recei v e d a t a . the top 2 bi t are us ed to conv e y meta informat io n in hdlc and 80 2 . 15. 4 mod e s. the y are u n u s e d i n raw a n d raw wi t h pre a mble mat c h mode s. the met a info rma t ion c o nsis t s of p a cket b e gin / end informat ion and t h e re sult of crc che c ks. the ax 505 1 cont ains on e fi f o . i t s dire ct ion is s w it ch ed d e pending on wh ether tr ansmi t or recei v e mo de is selected. the f i fo c a n be oper a t ed i n po ll ed or i n t e rr up t d r i v en mod e s. in po ll ed mod e , t h e mi cro- cont roller must periodically read the fi fo sta t u s r e g i s t e r o r th e f i f o c o u n t r e g i s t e r to d e termi n e w h e t h e r t h e f i fo ne ed s s e r v i c i n g. in i n terr up t mod e em pt y, not em pt y, fu ll , not fu ll and programma bl e le ve l i n te rrup t s ar e pro v i d ed . the a x 50 51 si gnals interr upt s by asser t i n g ( d riv i ng h i gh) it s i r q line. the in ter r up t lin e is l e vel triggered, act i ve high. i n terr u p ts ar e ac know led g ed by remo v i n g th e ca us e f o r t h e int e rr upt , i. e . by emptyi n g o r f i lli ng th e f i fo. basi c f i fo s t a t u s ( e m p ty, fu ll, ov err u n, u n d e rrun, and t h e t o p two bi ts of th e t o p f i fo word ) are also pro v i d ed d u ri n g each sp i acces s on m i so whi l e th e mi cro- con t rol l er s h i f t s ou t th e re giste r addre ss on mosi . se e t h e spi int e rface se ction for de tail s. this fe atu r e significant l y red u c e s th e nu mb er of sp i acc e ss es ne c e ssary during t r ansmi t and rec e i v e. versi o n 1. 6 datasheet a x 5051
circui t d e scr i pt ion 26 hdlc m o de note : hdlc mode foll ows high-lev el dat a link cont rol ( h dlc , i s o 13239) pro t ocol. hdlc mode is the main framing mod e of t h e ax 50 51 . i n t h is mo de , t h e ax5 051 performs a u to m a ti c p a c k e t d e li m i ti n g , a n d o p ti o n a l p a cket correc t ness check by inser t i n g and chec king a cyclic redundancy chec k ( c rc) field. the pa ck e t s t r u c t ur e i s gi ve n i n t h e f o llo wi ng t a b l e. flag address control infor m ation fcs (optional flag) 8 bit 8 bit 8 or 16 bit v a riabl e l e ngth, 0 or mor e bi t s in mul t ipl e s of 8 16 / 32 bit 8 bit hdlc pac k ets are deli mi ted wi t h flag seq u enc e s of con t en t 0x 7e. in ax5 051 t h e m e ani n g of ad d r ess and con t rol i s us er d e f i n ed . the frame ch eck s e q u enc e ( f cs) can b e program m e d t o b e cr c-cc itt, crc-16 or cr c - 32. the r e cei v er chec ks the crc, t h e r e s u l t can be r e t r i e ve d f r om t h e f i fo, t h e cr c i s appe nd ed t o the r e c e i v ed d a t a . for det a ils on impleme n ting a hdlc commu n icat ion see t h e a x 50 51 programming manua l . ra w m o d e in raw mode, t h e a x 505 1 do es no t perform any pack et deli mi t i ng or by te synchro n iza t ion. it simp ly seriali s es trans m i t bytes a n d de-seria lize s the recei v ed bit - stream a n d groups i t int o bytes. this mode is ide a l for impl eme n t i ng legacy prot ocol s in sof t ware . ra w mode w i th pr e a mb le ma tc h raw mode wi t h pr ea mble ma tch is similar t o ra w mode. in this mode, h o wever, t h e recei v er d o es no t r e c e i v e any t hi n g un t i l i t d e tec t s a u s er programma bl e bi t pa tte r n ( c alled t h e prea mb le) i n t h e rec e i v e bi t - s t r e a m . w h en i t d e tec t s t h e pr e a mb le, i t ali g ns t h e d e - se rial izat io n t o i t . the pr ea mb l e can b e b e tw ee n 4 a n d 32 bi ts lon g . versi o n 1. 6 datasheet a x 5051
circui t d e scr i pt ion 27 802 . 1 5 . 4 ( z i g bee) 80 2. 15. 4 us e s bi nary pha s e s h i f t key i n g ( p sk) wi t h 30 0 kbi t /s ( 8 68 m h z ban d ) or 600 kbi t /s ( 915 mhz band) on t h e radio. the usable bit ra te is only a 15 th of t h e radio bit r a t e , however. a spre ading funct i on in t h e t r ansmi t t e r e x pands t h e user bi t ra te by a fact or of 15, t o ma ke the t r a n sm is s i o n m o r e r o bu st . t h e des p rea d e r fu n c t i on o f t h e re ce iv e r u n does t h at . in 8 02. 1 5 . 4 mod e , t h e ax 505 1 framing u n i t pe rf orms t h e spre ading and despr e ading func t i on according to the 8 0 2 . 1 5 . 4 spe c ificat ion. i n re ce i v e mod e , t h e framing u n i t wil l al so au t o ma t i c a l l y searc h f o r th e 8 02. 15. 4 prea mb le, me ani n g t h a t no i n terru p t s wi ll ha ve t o b e ser v i c ed by th e mi cro- c o n t rol l er un t i l a pack e t s t ar t i s d e tec t ed . 5 . 11. rx a g c and rssi a x 50 51 fe atu r es t w o re ce iv e r s i g n a l st r e ng th indica t o rs ( r ssi ): 1 . rssi be fore the digit a l if channel filt er. the gain of the rece i v e r i s adju st e d in orde r t o kee p the analog i f filte r output l e v e l inside t h e working range of t h e adc and demod u la tor. the register agccounter con t ai ns th e curre n t val u e of th e a g c and can be us ed as an rss i . the s t ep si z e of thi s rss i i s 0. 62 5 d b . the val u e can b e u s ed as soon as t h e rf f r equ e ncy g e n e ra t i on sub-sys t em h a s been programmed. 2 . rssi be hind t h e digit a l i f channel filter. the demod u l a tor also prov id e s ampl i t u d e informat ion in t h e trk_ampl itude regist er. by combining bot h the agccounter and the trk_ampl itude regist er s , a high resolut i on ( b etter tha n 0. 1db) rssi va lue c a n b e c o mp u t ed a t th e exp e n s e of a f e w arit hmet ic o p e r at ions on the micro-cont roll er. formulas for t h i s computa t i o n can be fou n d in t h e a x 50 51 programming manua l . versi o n 1. 6 datasheet a x 5051
circui t d e scr i pt ion 28 5 . 12. mod u la t o r d e p e n d i n g o n th e tr a n s m i t t e r s e t t i n g s th e m o d u la t o r genera tes v a riou s inputs for the pa: modulation bit = 0 bit = 1 main lobe ban d width max. bitrate a s k pa off pa on b w = b i t ra t e 600kbit / s f s k / msk ? f=-f deviat io n ? f=+f deviat ion b w = ( 1 + h ) ? bi t r a t e 200kbit / s psk ? =0 0 ? =180 0 b w = b i t ra t e 6 0 0 k b i t / s h = m o d u la t i o n i n d e x . i t i s th e r a ti o o f th e d e vi a t i o n c o m p a r e d to th e b i t- r a t e ; f de v i at i o n = 0. 5 ? h ? bi trate , a x 505 1 can demodulat e signal s wi t h h < 3 2 . ask = am pl i t u d e shift ke ying fsk = fre q ue ncy shift ke ying msk = minimum shift ke ying ; msk is a spe c ial case of fsk, whe r e h = 0 . 5 , and th eref ore f dev i at i o n = 0. 25 ? b i tra t e; the ad v a n t age of m s k o v er fsk i s t h a t i t can b e demod u la te d more robust ly. psk = phas e shif t keying oqpsk = offset qua d ratur e shif t keying. the a x 50 51 s u p p or t s oqps k. however, un less compa t i b i l i t y t o an exi s t i ng sy s t em i s req u i r ed, m s k sho u ld b e pref err e d . a ll mo d u la ti o n sch e m e s are bi nary . 5. 1 3 . a u t o m atic frequency control ( a fc ) the ax 505 1 has a freq uency t r ac king regis t er trkfreq t o synchronize t h e re ce i v e r freque ncy t o a carri er si gnal. for a f c ad jus t me n t , t h e f r eq ue ncy of f s e t ca n be compu t ed wi th t h e fol l o wing formul a: fskmul bitrate trkfreq f = ? . fskmu l is t h e fsk o v e r sampl i ng fact or , it de pe nd s on the fsk bi t rate and dev i at io n u s e d . to dete rmine i t for a spe c ific case , se e the a x 50 51 programmin g manua l . for modu la t i ons o t he r than fs k, fskmu l =1. versi o n 1. 6 datasheet a x 5051
circui t d e scr i pt ion 29 5 . 14. pw rmode r e g i s t er the pwrmode regi s t er c o n t rols, whi c h par t s of th e chi p ar e opera t i n g. pw rm o d e register name description typical idd 0 0 0 0 p o w e rdo w n a l l di gi tal and anal og f u nc ti ons , ex cep t th e re gi s t er f i l e , ar e di s a b l ed. t h e c o re s u p p l y v o l t age i s re duc e d to cons erv e l e ak age pow e r. spi re g iste r s are s t ill acce ssib l e , bu t a t a s l ow e r spee d. 0. 5 a 0 1 0 0 v r ego n a l l di gi tal and anal og f u nc ti ons , ex cep t th e re gi s t er f i l e , ar e disabl e d . t h e core v o l t ag e, how e v e r is a t it s nominal v a l u e fo r ope r a t ion, a nd all sp i re g ist ers are acce ssibl e at the maximu m s p eed . 200 a 0 1 0 1 s t a n d b y t h e crystal osci ll ator is pow e red on; re ce iv e r and transmi t t e r are off. 650 a 1 0 0 0 s y n t h r x th e sy nthesizer i s running o n t h e receiv e frequency . t r a n smitt e r and re ce i v e r are s t ill off. t h is mode is use d t o l e t the synt he siz e r s e tt l e on t h e co r r e ct f r e q u e n c y f o r re ce iv e . 11 m a 1001 fu ll rx synthe size r and re ce i v e r are ru nning. 17 - 20 m a 1 1 0 0 s y n t h t x th e sy nthesizer i s running o n t h e t r ansmi t frequ e ncy . t r a n smitt e r and rece iv e r are st il l off. t h is m o de is use d to let t h e synt he si ze r sett l e on t h e corre ct fre q uency for t r a n smit. 10 m a 1 1 0 1 f u llt x sy nthesizer an d t r a n smitter ar e running. do no t s w i t ch in t o this mode b e fore the synt he siz e r has compl e t e l y s e tt l e d on the t r ansmit frequency ( i n synt h t x m o d e ), other w ise spuri o us spec t r al t r a n smissions w i l l occur. 11 - 40 m a versi o n 1. 6 datasheet a x 5051
circui t d e scr i pt ion 30 a t y pical pw rmode sequence for a t r an sm it se ss ion : step pw rm o d e remarks 1 p o w e rdo w n 2 s t a n dby th e sett l i ng t i m e is domina ted by t h e cry s t a l used , t y pical v a lue 3ms. 3 s y n t h t x t h e synthe size r sett l i ng t i m e is 5 ? 50 s de pe nding on s e tt ing s , se e sect ion a c charac teris t ics 4 f u llt x data t r a n s m i s s i o n 5 s y n t h t x this step must be programmed after fulltx mo de, or th e de vic e will n o t ent e r p o we rd own or s t an d b y mo de . 6 p o w e rdo w n a t y pical pw rmode seq u enc e for a recei v e session : step pw rm o d e[ 3: 0] remarks 1 p o w e rdo w n 2 s t a n dby th e sett l i ng t i m e is domina ted by t h e cry s t a l used , t y pical v a lue 3ms 3 s y n t h r x t h e synthe size r sett l i ng t i m e is 5 ? 50 s de pe nding on s e tt ing s , se e sect ion a c charac teris t ics 4 f u ll r x data re ce p t i o n 5 p o w e rdo w n versi o n 1. 6 datasheet a x 5051
circui t d e scr i pt ion 31 5.1 5 . seri al pe ri ph er al inte r f a c e ( s pi) the ax 505 1 can be programmed v i a a four wir e seri al inter f ace ac cordin g spi u s ing t h e pins clk, mosi , mi so a n d sel. registers for sett ing up t h e ax5 051 ar e program m ed v i a th e seri a l pe riphe r al inte rface in all dev i ce mo de s. w h e n t h e inte rface signal se l is pu lle d l o w, a 1 6 bit configu r at ion dat a st re am is e x pe ct e d on t h e input sig n al pin mosi, which is in terpreted a s d0... d7 , a0... a6 , r_n/ w . da t a read fr om t h e inter f ace appea r s on mi so. figure 3 sho w s a wri t e/r e ad acc e ss t o the inter f a c e . t h e d a t a s t r e a m i s b u i l t o f a n a d d r e s s byte incl u d i n g re ad/wri t e informat i o n and a da ta b y t e . de p e n d i n g o n th e r _ n / w bi t a n d address bi ts a[6.. 0 ], dat a d[7.. 0 ] can be wri t ten v i a mosi or read a t t h e pi n mi s o . r_n/ w = 0 me ans r e ad mode, r_n/ w = 1 mean s wri t e mod e . the r e ad sequence star ts wi th 7 bi ts of st a t us informat ion s[6 ..0 ] f o l l o we d by 8 dat a bi ts. the sta t us bits contain th e fol l o wing informat ion: s6 s5 s4 s3 s2 s1 s0 p ll lo ck fi fo o v er fi fo u n d e r fi fo f u ll fi fo emp t y fi fo st a t ( 1 ) fi fo st a t ( 0 ) spi t i ming ts h r/ w ss sc k mos i mi s o a6 a5 a4 a 3 a2 a1 d7 a 0 d6 d5 d4 d0 d1 d2 d3 d7 d6 d5 d4 d3 d 2 d1 d0 s6 s5 s4 s 3 s2 s1 s0 tssd tc o ts s t ck tch t cl th ts ts sz figure 3 serial p e ripheral interfa ce timing versi o n 1. 6 datasheet a x 5051
register bank descript io n 32 6. regi s te r b a nk d e scrip t io n thi s sec t i o n d e scri b e s t h e bi t s of t h e regi s t er b a nk i n d e t a i l . the regi s t ers are gro u p e d by f u n c ti o n a l b l o c k to f a c i li t a te p r o g r a m m i n g . no ch ecks are mad e wh e t h e r the programm ed combi n a t i o n of bi t s mak e s s e ns e! bi t 0 i s always the l s b. note w h ole registers or register bi t s marked as r e se r v ed sho u ld b e k e p t a t t h ei r d e f a ul t v a l u es. note a ll ad d r ess e s no t d o cum e n t ed her e m u s t n o t be accesse d , ne it he r in re ading nor in writ ing. versi o n 1. 6 datasheet a x 5051
register bank descript io n 33 6. 1 . cont rol regist er map addr name dir reset bit description 7 6 5 4 3 2 1 0 revision & interf ace probing 0 re v i s i o n r 00010100 si l i con r e v ( 7 : 0 ) s i l i c o n re v ision 1 sc r a tc h rw 11000101 s c r a t c h ( 7: 0) s c r a t c h r e g i s t e r operating mod e 2 pw rm o d e rw 0---0000 rs t - - - p w rmod e ( 3 : 0 ) po w e r mo d e crystal oscillator, part 1 3 xt al o s c rw ----0010 - - - - x t a l oscg m ( 3 : 0) gm of cry s t a l oscill at or fifo, part 1 4 fif o ct rl rw ------11 fi fo st a t ( 1 :0 ) fi fo o v er fi fo u n d e r fi fo f u ll fi fo emp t y fi fo cmd ( 1 : 0 ) fi fo control 5 fif o d a t a rw -------- fi fo da t a ( 7 :0 ) f i fo d a t a i n terrupt control 6 ir qm a s k rw --000000 - - i r qm a s k ( 5 : 0 ) i r q m a s k 7 ir qr eq u e s t r -------- - - i r qreq u e s t ( 5 :0 ) i r q request i n terf ace & p i n control 8 ifm o d e rw ----0011 - - - - i f mode ( 3 :0 ) i n t e rfa c e mod e must be set to 00 00 0c pin c fg 1 rw 11111000 reserv ed i r qz reserv ed sysc lk ( 3 : 0 ) pin configura t i o n 1 0d pin c fg 2 rw 00000000 ts t_pi n s i r q e reserv e d reserv e d i r q i reserv e d pin configura t i o n 2 tst_ pi ns( 1 :0) m u s t be s e t to 1 1 versi o n 1. 6 datasheet a x 5051
register bank descript io n 34 0e pin c fg 3 r -------- - - - sysc lkr reserv ed i r qr reserv ed pin configura t i o n 3 0f ir qi n v er s i o n rw --000000 - - i r q i nv ersi on ( 5 :0 ) i r q i n v e r s i o n modulation & fr aming 10 modul a t i o n rw -0000010 - m o d u la t i on ( 6 :0 ) modul a t i o n 11 en codin g rw ----0010 - - - - en c ma nch en c scra m en c di ff en c i n v enco der / d e co der s e tt i n gs 12 fr am ing rw -0000000 fr mr x h s up p cr cmo d e ( 1 : 0 ) fr m m o d e ( 2 : 0 ) fa bo r t fram i n g s e tti n g s 14 crc i nit 3 rw 11111111 crci n i t( 31 : 2 4 ) crc i n it ia l i zat i o n da t a or pre a mbl e 15 crc i nit 2 rw 11111111 crci n i t( 23 : 1 6 ) crc i n it ia l i zat i o n da t a or pre a mbl e 16 crc i nit 1 rw 11111111 crci n i t( 15 : 8 ) crc i n it ia l i zat i o n da t a or pre a mbl e 17 crc i nit 0 rw 11111111 crci n i t( 7 : 0 ) crc i n it ia l i zat i o n da t a or pre a mbl e voltage regula tor 1b vr eg r -------- - - - - ssds ssreg sds sreg vol t a g e r e gul a t o r s t a t us synthesizer 20 fr eq 3 rw 00111001 freq ( 3 1 : 24 ) s y n t h e s i z e r freq uency 21 fr eq 2 rw 00110100 freq ( 2 3 : 16 ) s y n t h e s i z e r freq uency 22 fr eq 1 rw 11001100 freq ( 1 5 : 8 ) s y n t h e s i z e r freq uency 23 fr eq 0 rw 11001101 freq ( 7 : 0 ) s y n t h e s i z e r freq uency 25 fskde v 2 rw 00000010 fsk d e v ( 2 3 : 1 6 ) f s k fr eq u e ncy dev i ati o n 26 fskde v 1 rw 01100110 fsk d e v ( 1 5 : 8 ) f s k fr eq u e ncy dev i ati o n 27 fskde v 0 rw 01100110 fsk d e v ( 7 :0 ) f s k fr eq u e ncy dev i ati o n 28 iff r eq h i rw 00100000 i ffr eq ( 1 5 : 8 ) 2 nd lo / i f freq uency 29 iff r eql o rw 00000000 i ffr eq ( 7 :0 ) 2 nd lo / i f freq uency 2c p lllo o p rw -0011101 - res e rv ed ba ndse l p llcp i ( 2 :0 ) fl t ( 1 : 0 ) sy nthes i z er loo p fi l t er s e tti n gs 2d p l l r an g i ng rw 00001000 s t i c k y lo ck p ll lo ck r n ger r r n g s t a r t vco r ( 3 :0 ) sy nthes i z er vc o a u to-r a n gi n g versi o n 1. 6 datasheet a x 5051
register bank descript io n 35 transmitter 30 txpwr rw ----1000 ? ? ? ? t x r n g ( 3 : 0 ) t r ansmi t po w e r 31 txr a t e hi rw 00001001 txr a te ( 2 3 : 1 6 ) t r a n s m i t t e r bi tra t e 32 txr a t e m i d rw 10011001 txr a te ( 1 5 : 8 ) t r a n s m i t t e r bi tra t e 33 txr a t e lo rw 10011010 txr a te ( 7 :0 ) t r a n s m i t t e r bi tra t e 34 modmisc rw ??????11 ? ? ? ? ? ? re se rv e d p ttclk ga t e misc rf f l ag s fifo, part 2 35 fif o co u n t r -------- - - - - - fi foco u n t( 2 : 0 ) fi f o fill st a t e 36 fi fothr esh rw -----000 - - - - - fi fot h r e sh ( 2 :0 ) fi f o t h r e shol d 37 fif o co nt rol 2 rw 0-----00 clea r - - - - - s t opon err ( 1 : 0 ) a ddit i onal f i f o con t rol recei ver 3a ag c a tt ac k rw 00010110 - - - ag c a t t ac k( 4: 0 ) ag c at t a c k 3b ag c d ec a y rw 0?010011 reserv e d ? reserv e d a g cdeca y ( 4 : 0 ) a g c decay 3c a g cco un t e r r ???????? a g cco u n te r ( 7: 0 ) a g c curren t v a l u e 3d cic s hift r --000100 - - resev e d ci csh i ft( 4 : 0 ) ci c shift fac t or 3f cic d ec rw 00000100 - - ci cdec ( 5 : 0 ) ci c decimat i o n fac t or 40 da tara teh i rw 00011010 d a ta r a te (1 5 : 8 ) d a t a r a t e 41 da tara te lo rw 10101011 d a ta r a te (7 : 0 ) d a t a r a t e 42 tmgg ainh i rw 00000000 t i m i n g g a in ( 1 5: 8) t i m i n g g a i n 43 tmgg ain l o rw 11010101 ti m i n g ga i n ( 7 : 0 ) t i m i n g g a i n 44 p h a s e g ai n rw 00??0011 reserv e d ? ? pha s eg ai n( 3 : 0 ) p h a s e g a i n 45 fr eqg a in rw 00001010 reserv e d f r e q g a i n ( 3 : 0 ) frequ e n c y g a i n 46 fr eqg a in2 rw ????1010 ? ? ? ? f r e q gai n 2 ( 3 : 0 ) f r e q ue ncy gain 2 47 am pl g a i n rw ???00110 ? ? ? re se rv e d a m pl gain( 3 : 0 ) a m p lit ude g a i n 48 tr kam p l h i r ???????? tr k a mp l ( 1 5 :8 ) a m pl i t u d e tra c k i n g 49 tr kam p ll o r ???????? t r k a m p l ( 7: 0) a m p l i t u d e t r a c k i n g 4a trkphas e hi r ???????? ? ? ? ? t r kpha s e ( 1 1 : 8 ) phase t r a c k i n g versi o n 1. 6 datasheet a x 5051
register bank descript io n 36 4b tr k p h a sel o r ???????? t r kpha se( 7 : 0 ) p h a s e t r a c k i n g 4c tr kf r e q h i r ???????? tr k f r e q ( 1 5 :8 ) f r e q u e n c y t r a c k i n g 4d trk f reqlo r ???????? t r k f re q ( 7: 0) f r e q ue nc y t r a c k i n g crystal oscillator, part 2 4f xt al c a p rw --000000 - - xt al c a p( 5: 0) c r y s ta l o s c i l l a t o r tu n i n g capacitanc e misc 72 pl l v c o i rw --000100 - - reserv e d vco_i [ 2: 0 ] sy nthesizer vc o curren t must be set to 00 1 7a locurst rw 00110000 loc u rs t r e s e r v e d lo c u r s t must be set to 1 7c re f rw --100011 - - reserv e d ref_i [ 2: 0 ] refer e nc e adj u st 7d rx mi sc rw --110110 - - reserv e d rx i m i x ( 1 :0 ) misc rf sett ing s rxim ix( 1 : 0 ) mu s t be s e t to 0 1 versi o n 1. 6 datasheet a x 5051
appl icat ion informat ion 37 7. appl ic at i o n i n fo rm at ion 7. 1 . typi cal a p pli c ation diagram nc tst1 tst2 gnd reset_n sysc lk sel nc v d d g n d an t p an t n g n d v d d gnd vreg vdd nc cl k16p cl k16n c l k mi s o mosi ts t3 irq vdd_i o n c a x5051 g n d an t e n n a to/f rom micr o-control l er nc 1 f from powe r su pply vreg g n d figure 4 t y pical application dia g ram it is mandatory t o add 1f ( l ow esr) between v r eg and gnd. de coupl i ng capaci t o rs are no t all drawn. it is re comme n d e d t o add 1 0 0 n f de coupl i ng capaci t o r for every v dd and v dd_i o pin. i n order t o re du ce noise on t h e ant e nna input s i t is recom m e nd ed t o ad d 2 7 pf on th e v d d pi ns close t o th e an t e nn a i n terf ace. versi o n 1. 6 datasheet a x 5051
appl icat ion informat ion 38 7 . 2. a n ten n a i n te r f a c e c i r c u i t r y the a n tp and an tn pins prov ide rf i n put t o t h e ln a when ax 505 1 is in rece i v e mode, and rf out p ut from t h e pa when ax5 051 is in t r ansmi t mode . a sm all an tenn a can be c o nnec t ed w i th a n o p ti o n a l tr a n s l a t i o n n e t w o r k . t h e n e t w o r k m u s t p r o v i d e d c p o w e r to t h e p a a n d ln a. a biasi n g t o v r e g is ne ce ssary. be side biasing and impe dance mat c hing, t h e propos ed networks a l so pro v id e low pa ss fil te ring t o l i mi t spu r iou s e m ission. s i ng le -e nded a n t e nna i n terf ace c1 c3 c6 l4 50 ? si n g l e - ende d equ ipm ent or ante n n a ic an ten na pins vdd vdd l3 l2 l1 c2 l5 c4 c5 l6 ca cb lb figure 5 structure of the ant e nn a interface to 50 ? single-ende d equipment or antenna frequency band l1 =l2 [nh ] c1 [pf] l3 =l4 [nh ] c2 [pf] c3 =c5 [pf] l5 =l6 [nh ] lb [nh ] ca =cb [pf] c4 =c6 [pf] 868 / 915 mhz 18 2. 2 12 2. 2 1. 8 18 6. 2 8. 2 220 4 3 3 mhz 3 3 3 3 3 3 . 3 3. 3 3 9 1 2 1 8 2 2 0 versi o n 1. 6 datasheet a x 5051
appl icat ion informat ion 39 d i pole a n tenna i n terface ic ante nn a pins v dd v dd di pol e ante n na c1 c2 l3 l4 l2 l1 figure 6 structure of the ant e nn a interface to a dipole ant e nn a frequency band l1 =l2 [nh ] c1 [pf] l3 =l4 [nh ] c2 [pf] 868 / 915 mhz 18 3. 9 6. 8 3. 3 433 mhz 33 8 15 6. 8 7. 3. v o ltage r e gula t o r the ax5 051 has an integrated v o ltage regula tor wh ich gene rates a stable suppl y v o lt ag e v r eg f r om the v o l t age appli e d a t v dd_ io. u s e v r eg t o su p p ly al l the v dd supp ly pi ns. versi o n 1. 6 datasheet a x 5051
q f n2 8 pa ck age inf o rma t i o n 40 8. qfn28 package infor m ation 8. 1 . package out l ine q f n28 notes 1. jedec ref mo-220 2. all dimensions are in millimet ers 3. pin 1 is ident if ied by cham f e r on corner of exposed die pad. 4. dat u m c and t he seat in g plane are def ined by t he f l at surf ace o f t he met a llised t e rminal 5. dimension ?e? represent t he t e rminal pit c h 6. dimension b appli e s t o met a llised t e rminal and is measured 0. 25 t o 0. 30mm f r om t e rminal t i p. 7. dimension l1 represent s t e rminal pull back f r o m package edge. t here t e rminal pull back esist s , only upper half of lead is visible on package edge du t o half et ching of leadf rame. 8. package surf ace shall be mat t e f i nish, ra 1. 6-2.2 9. package warp shall be 0. 050 maximum 10. leadf rame mat e rial is c opper a194 11. coplanarit y appl ies t o the exposed pad as well as t he t e rminal 12. yyww x x is t he packa ging lot code axsem ax5051-1 yywwxx versi o n 1. 6 datasheet a x 5051
q f n2 8 pa ck age inf o rma t i o n 41 8. 2. qfn28 so lder in g pr of ile profile feature pb-free proc ess av e r ag e ramp -u p ra t e 3 c/se c max . p r eh ea t p r e h ea t t e m p e r at ur e m i n t sm i n 1 5 0 c t e m p e r at ur e ma x t sm a x 2 0 0 c ti m e (t sm i n to t sm a x ) t s 60 ? 180 se c t i me 25c t o peak t e mp e r a t u r e t 25 t o peak 8 min max. re fl ow phas e liquidus t e mperat u r e t l 2 1 7 c t i m e ov er li q u i d us t e m p era t ur e t l 60 ? 150 se c peak t e mp era t ure t p 2 6 0 c t i me w i t h in 5c of ac t ual peak t e m p e r at ur e t p 20 ? 40 se c cool ing phase ramp-do w n ra te 6c/sec max. not e s : a l l t e m p era t ures refe r t o t he t o p side of t h e pa ckage, m e asured on t he pack age b o dy surface. time p r e h e a t r e f l o w c o o l i n g t p t l t sma x t sm i n t p 25 c t s t l t 25 t o peak temperature versi o n 1. 6 datasheet a x 5051
q f n2 8 pa ck age inf o rma t i o n 42 8. 3 . qfn28 recommended pad layout 1. pcb land an d solder mas k ing recomm enda t i ons are sho w n in figure 7. a = c l e a r a nc e f r o m pc b t h er m a l pad t o s o ld er m a s k o p e n i n g , 0. 0635 mm m i n i m u m b = cl ea r a n c e f r om ed g e o f p c b th e r m a l pa d to p c b l a n d , 0 . 2 m m mi ni m u m c = cl ea ra n c e f r o m p c b l a n d e d g e t o s o ld er m a s k o p e n in g to be as t i g h t a s p o s s ib le t o en s u r e t h at s o m e s o ld er m a s k r e m a in s bet w e e n pc b pads d = pc b lan d le n g t h = q f n s o ld er p a d le n g t h + 0 . 1 m m e = pc b l a nd w i dt h = q f n so l d e r p a d wi dt h + 0. 1 mm figure 7 : p c b la nd and so lder mask reco mme ndations 2. ther mal vi as shou ld b e us ed on the pcb th erm a l pad ( m i d d l e grou nd pad ) t o i m p r ove th erma l con d uc t i v i t y f r om t h e d e v i c e t o a copp er ground pl ane are a on t h e re ver s e si d e of t h e pri n t e d ci rcui t b o ard . the num b er of v i as d e p e nd s on t h e pa ckage th er mal req u i r em en t s , as d e ter m i n ed by t h er mal si m u la ti on or ac t u a l tes t i n g. 3. incre a si ng the n u mb er of v i as thro u g h t h e pri n ted ci rcui t b o ard wi ll i m pro v e th e th erma l c o n d u c ti v i ty to th e r e v e r s e s i d e g r o u n d p l a n e a n d e x t e r n a l h e a t s i n k . i n g e n e r a l, a d d i n g more m e t a l t h roug h th e p c board und e r the i c wi l l i m prove o p era t i o nal hea t t r a n sf er, but will requ i r e care f u l attent ion t o unifo rm hea t i n g of t h e bo ard during assembly. 8. 4. a ssembly proces s st en ci l desi gn & solder paste appli c ation 1. s t ai nl es s s t e e l s t e n ci ls ar e reco m m e n d e d f o r sol d er pas t e a ppli c a t i o n. 2. a sten ci l thi c kne ss of 0. 12 5 ? 0. 150 m m ( 5 ? 6 mi ls) i s recom m e n d e d f o r scree n i n g. 3. for t h e pc b t h erma l pa d, sold er pas t e sho u ld be pri n ted on t h e p c b by d e si gni n g a s t enci l wi t h an array of smal l e r ope n i n gs t h a t s u m t o 50% of th e q f n ex posed pad area. solder paste should be a ppli e d through an arra y of squar e s ( o r circles) a s show n in fig u re 8. 4. the a p er tur e op eni n g f o r th e si gna l pad s sho u l d be be tw e e n 5 0 - 80% of the q f n p a d area as sho w n in figur e 9. 5. op t i ona lly , for be tter sol d er pas t e r e lea s e, t h e a p er tur e wa l l s sho u ld b e t r ap ezoi d a l and the corner s rounded. versi o n 1. 6 datasheet a x 5051
q f n2 8 pa ck age inf o rma t i o n 43 6. the f i n e pi t c h of the ic l e ad s re qui r e s accura te ali g nm en t o f the s t e n ci l and t h e pri n ted circu i t board. the stencil and printed circu i t as se mbl y sho u ld be al igned t o wi t h in + 1 mi l pri o r t o app l i c a t i o n of t h e sold er pas t e. 7 . n o -cle an flu x is re co mmende d since flu x f r o m u n d e rn e a th the th e r mal p a d w i ll b e diff icu l t to cle a n if wate r-sol u ble flu x is u s e d . figure 8 : sold er paste applicati o n on ex p o sed pad minimum 50% coverage 62% coverage maximum 80% coverage figure 9 : sold er paste applicati o n on pins versi o n 1. 6 datasheet a x 5051
life su pport appl icat ions 44 9. l i fe su pport app l i c a t i o ns t h is p r o d u c t is n o t d e s i g n e d f o r u s e in l i f e s u pport appl i a nces, devi ces, or i n systems where m a l f un c t io n o f t h is p r o d u c t c a n r e as o n a b l y b e expected to res u l t i n pe rs o n al i n jury . axse m c u s t o m e r s us i n g o r s e l l in g t h is p r o d u c t f o r u s e in s u ch a p p l ic a t io n s do so a t t h e i r o w n r i s k a n d ag r e e t o f u l l y in d e m n if y a x s e m f o r a n y d a ma g e s r e s u l t in g f r o m s u c h im p r o p e r u s e o r s a l e . versi o n 1. 6 datasheet a x 5051
c o nt act i n for m at ion 45 10. c o nt a c t in for m at ion ax sem ag oskar-bider-s t rasse 1 ch- 8 60 0 d bend orf sw it z e r l a n d phon e +41 44 8 82 1 7 0 7 fax +41 44 8 82 1 7 0 9 e m ai l sale s@axsem.com www. axs e m . com for fu rt he r produ c t re lat e d or sal e s i n format ion ple a se v i si t ou r we bsi t e or cont act y o u r l o cal re present a t i v e . t h e s p ecif icat io ns in t his do cu m e nt are s u bject t o change a t a x s e m' s dis c r e t i o n . a x s e m as s u me s no res p o n s ibilit y f o r any claim s or d a m a g e s a r i s i n g out of t h e use of t h i s d o c u m e n t , or fr om t h e u s e o f pro d u c t s bas e d o n t his d o cu m e nt , inclu ding bu t no t limit ed t o c l aims o r da mages bas e d o n inf ringement o f pat e nt s , c o py right s o r o t her int ellect u a l pro p ert y right s . a x s e m make s no w a rran t ies , eit h er exp r es s e d o r implied w i t h res p ect t o t h e inf o r mat i o n and s p ecif ica t io ns co nt a ined in t his do cu ment . a x s e m do es no t s u ppo rt a n y applica t io ns i n co nne ct io n w i t h lif e s u ppo rt and co mmercia l aircraf t . p e rf o r mance c h aract eris t i cs lis t e d in t h i s do c u ment are es t i mat e s o nly and d o no t co n s t i t u t e a w a rra nt y or g u a r a n t ee of p r od uc t p e rf orm a n c e . th e co py ing , dis t ribu t i o n and u t iliz at io n o f t his do c u m e nt as w e ll as t h e co mmu nicat io n o f it s co nt ent s t o o t hers w i t h o u t expres s e d au t h o r iz at io n is pro hibit ed. o f f e nders w ill be held liable f o r t h e pay m ent of damages . all righ t s reserved . c o p y rig h t ? 2007 a x se m a g versi o n 1. 6 datasheet a x 5051

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