icl7106 / icl7107 1 icl7106 / icl7107 3 ? digit lcd/led display a/d converter product description the icl7106 and icl7107 are high performance, low power, 3 ? digit a/d converters. included are seven segment decoders, display drivers, a re ference, and a clock. the icl7106 is designed to interface with a liquid crystal display (lcd) and includes a multiplexed backplane drive; the icl7107 will directly drive an instrument size light emitting diode (led) display. the icl7106 and icl7107 bring together a combination of high accuracy, versatility, and true economy. true differential inputs and reference are useful in all syst ems, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge type trans ducers. finally, the true economy of single power supply operation (icl7106), enables a high performance panel mete r to be built with the addition of only 10 passive components and a display. display-hold, low-battery flag, integratio n and de-integration status flags are four additional f eatures which are available in the 44-pin package. ordering information part no. temp. range (c) package icl7106cpl 0 ? 70 c 40 ld. pdip icl7106cm44 0 ? 70 c 44 ld. pqfp icl7106cx 0 ? 70 c dice icl7107cpl 0 ? 70 c 40 ld. pdip icl7107cm44 0 ? 70 c 44 ld. pqfp icl7107cx 0 ? 70 c dice applications these devices can be used in a wide range of digital panel meter applications. most applications, however, involve the measurement and display of analog data: ? pressure ? conductance ? voltage ? current ? resistance ? speed ? temperature ? material thickness features ? guaranteed zero reading for 0v input on all scales ? true polarity at zero for precise null detection ? true differential input and reference, direct display drive -lcd icl7106 -led lcl7107 ? low noise - less than 15 v p-p ? on chip clock and reference ? low power dissipation - typically less than 10mw ? no additional active circuits required ? new small outline surface mount package available ? four additional features are available for 44 pin pqfp package: ? display ? hold ? low - battery indication ? integration status indication ? de-integration status indication
icl7106 / icl7107 2 electrical specifications (note 3) parameters test conditions min typ max unit system performance zero input reading v in = 0.0v, full scale = 200mv -000.0 r 000.0 +000.0 digital reading ratiometric reading v ln = v ref , v ref = 100mv 999 999/1000 1000 digital reading rollover error -v in = +v ln 200mv difference in reading for equal positive and negative inputs near full scale -1 - +1 counts linearity full scale = 200mv or full scale = 2v maximum deviation from best straight line fit (note 5) -1 - +1 counts common mode rejection ratio v cm = 1v, v in = 0v, full scale = 200mv (note 5) - 50 - v/v end power supply character v+ supply current v in = 0 (does not include led current for icl7107) - - 1.8 ma end power supply character v- supply current icl7107 only - - 1.8 ma common pin analog common voltage 25 k
between common and positive supply (with respect to + supply) 2.4 - 3.2 v display driver icl7106 only pk-pk segment drive voltage pk-pk backplane drive voltage v+ = to v- = 9v (note 4) 4 5 6 v display driver icl7107 only segment sinking current except pins 19 and 20 5 8 - ma pin 19 only 10 16 - ma pin 20 only v+ = 5v, segment voltage = 3v 4 7 - ma notes: 1. input voltages may exceed the supply voltages provided the input current is limited to r 100a. 2. ja is measured with the component mounted on a low effective thermal conductivity test board in free air. 3. unless otherwise noted, specifications apply to both the icl7106 and icl7107 at t a = 25c, f clock = 48khz. icl7106 is tested in the circuit of figure 1. icl7107 is tested in the circuit of figure 2. 4. back plane drive is in phase with segment drive for ?off ? segment, 180 degrees out of phase for ?on ? segment. frequency is 20 times conversion rate. average dc component is less than 50mv. 5. not tested, guaranteed by design. thermal information thermal resistance (typical, note 2) ja (c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . .50 mqfp package . . . . . . . . . . . . . . . . . . . . . . . . .75 maximum junction temperature . . . . . . . . . . . .150c maximum storage temperature range . . .-65c to 150c maximum lead temperature (soldering 10s) . . . .300c (mqfp - lead tips only) absolute maximum ratings supply voltage icl7106, v+ to v- . . . . . . . . . . . . . . . . . . . . . . . . . 15v icl7107, v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . 6v icl7107, v- to gnd . . . . . . . . . . . . . . . . . . . . . . . .-9v analog input voltage (either input) (note 1) . . . . . v+ to v- reference input voltage (either input). . . . . . . . . . v+ to v- clock input icl7106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .test to v+ icl7107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .gnd to v+
icl7106 / icl7107 3 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 (1000) ab4 pol 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 osc 1 osc 2 osc 3 test ref hi ref lo c ref + c ref - common in hi in lo a-z buff int v- g2 (10 s) c3 a3 g3 bp/gnd (1 s) (10 s) (100 s) (minus) (100 s) icl7106,icl7107 (pdip) top view osc 2 hold* osc 3 test inten* deen* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 osc 1 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 28 27 26 25 24 23 22 21 20 19 18 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol bp/gnd 39 38 37 36 35 34 33 32 31 30 29 44 43 42 41 40 in hi in lo a-z buff int v- lb* g2 c3 a3 g3 ref hi ref lo c ref + c ref - common icl7106, icl7107 (pqfp) top view pinouts
icl7106 / icl7107 4 typical applications and test circuits figure 1. icl7106 test circuit and typical application with lcd display components selected for 200mv full scale figure 2. icl7107 test circuit and typical application with led display components selected for 200mv full scale 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 v+ d1 c1 b1 a1 f1 g1 e1 d2 c2 b2 a2 f2 e2 d3 b3 f3 e3 ab4 pol osc 1 osc 2 osc 3 test ref hi ref lo c ref + c ref - com in hi in lo a-z buff int v- g2 c3 a3 g3 bp display display c 1 c 2 c 3 c 4 r 3 r 1 r 4 c 5 + - in r 5 r 2 9v icl7106 c 1 = 0.1 ? ? ? ? ? ? ? ? ? ?
icl7106 / icl7107 5 typical integrator ampli?r output waveform (int pin) design information summary sheet oscillator frequency f osc = 0.45/rc c osc > 50pf; r osc > 50k ? f osc (typ) = 48khz oscillator period t osc = rc/0.45 integration clock frequency f clock = f osc /4 integration period t int = 1000 x (4/f osc ) 60/50hz rejection criterion t int /t 60hz or t lnt /t 60hz = integer optimum integration current i int = 4 a full scale analog input voltage v lnfs (typ) = 200mv or 2v integrate resistor integrate capacitor integrator output voltage swing ? int maximum swing: (v- + 0.5v) < v int < (v+ - 0.5v), v int (typ) = 2v display count conversion cycle t cyc = t cl0ck x 4000 t cyc = t osc x 16,000 when f osc = 48khz; t cyc = 333ms common mode input voltage (v- + 1v) < v ln < (v+ - 0.5v) auto-zero capacitor 0.01 f < c az < 1 f reference capacitor 0.1 f < c ref < 1 f ? com biased between vi and v-. ? com ? regulation lost when v+ to v- < ? 6.8v if v com is externally pulled down to (v+ to v-)/2, the v com circuit will turn off. icl7106 power supply: single 9v v+ - v- = 9v digital supply is generated internally v gnd ? v+ - 4.5v icl7106 display: lcd type: direct drive with digital logic supply amplitude. icl7107 power supply: dual v+ = +5v to gnd v- = -5v to gnd digital logic and led driver supply v+ to gnd icl7107 display: led type: non-multiplexed common anode r int v infs i int ---------------- - = c int t int () i int () v int -------------------------------- = v int t int () i int () c int -------------------------------- = count 1000 v in v ref --------------- = auto zero phase (counts) 2999 - 1000 signal integrate phase fixed 1000 counts de-integrate phase 0 - 1999 counts total conversion time = 4000 x t clock = 16,000 x t osc
icl7106 / icl7107 6 detailed description analog section figure 3 shows the analog section for the icl7106 and icl7107. each measurement cycle is divided into three phases. they are (1) auto-zero (a-z), (2) signal integrate (int) and (3) de-integrate (de). auto-zero phase during auto-zero three things happen. first, input high and low are disconnected from the pins and internally shorted to analog common. second, the reference capacitor is charged to the reference voltage. third, a feedback loop is closed around the system to charge the auto-zero capacitor c az to compensate for offset voltages in the buffer amplifier, integrator, and comparator. since the comparator is included in the loop, the a- z accuracy is limited only by the noise of the system. in any case, the offset referred to the input is less than 10 v. signal integrate phase during signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. the converter then integrates the differential voltage between in hi and in lo for a fixed time. this differential voltage can be within a wide common mode range: up to 1v from either supply. if, on the other hand, the input signal has no return with respect to the converter power supply, in lo can be tied to analog common to establish the correct common mode voltage. at the end of this phase, the polarity of the integrated signal is determined. de-integrate phase the ?al phase is de-integrate, or reference integrate. input low is internally connected to analog common and input high is connected across the previously charged reference capacitor. circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. the time required for the output to return to zero is proportional to the input signal. speci?ally the digital reading displayed is: . differential input the input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5v below the positive supply to 1v above the negative supply. in this range, the system has a cmrr of 86db typical. however, care must be exercised to assure the integrator output does not saturate. a worst case condition would be a large positive common mode voltage with a near full scale negative differential input voltage. the negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. for these critical applications the integrator output swing can be reduced to less than the recommended 2v full scale swing with little loss of accuracy. the integrator output can swing to within 0.3v of either supply without loss of linearity. differential reference the reference voltage can be generated anywhere within the power supply voltage of the converter. the main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. if there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. this difference in reference for positive or negative input voltage will give a roll-over error. however, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (see component value selection.) display count = 1000 v in v ref --------------- ?? ?? ?? ()
icl7106 / icl7107 7 analog common this pin is included primarily to set the common mode voltage for battery operation (icl7106) or for any system where the input signals are ?ating with respect to the power supply. the common pin sets a voltage that is approximately 2.8v more negative than the positive supply. this is selected to give a minimum end-of-life battery voltage of about 6v. however, analog common has some of the attributes of a reference voltage. when the total supply voltage is large enough to cause the zener to regulate (>7v), the common voltage will have a low voltage coef?ient (0.001%/v), low output impedance ( ? 15 ? ), and a temperature coef?ient typically less than 80ppm/ o c. the limitations of the on chip reference should also be recognized, however. with the icl7107, the internal heating which results from the led drivers can cause some degradation in performance. due to their higher thermal resistance, plastic parts are poorer in this respect than ceramic. the combination of reference temperature coefficient (tc), internal chip dissipation, and package thermal resistance can increase noise near full scale from 25 v to 80 v p-p . also the linearity in going from a high dissipation count such as 1000 (20 segments on) to a low dissipation count such as 1111(8 segments on) can suffer by a count or more. devices with a positive tc reference may require several counts to pull out of an over-range condition. this is because over-range is a low dissipation mode, with the three least significant digits blanked. similarly, units with a negative tc may cycle between over-range and a non-over- range count as the die alternately heats and cools. all these problems are of course eliminated if an external reference is used. the icl7106, with its negligible dissipation, suffers from none of these problems. in either case, an external reference can easily be added, as shown in figure 4. analog common is also used as the input low return during auto-zero and de-integrate. if in lo is different from analog common, a common mode voltage exists in the system and is taken care of by the excellent cmrr of the converter. however, in some applications in lo will be set at a ?ed known voltage (power supply common for instance). in this application, analog common should be tied to the same point, thus removing the common mode voltage from the converter. the same holds true for the reference voltage. if reference can be conveniently tied to analog common, it should be since this removes the common mode voltage from the reference system. within the lc, analog common is tied to an n-channel fet that can sink approximately 30ma of current to hold the voltage 2.8v below the positive supply (when a load is trying to pull the common line positive). however, there is only 10 a of source current, so common may easily be tied to a more negative voltage thus overriding the internal reference. test the test pin serves two functions. on the icl7106 it is coupled to the internally generated digital supply through a 500 ? resistor. thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the lcd display. figures 5 and 6 show such an application. no more than a 1ma load should be applied. the second function is a ?amp test? when test is pulled high (to v+) all segments will be turned on and the display should read ?888? the test pin will sink about 15ma under these conditions. caution: in the lamp test mode, the segments have a constant dc voltage (no square-wave). this may burn the lcd display if main- tained for extended periods. figure 4a. figure 4b. figure 4. using an external reference icl7106 v ref lo icl7107 ref hi v+ v- 6.8v zener i z icl7106 v ref hi ref lo common v+ icl8069 1.2v reference 6.8k ? ? ?
icl7106 / icl7107 8 digital section figures 7 and 8 show the digital section for the icl7106 and icl7107, respectively. in the icl7106, an internal digital ground is generated from a 6v zener diode and a large p-channel source follower. this supply is made stiff to absorb the relative large capacitive currents when the back plane (bp) voltage is switched. the bp frequency is the clock frequency divided by 800. for three readings/sec., this is a 60hz square wave with a nominal amplitude of 5v. the segments are driven at the same frequency and amplitude and are in phase with bp when off, but out of phase when on. in all cases negligible dc voltage exists across the segments. figure 8 is the digital section of the icl7107. it is identical to the icl7106 except that the regulated supply and back plane drive have been eliminated and the segment drive has been increased from 2ma to 8ma, typical for instrument size common anode led displays. since the 1000 output (pin 19) must sink current from two led segments, it has twice the drive capability or 16ma. in both devices, the polarity indication is ?n?for negative analog inputs. if in lo and in hi are reversed, this indication can be reversed also, if desired. icl7106 v+ bp test decimal point select cd4030 gnd v+ to lcd decimal points figure 6. exclusive ?r?gate for decimal point drive 7 segment decode segment output 0.5ma 2ma internal digital ground typical segment output v+ lcd phase driver latch 7 segment decode ? ? ? three inverters one inverter shown for clarity figure 7. icl7106 digital section
icl7106 / icl7107 9 system timing figure 9 shows the clocking arrangement used in the icl7106 and icl7107. two basic clocking arrangements can be used: 1. figure 9a. an external oscillator connected to pin 40. 2. figure 9b. an r-c oscillator using all three pins. the oscillator frequency is divided by four before it clocks the decade counters. it is then further divided to form the three convert-cycle phases. these are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and auto-zero (1000 to 3000 counts). for signals less than full scale, auto-zero gets the unused portion of reference de-integrate. this makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. for three readings/second, an oscillator frequency of 48khz would be used. to achieve maximum rejection of 60hz pickup, the signal integrate cycle should be a multiple of 60hz. oscillator frequencies of 240khz, 120khz, 80khz, 60khz, 48khz, 40khz, 33 1 / 3 khz, etc. should be selected. for 50hz rejection, oscillator frequencies of 200khz, 100khz, 66 2 / 3 khz, 50khz, 40khz, etc. would be suitable. note that 40khz (2.5 readings/second) will reject both 50hz and 60hz (also 400hz and 440hz). 7 segment decode to segment 0.5ma 8ma digital ground typical segment output v+ latch 7 segment decode logic control 7 segment decode 1000 s 100 s 10 s 1 s to switch drivers from comparator output digital ground ? ? ? three inverters one inverter shown for clarity figure 8. icl7107 digital section clock internal to part 40 39 38 gnd icl7107
icl7106 / icl7107 10 component value selection integrating resistor both the buffer ampli?r and the integrator have a class a output stage with 100 a of quiescent current. they can supply 4 a of drive current with negligible nonlinearity. the integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the pc board. for 2v full scale, 470k ? is near optimum and similarly a 47k ? for a 200mv scale. integrating capacitor the integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing (approximately. 0.3v from either supply). in the icl7106 or the icl7107, when the analog common is used as a reference, a nominal +2v full- scale integrator swing is ?e. for the icl7107 with +5v supplies and analog common tied to supply ground, a 3.5v to +4v swing is nominal. for three readings/second (48khz clock) nominal values for c lnt are 0.22 f and 0.10 f, respectively. of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. an additional requirement of the integrating capacitor is that it must have a low dielectric absorption to prevent roll-over errors. while other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. auto-zero capacitor the size of the auto-zero capacitor has some in?ence on the noise of the system. for 200mv full scale where noise is very important, a 0.47 f capacitor is recommended. on the 2v scale, a 0.047 f capacitor increases the speed of recovery from overload and is adequate for noise on this scale. reference capacitor a 0.1 f capacitor gives good results in most applications. however, where a large common mode voltage exists (i.e., the ref lo pin is not at analog common) and a 200mv scale is used, a larger value is required to prevent roll-over error. generally 1 f will hold the roll-over error to 0.5 count in this instance. oscillator components for all ranges of frequency a 100k ? resistor is recommended and the capacitor is selected from the equation: reference voltage the analog input required to generate full scale output (2000 counts) is: v ln = 2v ref . thus, for the 200mv and 2v scale, v ref should equal 100mv and 1v, respectively. however, in many applications where the a/d is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. for instance, in a weighing system, the designer might like to have a full scale reading when the voltage from the transducer is 0.662v. instead of dividing the input down to 200mv, the designer should use the input voltage directly and select v ref = 0.341v. suitable values for integrating resistor and capacitor would be 120k ? and 0.22 f. this makes the system slightly quieter and also avoids a divider network on the input. the icl7107 with 5v supplies can accept input signals up to 4v. another advantage of this system occurs when a digital reading of zero is desired for v in 0. temperature and weighing systems with a variable fare are examples. this offset reading can be conveniently generated by connecting the voltage transducer between in hi and common and the variable (or ?ed) offset voltage between common and in lo. icl7107 power supplies the icl7107 is designed to work from 5v supplies. however, if a negative supply is not available, it can be generated from the clock output with 2 diodes, 2 capacitors, and an inexpensive lc. figure 10 shows this application. see icl7660 data sheet for an alternative. in fact, in selected applications no negative supply is required. the conditions to use a single +5v supply are: 1. the input signal can be referenced to the center of the common mode range of the converter. 2. the signal is less than 1.5v. 3. an external reference is used. f 0.45 rc ----------- for 48khz clock (3 readings/sec), = c 100pf. = icl7107 v+ osc 1 v- osc 2 osc 3 gnd v+ v- = 3.3v 0.047
|
