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nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 1 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. nt56v6610c0t (8mx8) nt56v6620c0t (4mx16) 64mb synchronous dram data sheet
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 2 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. revision log rev date version content of modification sep / 1999 1.0 1 st revision june / 2000 1.1 added speed grade ? 75b (pc133@cl3 & pc100@cl2) to following items as : 1. product family 2. dc currents 3. ac timing parameters
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 3 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. contents revision log ................................ ................................ ................................ ................................ ................................ 02 table of contents ................................ ................................ ................................ ................................ ......................... 03 description ................................ ................................ ................................ ................................ ................................ ... 05 features ................................ ................................ ................................ ................................ ................................ ........ 06 product family ................................ ................................ ................................ ................................ ............................ 07 pin assignment ................................ ................................ ................................ ................................ ............................ 07 pin description ................................ ................................ ................................ ................................ ............................. 08 functional block diagram ................................ ................................ ................................ ................................ ........... 09 ordering information ................................ ................................ ................................ ................................ ................... 10 dc characteristics ................................ ................................ ................................ ................................ ....................... 11 absolute maximum ratings ................................ ................................ ................................ ................................ ....... 11 recommended dc operating conditions ................................ ................................ ................................ ..................... 11 capacitance ................................ ................................ ................................ ................................ .......................... 11 dc electrical characteristics ................................ ................................ ................................ ................................ ..... 11 dc output load circuit ................................ ................................ ................................ ................................ ............ 12 oper ating, standby, and refresh currents ................................ ................................ ................................ ................... 13 ac characteristics ................................ ................................ ................................ ................................ ....................... 14 ac output load circuits ................................ ................................ ................................ ................................ ........... 14 ac timing parameters ................................ ................................ ................................ ................................ ................. 15 clock and clock enable parameters ................................ ................................ ................................ ............................ 15 common parameters ................................ ................................ ................................ ................................ ............... 15 mode register set cycle ................................ ................................ ................................ ................................ .......... 15 read cycle ................................ ................................ ................................ ................................ ........................... 16 refresh cycle ................................ ................................ ................................ ................................ ........................ 16 write cycle ................................ ................................ ................................ ................................ ........................... 16 clock frequency and latency ................................ ................................ ................................ ................................ .... 16 command truth table ................................ ................................ ................................ ................................ ................. 18 device operations ................................ ................................ ................................ ................................ ................. 24 power on and initialization ................................ ................................ ................................ ................................ ........ 24 programming the mode register ................................ ................................ ................................ ................................ 24 mode register definition ................................ ................................ ................................ ................................ .......... 24 burst mode operation ................................ ................................ ................................ ................................ .............. 25 burst length and sequence ................................ ................................ ................................ ................................ ...... 25 bank activate com mand ................................ ................................ ................................ ................................ .......... 26 bank select ................................ ................................ ................................ ................................ ........................... 26 read and write access modes ................................ ................................ ................................ ................................ .. 27 burst read command ................................ ................................ ................................ ................................ ............. 28 read interrupted by a read ................................ ................................ ................................ ................................ ....... 29 read interrupted by a write ................................ ................................ ................................ ................................ ...... 30 burst write command ................................ ................................ ................................ ................................ ............. 30 write interrupted by a write ................................ ................................ ................................ ................................ ...... 31 write interrupted by a read ................................ ................................ ................................ ................................ ...... 31 burst stop comm and ................................ ................................ ................................ ................................ .............. 32 auto - precharge operation ................................ ................................ ................................ ................................ ........ 33 precharge command ................................ ................................ ................................ ................................ ............... 37 bank selection for precharge by address bits ................................ ................................ ................................ ............... 37 precharge termination ................................ ................................ ................................ ................................ ............. 39 automatic refresh command ................................ ................................ ................................ ................................ .... 40 self refresh command ................................ ................................ ................................ ................................ ............ 40 power down mode ................................ ................................ ................................ ................................ .................. 41 data mask ................................ ................................ ................................ ................................ ............................ 41
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 4 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. no operation command ................................ ................................ ................................ ................................ ........... 41 deselect command ................................ ................................ ................................ ................................ ................. 41 clock suspend mode ................................ ................................ ................................ ................................ ............... 42 timing diagrams ................................ ................................ ................................ ................................ ......................... 43 ac parameters for write timing ................................ ................................ ................................ ................................ 43 ac parameters for read timing (3/3/3) ................................ ................................ ................................ ....................... 44 ac parameters for read timing (2/2/2) ................................ ................................ ................................ ....................... 45 ac parameters for read timing (3/2/2) ................................ ................................ ................................ ....................... 46 ac parameters for read timing (3/3/3) ................................ ................................ ................................ ....................... 47 mode register set ................................ ................................ ................................ ................................ .................. 48 power on sequence and auto refresh (cbr) ................................ ................................ ................................ ............... 49 clock suspension, dqm during burst read ................................ ................................ ................................ .................. 50 clock suspension, dqm during burst write ................................ ................................ ................................ ................. 51 power down mode and clock suspend ................................ ................................ ................................ ........................ 52 auto refresh (cbr) ................................ ................................ ................................ ................................ ................ 54 self refres h (entry and exit) ................................ ................................ ................................ ................................ ..... 54 random row read (interleaving banks) with precharge ................................ ................................ ................................ .. 55 random row read (interleaving banks) with auto precharge ................................ ................................ ........................... 56 random row write (interleaving banks) with auto precharge ................................ ................................ ........................... 57 random row write (interleaving banks) with prechar ge ................................ ................................ ................................ .. 58 read - write cycle ................................ ................................ ................................ ................................ ................... 59 interleaved column read cycle ................................ ................................ ................................ ................................ .. 60 auto precharge after read burst ................................ ................................ ................................ ............................... 61 auto precharge after write burst ................................ ................................ ................................ ................................ 62 burst read and single write operation ................................ ................................ ................................ ........................ 63 full page burst read and single write operation ................................ ................................ ................................ ........... 64 /cs function (only /cs signal needs to be asserted at minimum rate) ................................ ................................ ................. 65 package dimension ................................ ................................ ................................ ................................ ..................... 66
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 5 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. description the nt56v6610c0t and nt56v6620c0t are four - bank synchronous drams organized as 2mbit x 8 i/o x 4 bank and 1mbitx16i/ox4bank, respectively. these synchronous devices achieve high - speed data transfer rates of up to 133mhz by employing a pipeline chip architecture that synchronizes the output data to a system clock. the chip is fabricated with nanya advanced 64mbit single transistor cmos dram pr ocess technology. the device is designed to comply with all jedec standards set for synchronous dram products, both electrically and mechanically. all of the control, address, and data input/output (i/o or dq) circuits are synchronized with the positive e dge of an externally supplied clock. /ras, /cas, /we, and /cs are pulsed signals which are examined at the positive edge of each externally applied clock (clk). internal chip operating modes are defined by combinations of these signals and a command decode r initiates the necessary timings for each operation. a fourteen bit address bus accepts address data in the conventional /ras /cas multiplexing style. twelve row addresses (a0 - a11) and two bank select addresses (a12, a13) are strobed with /ras. ten colum n addresses (a0 - a9) plus bank select addresses and a10 are strobed with /cas. column address a9 is dropped on the x8 device and column addresses a8 and a9 are dropped on the x16 device. access to the lower or upper dram in a stacked device is controlled by /cs0 and /cs1, respectively. prior to any access operation, the /cas latency, burst length, and burst sequence must be programmed into the device by address inputs a0 - a9 during a mode register set cycle. in addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation. operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard drams. a sequential and gapless data rate of up to 133mhz is possible depending on burst length, /cas latency, and speed grade of the device. simultaneous operation of both decks of a stacked device is allowed, depending on the operation being done. auto refresh (cbr), self refresh, and low p ower operation are supported. feature jedec standard 3.3v 0.3v power supply lvttl compatible inputs and outputs four banks controlled by bank selects(a12/a13) single pulsed /ras interface fully synchronous to positive clock edge mrs cycle with address ke y programmability for : - cas latency ( 2, 3 ) - burst length ( 1, 2, 4, 8 & full - page ) - burst type ( sequential or interleave ) multiple burst read with single write option automatic and controlled precharge command data mask for re ad/write control (x8) dual data mask for byte control (x16) auto refresh (cbr) and self refresh suspend mode and power down mode standard power operation 4096 refresh cycles/64ms random column address every clk (1 - n rule) package:54 - pin 400 mil tsop - typ e ii
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 6 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. product family part no. organization speed ( mhz@cl - trp - trcd) interface package nt56v6610c0t - 75b 133 mhz @ 3 - 3 - 3 100 mhz @ 2 - 2 - 2 nt56v6610c0t - 75 133 mhz @ 3 - 3 - 3 - nt56v6610c0t - 8b 125 mhz @ 3 - 3 - 3 100mhz @ 2 - 2 - 2 nt56v6610c0t - 8a 8m x 8 125 mhz @ 3 - 3 - 3 100mhz @ 3 - 2 - 2 nt56v6620c0t - 7 143 mhz @ 3 - 3 - 3 - nt56v6620c0t - 75b 133 mhz @ 3 - 3 - 3 100 mhz @ 2 - 2 - 2 nt56v6620c0t - 75 133 mhz @ 3 - 3 - 3 - nt56v6620c0t - 8b 125 mhz @ 3 - 3 - 3 100mhz @ 2 - 2 - 2 nt56v6620c0t - 8a 4m x 16 125 mhz @ 3 - 3 - 3 100mhz @ 3 - 2 - 2 lvttl 54pin tsop ii
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 7 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. pin assignment ( top view ) 54 53 1 2 3 ? v dd 8m x 8 4m x 16 dq0 v ddq nc dq1 v ssq nc dq2 v ddq nc dq3 v ssq nc v dd nc we cas ras cs a13/bs0 a12/bs1 a10/ap a0 a1 a2 a3 v dd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 52 51 50 49 48 47 46 45 44 43 36 37 35 34 33 41 42 40 39 38 32 31 30 29 vss dq7 vss q nc dq6 v dd q nc dq5 v ssq nc dq4 v ddq nc v ss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss vss dq15 vss q dq14 dq13 v dd q dq12 dq11 v ssq dq10 dq9 v ddq dq8 v ss nc udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 v dd ldqm we cas ras cs a13/bs0 a12/bs1 a10/ap a0 a1 a2 a3 v dd 54-pin plastic tsop-ii 400 mil
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 8 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. pin description clk clock input dq0 - dq15 data input/output cke clock enable dqm, ldqm, udqm data mask /cs (/cs0, /c s1 ) chip select vdd power (+3.3v) /ras row address strobe vss ground /cas column address strobe vddq power for dqs (+3.3v) /we write enable vssq ground for dqs bs1, bs0 (a12, a13) bank select nc no connection a0 - a11 address inputs -- -- input / out put functional description symbol type polarity function clk input positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input active high activates the clk signal when high and deactivates the clk signal when low. by deactivating the clock, cke low initiates the power down mode, suspend mode, or the self refresh mode. /cs input active low /cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. /ras, /cas /we input active low when sampled at the positive rising edge of the clock, /cas, /ras, and /we define the operation to be executed by the sdram. bs1, bs0 (a12, a13) input -- selects which bank is to be active. a0 - a11 input -- during a bank activate command cycle, a0 - a11 defines the row address (ra0 - ra11) when sampled at the rising clock edge. during a read or write command cycle, a0 - a9 defines the column address (ca0 - ca9) when sampled at the rising clock edge. a10 is used to invoke auto - precharge operation at the end of the burst read or write cycle. if a10 is high, auto - precharge is selected and bs0, bs1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10 is used in conjunction with bs0, bs1 to control which bank(s) to precharge. if a10 is high, all banks will be precharged regardless of the state of bs. if a10 is low, then bs0 and bs1 are used to define wh ich bank to precharge. dq0 - dq15 input - output -- data input/output pins operate in the same manner as on conventional drams dqm ldqm udqm input active high the data input/output mask places the dq buffers in a high impedance state when sampled high. in x1 6 products, ldqm and udqm control the lower and upper byte i/o buffers, respectively. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. dqm low turns the output buffers on and dqm high turns them off . in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. vdd, vss supply -- power and ground for the input buffers and the core logic. vddq, vs sq supply -- isolated power supply and ground for the output buffers to provide improved noise immunity.
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 9 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. functional block diagram address buffers ( 14 ) control signal generator data control circuitry cell array memory bank 1 data input / output buffers sense amplifiers column decoder row decoder row decoder dq 0 dq x clk cke cs ras cas a12 a13 a10 cell array memory bank 3 sense amplifiers column decoder cell array memory bank 0 sense amplifiers row decoder column decoder column decoder row decoder cell array memory bank 2 sense amplifiers command decoder mode register clk buffer we refresh counter column address counter cke buffer a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a11 dqm cell array , per bank , for 2mb x 8 dq : 4096 row x 512 col x 8 dq (dq0-dq7 ). cell array , per bank , for 1mb x 16 dq : 4096 row x 256 col x 16 dq (dq0-dq15).
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 10 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. part number guide nt 56 v 6 6 10 c 0 t - xx nanya memory*(1) device*(2) voltage*(3) density*(4) refresh time*(5) configration*(6) revision*(7) interface*(8) package*(9) speed*(10) (5) refresh time (1) nanya memory (2) device (3) voltage (4) density 56 - - - - - - - - sdram v - - - - - - - - 3.3v 1 - - - - - - - - 16m 7 - - - - - - - - 2k/32ms (6) configuration (7) revision (8) interface (9) package (10) speed 10 - - - - - - - - 4 bank, x 8 a - - - - - - - - 1st version 0 - - - - - - - - lvttl 1 - - - - - - - - sstl t - - - - - - - -tsop ii f - - - - - - - -tqfp q - - - - - - - -qfp 7 - - - - - - - -143mhz 75 - - - - - - -133mhz 8 - - - - - - - -125mhz 20 - - - - - - - - 4 bank, x 16 b - - - - - - - - 2nd version c - - - - - - - - 3rd version d - - - - - - - - 4th version 6 - - - - - - - - 64m 2 - - - - - - - - 128m 6 - - - - - - - - 4k/64ms 10 - - - - - - -100mhz
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 11 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. dc characteristics absolute maximum ratings symbol parameter rating units notes v dd power supply voltage - 0.3 to +4.6 v 1 v ddq power supply voltage for output - 0.3 to +4.6 v 1 v in input voltage - 0.3 to v dd +0.3 v 1 v out output voltage - 0.3 to v dd +0.3 v 1 t a operating temperature (ambient ) 0 to +70 c 1 t stg storage temperature - 55 to +125 c 1 p d power dissipation 1.0 w 1 i out short circuit output current 50 ma 1 1.stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended dc operating conditions (t a = 0 to 70 c ) rating symbol parameter min. typ. max. units notes v dd power voltage 3.0 3.3 3.6 v 1 v ddq power voltage for output 3.0 3.3 3.6 v 1 v ih input high voltage 2.0 - v dd + 0 .3 v 1,2 v il input low voltage - 0.3 - 0.8 v 1,3 1. all voltages referenced to v ss and v ssq . 2. v ih (max) = v dd / v ddq + 1.2v for pulse width 5ns 3. v il (min) = v ss /v ssq - 1.2v for pulse width 5ns . capacitance (t a = 25 c, f = 1mhz, vdd = 3.3v 0.3v) symbol parameter min. typ. max. units notes input capacitance (a0 - a11, bs0, bs1, /cs, /ras, /cas, /we, cke, dqm) 2.5 3.0 3.8 c i input capacitance (clk) 2.5 2.8 3.5 c o output capacitance (dq0 ? dq15) 4.0 4.5 6.5 pf 1 1. multiply gi ven planar values by 2 for 2 - high stacked device except /cs.
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 12 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. dc electrical characteristics (t a = 0 to +70 c , v dd = 3.3v 0.3v) symbol parameter min. max. units notes i i(l) input leakage current, any input (0.0v v in v dd ), all ot her pins not under test = 0v - 1 +1 ua 1 i o(l) output leakage current (d out is disabled, 0.0v v out v ddq ) - 1 +1 ua 1 v oh output level (lvttl ) output "h" level voltage (i out = - 2.0ma) 2.4 - v - v ol output level (lvttl ) output "l" level voltage (i out = +2.0ma) - 0.4 v - 1. multiply given planar values by 2 for 2 - high stacked device. dc output load circuit v oh (dc) = 2.4v,i oh = -2ma v ol (dc) = 0.4v,i ol = -2ma 3.3 v 1200 ohms 870 ohms 50 pf output
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 13 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. operating, standby, and refresh currents (v dd = 3.3v 10% , t a =0 c to 70 c) version parameter symbo l test condition - 7 - 75(b) - 8b - 8a unit note operating current i cc1 1 bank operation , t rc = t rc (mim), t ck = min active - precharge command cycling without burst operation 75 75 70 70 ma 1,2,3 i cc2p cke <= v il (max), t ck = min, /cs = v ih (min), 2 ma 1 precharge standby current in power - down mode i cc2ps cke <= v il (max), t ck = oo , /cs = v ih (min) 2 ma 1 i cc2n cke >= v ih (min), /cs = v ih (min), t ck = min 35 35 25 25 ma 1 precharge standby current in non power - down mode i cc2ns ck e >= v ih (min), t ck = oo 5 ma 1,5 i cc3p cke<=v il (max), t ck = min 3 ma 1,7 no operating current ( active state : 4 bank) i cc3n cke >=v ih (min), /cs = v ih (min), t ck = min 40 40 30 30 ma 1,5 operating current ( burst mode ) i cc4 t ck =min , read/ write comman d cycling, multiple banks active, gapless data, bl=4 120 120 90 90 ma 1,6 auto(cbr) refresh current i cc5 t rc = t rc (min) ; t ck =min cbr command cycling 145 145 140 140 ma 1,3,4 self refresh current i cc6 cke <= 0.2v 1 ma 1 note : 1. currents given are val id for a single device. the total current for a stacked device depends on the operation being performed on the other deck. 2. these parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t and t .input signals are changed up to three times during t (min). 3. the specified values are obtained with the output open. 4. input signals are changed once during t (min). 5. input signals are changed once during three clock cycles. 6. active standby c urrent will be higher if clock suspend is entered during a burst read cycle (add 1ma per dq). 7. input signals are stable.
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 14 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac characteristics (t a = 0 to +70 c , v dd = 3.3v 0.3v) 1. an initial pause of 200 u s,with dqm and cke held high , is required after power - up. a precharge all banks command must be given followed by a minimum of eight auto (cbr) refresh cycles before or after the mode register set operation . 2. the transition time is measured between v ih and v il (or between v il and v ih ). 3. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. load circuit a : ac timing tests have v il = 0. 4 v and v ih = 2.4 v with the timing referenced to the 1.40v crossover point 5. load circuit a : ac measurements assume t t = 1.0ns. 6. load circuit b : ac timing tests have v il = 0.8 v and v ih = 2.0 v with the timing referenced to the 1.40v crossove r point 7. load circuit b : ac measurements assume t t = 1.2ns. ac output load circuits clock input output t hold t setup t ckl t ckh t t v ih v il 1.4v 1.4v t ac t lz toh 1.4v output zo = 50 ohm 50 pf ac output load circuit ( a ) vtt = 1.4v 50 ohm output zo = 50 ohm 50 pf ac output load circuit ( b )
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 15 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac timing parameters clock and clock enable parameters - 7 - 75b - 75 - 8b - 8a symbol parameter min. max. min. max. min. max. min. max. min. max. unit note tck3 clock cycle time, /cas latency = 3 7 - 7.5 - 7.5 - 8 - 8 - ns tck2 clock cycle time, /cas latency = 2 - - 10 - - - 10 - 12 - ns tac3(a) clock access time, /cas latency = 3 - 6 - - - - - - - - ns 1 tac2(a) clock access time, /cas latency = 2 - - - - - - - - - - ns 1 tac3(b) clock access time, /cas latency = 3 - - - 5.4 - 5.4 - 6 - 6 ns 2 tac2(b) clock access time, /cas latency = 2 - - 6 - - - - 6 - 6 ns 2 tckh clock high pulse width 3 - 2. 5 - 2.5 - 3 - 3 - ns tckl clock low pulse width 3 - 2.5 - 2.5 - 3 - 3 - ns tces clock enable set - up time 2 - 1.5 - 1.5 - 2 - 2 - ns tceh clock enable hold time 1 - 0.8 - 0.8 - 1 - 1 - ns tsb power down mode entry time 0 7 0 7.5 0 7.5 0 10 0 12 ns tt transition time (rise and fall) 0.5 10 0.5 10 0.5 10 0.5 10 0.5 10 ns 1.access time is measured at 1.4v. see ac characteristics: notes 1, 2, 3, 4, 5 and load circuit a 2.access time is measured at 1.4v. see ac characteristics: notes 1, 2, 3, 6, 7 and load circuit b. common parameters - 7 - 75b - 75 - 8b - 8a symbol parameter min. max. min. max. min. max. min. max. min. max. unit note tcs command setup time 2 - 1.5 - 1.5 - 2 - 2 - ns tch command hold time 1 - 0.8 - 0.8 - 1 - 1 - ns tas a ddress and bank select set - up time 2 - 1.5 - 1.5 - 2 - 2 - ns tah address and bank select hold time 1 - 0.8 - 0.8 - 1 - 1 - ns trcd /ras to /cas delay 21 - 20 - 20 - 20 - 20 - ns 1 trc bank cycle time 70 - 65 - 65 - 70 - 70 - ns 1 tras active command period 49 45 45 50 50 - ns 1 trp precharge time 21 - 20 - 20 - 20 - 20 - ns 1 trrd bank to bank delay time 14 - 15 - 15 - 20 - 20 - ns 1 tccd /cas to /cas delay time 1 - 1 - 1 - 1 - 1 - clk 1.these parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 16 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. mode register set cycle - 7 - 75b - 75 - 8b - 8a symbol parameter m in. max. min. max. min. max. min. max. min. max. unit note trsc mode register set cycle time 2 - 2 - 2 - 2 - 2 - clk 1 1.these parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cy cles = specified value of timing / clock period (count fractions as a whole number). read cycle - 7 - 75b - 75 - 8b - 8a symbol parameter min. max. min. max. min. max. min. max. min. max. unit note 2.5 - - - - - 2.5 - 2.5 - ns 1 toh data out hold time 2.7 - 2.7 - 3 - 3 - ns 2 tlz data out to low impedance time 0 - 0 - 0 - 0 - 0 - ns thz3 3 6 3 5.4 3 5.4 3 6 3 6 ns 3 thz2 data out to high impedance time - - - - - - 3 6 3 8 ns 3 tdqz dqm data out disable latency 2 - 2 - 2 - 2 - 2 - clk 1.a c output load circuit a. 2.ac output load circuit b. 3.referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. refresh cycle - 7 - 75b - 75 - 8b - 8a symbol parameter min. max. min. max. m in. max. min. max. min. max. unit note tref refresh period - 64 - 64 - 64 - 64 - 64 ms tsrex self refresh exit time 10 - 10 - 10 - 10 - 10 - ns write cycle - 7 - 75b - 75 - 8b - 8a symbol parameter min. max. min. max. min. max. min. max. min. ma x. unit note tds data in set - up time 2 - 1.5 - 1.5 - 2 - 2 - ns tdh data in hold time 1 - 0.8 - 0.8 - 1 - 1 - ns tdpl data input to precharge 14 - 15 - 15 - 15 - 15 - ns tdal3 data in to active delay /cas latency = 3 5 - 5 - 5 - 5 - 5 - clk tdal2 data in to active delay /cas latency = 2 - - - - - - 4 - 3 - clk tdqw dqm write mask latency 0 - 0 - 0 - 0 - 0 - ns
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 17 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. clock frequency and latency symbol parameter - 7 - 75b - 75 - 8b - 8a units tck clock frequency 143 133 100 133 125 100 125 83 mhz tck clock cycle time 7 7.5 10 7.5 8 10 8 12 ns taa /cas latency 3 3 2 3 3 2 3 2 clk trp precharge time 3 3 2 3 3 2 3 2 clk trcd /ras to /cas delay 3 3 2 3 3 2 3 2 clk trc bank cycle time 10 9 7 9 9 7 9 6 clk tras minimum bank active time 7 6 5 6 6 5 6 4 clk tdpl data in to precharge 2 2 2 2 2 2 2 2 clk tdal data in to active/refresh 5 5 4 5 5 4 5 4 clk trrd bank to bank delay time 2 2 2 2 2 2 2 2 clk tccd /cas to /cas delay time 1 1 1 1 1 1 1 1 clk twl write latency 0 0 0 0 0 0 0 0 clk tdqw dqm write mask latency 0 0 0 0 0 0 0 0 clk tdqz dqm data disable latency 2 2 2 2 2 2 2 2 clk tcsl clock suspend latency 1 1 1 1 1 1 1 1 clk
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 18 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. command truth table cke function device state previous cycle current cycle /cs /ras /cas /we dqm a12, a13 a1 0 a11, a0 - a9 notes mode register set idle h x l l l l x op code auto (cbr) refresh idle h h l l l h x x x x entry self refresh idle h l l l l h x x x x h x x x exit self refresh idle(self - refresh) l h l h h h x x x x single bank precharge see current state table h x l l h l x bs l x 2 precharge all banks see current state table h x l l h l x x h x bank activate idle h x l l h h x bs row address 2 write active h x l h l l x bs l column 2 write with auto - precharge active h x l h l l x bs h column 2 read active h x l h l h x bs l column 2 read with auto - precharge active h x l h l h x bs h column 2 burst termination active h x l h h l x x x x 3,8 no operation any h x l h h h x x x x device d eselect any h x h x x x x x x x clock suspend mode entry active h l x x x x x x x x clock suspend mode exit active l h x x x x x x x x 4 data write/output enable active h x x x x x l x x x data mask/output disable active h x x x x x h x x x 5 h x x x power down mode entry idle/active h l l h h h x x x x 6,7 h x x x power down mode exit any (power down) l h l h h h x x x x 6,7 1 all of the sdram operations are defined by states of /cs, /we, /ras, /cas, and dqm at the positive ris ing edge of the clock. operation of both decks of a stacked device at the same time is allowed, depending on the operation being performed on the other deck. refer to the current state truth table. 2. bank select(bs0,bs1):bs0,bs1=0,0 selects bank0; bs0,bs1=0,1 selects bank1; bs0,bs1=1,0 selects bank2; bs0,bs1= 1,1 selects bank 3. 3. during a burst write cycle there is a zero clock delay; for a burst read cycle the delay is equal to the /cas latency. 4. during normal access mode, cke is hel d high and clk is enabled. when it is low, it freezes the internal clock and extends data read and write operations. one clock delay is required for mode entry and exit. 5. the dqm has two functions for the data dq read and write operations. during a read cyc le, when dqm goes high data clock timing the data outputs are disabled and become high impedance after a two - clock delay. dqm also provides a data mask function for write cycles. when it activates, the write operation at the clock is prohib ited (zero clock latency). 6. all banks must be precharged before entering the power down mode. (if this command is issued during a burst operation, the device state will be clock suspend mode.) the power down mode does not perform any refresh operati ons; therefore the device can?t remain in this mode longer than the refresh period (t ref ) of the device. one clock delay is required for mode entry and exit. 7. a no operation or device deselect command is required on the next clock edge follow ing cke going high. 8. device state is full page burst operation. use of this command to terminate other burst length operations is illegal.
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 19 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. clock enable (cke) truth table cke comma nd current state previous cycle current cycle /cs /ras /cas /we a12, a13 a11 ? a10 action notes h x x x x x x x invalid 1 l h h x x x x x exit self refresh with device deselect 2 l h l h h h x x exit self refresh with no operation 2 l h l h h l x x illegal 2 l h l h l x x x illegal 2 l h l l x x x x illegal 2 self fresh l l x x x x x x maintain self refresh h x x x x x x x invalid 1 l h h x x x x x power down mode exit, all banks idle 2 l h l x x x x x illegal 2 power down l l x x x x x x maintain power down mode h h h x x x 3 h h l h x x 3 h h l l h x refer to the idle state section of the current state truth table 3 h h l l l h x x cbr refresh h h l l l l op code mode register set 4 h l h x x x 3 h l l h x x 3 h l l l h x refer to the idle state section of the current state truth table 3 h l l l l h x x entry self refresh 4 h l l l l l op code mode register set all banks idle l x x x x x x x power down 4 h h x x x x x x refer to operations in the current state truth table h l x x x x x x begin clock suspend next cycle 5 l h x x x x x x exit clock suspend next cycle any state other than listed above l l x x x x x x maintain clock suspend 1. for the given current state cke must be low in the previous cycle. 2. when cke has a low to high transition, the clock and other inputs are re - enabled asynchronously. the minimum setup time for cke (t ces ) must be satisfied. when exiting power down mode, a nop command (or device deselect com mand) is required on the first rising clock after cke goes high . 3. the address inputs (a13 - a0) depend on the command that is issued. see the idle state section of the current state truth table for more information. 4. the precharge power down mode,the self refresh mode,and the mode register set can only be entered from the all banks idle state. 5. must be a legal command as defined in the current state truth table.
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 20 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. current state truth table (part 1 of 3)(see note 1) command current state /cs /ras /cas /we a12, a13 a11 - a0 description action notes l l l l op code mode register set set the mode register 2 l l l h x x auto or self refresh start auto or self refresh 2,3 l l h l bs x precharge n o operation l l h h bs row address bank active activate the specified bank and row l h l l bs column write illegal 4 l h l h bs column read illegal 4 l h h l x x burst termination no operation l h h h x x no operation no operation idle h x x x x x device deselect no operation or power down 5 l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge precharge 6 l l h h bs row address bank active illegal 4 l h l l bs column write start write; determine if auto precharge 7,8 l h l h bs column read start read; determine if auto precharge 7,8 l h h l x x burst termination no operation l h h h x x no operation no operation row active h x x x x x device deselect no operation l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge terminate burst; start the precharge l l h h bs row address bank active illegal 4 l h l l bs column write terminate burst; start the write cycl e 8,9 l h l h bs column read terminate burst; start a new read cycle 8,9 l h h l x x burst termination terminate the burst l h h h x x no operation continue the burst read h x x x x x device deselect continue the burst l l l l op code mode reg ister set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge terminate burst; start the precharge l l h h bs row address bank active illegal 4 l h l l bs column write terminate burst; start a new write cycle 8,9 l h l h bs column read terminate burst; start the read cycle 8,9 l h h l x x burst termination terminate the burst l h h h x x no operation continue the burst write h x x x x x device deselect continue the burst 1. cke is assumed to be active (high) in the previou s cycle for all entries. the current state is the state of the bank that the command is being applied to. 2. all banks must be idle; otherwise, it is an illegal action. 3. if cke is active (high) the sdram will start the auto(cbr) refresh operation, if cke is in active(low) than the self refresh mode is entered. 4. the current state refers to only one of the banks. if bs selects this bank then the action is illegal. if bs selects the bank not being referenced by the current state then the action may be legal depending on the state of that bank. 5. if cke is inactive (low) then the power down mode is entered; otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satisfied. 7. the ras to cas delay (t rcd ) must occur before the command i s given. 8. column address a10 is used to determine if the auto precharge function is activated. 9. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied.
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 21 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. current state truth table (part 2 of 3)(see note 1) command current state /cs /ras /cas /we a12, a13 a11 - a0 description action notes l l l l op code mode register set illegal l l l h x x auto or se lf refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank active illegal 4 l h l l bs column write illegal 4 l h l h bs column read illegal 4 l h h l x x burst termination illegal l h h h x x no operation continue the bu rst read with auto precharge h x x x x x device deselect continue the burst l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank active illegal 4 l h l l bs column write illegal 4 l h l h bs column read illegal 4 l h h l x x burst termination illegal l h h h x x no operation continue the burst write with auto precharge h x x x x x device deselect continue the burst l l l l op code mode register set illeg al l l l h x x auto or self refresh illegal l l h l bs x precharge no operation; bank(s) idle after t rp l l h h bs row address bank active illegal 4 l h l l bs column write illegal 4 l h l h bs column read illegal 4 l h h l x x burst termin ation no operation; bank(s) idle after t rp l h h h x x no operation no operation; bank(s) idle after t rp precharging h x x x x x device deselect no operation; bank(s) idle after t rp l l l l op code mode register set illegal l l l h x x auto o r self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank active illegal 4,10 l h l l bs column write illegal 4 l h l h bs column read illegal 4 l h h l x x burst termination no operation; row active after t rcd l h h h x x no operation no operation; row active after t rcd row activating h x x x x x device deselect no operation; row active after t rcd 1. cke is assumed to be active (high) in the previous cycle for all entries. the current state is the state of the bank that the comm and is being applied to. 2. all banks must be idle; otherwise, it is an illegal action. 3. if cke is active (high) the sdram will start the auto(cbr) refresh operation, if cke is inactive(low) than the self refresh mode is entered. 4. the current state refers to on ly one of the banks. if bs selects this bank then the action is illegal. if bs selects the bank not being referenced by the current state then the action may be legal depending on the state of that bank. 5. if cke is inactive (low) then the power dow n mode is entered; otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satisfied. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. column address a10 is used to determine if the auto precharge function i s activated. 9. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied.
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 22 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. current state truth table (part 3of 3)(see note 1) command curr ent state /cs /ras /cas /we a12, a13 a11 - a0 description action notes l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activ e illegal 4 l h l l bs column write start write; determine if auto precharge 9 l h l h bs column read start write; determine if auto precharge 9 l h h l x x burst termination no operation; row active after t dpl l h h h x x no operation no operati on;row active after t dpl write recovering h x x x x x device deselect no operation; row active after t dpl l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank active illegal 4 l h l l bs column write illegal 4,9 l h l h bs column read illegal 4,9 l h h l x x burst termination no operation; precharge active after t dpl l h h h x x no operation no operation; precharge active a fter t dpl write recovering with auto precharge h x x x x x device deselect no operation; precharge active after t dpl l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal l l h h bs row address bank active i llegal l h l l bs column write illegal l h l h bs column read illegal l h h l x x burst termination no operation; idle after t rc l h h h x x no operation no operation; idle after t rc refreshing h x x x x x device deselect no operation; idle after t r c l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal l l h h bs row address bank active illegal l h l l bs column write illegal l h l h bs column read illegal l h h l x x burst termination illegal l h h h x x no operation mode register accessing h x x x x x device deselect
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 23 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. 1. cke is assumed to be active (high) in the previous cycle for all entries. the current state is the state of the bank that the command is bei ng applied to. 2. all banks must be idle; otherwise, it is an illegal action. 3. if cke is active (high) the sdram will start the auto(cbr) refresh operation, if cke is inactive(low) than the self refresh mode is entered. 4. the current state refers to only one of the banks. if bs selects this bank then the action is illegal. if bs selects the bank not being referenced by the current state then the action may be legal depending on the state of that bank. 5. if cke is inactive (low) then the power down mode is entered; otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satisfied. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. column address a10 is used to determine if the auto precharge function is activate d. 9. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied.
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 24 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. device operations power on and in itialization the default power on state of the mode register is supplier specific and may be undefined. the following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. like a conventional dram, the synchronous dram must be powered up and initialized in a predefined manner. during power on, all vdd and vddq pins must be built up simultaneously to the specified voltage when the input signals are held in the "nop" state. the power on voltage must not ex ceed vdd+0.3v on any of the input pins or vdd supplies. the clk signal must be started at the same time. after power on, an initial pause of 200s is required followed by a precharge of all banks using the precharge command. to prevent data contention on t he dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. a minimum of eight auto re fresh cycles (cbr) are also required. these may be done before or after programming the mode register. failure to follow these steps may lead to unpredictable start - up modes. programming the mode register for application flexibility, /cas latency, burst length, burst sequence, and operation type are user defined variables and must be programmed into the sdram mode register with a single mode register set command. any content of the mode register can be altered by re - executing the mode register set command . if the user chooses to modify only a subset of the mode register variables, all four variables must be redefined when the mode register set command is issued. after initial power up, the mode register set command must be issued before read or write cycl es may begin. all banks must be in a precharged state and cke must be high at least one cycle before the mode register set command can be issued. the mode register set command is activated by the low signals of /ras, /cas, /cs, and /we at the positive edge of the clock. the address input data during this cycle defines the parameters to be set as shown in the mode register operation table. a new command may be issued following the mode register set command once a delay equal to trsc has elapsed. /cas latenc y the /cas latency is a parameter that is used to define the delay from when a read command is registered on a rising clock edge to when the data from that read command becomes available at the outputs. the /cas latency is expressed in terms of clock cycl es and can have a value of 2 or 3 cycles. the value of the /cas latency is determined by the speed grade of the device and the clock frequency that is used in the application. a table showing the relationship between the /cas latency, speed grade, and cloc k frequency appears in the electrical characteristics section of this document. once the appropriate /cas latency has been selected it must be programmed into the mode register after power up, for an explanation of this procedure see programming the mode r egister in the previous section.
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 25 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. mode register definition mode register set: (programming mode) a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address bus (ax) operation mode cas latency bt burst length mode register (mx) cas latenc y burst type burst length m6 m5 m4 latency m3 type m2 m1 m0 bt=0 bt=1 0 0 0 reserved 0 sequential 0 0 0 1 1 0 0 1 reserved 1 interleave 0 0 1 2 2 0 1 0 2 0 1 0 4 4 0 1 1 3 0 1 1 8 8 1 0 0 reserved 1 0 0 reserved reserved 1 0 1 reserved 1 0 1 res erved reserved 1 1 0 reserved 1 1 0 reserved reserved 1 1 1 reserved 1 1 1 full page reserved operation mode m13 m12 m11 m10 m9 m8 m7 mode 0 0 0 0 0 0 0 normal 0 0 0 0 1 0 0 multiple burst with single write burst mode operation burst mode oper ation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). three parameters define how the burst mode will operate: burst sequence, burst length, and operation mode. the burst sequence and bur st length are programmable and are determined by address bits a0 - a3 during the mode register set command. operation mode is also programmable and is set by address bits a7 - a13. burst sequence defines the order in which the burst data will be delivered or stored to the sdram. the two types of burst sequence supported are sequential and interleaved. see the table below. the burst length controls the number of bits that will be output after a read command, or the number of bits to be input after a write command. the burst length can be programmed to have values of 1, 2, 4, 8 or full page (actual page length is dependent on organization: x4, x8, or x16). full page burst operation is only possible using the sequential burst type. burst operation mode can b e normal operation or multiple burst with single write operation. normal operation implies that the device will perform burst operations on both read and write cycles until the desired burst length is satisfied. multiple burst with single write operation was added to support write through cache operation. here, the programmed burst length only applies to read cycles. all write cycles are single write operations when this mode is selected.
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 26 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. burst length and sequence burst length starting bit in terleave sequential a0 0 0 - 1 0 - 1 2 1 1 - 0 1 - 0 a1 a0 0 0 0 - 1 - 2 - 3 0 - 1 - 2 - 3 0 1 1 - 0 - 3 - 2 1 - 2 - 3 - 0 1 0 2 - 3 - 0 - 1 2 - 3 - 0 - 1 4 1 1 3 - 2 - 1 - 0 3 - 0 - 1 - 2 a2 a1 a0 0 0 0 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 0 1 1 - 0 - 3 - 2 - 5 - 4 - 7 - 6 1 - 2 - 3 - 4 - 5 - 6 - 7 - 0 0 1 0 2 - 3 - 0 - 1 - 6 - 7 - 4 - 5 2 - 3 - 4 - 5 - 6 - 7 - 0 - 1 0 1 1 3 - 2 - 1 - 0 - 7 - 6 - 5 - 4 3 - 4 - 5 - 6 - 7 - 0 - 1 - 2 1 0 0 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 1 0 1 5 - 4 - 7 - 6 - 1 - 0 - 3 - 2 5 - 6 - 7 - 0 - 1 - 2 - 3 - 4 1 1 0 6 - 7 - 4 - 5 - 2 - 3 - 0 - 1 6 - 7 - 0 - 1 - 2 - 3 - 4 - 5 8 1 1 1 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 7 - 0 - 1 - 2 - 3 - 4 - 5 - 6 full page (note ) n n n not supported cn, cn+1,cn+2?.. note : page length is a function of i/o organization and column addressing. x 8 organization (ca0 - ca8); page length = 512 bits x16 organization (ca0 - ca7); page length = 256 bits bank act ivate command in relation to the operation of a fast page mode dram, the bank activate command corresponds to a falling /ras signal. the bank activate command is issued by holding /cas and /we high with /cs and /ras low at the rising edge of the clock. th e bank select address a12 - a13 is used to select the desired bank. the row address a0 - a11 is used to determine which row to activate in the selected bank. activation of banks within both decks of a 2 - high stacked device is allowed. the bank activate co mmand must be applied before any read or write operation can be executed. the delay from when the bank activate command is applied to when the first read or write operation can begin must meet or exceed the /ras to /cas delay time (trcd). once a bank has b een activated, it must be precharged before another bank activate command can be applied to the same bank. the minimum time interval between successive bank activate commands to the same bank is determined by the ras cycle time of the device (trc). the min imum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank delay time (trrd). the maximum time that each bank can be held active is specified as tras(max).
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 27 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. bank activate command cycle clk address command t0 t1 t2 t3 tn tn+1 tn+2 tn+3 bank a row addr. bank a col. addr. bank a activate nop write a with aotu precharge bank b row addr. bank a row addr. bank b activate nop bank a activate nop ras cycle time (trc) ras-cas delay(trcd) ras-ras delay(trcd) cas latency = 3, trcd = 3 : "h" or "l" bank select the bank select inputs, bs0 and bs1, determine the bank to be used during a bank activate, precharge, read, or write operation. bank selection bits bs0 bs1 bank 0 0 bank 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 read and write access modes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting /ras high and /cas low at the clock's rising edge after the necessary /ras to /cas delay (trcd). /we must also be defined a t this time to determine whether the access cycle is a read operation (/we high), or a write operation (/we low). the address inputs determine the starting column address. the sdram provides a wide variety of fast access modes. a single read or write comm and will initiate a serial read or write operation on successive clock cycles at data rates of up to 147 mhz. the number of serial data bits for each access is equal to the burst length, which is programmed into the mode register. if the burst length is fu ll page, data is repeatedly read out or written until a burst stop or precharge command is issued. similar to page mode of conventional drams, a read or write cycle can not begin until the sense amplifiers latch the selected row address information. the r efresh period (tref) is what limits the number of random column accesses to an activated bank. a new burst access can be done even before the previous burst ends. the ability to interrupt a burst operation at every clock cycle is supported; this is referre d to as the 1 - n rule. when the previous burst is interrupted by another read or write command, the remaining addresses are overridden by the new address. precharging an active bank after each read or write operation is not necessary, providing the same ro w is to be accessed again. to perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new bank activate command must be issued. when more than one bank is activated, interleaved (ping pong) bank read or write operations are possible. by using the programmed burst length and alternating the access and precharge operations between multiple banks, fast and seamless data access operation among many different pages can be realized. when multiple banks are acti vated, column to column interleave operation can be done between different pages. finally, read or write commands can be issued to the same bank or between active banks on every clock cycle.
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 28 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. burst read command the burst read command is initiated by ha ving /cs and /cas low while holding /ras and /we high at the rising edge of the clock. the address inputs determine the starting column address for the burst. the mode register sets the type of burst (sequential or interleave) and the burst length (1, 2, 4 , 8, full page). the delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the /cas latency that is set in the mode register. burst read operation clk command t0 t1 t2 t3 t4 t5 t6 t7 read a nop nop nop nop nop nop nop burst length = 4, cas latency = 2, 3 t8 nop cas latency = 2 tck2, dqs cas latency = 3 tck3, dqs dou a0 dou a1 dou a2 dou a3 dou a0 dou a1 dou a2 dou a3 read interr upted by a read a burst read may be interrupted before completion of the burst by another read command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. when the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. the data from the first read command continues to appear on the outputs until the /cas latency from the interrupting read command is satisfied, at this point the data fr om the interrupting read command appears. read interrupted by a read clk command t0 t1 t2 t3 t4 t5 t6 t7 read a read b nop nop nop nop nop nop burst length = 4, cas latency = 2, 3 t8 nop cas latency = 2 tck2, dqs cas latency = 3 tck3, dqs dou a0 dou b0 dou b1 dou b2 dou a0 dou b0 dou b1 dou b2 dou b3 dou b3
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 29 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. read interrupted by a write to interrupt a burst read with a write command, dqm may be needed to place the dqs (output drivers) in a high impedance sta te to avoid data contention on the dq bus. if a read command will issue data on the first and second clocks cycles of the write operation, dqm is needed to insure the dqs are tri - stated. after that point the write command will have control of the dq bus. minimum read to write interval clk dqm t0 t1 t2 t3 t4 t5 t6 t7 nop read a write a nop nop nop nop nop burst length = 4, cas latency = 2, 3 t8 nop cas latency = 2 tck2, dqs cas latency = 3 tck3, dqs command din a0 din a1 din a2 din a3 din a0 din a1 din a2 din a3 : "h" or "l" non - minimum read to write interval clk dqm t0 t1 t2 t3 t4 t5 t6 t7 nop read a nop write a nop nop nop nop burst length = 4, cas latency = 2, 3 t8 nop cas latency = 2 tck2, dqs cas latency = 3 tck3, dqs command din a0 din a1 din a2 din a3 din a0 din a1 din a2 din a3 : dqm high for cas latency = 2 : dqm high for cas latency = 3 cl = 2 : dqm needed to mask first, second bit of read data. cl = 3 : dqm needed to mask first, second bit of read data.
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 30 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. burst write command the burst write command is initiated by having /cs, /cas, and /we low while holding /ras high at the rising edge of the clock. the address inputs determine the starting column address. there is no /cas latency required for burst write cycles. data for the first burst write cycle must be applied on the dq pins on the same clock cycle that the write comman d is issued. the remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. when the burst has finished, any additional data supplied to the dq pins will be ignored. burst write operation clk command t0 t1 t2 t3 t4 t5 t6 t7 nop write a nop nop nop nop nop nop burst length = 4, cas latency = 2, 3 t8 nop dqs dou a0 dou a1 dou a2 dou a3 don't care extra data is masked the first data elemant and the write are registered on the same clock edge. write interrupted by a write a burst write may be interrupted before completion of the burst by another write command. when the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be writ ten into the device until the programmed burst length is satisfied. write interrupted by a write clk command t0 t1 t2 t3 t4 t5 t6 t7 nop write a nop nop nop nop nop nop burst length = 4, cas latency = 2, 3 t8 nop dqs din a0 din b0 din b1 din b3 din b2 1 clk interval
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 31 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. write interrupted by a read a read command will interrupt a burst write operation on the same clock cycle that the read command is registered. the dqs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. when the read command is registered, any residual data from the burst wr ite cycle will be ignored. data that is presented on the dq pins before the read command is initiated will actually be written to the memory. minimum write to read interval clk command t0 t1 t2 t3 t4 t5 t6 t7 write a read b nop nop nop nop nop nop burst length = 4, cas latency = 2, 3 t8 nop cas latency = 2 tck2, dqs cas latency = 3 tck3, dqs dou b0 dou b1 dou b2 dou b3 din a0 don't care din a0 don't care dou b0 dou b1 dou b2 dou b3 input data for the write is masked don't care input data must be removed from the dqs at least one clock cycle before the data appears on the outputs to avoid data contention. non - minimum write to read interval clk command t0 t1 t2 t3 t4 t5 t6 t7 write a nop read b nop nop nop nop nop burst length = 4, cas latency = 2, 3 t8 nop cas latency = 2 tck2, dqs cas latency = 3 tck3, dqs dout b0 dout b1 dout b2 dout b3 din a0 din a1 din a0 dout b0 dout b1 dout b2 input data for the write is masked don't care input data must be removed from the dqs at least one clock cycle before the data appears on the outputs to avoid data contention. don't care din a1 don't care dout b3
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 32 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. burst stop command once a burst read or write operation has been initiated, there exist several methods in which to terminate the burst operation prematurely. these methods include using another read or write command to interrup t an existing burst operation or using a precharge command to interrupt a burst cycle and close the active bank. when interrupting a burst with another read or write command care must be taken to avoid dq contention. if the burst length is full page, the burst stop command may also be used to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank. use of the burst stop command during other burst length operations is illegal. the burst stop command is defined by having /ras and /cas high with /cs and /we low at the rising edge of the clock. when using the burst stop command during a burst read cycle, the data dqs go to a high impedance state after a delay which is equal to the /ca s latency set in the mode register. termination of a burst read operation clk command t0 t1 t2 t3 t4 t5 t6 t7 read a nop nop nop nop nop nop nop burst length = full page, cas latency = 2, 3 t8 burst stop cas latency = 2 tck2, dqs cas latency = 3 tck3, dqs dout a0 dout a1 dout a2 dout a0 dout a1 dout a2 dout a3 dout a3 the burst ends after a delay equal to the cas latency. if a burst stop command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored. data that is presented on the dq pins before the burst stop command is registered will be written to the memory. termination of a burst write operation clk command t0 t1 t2 t3 t4 t5 t6 t7 nop write a nop nop nop nop nop nop burst length = full page, cas latency = 2, 3 t8 burst stop cas latency=2,3 dqs din a0 din a1 din a2 don't care input data for the write is masked
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 33 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. auto - precharge operation before a new row in an active bank can be open ed, the active bank must be precharged using either the precharge command or the auto - precharge function. when a read or a write command is given to the sdram, the /cas timing accepts one extra address, column address a10, to allow the active bank to autom atically begin precharge at the earliest possible moment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of th e burst sequence. if a10 is high when the read or write command is issued, then the auto - precharge function is engaged. during auto - precharge, a read command will execute as normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed. regardless of burst length, the precharge will begin (/cas latency - 1) clocks prior to the last data output. auto - precharge can also be implemented during write commands. a read or write command without auto - prechar ge can be terminated in the midst of a burst operation. however, a read or write command with auto - precharge can not be interrupted by a command to the same bank. therefore use of a read, write, or precharge command to the same bank is prohibited during a read or write cycle with auto - precharge until the entire burst operation is completed. once the precharge operation has started the bank cannot be reactivated until the precharge time (trp) has been satisfied. it should be noted that the device will not re spond to the auto - precharge command if the device is programmed for full page burst read or write cycles, or full page burst read cycles with single write operation. when using the auto - precharge command, the interval between the bank activate command and the beginning of the internal precharge operation must satisfy tras(min). if this interval does not satisfy tras(min) then trcd must be extended. burst read with auto - precharge clk command t0 t1 t2 t3 t4 t5 t6 t7 read a auto- precharge nop nop nop nop nop nop nop burst length = 1, cas latency = 2, 3 t8 nop cas latency = 2 tck2, dqs cas latency = 3 tck3, dqs dout a0 dout a0 begin auto-precharge trp# trp# * * * # bank can be reactivated at completion of trp. trp is a function of clock cycle time and speed sort. see the clock frequency and latency table.
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 34 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. burst read with auto - precharge clk command t0 t1 t2 t3 t4 t5 t6 t7 read a auto- precharge nop nop nop nop nop nop nop burst length = 2, cas latency = 2, 3 t8 nop cas latency = 2 tck2, dqs cas latency = 3 tck3, dqs dout a0 dout a0 begin auto-precharge trp# trp# * * * # bank can be reactivated at completion of trp. trp is a function of clock cycle time and speed sort. see the clock frequency and latency table. dout a1 dout a1 burst read with auto - precharge clk command t0 t1 t2 t3 t4 t5 t6 t7 read a auto- precharge nop nop nop nop nop nop nop burst length = 4, cas latency = 2, 3 t8 nop cas latency = 2 tck2, dqs cas latency = 3 tck3, dqs dout a0 dout a0 begin auto-precharge trp# trp# * * * # bank can be reactivated at completion of trp. trp is a function of clock cycle time and speed sort. see the clock frequency and latency table. dout a1 dout a1 dout a2 dout a3 dout a2 dout a3
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 35 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. although a read command with auto - precharge cannot be interrupted by a command to the same bank, it can be interrupted by a read or write command to a dif ferent bank. if the interrupting command is issued before auto - precharge begins then the precharge function will begin with the new command. the bank being auto - precharged may be reactivated after the delay trp. burst read with auto - precharge interrupted by read clk command t0 t1 t2 t3 t4 t5 t6 t7 read a auto- precharge nop read b nop nop nop nop nop burst length = 4, cas latency = 2, 3 t8 nop cas latency = 2 tck2, dqs cas latency = 3 tck3, dqs dout a0 dout a0 trp# trp# * * * # bank can be reactivated at completion of trp. trp is a function of clock cycle time and speed sort. see the clock frequency and latency table. dout a1 dout a1 dout b0 dout b1 dout b2 dout b3 dout b0 dout b1 dout b2 dout b3 if interrupting a read command with auto - precharge with a write command, dqm must be used to avoid dq contention. burst read with auto - precharge interrupted by write clk command t0 t1 t2 t3 t4 t5 t6 t7 read a auto- precharge nop nop write b nop nop nop nop burst length = 8, cas latency = 2 t8 nop cas latency = 2 tck2, dqs dqm trp# * * # bank can be reactivated at completion of trp. trp is a function of clock cycle time and speed sort. see the clock frequency and latency table. dout a0 dout b0 dout b1 dout b2 dout b3 dout b4 if a10 is high whe n a write command is issued, the write with auto - precharge function is initiated. the bank undergoing auto - precharge can not be reactivated until tdal, data - in to active delay , is satisfied.
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 36 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. burst write with auto - precharge clk command t0 t1 t2 t3 t4 t5 t6 t7 read a auto- precharge nop nop nop nop nop nop nop burst length = 2, cas latency = 2, 3 t8 nop cas latency = 2 tck2, dqs cas latency = 3 tck3, dqs tdal# tdal# * * * # bank can be reactivated at completion of tdal. number of clocks required depends on clock cycle time and speed sort. see the clock frequency and latency table. din a0 din a1 din a0 din a1 similar to the read command, a write command with auto - precharge can not be interrupted by a command to the same bank. it can be interrupted by a read or write command to a different bank, however. the precharge function will begin with the new com mand. the bank may be reactivated after trp is satisfied. burst write with auto - precharge interrupted by write clk command t0 t1 t2 t3 t4 t5 t6 t7 write a auto- precharge nop write b nop nop nop nop nop burst length = 4, cas latency = 3 t8 nop cas latency = 3 tck3, dqs tdal# * * # bank can be reactivated at completion of tdal. number of clocks required depends on clock cycle time and speed sort. see the clock frequency and latency table. din a0 din a1 din b0 din b1 din b2 din b3
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 37 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. burst write with auto - precharge interrupted by read clk command t0 t1 t2 t3 t4 t5 t6 t7 write a auto- precharge nop nop read b nop nop nop nop burst length = 4, cas latency = 3 t8 nop cas latency = 3 tck3, dqs tdal# * * # bank a can be reactivated at completion of tdal. number of clocks required depends on clock cycle time and speed sort. see the clock frequency and latency table. din a0 din a1 din a2 dout b1 dout b2 dout b0 precharge command th e precharge command is used to precharge or close a bank that has been activated. the precharge command is triggered when /cs, /ras, and /we are low and /cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank separately or all banks simultaneously. three address bits -- a10, a12, and a13 -- are used to define which bank(s) is to be precharged when the command is issued. bank selection for precharge by address bits a10 bank select precharged bank(s) low bs0, bs1 bank defined by bs0, bs1 only high don't care all banks for read cycles, the precharge command may be applied (/cas latency - 1) clocks prior to the last data output. for write cycles, a delay must be satisfied from the start of the last burst write cyc le until the precharge command can be issued. this delay is known as tdpl, data - in to precharge delay. after the precharge command is issued, the precharged bank must be reactivated before a new read or write access can be executed. the delay between the precharge command and the activate command must be greater than or equal to the precharge time (trp).
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 38 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. burst read followed by the precharge command clk command t0 t1 t2 t3 t4 t5 t6 t7 read ax0 nop nop nop precharge a nop nop nop burst length = 4, cas latency = 2 t8 nop cas latency = 2 tck2, dqs trp * * bank a can be reactivated at completion of trp. dout ax0 dout ax3 dout ax1 dout ax2 burst write followed by the precharge command clk command t0 t1 t2 t3 t4 t5 t6 t7 nop activate bank ax nop write ax0 nop precharge a nop nop burst length = 2, cas latency = 2 t8 nop cas latency = 2 tck2, dqs tdpl# * * # bank can be reactivated at completion of trp. tdpl and trp are functions of clock cycle time and speed sort.see the clock frequency and latency table. din ax0 din ax1 trp#
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 39 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. precharge termination the precharge command may be used to terminate either a burst read or burst write operation. when the precharge command is issued, the burst operation is terminated and bank precharge begins. for burst re ad operations, valid data will continue to appear on the data bus as a function of /cas latency. burst read interrupted by precharge clk command t0 t1 t2 t3 t4 t5 t6 t7 read ax0 nop nop nop nop nop nop nop burst length = 8, cas latency = 2, 3 t8 precharge a cas latency = 2 tck2, dqs cas latency = 3 tck3, dqs trp# trp# * * * # bank a can be reactivated at completion of trp. trp is a function of clock cycle time and speed sort. see the clock frequency and latency table. dout ax0 dout ax1 dout ax2 dout ax3 dout ax0 dout ax1 dout ax2 dout ax3 burst write operations will be terminated by the precharge command. the last write data that will be properly stored in the device is that write data that is presented to the device a number of clock cycles prior to the precharge command equal to the data - in to precharge delay, tdpl. precharge termination of a burst write clk command t0 t1 t2 t3 t4 t5 t6 t7 nop nop write ax0 nop nop precharge a nop nop burst length = 8, cas latency = 2, 3 t8 nop dqm cas latency = 2 tck2, dqs tdpl# # tdpl is an asynchronous timing and may be completed in one or two clock cycles depending on clock cycle time . din ax1 din ax2 cas latency = 3 tck3, dqs din ax0 din ax1 din ax2 din ax0 tdpl
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 40 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. automatic refresh command ( /cas before /ras refresh) when /cs, /ras, and /cas are held low with cke and /we high at the rising edge of the clock, the chip enters the automatic refresh mode (cbr). all banks of the sdram must be precharged and idle for a minimum of the precharge time (trp) before the auto refresh command (cbr) can be applied. for a stacked device, both decks may be refreshed at the same time using automatic refresh mode. an address counter, internal to the device provides the addres s during the refresh cycle. no control of the external address pins is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharged (idle) state. a delay between the auto refresh command (cbr) and the next activate command or subsequent auto refresh command must be greater than or equal to the /ras cycle time (trc). self refresh command the sdram device has a built - in timer to accommodate self refresh operation. the self refresh command is de fined by having /cs, /ras, /cas, and cke held low with /we high at the rising edge of the clock. all banks must be idle prior to issuing the self refresh command. once the command is registered, cke must be held low to keep the device in self refresh mode. when the sdram has entered self refresh mode all of the external control signals, except cke, are disabled. the clock is internally disabled during self refresh operation to save power. the user may halt the external clock while the device is in self refr esh mode, however, the clock must be restarted before the device can exit self refresh operation. once the clock is cycling, the device will exit self refresh operation after cke is returned high. a minimum delay time is required when the device exits self refresh operation and before the next command can be issued. this delay is equal to the /ras cycle time (trc) plus the self refresh exit time (tsrex). when using self refresh, both decks of a stacked device may be refreshed at the same time. power down m ode in order to reduce standby power consumption, two power down modes are available: precharge and active power down mode. to enter precharge power down mode, all banks must be precharged and the necessary precharge delay (trp) must occur before the sdra m can enter the power down mode. if a bank is activated but not performing a read or write operation, active power down mode will be entered. (issuing a power down mode command when the device is performing a read or write operation causes the device to en ter clock suspend mode. see the following section.) once the power down mode is initiated by holding cke low, all of the receiver circuits except cke are gated off. the power down mode does not perform any refresh operations, therefore the device can't rem ain in power down mode longer than the refresh period (tref) of the device. the power down mode is exited by bringing cke high. when cke goes high, a no operation command (or a device deselect command) is required on the next rising clock edge. power down mode exit timing clk cke tm tm+1 tm+2 tm+3 tm+4 tm+5 tm+6 tm+7 nop command nop nop nop nop tm+8 nop command tck tces(min) : "h" or "l"
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 41 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. data mask the sdram has a data mask function that can be used in conjunction with data read and write cycles. when the data mask is activated (dqm high) during a write cycle, the write operation is proh ibited immediately (zero clock latency). if the data mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two clock delay, independent of /cas latency. data mask activated during a read cycle clk dqm t0 t1 t2 t3 t4 t5 t6 t7 nop nop nop nop nop nop t8 command nop read a : "h" or "l" dqs dout a0 dout a1 nop a two-clock delay before the dqs become hi-z ( burst length = 4, cas latency = 2) no operation command the no operation command should be used in cases when the sdram is in a idle or a wait state. the purpose of the no operation command is to prevent the sdram from registering any unwanted commands between operations. a no operation command is registered when /cs is low with /ras, /cas, and /we held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. deselect command the deselect command performs the same function as a no operation command. deselect command occurs when /cs is brought high, the /ras, /cas, and /we signals become don't cares. clock suspend mode during normal access mode, cke is held high enabl ing the clock. when cke is registered low while at least one of the banks is active, clock suspend mode is entered. the clock suspend mode deactivates the internal clock and suspends or "freezes" any clocked operation that was currently being executed. the re is a one clock delay between the registration of cke low and the time at which the sdram's operation suspends. while in clock suspend mode, the sdram ignores any new commands that are issued. the clock suspend mode is exited by bringing cke high. there is a one clock cycle delay from when cke returns high to when clock suspend mode is exited. when the operation of the sdram is suspended during the execution of a burst read operation, the last valid data output onto the dq pins will be actively held vali d until clock suspend mode is exited.
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 42 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. clock suspend during a read cycle clk cke t0 t1 t2 t3 t4 t5 t6 t7 nop nop nop nop nop t8 command nop read a : "h" or "l" dqs dout a0 dout element at the dqs when the suspend operation starts is held valid ( burst length = 4, cas latency = 2) a one clock delay before suspend operaton starts a one clock delay to exit the suspend command dout a1 dout a2 if clock suspend mode is initiated during a burst write operation, then the input data is masked and ignored until the clock suspend mode is exi ted. clock suspend during a write cycle clk cke t0 t1 t2 t3 t4 t5 t6 t7 nop nop nop nop nop t8 command nop write a : "h" or "l" dqs din a2 din is masked during the clock suspend period ( burst length = 4, cas latency = 2) a one clock delay before suspend operaton starts a one clock delay to exit the suspend command din a1 din a0 din a3
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 43 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. timing waveform diagram ac parameters for write timing clk cke cs ras cas ( burst length = 4, cas latency = 2 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we *bs1 a10 a0-a9,a11 dqm dq ay0 ay1 ay2 ay3 ax0 ax1 ax2 ax3 bx0 bx1 bx2 bx3 hi-z tdh tds tdpl# trp trrd tdal# trc trcd activate command bank0 activate command bank1 write with aotu precharge command bank0 write with aotu precharge command bank1 activate command bank0 write command bank0 precharge command bank0 activate command bank0 activate command bank1 #tdpl and #tdal depand on clock time and speed sort. see the clock frequncy and latency table. tche tces tckl tckh tck2 tcs tch rax rax rbx ray raz rby raz rby cax rbx cbx ray cay *bs0 = "l" bank2,3 = idle
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 44 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac parameters for read timing (3/3/3) clk cke cs ras cas burst lenght = 4 , ( cas latency = 3 ; t rcd = 3 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 we *bs1 a10 a0-a9,a11 dqm dq hi-z activate command bank 0 t ck3 rax rax cax activate command bank 0 read with auto precharge command bank 1 *bs0="l" bank2,3=idle ax3 activate command bank 1 begin auto precharge bank 0 begin auto precharge bank 1 rbx rbx rbx rbx cbx ray ray t rrd t ras t rc t rp t rcd ax0 ax1 ax2 bx0 bx1 read with auto precharge command bank 1
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 45 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac parameters for rea d timing (2/2/2) clk cke cs ras cas burst lenght = 2 , ( cas latency = 2 ; t rcd ,t rp = 2 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 we *bs1 a10 a0-a9,a11 dqm dq hi-z activate command bank 0 t ck3 rax rax cax activate command bank 0 read with auto precharge command bank 1 *bs0="l" bank2,3=idle activate command bank 1 begin auto precharge bank 0 begin auto precharge bank 1 rbx rbx rbx rbx cbx ray ray t rrd t ras(min) t rc t rp t rcd ax0 ax1 bx0 bx1 read with auto precharge command bank 0 t ceh t ces t cs t ch t hz t oh t ac2 t lz t hz t rp t ah t as
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 46 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac parameters for read timing (3/2/2) clk cke cs ras cas burst lenght = 2 , ( cas latency = 3 ; t rcd ,t rcd = 2 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 we *bs1 a10 a0-a9,a11 dqm dq hi-z activate command bank 0 t ck3 rax rax cax activate command bank 0 read with auto precharge command bank 1 *bs0="l" bank2,3=idle activate command bank 1 begin auto precharge bank 0 begin auto precharge bank 1 rbx rbx rbx rbx cbx ray ray t rrd t ras t rc t rp t rcd ax0 ax1 bx0 bx1 read with auto precharge command bank 0 note:must satisfy tras(min) extended trcd 1 clock. nor required for bl>= 4. t ac3 t oh t hz t rp
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 47 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac parameters for read timing (3/3/3) clk cke cs ras cas burst lenght = 2 , ( cas latency = 3 ; t rcd = 3 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 we *bs1 a10 a0-a9,a11 dqm dq hi-z activate command bank 0 t ck3 rax rax cax activate command bank 0 read with auto precharge command bank 1 *bs0="l" bank2,3=idle activate command bank 1 begin auto precharge bank 0 begin auto precharge bank 1 rbx rbx rbx rbx cbx ray ray t rrd t ras(min) t rc t rp t rcd ax0 ax1 bx0 read with auto precharge command bank 0 cbx t rp t oh t ac3 note:must satisfy tras(min). extended trcd not requred for bl >= 4 .
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 48 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. mode register set clk cke cs ras cas ( cas latency = 2 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we bs0,bs1 a10,a11 a0-a9 dqm dq hi-z trp precharge command all banks any command mode register set command t ck2 address key t rsc
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 49 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. power on sequence and auto refresh (cbr) clk cke cs ras cas t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we bs a10 a0-a9,a11 dqm dq hi-z t rp precharge command all banks 1st auto refresh command t ck address key 2 clock min. minimun of 8 refresh cycles are required mode register set command any command 8th auto refresh command input must be stable for 200us high level is required t rc
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 50 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. clock suspension, dqm during burst read clk cke cs ras cas burst lenght = 8 , ( cas latency = 3 ; t rcd = 3 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we *bs1 a10 a0-a9,a11 dqm dq hi-z activate command bank 0 read command bank 0 t ck3 t ces t ceh rax rax cax ax0 ax1 ax2 ax3 ax6 ax7 ax4 t hz clock suspend 3 cycles clock suspend 2 cycles clock suspend 1 cycles *bs0="l" bank2,3=idle
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 51 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. clock suspension, dqm during burst write clk cke cs ras cas burst lenght = 8 , ( cas latency = 3 ; t rcd = 3 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we *bs1 a10 a0-a9,a11 dqm dq hi-z activate command bank 0 read command bank 0 t ck3 rax rax cax dax6 dax7 clock suspend 3 cycles clock suspend 2 cycles *bs0="l" bank2,3=idle dax0 dax1 dax2 dax3 dax5 clock suspend 1 cycles
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 52 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. power down mode and clock suspend clk cke cs ras cas burst lenght = 4 , ( cas latency = 2 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we *bs1 a10 a0-a9,a11 dqm dq hi-z activate command bank 0 t ck2 rax rax cax clock suspend end clock suspend start *bs0="l" bank2,3=idle ax0 ax1 ax3 t ces t ces t sb t ces t sb ax2 t hz active standby nop read command bank 0 precharge standby nop any command
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 53 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. auto refresh (cbr) clk cke cs ras cas ( cas latency = 2 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we bs a10 a0-a9,a11 dqm dq hi-z precharge command all banks auto refresh command t rp t ck2 t rc t rc auto refresh command
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 54 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. self refresh (entry and exit) clk cke cs ras cas t0 t1 t2 t3 t4 t m t m+1 t m+2 t m+3 t m+4 t m+5 t m+6 t m+7 t m+8 t m+9 t m+10 t m+11 t m+12 t m+13 t m+14 t m+15 we bs a10 a0-a9,a11 dqm dq hi-z t sb all banks must be idle self refresh entry t ces any command self refresh exit t rc t ces power down entry t srex power down exit ( note : the clk signal must be reestablished prior to cke returning high.)
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 55 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. random row read (interleaving banks) with precharge clk cke cs ras cas burst lenght = 8 , ( cas latency = 3 ; t rcd , t rp = 3 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we *bs1 a10 a0-a9,a11 dqm dq hi-z activate command bank 1 read command bank 1 t ck3 rbx rbx cbx ax6 dax7 *bs0="l" bank2,3=idle bx0 bx1 bx2 bx3 ax0 ax1 ax4 bx4 bx5 bx6 ax5 by0 activate command bank 0 read command bank 0 precharge command bank 1 activate command bank 1 read command bank 1 read command bank 0 t rcd t ac3 cax rax rby cby rax rby high
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 56 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. random row read (interleaving banks) with auto precharge clk cke cs ras cas burst lenght = 8 , ( cas latency = 3 ; t rcd , t rp = 3 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we *bs1 a10 a0-a9,a11 dqm dq hi-z activate command bank 1 read with auto precharge command bank 1 t ck3 rbx rbx cbx ax6 ax7 *bs0="l" bank2,3=idle bx0 bx1 bx2 bx3 bx7 ax0 ax1 ax4 bx4 bx5 bx6 ax5 activate command bank 0 read with auto precharge command bank 0 activate command bank 1 read with auto precharge command bank 1 t rcd t ac3 cax rax rby cby rax rby high start auto precharge bank1 start auto precharge bank 0 by0
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 57 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. random row write (interleaving banks) with auto precharge clk cke cs ras cas burst lenght = 8 , ( cas latency = 3 ; t rcd , t rp = 3 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we *bs1 a10 a0-a9,a11 dqm dq hi-z activate command bank 0 write with auto precharge command bank 0 t ck3 rax rax cax day0 *bs0="l" bank2,3=idle dax4 dax5 dax6 dbx3 dbx4 dbx5 dbx6 dax7 dbx0 dbx1 dbx7 activate command bank 1 write with auto precharge command bank 1 activate command bank 0 write with auto precharge command bank 0 t rcd cbx rbx ray cay rbx ray high by0 dax0 dax1 dbx2 t dal # t dal # # number of clocks depends on clock cycle time and speed sort. see the clock frequency and latency table. bank may be reactivated the completion of t dal
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 58 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. random row write (interleaving banks) with precharge clk cke cs ras cas burst lenght = 8 , ( cas latency = 3 ; t rcd , t rp = 3 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we *bs1 a10 a0-a9,a11 dqm dq hi-z activate command bank 0 write command bank 0 t ck3 rax rax cax day0 *bs0="l" bank2,3=idle dax4 dax5 dax6 dbx3 dbx4 dbx5 dbx6 dax7 dbx0 dbx1 dbx7 activate command bank 1 write command bank 1 activate command bank 0 write command bank 0 t rcd cbx rbx ray cay rbx ray high day1 dax0 dax1 dbx2 t dpl t rp precharge command bank 1 precharge command bank 0
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 59 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. read - write cycle clk cke cs ras cas burst lenght = 8 , ( cas latency = 3 ; t rcd , t rp = 3 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we *bs1 a10 a0-a9,a11 dqm dq hi-z activate command bank 0 read command bank 0 t ck3 rax rax cax *bs0="l" bank2,3=idle ax0 ax1 ax2 day1 day3 ax3 day0 day4 write command bank 0 the write data is masked with a zero clock latency precharge command bank 0 cay the read data is masked with a two clock latency
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 60 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. interle aved column read cycle clk cke cs ras cas burst lenght = 4 , ( cas latency = 3 ; t rcd , t rp = 3 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we *bs1 a10 a0-a9,a11 dqm dq hi-z activate command bank 0 read command bank 0 t ck3 rax rax cax *bs0="l" bank2,3=idle ax0 ax1 ax2 by0 by1 bz0 ax3 bx1 bz1 read command bank 1 read with auto precharge command bank 0 precharge command bank 1 cby start auto precharge bank 0 rbx rbx cbx cbz cay t ac3 t rcd bx0 ay0 ay1 ay2 ay3 read command bank 1 read command bank 1 activate command bank 1
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 61 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. auto precharge after read burst clk cke cs ras cas burst lenght = 4 , ( cas latency = 3 ; t rcd , t rp = 3 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we *bs1 a10 a0-a9,a11 dqm dq hi-z activate command bank 0 read command bank 0 t ck3 rax rax cax *bs0="l" bank2,3=idle ax0 ax1 ax2 bx2 bx3 ax3 bx1 activate command bank 1 read with auto precharge command bank 1 rbx rbx cbx bx0 ay0 ay1 ay2 ay3 read with auot precharge command bank 0 activate command bank 1 high rbx cay rby cby start auto precharge bank 1 start auto precharge bank 0 start auto precharge bank 1 read with auot precharge command bank 1 by0 by1
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 62 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. auto precharge after write burst clk cke cs ras cas burst lenght = 4 , ( cas latency = 2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we *bs1 a10 a0-a9,a11 dqm dq hi-z activate command bank 0 write command bank 0 t ck2 rax rax cax *bs0="l" bank2,3=idle dax0 dax1 dax2 dbx2 dbx3 dax3 dbx1 activate command bank 1 write with auto precharge command bank 1 rbx cbx dbx0 day0 day1 day2 day3 activate command bank 1 high cay rby write with auot precharge command bank 0 raz caz raz cby rby rbx dby0 dby1 dby2 dby3 daz0 daz1 daz2 daz3 t dal# t dal# t dal# activate command bank 0 write with auto precharge command bank 0 write with auot precharge command bank 1 # number of clocks depends on clock cycle and speed sort. see the clock frequency and latency table. bank may be reactivated at the completion of t dal .
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 63 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. burst read and single write operation clk cke cs ras cas burst lenght = 4 , ( cas latency = 2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we *bs1 a10 a0-a9,a11 ldqm dq 0 - dq 7 hi-z activate command bank 0 read command bank 0 t ck2 rav rav cav *bs0="l" bank2,3=idle av0 av1 av2 av3 singal write command bank 0 read command bank 0 rbx daw0 high cay raz caz ay0 ay3 daz0 upper byte is masked singal write command bank 0 rbx caw cax udqm dq 8 - dq 15 ay1 hi-z av0 av1 av2 av3 dax0 ay0 ay3 daz0 ay2 singal write command bank 0 lower byte is masked lower byte is masked ay0
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 64 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. full p age burst read and single write operation clk cke cs ras cas burst lenght = full page , ( cas latency = 3 , t rcd ,t rp = 3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we *bs1 a10 a0-a9,a11 ldqm dq 0 - dq 7 hi-z activate command bank 0 read command bank 0 t ck3 rav rav cav *bs0="l" bank2,3=idle av0 av1 av2 av3 singal write command bank 0 read command bank 0 daw0 dax0 high cax caz ay0 ay3 burst stop command caw udqm dq 8 - dq 15 ay1 hi-z av0 av1 av2 av3 dax0 ay0 ay3 singal write command bank 0 ay0 caw cay daw0 ay1 ay2 ay2 burst stop command
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 65 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. /cs function (only /cs signal needs to be asserted at minimum rate) clk cke cs ras cas at 100mhz burst lenght = 4 , ( cas latency = 3 ; t rcd , t rp = 3 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 we a11(bs) a10 a0-a9 dqm dq hi-z activate command bank a t ck3 ax0 ax1 ax2 day0 ax3 write command bank a precharge command bank a day1 day2 day3 high read command bank a rax rax rax cax cay low t rcd t dpl
nt56v6610c0t nt56v6620c0t 64mb : x8 x16 pc133 / pc100 synchronous dram rev 1.1 june , 2000 66 ?nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. package dimension ( 400 mil; 54 pin; thin small outline package ) millimeter inch symbol min. nom. max. min. nom. max. a 1.20 0.047 a1 0.05 0.10 0.15 0.002 0.004 0.006 a2 0.95 1.00 1.05 0.037 0.039 0.041 b 0.30 0.35 0.45 0.012 0.014 0.018 c 0.12 0.21 0.005 0.008 d 22.22 bsc 0.875 bsc h e 11.56 11.76 11.96 0.460 0.463 0.470 e 10.03 10.16 10.29 0.390 0.400 0.410 e 0.80 bsc 0.031 l 0.40 0.50 0.60 0.016 0.020 0.024 l1 0.80 ref 0.031 ref s 0.71 ref 0.028 ref q 0 - 8 0 - 8 note: 1. dimension d odes not include mold protrusions or gat e burrs. 2. mold protrusion and gate burrs shall exceed 0.15 mm per side. 3. dimension e1 does not include interlead mold protrusions. 4. interlead mold protrusions shall not exceed 0.25 mm per side.

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