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10-bit, 170/200 msps 3.3 v a/d converter AD9411 rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures snr = 60 db @ f in up to 7 0 mh z @ 200 msps en ob of 9.8 @ f in up to 70 mhz @ 2 00 msps (C 0.5 dbfs) sfdr = 80 db c @ f in up to 70 m hz @ 20 0 msps (C0.5 dbfs) excellent linea r ity: dnl = 0.15 lsb (typical) i n l = 0.25 lsb (typical) lvds o u tput l e vels 700 mh z fu ll-p o wer analog bandwidth on-chip reference and track-a nd-hold power dissipati o n = 1.25 w typical @ 20 0 ms ps 1.5 v input volt age range 3.3 v supply op eration output data format option clock du ty cy cle stabilizer pin co mpatible to lvds mo de ad94 30 a pplic a t io ns wireless and w i red bro a dban d co mmunicatio n s cable re verse path communications test eq uipm ent radar an d sate llite s u bsystem s func ti onal bl oc k di a g ram AD9411 sense vref vin+ vin? clk+ clk? s1 s5 dco+ dco? scalable reference lvds outputs data, overrange in lvds track and hold lvds timing clock management adc 10-bit pipeline core 10 / agnd drgnd drvdd avdd 04530-0-001 fi g u r e 1 . power amplifie r linearization gener a l de scription the AD9411 is a 10-b i t m o n o li t h ic s a m p l i n g a n alog-t o-dig i t a l co n v er t e r o p timize d f o r high p e r f o r ma n c e , lo w p o w e r , an d ease o f us e . the p r o d uc t o p er a t es u p t o a 200 ms p s co n v ersio n r a te a nd is o p t i mi ze d fo r o u tst a n d ing d y na mic p e r f o r ma n c e in wi deb a n d ca r r i e r a n d b r o a d b and sy stem s. al l ne cess a r y f u n c t i o n s, i n cl u d in g t r ack-and- h o ld (t /h) an d r e fer e n c e, a r e in cl ude d o n t h e c h i p t o p r o v ide a co m p lete con v ersio n s o l u tion. the ad c r e q u i r es a 3.3 v p o wer s u p p l y a nd a dif f er en t i al s a m p le clo c k for f u l l p e r f o r ma nce o p era t ion. th e dig i t a l o u t p uts a r e l v ds co m p a t ib le an d su p p o r t b o t h tw os c o m p lemen t and o f fs et b i na r y f o rma t . a da t a c l o c k o u t p u t is a v a i l a b l e t o eas e da ta ca p t ur e . f a b r ica t ed on an advan c ed bicm os p r o c es s, t h e AD9411 is a v a i la b l e in a 100-le ad sur f ace-m o un t plast i c p a cka g e (e - p a d t q fp -100) s p e c if ied o v er t h e ind u s t r i al t e m p era t ur e ra n g e (C40c t o +85c). pr oduc t highligh t s 1. hi g h p e r f o r m a n c e . m a in ta in s 60 db s n r @ 200 m s ps wi t h a 70 mh z in p u t. 2. lo w po w e r . c o n s u m es onl y 1.25 w @ 200 ms ps. 3. ea s e o f u s e . l v ds o u t p u t d a ta a n d o u t p u t c l oc k si gn al allo w i n t e rface to c u r r e n t f p g a te ch nol o g y . t h e on- c h i p re fe re nc e and s a m p le-and- h o l d f u n c t i o n p r o v ide f l exi b i l i t y in sys t em desig n . u s e o f a sin g le 3.3 v su p p l y sim p lif i es sys t em p o we r su p p ly d e s i g n . 4. ou t - o f - r a n g e (o r ) . the o r o u t p u t b i t i n dica t e s w h en t h e i n p u t sig n al is b e y o nd t h e s e l e c t e d i n put r a ng e.
AD9411 rev. a | page 2 of 28 table of contents dc specifications ............................................................................. 3 ac specifications .............................................................................. 4 digital specifications ........................................................................ 5 switching specifications .................................................................. 6 explanation of test levels ........................................................... 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 ter mi nolo g y .................................................................................... 10 equivalent circuits ......................................................................... 12 typical performance characteristics ........................................... 13 application notes ........................................................................... 18 clock input .................................................................................. 18 analog input ............................................................................... 18 lvds outputs ............................................................................. 19 clock outputs (dco+, dcoC) ............................................... 19 volt age reference ....................................................................... 19 noise power ratio testing (npr) ............................................ 19 evaluation board ............................................................................ 21 power connector ........................................................................ 21 analog inputs ............................................................................. 21 gain .............................................................................................. 21 clock ............................................................................................ 21 volt age reference ....................................................................... 21 data format select ..................................................................... 21 data outputs ............................................................................... 21 clock xtal ................................................................................. 21 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 7/04data sheet changed from rev. 0 to rev. a added 200 msps grade ....................................................universal updated outline dimensions ....................................................... 27 changes to ordering guide .......................................................... 27 rev 0 : initial version
AD9411 rev. a | page 3 of 28 dc specifications avdd = 3.3 v, drvdd = 3.3 v, t min = C40c, t max = +85c, f in = C0.5 dbfs, internal reference, full scale = 1.536 v, unless otherwise noted. table 1. AD9411-170 AD9411-200 parameter temp test level min typ max min typ max unit resolution 12 12 bits accuracy no missing codes full vi guaranteed guaranteed offset error 25c i C3 +3 C3 +3 mv gain error 25c i C5 +5 C5 +5 % fs differential nonlinearity (dnl) 25c i C0.5 0.15 +0.5 C0.5 0.15 +0.5 lsb full vi C0.6 0.25 +0.6 C0.6 0.25 +0.6 lsb integral nonlinearity (inl) 25c i C0.8 0.5 +0.8 C0.8 0.5 +0.8 lsb full vi C1 0.5 +1 C1 0.5 +1 lsb temperature drift offset error full v 58 58 v/c gain error full v 0.02 0.02 %/c reference out (vref) full v +0.12/ C0.24 +0.12/ C0.24 mv/c reference reference out (vref) 25c i 1.15 1.235 1.3 1.15 1.235 1.3 v output current 1 25c iv 3.0 3.0 ma i vref input current 2 25c i 20 20 ma i sense input current 2 25c i 1.6 5.0 1.6 5.0 ma analog inputs (vin+, vinC) 3 differential input voltage range (s5 = gnd) full v 1.536 1.536 v differential input voltage range (s5 = avdd) full v 0.766 0.766 v input common-mode voltage full vi 2.65 2.8 2.9 2.65 2.8 2.9 v input resistance full vi 2.2 3 3.8 2.2 3 3.8 k? input capacitance 25c v 5 5 pf power supply (lvds mode) avdd full iv 3.1 3.3 3.6 3.2 3.3 3.6 v drvdd full iv 3.0 3.3 3.6 3.0 3.3 3.6 v supply currents i analog (avdd = 3.3 v) 4 full vi 335 372 385 425 ma i digital (drvdd = 3.3 v) 4 full vi 49 57 49 57 ma power dissipation 4 full vi 1.27 1.42 1.43 1.59 w power supply rejection 25c v C7.5 C7.5 mv/v 1 internal reference mode; sense = floats. 2 external reference mode; sense = drvdd; vref driven by external 1.23 v reference. 3 s5 (pin 1) = gnd. see the analog input section. s5 = gnd in all dc, ac tests, unless otherwise specified 4 i avdd and i drvdd are measured with an analog input of 10.3 mhz, C0.5 dbfs, sine wave, rated clock rate, and in lvds output mode. see the and sect ions for i typical performance characteristics applicat ion notes drvdd . power consumption is measured with a dc inpu t at rated clock rate in lvds output mode.
AD9411 rev. a | page 4 of 28 ac specifications 1 avdd = 3.3 v, drvdd = 3.3 v, t min = C40c, t max = +85c, f in = C0.5 dbfs, internal reference, full scale = 1.536 v, unless otherwise noted. table 2. AD9411-170 AD9411-200 parameter temp test level min typ max min typ max unit snr analog input @ C0.5 dbfs 10 mhz 25c i 59 60.2 59 60.2 db 70 mhz 25c i 59 60.1 59 60.1 db 100 mhz 25c v 60 60 db 240 mhz 25c v 59.1 59.1 db sinad analog input @ C0.5 dbfs 10 mhz 25c i 58.5 60 58.5 60 db 70 mhz 25c i 58.5 60 58.5 60 db 100 mhz 25c v 59.5 59.5 db 240 mhz 25c v 57.5 57.5 db effective number of bits (enob) 10 mhz 25c i 9.5 9.8 9.5 9.8 bits 70 mhz 25c i 9.5 9.8 9.5 9.8 bits 100 mhz 25c v 9.7 9.7 bits 240 mhz 25c v 9.3 9.3 bits worst harmonic (second or third) analog input @ C0.5 dbfs 10 mhz 10 mhz 25c i C80 C73 C80 C70 dbc 70 mhz 25c i C80 C73 C80 C70 dbc 100 mhz 25c v ?74 ?74 dbc 240 mhz 25c v ?69 ?69 dbc worst harmonic (fourth or higher) analog input @ C0.5 dbfs 10 mhz 10 mhz 25c i C82 C75 C82 C75 dbc 70 mhz 25c i C82 C75 C82 C75 dbc 100 mhz 25c v ?76 ?76 dbc 240 mhz 25c v ?70 ?70 dbc two-tone imd 2 f1, f2 @ C7 dbfs 25c v 70 70 dbc analog input bandwidth 25c v 700 700 mhz 1 all ac specifications tested by driving clk+ and clkC differentially. 2 f1 = 30.5 mhz, f2 = 31 mhz.
AD9411 rev. a | page 5 of 28 digital specifications avdd = 3.3 v, drvdd = 3.3 v, t min = C40c, t max = +85c, unless otherwise noted. table 3. AD9411-170 AD9411-200 parameter temp test level min typ max min typ max unit clock inputs (clk+, clkC) 1 differential input voltage 2 full iv 0.2 0.2 v common-mode voltage 3 full vi 1.375 1.5 1.575 1.375 1.5 1.575 v input resistance full vi 3.2 5.5 6.5 3.2 5.5 6.5 k? input capacitance 25c v 4 4 pf logic inputs (s1, s2, s4, s5) logic 1 voltage full iv 2.0 2.0 v logic 0 voltage full iv 0.8 0.8 v logic 1 input current full vi 190 190 a logic 0 input current full vi 10 10 a input resistance 25c v 30 30 k? input capacitance 25c v 4 4 pf lvds logic outputs 4 v od differential output voltage full vi 247 454 247 454 mv v os output offset voltage full vi 1.125 1.375 1.125 1.375 v output coding twos complement or binary twos complement or binary 1 see the section. equivalent circuits 2 all ac specifications tested by driving clk+ and clkC differentially, |(clk+) C (clkC)| > 200 mv. 3 clock inputs common mode can be externally set, such that 0.9 v < clk < 2.6 v. 4 lvds r term = 100 ?, lvds output current set resistor (r set ) = 3.74 k? (1% tolerance).
AD9411 r e v. a | pa ge 6 o f 2 8 switching specifica tions a v d d = 3.3 v , d r vd d = 3.3 v , t min = C40c, t max = + 8 5 c , u n l e ss ot he r w i s e no te d. table 4. ad94 11-1 7 0 a d 9 4 11-2 0 0 parameter ( c onditions) temp test lev e l min typ max min typ max unit maximum conv ersion rate 1 f u l l v i 1 7 0 200 msps minimum conversion rate 1 f u l l v 40 4 0 m s p s clk+ pulse width high (t eh ) 1 f u l l i v 2 1 2 . 5 2 1 2 . 5 n s clk+ pulse width low (t el ) 1 f u l l i v 2 1 2 . 5 2 1 2 . 5 n s output (l vds mode) val i d time (t v ) f u l l v i 2 . 0 2 . 0 n s propagation de l a y (t pd ) f u l l v i 3 . 2 4 . 3 3 . 2 4 . 3 n s rise time (t r ) (2 0% to 80%) 25c v 0 . 5 0 . 5 n s fall t ime ( t f ) (20 % to 80%) 25c v 0 . 5 0 . 5 n s dco propagatio n delay (t cpd ) f u l l v i 1 . 8 2 . 7 3 . 8 1 . 8 2 . 7 3 . 8 n s data to dco skew (t pd Ct cpd ) f u l l i v 0 . 2 0 . 5 0 . 8 0 . 2 0 . 5 0 . 8 n s l a t e n c y f u l l i v 1 4 1 4 c y c l e s aperture delay ( t a ) 25c v 1 . 2 1 . 2 n s aperture uncertainty (j itter, t j ) 25c v 0 . 2 5 0 . 2 5 ps rms out-of-range recovery time 25c v 1 1 c y c l e s 1 a l l a c sp eci f i c a t i o n s t e st ed by dri v i n g clk+ a n d clkC di ff eren t i a lly. expl ana t ion of test levels i. 100% pr oduc ti on t e sted . ii. 100% pr oduc ti on t e sted at 2 5 c and sample t e st e d a t specif ied t e mpera t ures . iii. sample test ed only . iv. p a rame t e r is gu aranteed by d e sig n and chara c t e r i za tion t e sti n g . v. p a r a met e r is a t y pical value only . vi. 100% pr oduc ti on t e sted at 2 5 c; gu arant eed b y d e sig n and char ac t e r i za tion t e stin g f o r in dustr i al t e mp era t u r e range; 10 0% pr oduc tion t e sted a t tempera t ur e ex t r emes f o r militar y devi ces . clk+ a in t eh t el t pd t cpd 1/f s dco+ dco n 1 n 14 n 13 n 14 ccles n+1 n+1 n clk data out 04530-0-002 f i gure 2. l v ds tim i ng d i agr a m
AD9411 r e v. a | pa ge 7 o f 2 8 absolute maximum ra tings table 5. parameter rating avdd, dr vdd 4 v analog inputs C0.5 v to av dd +0.5 v digital inputs C0.5 v to dr vd d +0.5 v refin inputs C0.5 v to av dd +0.5 v digital output c u rrent 20 ma operating tem p erature C55oc to +125c storage temperature C65oc to +150c maximum junction temperature 150c maximum case temperature 150c ja 1 25c/w, 32c/w 1 typical ja = 32 c/ w (h ea t slug n o t so lde red ) ; t y pi ca l ja = 25c/w (h ea t slu g sol d er ed ) for m u lt i l a y er boa r d i n st i l l a i r wi t h so li d g r oun d pla n e. s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly a n d f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io n s o u tside o f t h os e i n dic a t e d in t h e op era t ion s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te maxim u m ra t i ngs co ndi tion s fo r ext e n d e d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge without detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
AD9411 r e v. a | pa ge 8 o f 2 8 pin conf igura t ion and fu nction descriptions s5 dnc agnd agnd agnd avdd avdd avdd agnd agnd agnd avdd avdd agnd clk+ clk? agnd avdd avdd agnd dnc dnc dnc dnc dnc drvdd drgnd dnc dnc agnd avdd avdd agnd agnd avdd avdd agnd agnd agnd avdd avdd avdd agnd agnd or+ or? dvrdd drgnd d9+ d9? d8+ d8? d7+ d7? avdd s1 lvdsbias avdd agnd sense vref agnd agnd avdd avdd agnd agnd avdd avdd agnd vin+ vin? agnd avdd agnd drvdd drgnd d6+ d6? d5+ d5? d4+ d4? drgnd d3+ d3? dco+ dco? drvdd drgnd d2+ d2? d1+ d1? d0+ d0? drvdd drgnd dnc dnc AD9411 top view (not to scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 04530-0-003 fi g u r e 3 . t q f p / e p p i n o u t
AD9411 rev. a | page 9 of 28 table 6. pin function descriptions pin no. mnemonic function 1 s5 full-scale adjust pin. avdd sets fs = 0.768 v p-p differential; gnd sets fs = 1.536 v p-p differential. 2, 42C46,49C52 dnc do not connect. 3, 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 32, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100 agnd analog ground. agnd and drgnd shou ld be tied together to a common ground plane. 5, 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34, 39, 40, 88, 89, 90, 94, 95, 98, 99 avdd 3.3 v analog supply. 6 s1 data format select. gnd = binary; avdd = twos complement. 7 lvdsbias set pin for lvds output current. place a 3.74 k? resistor terminated to ground. 10 sense reference mode select pin. float for internal reference operation. 11 vref 1.235 v reference input/outp ut. function depends on sense. 21 vin+ analog input. true. 22 vinC analog input. complement. 36 clk+ clock input. true (lvpecl levels). 37 clkC clock input. complement (lvpecl levels). 47, 54, 62, 75, 83 drvdd 3.3 v digital output supply (3.0 v to 3.6 v). 48, 53, 61, 67, 74, 82 drgnd digital output ground. agnd and drgn d should be tied together to a common ground plane. 56 d0+ d0 true output bit. 57 d1C d1 complement output bit. 58 d1+ d1 true output bit. 59 d2C d2 complement output bit. 60 d2+ d2 true output bit. 63 dcoC data clock output. complement. 64 dco+ data clock output. true. 65 d3C d3 complement output bit. 66 d3+ d3 true output bit. 68 d4C d4 complement output bit. 69 d4+ d4 true output bit. 70 d5C d5 complement output bit. 71 d5+ d5 true output bit. 72 d6C d6 complement output bit. 73 d6+ d6 true output bit. 76 d7C d7 complement output bit. 77 d7+ d7 true output bit. 78 d8C d8 complement output bit. 79 d8+ d8 true output bit. 80 d9C d9 complement output bit. 81 d9+ d9 true output bit. 84 orC overrange complement output bit. 85 or+ overrange true output bit.
AD9411 rev. a | page 10 of 28 terminology ana l og b a n d w i d t h t h e a n al og in p u t f r eq ue n c y a t wh i c h t h e s p ect r al po w e r o f th e f u ndam e n t a l f r e q uen c y (as det e r m ine d b y t h e f f t a n a l y s is) is r e d u ced b y 3 db . ap e r t u r e d e l a y the de l a y b e t w e e n t h e 50 % p o i n t o f t h e r i sin g e d g e o f t h e clo c k co mman d and t h e in st a n t a t w h ich t h e a n a l og i n p u t is s a m p le d. ap e r t u r e un c e r t a i n t y ( j i t t e r ) the s a m p le -t o-s a m p le va r i a t io n in a p er t u r e dela y . cr o s s t al k c o u p lin g o n t o o n e c h a n n e l bein g d r i v en b y a l o w lev e l (C 40 db fs ) sig n a l w h e n t h e ad jace n t in ter f er in g cha n ne l is dr i v en b y a f u l l - scale si gnal . d i ff e r e n t i al a n alo g i n p u t r e s i s t a n c e , d i ff e r e n t i al a n alo g input c a p a c i t a n c e , a n d d i f f erent i a l a n a l o g input imp e d a n c e the r e a l and co m p lex im p e dances m e a s ur e d a t e a ch a n a l o g in p u t p o r t . t h e re s i st anc e is me asu r e d st a t i c a l ly and t h e ca p a ci t a n c e and dif f er en t i al i n pu t im p e dan c es ar e m e as ur e d wi t h a n e tw o r k a n a l y z er . d i f f erent i a l a n a l o g input v o lt a g e r a ng e the p e ak- t o-p e ak dif f er en t i a l vol t a g e t h a t m u st b e a p plie d t o t h e co n v er t e r t o g e n e ra t e a f u l l - s cale r e sp o n s e . p e ak dif f er en t i a l v o l t a g e is co m p u t e d b y obs e r v i n g t h e v o l t a g e o n a si n g le p i n a nd s u b t rac t in g th e v o l t a g e f r o m t h e o t h e r p i n, which is 180 o u t o f p h a s e . p e ak -t o- pe ak d i f f er en tial i s co m p u t ed b y r o ta tin g th e in p u t s p h as e 180 a nd a g a i n tak i n g t h e p e a k m e as ur em en t. the dif f er en ce i s t h e n co m p u t e d b e t w e e n b o t h p e ak me a s u r e m e n t s . d i f f erenti a l n o n l i n e a r i ty t h e devia t i o n o f a n y cod e wi d t h f r o m a n i d eal 1 l s b s t ep . ef f e c t ive n u mb er o f b i ts (eno b) c a lc u l a t e d f r o m t h e m e as ur ed s n r bas e d on t h e e q u a tio n 02 . 6 db 76 . 1 ? = measured snr enob c l o c k pu ls e w i d t h/d u ty cy cl e pu ls e wi d t h hig h is t h e m i ni m u m am o u n t o f t i m e t h e clo c k p u ls e sho u l d b e lef t i n t h e l o g i c 1 st a t e t o achi e ve r a te d pe rf o r m a n c e ; pu ls e wi d t h lo w i s t h e mini m u m t i m e t h e clo c k p u ls e sh o u ld be lef t in t h e l o w s t a t e . ref e r t o t h e timin g im pli c a t io n s o f cha n g i n g t en ch in t h e a p p l ica t i o n n o t e s, cloc k i n p u t s e c t io n. a t a g i v e n clo c k r a t e , t h e s e sp e c if ica t io n s def i n e an a c c e pt abl e c l o c k d u t y c y cl e. f u l l - s c a l e input p o wer e x p r ess e d in dbm. c o m p ute d u s in g t h e fol l o w i n g e q u a t i on: ? ? ? ? ? ? ? ? ? ? ? ? = 001 . 0 log 10 2 input rms fullscale fullscale z v power ga in e r r o r the dif f er en ce b e tw e e n t h e m e as ur e d an d ide a l f u l l -s cale in put v o l t a g e ra n g e o f t h e ad c. ha r m on i c d i s t or t i on , s e c o n d the ra t i o o f t h e r m s sig n al a m pl i t u d e t o t h e r m s val u e o f t h e s e c o n d h a rm o n i c c o m p o n e n t , r e p o rt e d i n d b c . ha r m on i c d i s t or t i on , t h i r d the ra t i o o f t h e r m s sig n al a m pl i t u d e t o t h e r m s val u e o f t h e t h ir d ha r m o n ic co m p on e n t, r e p o r t e d in db c. inte g r a l n o n l i n e a r i t y the de v i a t ion o f t h e t r a n sfer f u n c t i on f r o m a r e fer e n c e line m e as ur ed in f r ac tio n s o f 1 ls b usin g a b est s t r a ig h t lin e det e r m i n e d b y a le ast s q ua r e c u r v e f i t. minim u m c o n v ersi o n r a t e the cl o c k ra te a t w h ich t h e snr o f t h e lo w e st a n alog sig n al f r e q u e nc y d r op s b y no more t h an 3 d b b e l o w t h e g u ar an t e e d limi t. ma x i mu m c o nve r si on r a te the clo c k ra te a t w h ich p a ra m e t r ic t e st i n g is p e r f o r m e d . ou t p u t p r o p aga t io n de la y the d e l a y b e t w e e n a dif f er en t i a l cr o s sin g o f clk+ a nd cl kC a n d t h e tim e w h en all o u t p u t da ta b i t s a r e wi thi n vali d logi c l e vel s .
AD9411 rev. a | page 11 of 28 n o is e (f o r an y r a n g e w i thin t h e ad c) cal c ula t e d a s f o ll o w s : ? ? ? ? ? ? ? ? = 10 10 001 . 0 dbfs dbc dbm noise signal snr fs z v w h er e z is t h e i n p u t im p e dan c e , fs is t h e f u l l s c ale o f t h e de vic e fo r t h e f r e q uen c y in q u es t i on, snr is t h e va l u e o f t h e p a r t ic u l a r i n pu t l e vel , and si g n al i s th e s i gn a l l e v e l w i th i n th e a d c r e po rt ed in db b e lo w f u l l s c ale . this v a l u e i n cl udes b o t h t h er ma l a nd q u an t i za t i on n o is e. p o wer s u pply rej e c t i o n r a ti o ( p s rr) the ra t i o o f a cha n g e i n i n p u t o f fs et v o l t a g e t o a cha n g e i n p o we r su p p ly v o l t age. si g n a l - t o - n o i s e - a n d - d i s t or t i on ( s i n a d ) the ra t i o o f t h e r m s sig n al a m pl i t u d e (s e t 1 db b e lo w f u l l s c ale) t o t h e r m s val u e o f t h e s u m o f al l o t h e r sp e c t r al co m p on e n ts, in cl ud in g ha r m o n ics b u t excl udin g dc. s i g n a l -t o-n o is e r a ti o (w itho u t h a rmo n i c s) the ra t i o o f t h e r m s sig n al a m pl i t u d e (s e t a t 1 db b e lo w f u l l s c ale) t o t h e r m s val u e o f t h e s u m o f al l o t h e r sp e c t r al co m p o - n e n t s , e x c l u d i n g t h e fi r s t fi v e h a r m o n i c s a n d d c . s p uri o us-f r e e d y na mi c r a n g e (s fd r) the ra t i o o f t h e r m s sig n al a m pl i t u d e t o t h e r m s val u e o f t h e p e ak s p ur io us sp ec tral co m p o n en t. th e p e ak sp ur io us co m p o - n e n t ma y o r m a y n o t be a h a r m o n i c . m a y be r e po r t ed in d b c (i .e ., deg r ades as sig n al leve l is l o w e r e d) o r db f s (al w a y s r e la t e d bac k t o con v er ter f u l l s c ale). t w o-t o ne i n t e rmo d u l a t i o n d i st o r ti o n rej e c t i o n the r a t i o of t h e r m s v a l u e o f e i t h er i n pu t ton e to t h e r m s v a l u e o f t h e w o rst t h ird - o r der in ter m o d u l a t ion p r o d u c t, r e p o r t e d i n db c . tw o - t o n e s f d r the ra t i o o f t h e r m s val u e o f ei t h er in p u t t o n e to t h e r m s v a l u e o f th e p e ak s p ur io us co m p on en t. the p e ak sp ur io us co m p o n en t m a y o r m a y n o t be a n imd p r o d uct. m a y be r e po r t ed in d b c (i .e ., deg r ades as sig n al le ve l is l o w e r e d) o r in db fs (al w a y s rel a te d b a ck to c o n v e r te r f u l l s c a l e ) . w o rst o t h e r s p ur the ra t i o o f t h e r m s sig n al a m pl i t u d e t o t h e r m s val u e o f t h e w o rst sp ur io us co m p on e n t (excl u ding t h e s e cond an d t h ir d ha r m o n ics) r e p o r t e d in db c. tr a n s i e n t r e s p o n s e t i m e the t i m e i t t a k e s fo r t h e ad c to r e acq u ir e t h e a n alog in p u t af te r a t r ans i e n t f r om 1 0 % ab o v e n e g a t i v e f u l l s c a l e to 1 0 % b e l o w p o s i t i ve f u l l s c a l e. ou t- o f - r a n ge r e co v e r y t i me the t i m e i t t a k e s fo r t h e ad c to r e acq u ir e t h e a n alog in p u t a f t e r a t r a n sien t f r o m 10% a b o v e p o si t i v e f u l l s c ale t o 10% ab o v e n e g a ti v e f u l l s c a l e , o r f r o m 10% b e lo w n e g a ti v e f u l l s c ale t o 10 % b e l o w p o s i t i ve f u l l s c a l e.
AD9411 rev. a | page 12 of 28 equiv a lent ci rcuits 04530-0-004 12k ? 150 ? 150 ? 12k ? 10k ? 10k ? clk+ avdd clk? fi g u r e 4 . c l o c k i n p u t s avdd 3.5k ? 3.5k ? 20k ? 20k ? vin+ vin? 04530-0-005 fi g u r e 5 . a n a l o g i n p u t s vdd 30k ? s1,s5 04530-0-006 f i g u r e 6 . s1 to s5 i n p u ts 04530-0-007 vref k a1 disable a1 sense vdd 200 ? 1v 0.1 f full scale 1k ? f i gur e 7 . vref , sense i/ o 04530-0-008 v+ v+ dx+ drvdd dx? v? v? f i g u r e 8 . da ta ou tp u t s
AD9411 rev. a | page 13 of 28 typical perf orm ance cha r acte ristics ? 120 ? 100 ?80 ?90 ? 110 ?60 ?70 db ?40 ?50 ?20 ?30 0 ?10 40 30 10 20 0 5 06 07 08 0 mhz 04530-0-009 snr = 60.1db sinad = 59.9db h2 = ? 91.3dbc h3 = ? 75.2dbc sfdr = 75.3dbc f i gu r e 9 . f f t : fs = 17 0 ms p s , ai n = 10 .3 mh z @ ? 0 .5 d b fs 40 30 10 20 0 5 06 0 7 08 0 ? 120 ? 100 ?80 ?90 ? 110 ?60 ?70 db ?40 ?50 ?20 ?30 0 ?10 mhz 04530-0-010 snr = 59.8db sinad = 59.8db h2 = ? 91.9dbc h3 = ? 80.6dbc sfdr = 73.2dbc f i g u re 10. fft : f s = 17 0 m s ps, a i n = 6 5 m h z @ C 0 . 5 dbfs 40 30 10 2 0 0 5 06 07 08 0 ? 120 ? 100 ?80 ?90 ? 110 ?60 ?70 db ?40 ?50 ?20 ?30 0 ?10 mhz 04530-0-011 snr = 59.2db sinad = 59.1db h2 = ? 70.1dbc h3 = ? 87.0dbc sfdr = 69.8dbc f i g u re 11. fft : f s = 17 0 m s ps, a i n = 1 0 . 3, m h z @ C 0 .5 dbf s , single-ended i n put , 0. 76 v input rang e 04530-a - 001 mhz 100 02 0 10 40 30 60 50 80 90 70 db 0 ?20 ?10 ?40 ?30 ?60 ?50 ?80 ?70 ?100 ?90 ?110 ?120 snr = 59.7db sinad = 59.5db h2 = ? 83.6dbc h3 = ? 72.6dbc sfdr = 72.5dbc f i g u re 12. fft : f s = 20 0 m s ps, a i n = 1 0 . 3 m h z @ ?0 .5 d b f s 04530-a - 002 mhz 100 02 0 3 0 10 40 50 60 70 80 90 db 0 ?20 ?10 ?40 ?30 ?60 ?50 ?80 ?70 ?100 ?90 ?120 ?110 snr = 59.5db sinad = 59.4db h2 = ? 82.5dbc h3 = ? 72.8dbc sfdr = 72.7dbc f i g u re 13. fft : f s = 20 0 m s ps, a i n = 6 5 m h z @ ? 0 .5 dbfs 04530-a - 003 mhz 100 02 0 10 40 30 60 50 80 90 70 db 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?120 ?110 snr = 50.6db sinad = 43.8db h2 = ? 44.8dbc h3 = ? 67.4dbc sfdr = 43.6dbc f i g u re 14. fft : f s = 20 0 m s ps, a i n = 7 0 m h z @ ? 0 .5 dbfs, single -ended d r ive , 1. 5 v input rang e
AD9411 rev. a | page 14 of 28 40 50 60 70 80 90 100 db 200 15 0 50 1 0 0 0 250 300 3 5 0 400 a in (mhz) 04530-0-015 third sfdr second f i gur e 1 5 . ha rm onic di stor ti on (s e c ond a n d thir d) a n d sfdr vs . ain f r equ e nc y @ 17 0 m s ps 04530-a - 006 (mhz) 400 0 5 0 100 150 200 250 300 350 (db) 100 90 80 70 60 50 40 third second sfdr f i gur e 1 6 . ha rm onic di stor ti on (s e c ond a n d thir d) a n d sfdr vs . ain f r equ e nc y @ 20 0 m s ps 04530-a - 007 (mhz) 450 0 5 0 100 150 200 250 300 350 400 (db) 61 59 57 55 53 51 49 47 45 snr_200 snr_170 sinad_200 sinad_170 f i gur e 1 7 . snr a n d sinad vs . ain f r e q ue nc y ; fs = 17 0/ 200 msp s , a i n @ C 0 . 5 dbfs f u ll s c al e = 1. 5 36 v ? 120 ? 100 ?80 ?90 ? 110 ?60 ?70 db ?40 ?50 ?20 ?30 0 ?10 40 30 10 20 0 5 06 07 08 0 mhz 04530-0-019 sfdr = 71.5dbc f i g u re 18. t w o - t o n e int e r m odu l at io n d i s t o r t i on (30. 5 m h z and 31 .0 m h z; f s = 1 70 m s p s ) 04530-a - 004 (mhz) 100 0 2 04 0 6 08 0 9 0 10 30 50 70 (db) 0 ?20 ?40 ?60 ?80 ?100 ?120 sfdr = 78.8dbc f i g u re 19. t w o - t o n e int e r m odu l at io n d i s t o r t i on (69. 3 m h z and 70 .3 m h z; f s = 2 00 m s p s ) 04530-a - 008 (msps) 250 0 5 0 100 150 200 (db) 80 70 75 65 55 60 50 45 40 sfdr_170 sfdr_200 sinad_170 sinad_200 f i gure 20. sinad and sfdr vs. clock rate ( a in = 1 0 . 3 m h z @ C 0 .5 dbfs) 17 0/2 00 gr a d e
AD9411 rev. a | page 15 of 28 0 10 20 30 40 50 60 70 80 90 i drv dd outp ut s u p p l y curre nt (ma) 0 50 100 150 200 250 300 350 400 450 i av dd analog s u p p l y curre nt (ma) 100 120 140 160 180 200 220 240 encode (msps) 04530-2-023 output supply current analog supply current f i g u re 21. ia v dd a n d idr v dd v s . clo c k rat e , 17 0 m s ps g r ad e , cl oa d = 5 pf (a in = 10. 3 m h z @ C0. 5 dbf s ) 04530-a-009 sample rate (msps) 240 100 120 140 180 160 200 220 i drv dd o u tp ut s u p p l y curre nt (m a) 0 90 80 70 60 50 40 30 20 10 i av dd analo g s u p p l y curre nt (m a) 450 400 350 300 250 200 150 100 50 0 output supply current analog supply current f i gu r e 22. ia vdd and idr v dd vs. cloc k rate , 200 ms ps g r ad e , cl o a d = 5 pf (a in = 10. 3 m h z @ C0. 5 dbf s ) 55 57 59 61 63 65 67 69 71 73 75 db 20 30 40 50 60 70 80 90 encode positive duty cycle (%) 04530-0-025 sfdr snr sinad f i gure 23. sinad and sfdr vs. clock p u lse w i dth high (a in = 10. 3 m h z @ C0. 5 dbf s , 17 0 m s p s ) 04530-a - 010 sample clock positive duty cycle 80 20 30 40 50 60 70 (db) 80 75 70 65 60 55 50 sfdr snr sinad f i gure 24. sinad and sfdr vs. clock p u lse w i dth high (a in = 10. 3 m h z @ C0. 5 dbf s , 20 0 m s p s ) 04530-a - 016 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 v re f (v ) 4 3 12 05 6 i load (ma) 7 8 r o = 13 ? typ f i gure 25. vr e f out v s . il oa d (both s p eed g r ad es) 04530-a - 011 v ref (v) 1.5 0.5 0.7 0.9 1.1 1.3 (db) 80 75 70 65 60 55 50 sfdr sinad f i gure 26. sin a d , sf dr v s . vre f in e x te rna l refe r e n c e m o d e (a in = 70 m h z @ C 0 .5 dbfs, 20 0 m s ps )
AD9411 rev. a | page 16 of 28 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 gain e rror (%) 1.0 1.5 2.0 ? 5 0 ? 30 ?10 1 0 3 0 5 0 7 0 9 0 temperature ( c) 04530-0-028 % gain error using ext ref f i g u re 27. f u ll- s c al e g a in e r r o r v s . t e mpe r at u r e (a in = 10. 3 m h z @ C0. 5 dbf s , 17 0/ 20 0 m s ps) 04530-a - 012 temperature (c) 80 ? 4 0 ? 2 0 0 2 04 06 0 (db) 60 59 58 57 56 55 avdd = 3.0v avdd = 3.15v avdd = 3.3v avdd = 3.6v f i gure 28. sinad vs. t e mp e r atu r e and a v dd (a in = 10. 3 m h z @ C0. 5 dbf s , 20 0 m s p s ) 04530-0-029 1.225 1.230 1.235 1.240 1.245 1.250 v re fout (v ) 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 avdd (v) f i g u re 29. v r e f o u t p ut v o lt ag e v s . a v dd (bot h spe e d gr ades ) 50 55 60 65 70 75 db 80 85 90 ?50 ? 30 ?10 1 0 3 0 5 0 7 0 9 0 temperature (c) 04530-0-030 sfdr snr sinad f i gure 30. snr, si n a d , and sfdr vs. t e mper atur e (a in = 10. 3 m h z @ C0. 5 dbf s , 17 0 m s p s ) ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 lsb 0.50 0.75 1.00 0 100 200 300 400 500 600 700 800 900 1000 code 04530-0-032 f i g u re 31. t y pic a l i n l pl ot (a in = 10. 3 m h z @ C0. 5 dbf s , 17 0/ 20 0 m s ps) ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 lsb 0 100 200 300 400 500 600 700 800 900 1000 code 04530-0-033 f i g u re 32. t y pic a l d n l pl ot (a in = 1 0 .3 m h z @ C 0 .5 dbfs) 17 0/ 20 0 m s ps
AD9411 rev. a | page 17 of 28 0 10 30 70 90 110 50 20 60 80 100 40 db ?90 ? 80 ?70 ? 60 ?50 ? 40 ?30 ? 20 ? 1 0 0 analog input level (dbfs) 04530-0-034 sfdr ?dbfs sfdr ?dbc 80db reference line f i gure 33. sfdr vs. ain input l e vel 10. 3 mh z, ain @ 170 msps 04530-a - 013 analog input level (dbfs) 0 ?70 ? 60 ?50 ? 40 ? 3 0 ? 20 ?10 db 90 80 70 60 50 40 30 20 10 0 70db reference line sfdr ? dbc sfdr ?dbfs f i gur e 3 4 . sfdr vs . ain input l e v e l 70 mhz , ain @ 200 msp s ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 noise level (db) 04530- 0- 035 mhz 10 02 0 3 0 4 0 npr = 51.2db encode = 170msps notch @ 18.15mhz f i g u re 35. no is e p o wer r a t i o plot ( 1 7 0 m s ps g r ad e) 04530-a - 005 mhz 40 0 5 10 15 20 25 30 35 db 0 ?20 ?40 ?60 ?80 ?100 ?120 npr = 51 db clk = 200msps notch at 18.5mhz f i g u re 36. no is e p o wer r a t i o plot ( 2 0 0 m s ps g r ad e) ns 2.5 3.0 3.5 4.0 4.5 04530-0-036 ?40 ? 20 0 2 0 4 0 6 0 8 0 100 temperature ( c) t pd t cpd f i g u re 37. p r opag a t ion d e l a y v s . t e mper at u r e ( b ot h s p ee d gr ad es ) 0 100 200 300 400 500 600 700 800 900 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 v dif (mv ) v os (v ) 04530-0-037 02 4 6 8 1 0 1 2 1 4 rset (k ?) v os v od f i gure 38. l v ds o u tput s w ing , com m o n-mod e v o ltag e v s . rse t , p l aced at l v dsbia s (bot h speed g r ad e s )
AD9411 rev. a | page 18 of 28 appli c a t ion notes the AD9411 a r c h i t ec t u r e is o p t i mize d f o r hig h s p eed and eas e o f us e . the a n al og in p u ts dr i v e a n in t e g r a t e d hig h ban d wid t h tra c k - a n d - h o ld ci r c ui t tha t sa m p le s th e si gnal p r i o r t o q u a n t i za - ti o n b y th e 10- b i t co r e . f o r ea se o f use , th e pa r t in c l ud es a n o n - b o a r d r e fer e n c e a nd i n p u t lo g i c t h a t acc e p t s t t l, cmos, o r l v p e cl le ve ls. the dig i t a l o u t p u t s log i c le v e l s a r e l v ds (ans i-644) com p a t i b le . cl ock inpu t an y hig h sp e e d a/d con v er t e r i s ext r em e l y s e n s i t i v e t o t h e q u al i t y o f t h e s a m p lin g clo c k p r o v i d e d b y t h e u s er . a t r ack-an d- ho l d c i rc u i t i s e s s e n t i a l l y a m i x e r , an d a n y noi s e, d i s t or t i on , or ti m i n g ji t t e r o n th e c l ock i s co m b in e d wi t h t h e d e si r e d si gn al a t th e a / d o u t p u t . f o r th i s r e a s o n , co n s i d e r a b le ca r e h a s been tak e n in the des i g n o f t h e c l o c k in p u ts o f t h e AD9411, a nd t h e us er is ad vis e d to g i v e ca r e f u l tho u g h t t o t h e c l o c k s o ur ce . th e AD9411 has a n in t e r n al c l o c k d u ty c y c l e s t a b iliza t io n cir c ui t tha t lo cks t o the r i sin g e d g e o f clk+ and o p timizes timin g in t e r n al ly . this al lo ws a wide ra n g e o f in p u t d u ty c y c l es a t t h e in pu t wi t h o u t deg r a d in g p e r f o r ma n c e . j i t t e r in t h e r i sin g e d ge o f t h e i n p u t is st i l l o f p a ra m o u n t con c er n a nd is n o t r e d u ced b y t h e in t e rn al sta b iliz a t i o n ci r c ui t . t h e d u t y c y c l e co n t r o l lo o p do es n o t f u n c tion f o r c l o c k ra t e s les s tha n 30 m h z n o mi n a ll y . th e tim e co n s ta n t as soci a t ed wi th t h e loo p s h o u ld b e co n s i d er e d i n a p pli c a t io n s w h er e t h e clo c k ra t e cha n g e s d y na mical l y , r e q u ir in g a wai t t i m e o f 1.5 s t o 5 s a f t e r a d y namic clo c k f r eq u e n c y incr eas e bef o re va lid da t a is a v a i l a b l e . this cir c u i t is alwa ys o n and cann ot b e dis a b l e d b y t h e us er . the clo c k in pu t s a r e in ter n a l ly b i a s e d t o 1.5 v (n o m in a l ) an d s u p p o r t ei t h er dif f er en t i al o r sing le-e n d e d sig n a l s. f o r b e s t d y na mic p e r f o r ma n c e, a dif f er en t i a l sig n a l is r e co mm e nde d . a n m c 100l vel16 p e r f o r m s w e l l in t h e cir c u i t t o dr i v e t h e c l o c k in p u ts, as i l l u st r a t e d in f i gur e 3 9 . n o t e t h a t fo r t h is lo w v o l t a g e p e cl device , t h e ac co u p lin g is o p tio n al . 04530-a - 017 AD9411 clk+ 0.1 f 0.1 f 510 ? 510 ? pecl gate clk? f i g u re 39. d r iv ing clo c k input s wit h l v e l 16 table 7. out p ut select coding 1 s1 ( data for m at select) s5 (full-scale select) 2 mode 1 x twos complem e nt 0 x offset binary x 1 full scale = 0.76 8 v x 0 full scale = 1.53 6 v 1 x = do nt c a re . 2 s5 ful l -scale ad ju st (r ef er t o the an alog i n put sec t ion). anal og input the a n alog i n pu t t o t h e a d 941 1 is a dif f er en t i a l b u f f er . f o r b e s t d y na mic p e r f o r ma n c e, i m p e dan c es a t vi n+ and vin C sh o u l d ma t c h. t h e ana l og in p u t is o p t i mi ze d t o p r o v i d e su p e r i o r wide - b a nd p e r f o r ma n c e and r e q u ir e s t h a t t h e a n a l o g in p u ts b e dr iven dif f er en t i al l y . snr and s i n a d p e r f o r ma n c e deg r ades sig n if i- ca n t ly if t h e a n a l o g in p u t is dr i v en wi t h a s i n g le -ende d sig n a l . a w i deb a nd t r a n sfo r m e r , such as mini -cir c u i t s adt1 -1w t , ca n p r o v i d e t h e dif f er en t i al a n al og in p u ts fo r a pplica t ion s t h a t r e q u ir e a sing le- e nde d - t o - d if fer e n t ia l con v ersion. b o t h a n a l og in p u ts a r e s e lf- b ias e d b y a n o n - c hi p r e sisto r div i der to a n o minal 2.8 v ( r efer t o t h e e q u i vale n t cir c u i ts s e c t io n). n o t e t h a t t h e in p u t c o mm on- m o d e ca n b e o v er dr i v en b y a p p r o x ima t e l y +/?150 mv a r ound t h e s e lf-b ias p o in t, as sh o w n in f i gur e 42. s p e c ia l ca r e was t a k e n in t h e de sig n o f t h e a n a l og in p u t s e c t ion o f th e AD9411 to p r ev en t da mag e a nd co r r u p tio n o f da ta w h en t h e in p u t is o v erdr i v en. th e n o minal dif f er en t i al in p u t ra n g e is a p p r o x ima t e l y 1.5 v p-p ~ (768 mv 2). n o t e t h a t t h e best p e r f o r ma n c e is ac hiev e d wi th s 5 = 0 (f u l l-s c ale = 1.5). s e e f i gur e 40 an d f i gur e 41. 04530-0-041 s5 = gnd vin+ 2.8v 768mv 2.8v vin? digitalout = all 1s digitalout = all 0s f i g u re 40. d i f f e r e nt ia l a n a l og input r a ng e
AD9411 rev. a | page 19 of 28 04530-0-042 s5 = avdd vin+ 2.8v 768mv 2.8v vin ? = 2.8v f i gure 41. sing le -ended a n alog input range 04530-a - 014 analog input common mode (v) 3.2 2.0 2.2 2.4 2.6 2.8 3.0 db 61 60 59 58 57 56 sinad f i g u re 42. sina d s e ns it iv it y to a n a l o g input co m m on- m ode v o lt ag e , (a in = ?. 5 dbf s d i f f e r e nt ia l d r iv e , s 5 = 0) lv d s o u t p u t s the o f f-chi p dr iv ers p r o v ide l v ds co m p a t i b l e o u t p ut le ve ls. a 3.74 k? rs et r e sis t o r p l aced a t p i n 7 (l vds b i a s) t o g r o u n d s e ts t h e l v ds ou t p ut c u r r en t. th e r s et r e sis t o r c u r r en t is ra tio e d on-c hi p , s e t t in g t h e o u t p u t c u r r en t a t eac h o u t p u t eq ual t o a n o mina l 3. 5 ma (11 irs e t). a 100 ? dif f er en tial t e r m i- n a t i on re s i stor p l a c e d a t t h e l v d s re c e ive r i n p u t s re su lt s i n a n o minal 350 mv swin g a t t h e recei v er . l v ds m o de facil i t a t e s in t e r f acin g w i t h l v ds r e cei v ers in c u st om as ics a nd fpg a s th a t ha v e l v d s c a pa b i l i t y f o r s u pe ri o r s w i t c h in g pe rf o r m a n c e in no isy e n v i r o n m e n ts. si n g l e p o in t- t o - p o i n t n e tw ork t o p o log i e s a r e r e co mm ended wi t h a 100 ? t e r m ina t io n r e s i s t o r as c l os e t o t h e r e ce i v er as p o s s i b le . i t is r e c o mm e nde d t o ke ep t h e t r ace len g t h s < 4 i n ches a nd t o k e ep dif f er en t i al o u t p ut t r ace len g t h s as e q ua l as p o ssi b le. cl ock ou t p ut s (dc o + , dc o C ) the i n p u t clo c k is b u f f er e d o n - c hi p an d a v ai lable o f f-chi p a t d c o+ an d d c oC. th es e c l o c ks ca n fac i li t a te l a t c hin g o f f-c h i p , pro v i d i n g a l o w ske w cl o c k i ng s o lut i on ( s e e fi g u re 2 ) . t h e on - ch i p cl o c k b u f f e r s s h ou l d not dr ive more t h an 5 p f of c a p a c i t a nc e t o limi t swi t chin g tra n sien t ef fe c t s o n p e r f o r ma n c e. th e o u t p u t clo c ks a r e l v ds sig n al s r e quir i n g 10 0 ? dif f eren t i a l t e r m ina t ion at r e c e i v e r . v o l t a g e reference a s t a b l e an d ac c u ra t e 1.23 v v o l t a g e r e f e r e n c e is b u il t in t o t h e AD9411 (vref ) . the a n alog in p u t f u l l -s c a le ran g e is lin e a r l y prop or t i on a l to t h e vo lt age a t v r e f . n o te t h a t a n e x te r n a l re f e re nc e c a n b e u s e d b y c o n n e c t i ng t h e se n s e pi n to v d d (dis a b li n g i n ter n a l r e fer e n c e) and dr ivi n g vre f wi t h t h e ext e r n al r e fer e nce s o ur ce . n o a p p r e c ia b l e deg r ada t ion i n p e r f o r ma n c e o c c u rs when v r e f is ad j u s t ed 5 %. a 0.1 f ca p a ci to r to g r o u nd is r e co m m e n de d a t t h e v r ef p i n i n in t e r n a l an d exter n a l r e fer e n c e a p plic a t io n s . flo a t t h e s e ns e p i n fo r in ter n a l r e fer e nc e o p er a t io n. 04530-0-043 vref k a1 disable a1 sense vdd 200 ? 1v 3.3v external 1.23v reference 0.1 f full scale s5 = 0 k = 1.24 s5 = 1 k = 0.62 1k ? f i gure 43. u s ing an e x tern al r e ference noise pow e r r a tio testing (n pr) npr i s a te s t t h a t i s c o m m on ly u s e d to ch ar a c te r i z e t h e re t u r n p a t h o f cab l e sys t em s w h er e t h e sig n als a r e typ i cal l y q a m sig - na ls w i t h a n o i s e -li k e f r e q uenc y sp e c t r um. n p r p e r f o r ma n c e o f th e AD9411 was c h a r ac t e r ized in t h e l a b y i eldin g an ef f e c t i v e np r = 51.2 db a t a n analog in p u t o f 18 mh z. this a g r e es wi t h a th eo r e tical maxim u m np r o f 5 1 .6 db f o r a 10-b i t ad c a t 13 db b a ck o f f. the r m s n o is e p o w e r o f t h e s i g n al i n side t h e n o t c h is co m p a r e d wi t h t h e r m s n o i s e le v e l o u tsi d e t h e n o t c h usin g an f f t . t h i s te st re qu i r e s su f f i c i e n t l y l o ng re c o rd l e ng t h s to gua r a n t e e a la rg e n u m b er o f s a m p les in side t h e n o t c h. a hig h - o r der b a nd-sto p f i l t er t h a t p r o v i d es t h e r e q u ir e d n o tch de p t h fo r t e st in g is a l s o n e e d e d .
AD9411 rev. a | page 20 of 28 04530-0-044 AD9411 evaluation board avdd gnd gnd gnd vdl drvdd 3.3v 3.3v 3.3v ++ + signal generator band-pass filter data capture and processing analog j4 clock j5 signal generator refin 10mhz refout f i g u re 44. ev aluat i on b o a r d conn ec t i ons
AD9411 rev. a | page 21 of 28 evaluation board the AD9411 evaluation board offers an easy way to test the AD9411 in lvds mode. it requires a clock source, an analog input signal, and a 3.3 v power supply. the clock source is buffered on the board to provide the clocks for the adc, latches, and a data-ready signal. the digital outputs and output clocks are available at a 40-pin connector, p23. the board has several different modes of operation and is shipped in the following configurations: ? offset binary ? internal voltage reference ? full-scale adjust = low power connector power is supplied to the board via a detachable 12-lead power strip (three 4-pin blocks). table 8. power connector, lvds mode avdd 1 3.3 v analog supply for adc (350 ma) drvdd 1 3.3 v output supply for adc (50 ma) vdl 1 3.3 v supply for support logic vclk/v_xtal supply for cloc k buffer/optional xtal ext_vref 2 optional external reference input 1 avdd, drvdd, and vdl are the min imum required power connections. 2 lvel16 clock buffer can be powered from avdd or vclk at e47 jumper. analog inputs the evaluation board accepts a 1.3 v p-p analog input signal centered at ground at smb connector j4. this signal is terminated to ground through 50 ? by r16. the input can be alternatively terminated at the t1 transformer secondary by r13 and r14. t1 is a wideband rf transformer that provides a single-ended-to-differential conversion, allowing the adc to be driven differentially, which minimizes even-order harmonics. an optional second transformer, t2, can be placed following t1 if desired. this provides some performance advantage (~1 db to 2 db) for high analog input frequencies (>100 mhz). if t2 is placed, cut the two shorting traces at the pads. the analog signal can be low-pass filtered by r41, c12 and r42, c13 at the adc input. the footprint for transformer t2 can be modified to accept a wideband differential amplifier (ad8351) for low frequency applications where gain is required. see the pcb schematic for more information. gain full scale is set at e17Ce19, e17Ce18 sets s5 low, full scale = 1.5 v differential; e17Ce19 sets s5 high, full scale = 0.75 v differential. best performance is obtained at 1.5 v full scale. clock the clock input is terminated to ground through 50 ? resistor at smb connector j5. the input is ac-coupled to a high speed differential receiver (lvel16) that provides the required low jitter, fast edge rates needed for optimum performance. j5 input should be > 0.5 v p-p. power to the lvel16 is set at jumper e47. e47Ce45 powers the buffer from avdd; e47Ce46 powers the buffer from vclk/v_xtal. voltage reference the AD9411 has an internal 1.23 v voltage reference. the adc uses the internal reference as the default when jumpers e24Ce27 and e25Ce26 are left open. the full scale can be increased by placing an optional resistor (r3). the required value varies with the process and needs to be tuned for the specific application. full scale can similarly be reduced by placing r4; tuning is required here as well. an external reference can be used by shorting the sense pin to 3.3 v (place jumper e26Ce25). jumper e27Ce24 connects the adc vref pin to the ext_vref pin at the power connector. data format select data format select (dfs) sets the output data format of the adc. setting dfs (e1Ce2) low sets the output format to be offset binary; setting dfs high (e1Ce3) sets the output to twos complement. data outputs the adc lvds digital outputs are routed directly to the connector at the card edge. resistor pads placed at the output connector allow for termination if the connector receiving logic lack the differential termination for the data bits and dco. each output trace pair should be terminated differentially at the far end of the line with a single 100 ohm resistor. clock xtal an optional xtal oscillator can be placed on the board to serve as a clock source for the pcb. power to the xtal is through the vclk/vxtal pin at the power connector. if an oscillator is used, ensure proper termination for best results. the board was tested with a valpey fisher vf561 and a vectron jn00158-163.84.
AD9411 rev. a | page 22 of 28 table 9. evaluation board bill of materialAD9411 pcb no. quantity reference designator device package value 1 33 c1, c3*, c4Cc11, c15Cc17, c18*, c19Cc32, c35, c36, c39*, c40*, c58-c62 capacitor 0603 0.1 f 2 4 c33*, c34*, c37*, c38* capacitor 0402 0.1 f 3 4 c63Cc66 capacitor tajd capl 10 f 4 1 c2* capacitor 0603 10 pf 5 2 c12*, c13* capacitor 0603 20 pf 6 2 j4, j5 jacks smb 7 2 p21, p22 power connectorstop 25.602.5453.0 wieland 8 2 p21, p22 power connectorsposts z5.531.3425.0 wieland 9 1 p23 40-pin right angle connector digi-key s2131-20-nd 10 16 r1, r6Cr12*, r15*, r31Cr37* resistor 0402 100 11 1 r2 resistor 0603 3.7 k ? 12 3 r5, r16, r27 resistor 0603 50 13 2 r17, r18 resistor 0603 510 14 2 r19, r20 resistor 0603 150 15 2 r29, r30 resistor 0603 1 k ? 16 2 r41, r42 resistor 0603 25 17 2 r3, r4 resistor 0603 3.8 k ? 18 2 r13, r14 resistor 0603 25 19 6 r22*, r23*, r24*, r25*, r26*, r28* resistor 0603 100 20 5 r38*, r39*, r40*, r45*, r47* resistor 0402 25 21 2 r43*, r44* resistor 0402 10 k ? 22 1 r46* resistor 0402 1.2 k ? 23 2 r48*, r49* resistor 0402 0 24 2 r50*, r51* resistor 0402 1 k ? 25 1 t1, t2* rf transformer mini circuits adt1-1wt 26 1 u2 rf amp ad8351 27 1 u9 optional xtal jn00158 or vf561 28 1 u1 AD9411 tqfp-100 29 1 u3 mc100lvel16 so8nb * c2, c3, c12, c13, c18, c33, c34, c37, c38, c39, c40, r1, r6Cr12, r15, r22Cr26, r28, r31C r40, r43Cr51 and t2 not placed.
AD9411 rev. a | page 23 of 28 gn d 40 drb 38 gn d 36 d11b 34 d10b 32 gn d dr gn d d11 d10 39 37 35 33 31 d9b 30 d8b 28 d7b 26 d6b 24 d5b 22 d9 d8 d7 d6 d5 29 27 25 23 21 d4b 20 d3b 18 d2b 16 d1b 14 d0b 12 d4 d3 d2 d1 d0 19 17 15 13 11 d1fb 10 d2fb 8 do rb 6 4 gn d 2 d1f d2f do r gn d 9 7 5 3 1 p4 0 p3 8 p3 6 p3 4 p3 2 p3 0 p2 8 p2 6 p2 4 p2 2 p2 0 p1 8 p1 6 p1 4 p1 2 p1 0 p8 p6 p4 p2 p3 9 p3 7 p3 5 p3 3 p3 1 p2 9 p2 7 p2 5 p2 3 p2 1 p1 9 p1 7 p1 5 p1 3 p1 1 p9 p7 p5 p3 p1 u1 a d 9411 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 r1 100 ? do r do rb r6 100 ? d11 d11b r7 100 ? d10 d10b r8 100 ? d9 d9b r15 100 ? d1 d1b r36 100 ? d0 d0b r35 100 ? d1f d1fb r34 100 ? d2f d2fb r31 100 ? d2 d2b r10 100 ? d6 d6b r37 100 ? dr drb r32 100 ? d3 d3b r11 100 ? d7 d7b r9 100 ? d5 d5b r33 100 ? d4 d4b r12 100 ? d8 d8b gn d vcc vcc gn d gn d vcc vcc gn d gn d gn d vcc vcc vcc gn d gn d drvdd gn d drvdd drvdd drvdd gn d gn d gn d gn d gn d vcc vcc vcc vcc vcc gn d gn d gn d gn d gn d drvdd gn d ~e n c vcc c4 0. 1 f gn d gn d r5 50 ? c10 0. 1 f c9 0. 1 f elo u t elo u tb gn d r19 510 ? r20 510 ? gn d c36 0. 1 f vcc vee vbb dn d q qn 2 3 4 5 6 7 8 gn d r18 510 ? r17 510 ? c8 0. 1 f vcc e46 e47 vdl e45 10e l16 u3 j5 gn d gn d c5 0. 1 f enco de r27 50 ? c13 20pf gn d gn d vcc gn d gn d vcc vcc gn d gn d vcc vcc gn d gn d gn d vcc c12 20pf c15 0. 1 f c3 0. 1 f c2 10pf c30 0. 1 f c7 0. 1 f c1 1 0. 1 f c6 0. 1 f j4 gn d r16 50 ? r1 4 25 ? r42 25 ? t 2 op t ion a l gn d gn d r1 3 25 ? gn d am pi nb am pi n r41 25 ? t1 a d t 1-1w t 1 5 3 4 2 6 t2 a d t 1-1w t 1 5 3 4 2 6 nc nc pr i sec p r i sec gn d gn d am p analo g vcc e19 vcc e3 e17 gn d gn d e18 r30 1k ? vcc r29 1k ? e1 gn d e2 r2 3. 8k ? gn d gn d r3 3. 8k ? r4 3. 8k ? vcc e26 vref e24 e25 e27 gn d c1 0. 1 f p16 gn d g r o und pad under part p1 p2 1 2 gn d vref p3 p4 3 4 gn d vdl p1 p2 1 2 gn d drvdd p3 p4 3 4 gn d vcc p21 ptm1cro4 p22 ptm1cro4 h4 mth o le6 h3 mth o le6 h2 mth o le6 h1 mth o le6 gn d co nnecto r ag nd avdd avdd ag nd ag nd avdd avdd ag nd ag nd ag nd avdd avdd avdd ag nd ag nd or + or ? dvrdd drg nd d9+ d9 ? d8+ d8 ? d7+ d7 ? drvdd drg n d d6+ d6 ? d5+ d5 ? d4+ d4 ? drg n d d3+ d3 ? dc0+ dc0 ? drvdd drg n d d2+ d2 ? d1+ d1 ? d0+ d0 ? drvdd drg n d dnc dnc s5 dnc s4 ag nd s2 s1 lvdsbi as avdd ag nd sense vref ag nd ag nd avdd avdd ag nd ag nd avdd avdd gn d ai n ai nb ag nd avdd ag nd ag nd avdd avdd avdd ag nd ag nd ag nd avdd avdd ag nd clk+ clk ? ag nd avdd avdd ag nd dnc dnc dnc dnc dnc drvdd drg nd dnc dnc 04530- a- 015 f i g u re 45. ev aluat i on b o a r d s c h e m a t i c
AD9411 rev. a | page 24 of 28 04530-0-046 + c64 10 f c16 0.1 f c17 0.1 f c19 0.1 f c21 0.1 f c20 0.1 f c23 0.1 f c22 0.1 f c25 0.1 f c24 0.1 f c27 0.1 f c26 0.1 f c29 0.1 f c28 0.1 f c31 0.1 f c32 0.1 f c35 0.1 f vcc gnd + c65 10 f c61 0.1 f c62 0.1 f c60 0.1 f c59 0.1 f c58 0.1 f drvdd gnd c66 10 f c18 0.1 f vdl gnd + c63 10 f vref gnd + to use vf561 crystal e/d 1 nc 2 gnd 3 vcc outputb output 6 5 4 jn00158 u9 gnd r28 100 ? r22 100 ? gnd vdl vdl gnd r23 100 ? r25 100 ? vdl gnd r24 100 ? r26 100 ? p4 p5 f i g u re 46. ev aluat i on b o a r d s c h e m a t i c (c ont i nued) 04530-0-053 vdl vdl gnd gnd gnd amp in amp power down use r43 or r44 u2 ad8351 r44 10k ? r39 25k ? r38 25k ? r40 25k ? r46 1.2k ? r45 25k ? r43 10k ? c33 0.1 f c34 0.1 f vdl gnd gnd r51 1k ? r50 1k ? c38 0.1 f c37 0.1 f r49 0 ? c39 0.1 f r48 0 ? c40 0.1 f ampinb ampin gnd r47 25k ? pwup 1 rgp1 2 inhi 3 inlo 4 rpg2 5 vocm vpos ophi oplo comm 10 9 8 7 6 f i g u re 47. ev aluat i on b o a r d s c h e m a t i c (c ont i nued)
AD9411 rev. a | page 25 of 28 f i gure 48. pcb t o p side s ilkscr e en 04530-0-048 f i gure 49. pcb t o p side cop p er r o utin g 04530-0-049 f i gure 50. pcb gro u nd laye r 04530-0-050 f i g u re 51. pcb spl i t p o wer plan e
AD9411 rev. a | page 26 of 28 04530-0-052 04530-0-051 f i g u r e 5 2 . p c b b o t t o m s i de c o pp er r o u t i n g f i g u re 53. pcb bot t o m sid e s ilk s c r e e n
AD9411 rev. a | page 27 of 28 outline dimensions top view (pins down) 1 25 26 50 76 100 75 51 14.00 sq 16.00 sq 0.27 0.22 0.17 0.50 bsc 1.05 1.00 0.95 0.15 0.05 0.75 0.60 0.45 seating plane 1.20 max 1 25 26 50 76 100 75 51 conductive heat sink 6.50 nom compliant to jedec standards ms-026aed-hd notes 1. center figures are typical unless otherwise noted. 2. the AD9411 has a conductive heat slug to help dissipate heat and ensure reliable operation of the device over the full industrial temperature range. the slug is exposed on the bottom of the package and electrically connected to chip ground. it is recommended that no pcb signal traces or vias be located under the package that could come in contact with the conductive slug. attaching the slug to a ground plane will reduce the junction temperature of the device which may be beneficial in high temperature environments. 7 3.5 0 coplanarity 0.08 0.20 0.09 f i g u re 54. 1 00-l e a d thin p l as t i c q u ad f l at p a ckag e , e x po s e d p a d [ t qfp /e p ] (sv - 10 0) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature range package descri ption package option AD9411bsv-170 AD9411bsv-200 C40c to +85c C40c to +85c tqfp/ep tq fp/ e p sv-100 sv-100 AD9411/pcb evalua t ion b o ard
AD9411 rev. a | page 28 of 28 notes ? 2004 a n al og d e vic e s , inc . a ll righ t s r e ser v ed . t r a d em arks and r e gist er e d tr adem ar ks ar e t h e proper t y of t h eir respec tiv e o w ners . d04530-0-7/04( a )

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