philips semiconductors programmable logic devices product specification plus173b/d programmable logic arrays (22 42 10) 33 october 22, 1993 8531298 11164 description the plus173 plds are high speed, combinatorial programmable logic arrays. the philips semiconductors state-of-the-art oxide isolated bipolar fabrication process is employed to produce propagation delays as short as 12ns. the 24-pin plus173 devices have a programmable and array and a programmable or array. unlike pal ? devices, 100% product term sharing is supported. any of the 32 logic product terms can be connected to any or all of the 10 output or gates. most pal ics are limited to 7 and terms per or function; the plus173 devices can support up to 32 input wide or functions. the polarity of each output is user- programmable as either active-high or active-low, thus allowing and-or or and-nor logic implementation. this feature adds an element of design flexibility , particularly when implementing complex decoding functions. the plus173 devices are user- programmable using one of several commercially available, industry standard pld programmers. features ? i/o propagation delays (worst case) plus173b 15ns max. plus173d 12ns max. ? functional superset of 20l10 and most other 24-pin combinatorial pal devices ? two programmable arrays supports 32 input wide or functions ? 12 inputs ? 10 bi-directional i/o ? 42 and gates 32 logic product terms 10 direction control terms ? programmable output polarity active-high or active-low ? security fuse ? 3-state outputs ? power dissipation: 750mw (typ.) ? ttl compatible applications ? random logic ? code converters ? fault detectors ? function generators ? address mapping ? multiplexing pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 n package i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 v cc b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 i11 gnd a package n = plastic dual in-line (300mil-wide) i0 i1 i2 i3 v cc b9 b8 nc i4 i5 i6 i7 i8 nc i9 i10 gnd i11 b0 b1 b2 nc b3 b7 b6 b5 b4 nc a = plastic leaded chip carrier ordering information description t pd (max) order code drawing number 24-pin plastic dual in-line 300mil-wide 15ns plus173bn 0410d 24-pin plastic dual in-line 300mil-wide 12ns plus173dn 0410d 28-pin plastic leaded chip carrier 15ns plus173ba 0401f 28-pin plastic leaded chip carrier 12ns plus173da 0401f ? pal is a registered trademark of advanced micro devices corporation.
philips semiconductors programmable logic devices product specification plus173b/d programmable logic arrays (22 42 10) october 22, 1993 34 logic diagram notes: 1. all programmed `and' gate locations are pulled to logic a1o. 2. all programmed `or' gate locations are pulled to logic a0o. 3. programmable connection. (logic termsp) (control terms) 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 i11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 31 24 23 16 15 8 7 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
philips semiconductors programmable logic devices product specification plus173b/d programmable logic arrays (22 42 10) october 22, 1993 35 functional diagram p31 p0 d0 d9 i0 i11 b0 b9 b9 b0 s0 s9 x9 x0 absolute maximum ratings 1 thermal ratings rating symbol parameter min max unit v cc supply voltage +7 v dc v in input voltage +5.5 v dc v out output voltage +5.5 v dc i in input currents 30 +30 ma i out output currents +100 ma t amb operating free-air temperature range 0 +75 c t stg storage temperature range 65 +150 c notes: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only . functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. temperature maximum junction 150 c maximum ambient 75 c allowable thermal rise 75 c ambient to junction
philips semiconductors programmable logic devices product specification plus173b/d programmable logic arrays (22 42 10) october 22, 1993 36 dc electrical characteristics 0 c t amb +75 c, 4.75 v cc 5.25v limits symbol parameter test conditions min typ 1 max unit input voltage 2 v il low v cc = min 0.8 v v ih high v cc = max 2.0 v v ic clamp v cc = min, i in = 12ma 0.8 1.2 v output voltage 2 v cc = min v ol low 4 i ol = 15ma 0.5 v v oh high 5 i oh = 2ma 2.4 v input current 9 v cc = max i il low v in = 0.45v 100 m a i ih high v in = v cc 40 m a output current v cc = max i o(off) hi-z state 8 v out = 2.7v 80 m a v out = 0.45v 140 i os short circuit 3, 5, 6 v out = 0v 15 70 ma i cc v cc supply current 7 v cc = max 150 200 ma capacitance v cc = 5v i in input v in = 2.0v 8 pf c b i/o v b = 2.0v 15 pf notes: 1. all typical values are at v cc = 5v, t amb = +25 c. 2. all voltage values are with respect to network ground terminal. 3. test one at a time. 4. measured with inputs i0 i4 = 0v , inputs i5 i9 = 4.5v, i11 = 4.5v and i19 = 10v . for outputs b0 b4 and for outputs b5 b9 apply the same conditions except i11 = 0v. 5. same conditions as note 4 except input i1 1 = +10v. 6. duration of short circuit should not exceed 1 second. 7. i cc is measured with inputs i0 i11 and b0 b9 = 0v. part in virgin state. 8. leakage values are a combination of input and output leakage. 9. i il and i ih limits are for dedicated inputs only (i0 i1 1).
philips semiconductors programmable logic devices product specification plus173b/d programmable logic arrays (22 42 10) october 22, 1993 37 ac electrical characteristics 0 c t amb +75 c, 4.75 v cc 5.25v, r 1 = 300 w , r 2 = 390 w limits symbol parameter from to test plus173b plus173d unit condition min typ max min typ max t pd propagation delay 2 input +/ output +/ c l = 30pf 11 15 10 12 ns t oe output enable 1 input +/ output c l = 30pf 11 15 10 12 ns t od output disable 1 input +/ output + c l = 5pf 11 15 10 12 ns notes: 1. for 3-state outputs; output enable times are tested with c l = 30pf to the 1.5v level, and s 1 is open for high-impedance to high tests and closed for high-impedance to low tests. output disable times are tested with c l = 5pf . high-to-high impedance tests are made to an output voltage of v t = (v oh 0.5v) with s 1 open, and low-to-high impedance tests are made to the v t = (v ol + 0.5v) level with s 1 closed. 2. all propagation delays are measured and specified under worst case conditions. voltage waveform measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. 90% 10% 5ns 5ns 5ns 5ns 90% 10% +3.0v +3.0v 0v 0v t r t f input pulses timing definitions symbol parameter t pd propagation delay between input and output. t od delay between input change and when output is off (hi-z or high). t oe delay between input change and when output reflects specified output level. test load circuit timing diagram test load circuit +5v c l r 1 r 2 s 1 gnd b z b z inputs i n i n b m b m outputs c 2 c 1 dut note: c 1 and c 2 are to bypass v cc to gnd. v cc +3v 0v v oh v ol i, b b t pd 1.5v 1.5v 1.5v 1.5v 1.5v t od t oe v t
philips semiconductors programmable logic devices product specification plus173b/d programmable logic arrays (22 42 10) october 22, 1993 38 logic programming the plus173 series is fully supported by industry standard (jedec compatible) pld cad tools, including philips semiconductors snap design software package. abel ? and cupl ? design software packages also support the plus173 architecture. all packages allow boolean and state equation entry formats. snap, abel and cupl also accept, as input, schematic capture format. plus173 logic designs can also be generated using the program table entry format, which is detailed on the following page. this program table entry format is supported by snap only. t o implement the desired logic functions, the state of each logic variable from logic equations (i, b, o, p, etc.) is assigned a symbol. the symbols for true, complement, inactive, preset, etc., are defined below. programming and software support refer to section 9 (development software) and section 10 (third-party programmer/ software support) of this data handbook for additional information. and array (i, b) code o state inactive 1, 2 code state code state code state i, b h l p, d i, b i , b i, b i , b p, d i, b i , b i, b p, d i, b i , b i, b p, d i, b i , b i, b don't care or array (b) virgin state a factory shipped virgin device contains all fusible links intact, such that: 1. all outputs are at aho polarity. 2. all p n terms are disabled. 3. all p n terms are active on all outputs. notes: 1. this is the initial unprogrammed state of all link pairs. it is normally associated with all unused (inactive) and gates p n , d n . 2. any gate p n , d n will be unconditionally inhibited if both the true and complement of any input (i, b) are left intact. abel is a trademark of data i/o corp. cupl is a trademark of logical devices, inc. code active level low (inverting) l code active level high 1 (non-inverting) h s x b s x b output polarity (b) code inactive a code p n status active 1 ? p s p n status p s
philips semiconductors programmable logic devices product specification plus173b/d programmable logic arrays (22 42 10) october 22, 1993 39 program table polarity 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pin t e r m and or active inactive control high low a inactive h l b(0) (pol) don't care i, b i, b i, b(i) customer name philips device # program t able # rev date 0 h l e variable name and or b(0) 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 b(i) 13 11 10 9 8 7 6 5 4 3 2 1 23 22 21 20 19 18 17 16 15 14 23 22 21 20 19 18 17 16 15 14 notes 1. 2. 3. the pla is shipped with all links intact. thus a background (shown blank for clarity .) unused i and b bits in the and array must be programmed unused product terms can be left blank. don't care (e). of entries corresponding to states of virgin links exists in the table. 0 i
philips semiconductors programmable logic devices product specification plus173b/d programmable logic arrays (22 42 10) october 22, 1993 40 snap resource summary designations cand and p 31 p 0 d 0 d 9 i 0 i 11 b 0 b 9 b 9 b 0 s 0 s 9 x 9 x 0 or din173 nin173 exor173 tout173 din173 nin173
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