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BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 1 of 94 _?`??qjolj=m??j?jd??= data sheet _?`??qjolj=m??j?jd?? device features data sheet advance informationcsr plc2005 c2005bc41b143a-ds-003p? 2005 cambridge silicon radio limited ? fully qualified blue tooth v2.0+edr system ? full speed bluetooth operation with full piconet support ? scatternet support ? low power 1.8v operation ? 10 x 10mm 96-ball lfbga package ? minimum external components ? integrated 1.8v regulator ? dual uart ports ? rf plug-n-go package ? 50 ? matched connection to antenna ? rohs compliant single chip bluetooth ? v2.0 + edr system advance information data sheet for bc41b143a july 2005 general description applications the _?`? ? qjolj=m??j?jd? ? is a single chip radio and baseband ic for bluetooth 2.4ghz systems. it is implemented in 0.18 m cmos technology. ? automotive ? mice ? keyboards bc41b143a contains 4mbit of internal rom memory. when used with csr bluetoot h stack, it provides a fully compliant bluet ooth system to v2.0 + edr of the specification for data and voice. bluecore4-rom plug-n-go has the same pinout and electrical characteristics as available in bluecore4-flash plug-n-go to enable development of custom code before committing to rom. it also has the same pinout as bluecore2-rom plug-n-go and bluecore2-flash plug-n-go to keep compatibility. system architecture bluecore4-rom plug-n-go has been designed to reduce the number of external components required which ensures production costs are minimised. the 0.8mm pitch bluecore4-rom plug-n-go can be used on either two or four layer pcb construction. the device incorporates auto-calibration and built in self test (bist) routines to simplify development, type approval and production test. all hardware and device firmware is fully compliant with the bluetooth v2.0 + edr specification. spi uart/usb 2.4 ghz radio i/o rf out ram baseband dsp mcu rom pio pcm rf in xtal
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 2 of 94 _?`??qjolj=m??j?jd??= data sheet contents 1 status information ........................................................................................................... ............................... 7 2 key features ................................................................................................................. ................................... 8 3 package information ...... .............. .............. .............. .............. ........... ........... ............ .......... ............................. 9 3.1 bc41b143a pinout diagram ................................................................................................... ................ 9 3.2 bc41b143a-ann-e4 device terminal functions ....... .......................................................................... 10 4 electrical characteristics ............................. ...................................................................... .......................... 14 4.1 power consumption .......................................................................................................... .................... 19 5 radio characteristics - basic data rate ............. ......................................................................... ............... 20 5.1 temperature +20c .......................................................................................................... ..................... 20 5.1.1 transmitter .............................................................................................................. .................. 20 5.1.2 receiver ................................................................................................................. ................... 22 5.2 temperature -40c .......................................................................................................... ...................... 24 5.2.1 transmitter .............................................................................................................. .................. 24 5.2.2 receiver ................................................................................................................. ................... 24 5.3 temperature -25c .......................................................................................................... ...................... 25 5.3.1 transmitter .............................................................................................................. .................. 25 5.3.2 receiver ................................................................................................................. ................... 25 5.4 temperature +85c .......................................................................................................... ..................... 26 5.4.1 transmitter .............................................................................................................. .................. 26 5.4.2 receiver ................................................................................................................. ................... 26 6 radio characteristics - enhanced data rate ........ ........................................................................... .......... 27 6.1 temperature +20c .......................................................................................................... ..................... 27 6.1.1 transmitter .............................................................................................................. .................. 27 6.1.2 receiver ................................................................................................................. ................... 28 6.2 temperature -40c .......................................................................................................... ...................... 29 6.2.1 transmitter .............................................................................................................. .................. 29 6.2.2 receiver ................................................................................................................. ................... 29 6.3 temperature -25c .......................................................................................................... ...................... 30 6.3.1 transmitter .............................................................................................................. .................. 30 6.3.2 receiver ................................................................................................................. ................... 30 6.4 temperature +85c .......................................................................................................... ..................... 31 6.4.1 transmitter .............................................................................................................. .................. 31 6.4.2 receiver ................................................................................................................. ................... 31 7 device diagram .............................................................................................................. .............................. 32 8 description of functional blocks ............................................................................................. ................... 33 8.1 rf receiver ................................................................................................................ ........................... 33 8.1.1 low noise amplifier ...................................................................................................... ............ 33 8.1.2 analogue to digital converter ............................................................................................ ....... 33 8.2 rf transmitter ............................................................................................................. .......................... 33 8.2.1 iq modulator ............................................................................................................. ................ 33 8.2.2 power amplifier .......................................................................................................... ............... 33 8.2.3 auxiliary dac ............................................................................................................ ................ 33 8.3 balun and filter ........................................................................................................... .......................... 33 8.4 rf synthesiser ............................................................................................................. ......................... 33 8.5 clock input and generation ..... ............................................................................................ .................. 33 8.6 baseband and logic ................ .............. .............. .............. .............. ........... ........... ........... ..................... 34 8.6.1 memory management unit ................................................................................................... .... 34 8.6.2 burst mode controller ............................. ....................................................................... ........... 34 8.6.3 physical layer hardware engine dsp ..................................................................................... 34
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 3 of 94 _?`??qjolj=m??j?jd??= data sheet 8.6.4 ram (48kbytes) ........................................................................................................... ............ 34 8.6.5 rom ...................................................................................................................... ................... 34 8.6.6 usb ...................................................................................................................... .................... 34 8.6.7 synchronous serial interface ............ .............. .............. .............. .............. .............. ........... ....... 34 8.6.8 uart ..................................................................................................................... ................... 34 8.7 microcontroller ............................................................................................................ ........................... 35 8.7.1 programmable i/o ......................................................................................................... ........... 35 8.7.2 802.11 co-existence interface ....................... ..................................................................... ..... 35 9 csr bluetooth software stacks ................................................................................................ .................. 36 9.1 bluecore hci stack ........................................................................................................ ..................... 36 9.1.1 key features of the hci stack: standard bluetooth functionality ........................................... 37 9.1.2 key features of the hci stack: extra functionality .................................................................. 38 9.2 bluecore rfcomm stack ...................................................................................................... .............. 39 9.2.1 key features of the bluecore4-rom plug-n-go rfcomm stack .......................................... 40 9.3 bluecore virtual machine stack ....................... ...................................................................... ............... 41 9.4 bluecore hid stack ......................................................................................................... ..................... 42 9.5 host-side software ......................................................................................................... ....................... 43 9.6 device firmware upgrade .................................................................................................... ................. 43 9.7 bchs software .............................................................................................................. ....................... 43 9.8 additional software for other em bedded applications ......... .............. .............. .............. ........... .......... .. 43 9.9 csr development systems ................................ .................................................................... .............. 43 10 device terminal descriptions ................................................................................................ ...................... 44 10.1 rf ports .................................................................................................................. .............................. 44 10.1.1 rf plug-n-go ............................................................................................................ ................ 44 10.1.2 single-ended input (rf_in) .. .............. .............. .............. .............. .............. ........... ........... ....... 45 10.2 external reference clock input (xtal_in) .................................................................................. ......... 46 10.2.1 external mode ........................................................................................................... ................ 46 10.2.2 xtal_in impedance in external mode .................................................................................... 46 10.2.3 clock timing accuracy ................................................................................................... .......... 46 10.2.4 clock start-up delay .................................................................................................... ............ 47 10.2.5 input frequencies and ps key settings ............ .............. .............. ........... ........... ............ ......... 48 10.3 crystal oscillator (xtal_in, xtal_out) ........... ......................................................................... ......... 49 10.3.1 xtal mode ............................................................................................................... ................ 49 10.3.2 load capacitance ........................................................................................................ ............. 50 10.3.3 frequency trim .......................................................................................................... ............... 51 10.3.4 transconductance driver model ........................................................................................... .... 52 10.3.5 negative resistance model ... ............................................................................................ ....... 52 10.3.6 crystal ps key settings ................................................................................................. ........... 53 10.3.7 crystal oscillator characteristics ............... ....................................................................... ........ 53 10.4 uart interface ............................................................................................................ .......................... 56 10.4.1 uart bypass ............................................................................................................. .............. 58 10.4.2 uart c onfiguration while reset is acti ve ........... .............. .............. .............. .............. ......... 58 10.4.3 uart bypass mode ........................................................................................................ ......... 58 10.4.4 current consumption in uart bypass mode .......................................................................... 58 10.5 usb interface ............................................................................................................. ........................... 59 10.5.1 usb data connections .............................. ...................................................................... ......... 59 10.5.2 usb pull-up resistor ................................ .................................................................... ........... 59 10.5.3 power supply ............................................................................................................ ................ 59 10.5.4 self-powered mode ............... .............. .............. .............. .............. ........... ........... .......... ........... 60 10.5.5 bus-powered mode ............... .............. .............. .............. .............. ........... ........... ........... .......... 61 10.5.6 suspend current ......................................................................................................... .............. 62
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 4 of 94 _?`??qjolj=m??j?jd??= data sheet 10.5.7 detach and wake_up signalling .................... ....................................................................... ... 62 10.5.8 usb driver .............................................................................................................. .................. 62 10.5.9 usb 1.1 compliance ...................................................................................................... .......... 63 10.5.10 usb 2.0 compatibility ......... .............. .............. .............. .............. ........... ............ .......... ............. 63 10.6 serial peripheral interface . .............................................................................................. ...................... 64 10.6.1 instruction cycle ....................................................................................................... ................ 64 10.6.2 writing to bluecore4-rom plug-n-go ............... ....................................................................... 65 10.6.3 reading from bluecore4-rom plug-n-go ........... .................................................................... 65 10.6.4 multi-slave operation ................................................................................................... ............ 65 10.7 pcm codec interface .................................. ..................................................................... ................... 66 10.7.1 pcm interface master/slave ........................ ...................................................................... ....... 67 10.7.2 long frame sync ......................................................................................................... ............ 68 10.7.3 short frame sync ........................................................................................................ ............. 68 10.7.4 multi-slot operation .................................................................................................... ............... 69 10.7.5 gci interface ........................................................................................................... ................. 69 10.7.6 slots and sample formats . ............................................................................................... ....... 70 10.7.7 additional features ..................................................................................................... .............. 70 10.7.8 pcm timing information ..... ............................................................................................. ......... 71 10.7.9 pcm configuration ....................................................................................................... ............ 76 10.8 i/o parallel ports ............ ............................................................................................ ........................... 78 10.8.1 pio defaults for bluecore4-rom plug-n-go ........................................................................... 78 10.9 i2c interface ............................................................................................................. ............................. 79 10.10 tcxo enable or function ........................... ....................................................................... ................. 80 10.11 reset and resetb ..... .............. .............. .............. .............. ............ ........... ........... .......... ................... 81 10.11.1 pin states on reset .................................................................................................... .............. 82 10.11.2 status after reset .......... ........................................................................................... ................ 82 10.12 power supply ............................................................................................................. ........................... 83 10.12.1 voltage regulator (plug-n-go) .................. ........................................................................ ....... 83 10.12.2 sequencing ........... .............. .............. .............. .............. .............. .............. .............. .................. 83 10.12.3 sensitivity to disturbances ............. .............. .............. .............. .............. ............ ........... ............ 83 10.12.4 vreg_en pin ............................................................................................................ .............. 83 11 product reliability tests ................................................................................................... ........................... 84 12 product reliability tests for bluecore4-rom plug-n-go automotive ..................................................... 85 12.1 aec-q100 .............. .............. .............. .............. .............. ........... ........... ............ .......... ........................... 85 13 application schematic ....................................................................................................... ........................... 86 14 package dimensions ..... .............. .............. .............. .............. ........... ........... ............ ........... .......................... 87 14.1 10 x 10 lfbga 96-ball 1.6mm package ............ .......................................................................... ........ 87 15 ordering information ........................................................................................................ ............................ 88 15.1 bluecore4-rom plug-n-go .............................. ..................................................................... ................ 88 16 contact information ......................................................................................................... ............................. 89 17 document references .............. ........................................................................................... ......................... 90 18 terms and definitions ....................................................................................................... ........................... 91 19 document history ............................................................................................................ ............................. 94
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 5 of 94 _?`??qjolj=m??j?jd??= data sheet list of figures figure 3.1 bluecore4-rom plug-n-go 10 x 10mm lfbga pa ckage ........................................................... 9 figure 7.1 bluecore4-rom plug-n-go de vice diagram ............................................................................. 32 figure 9.1 bluecore hci stack............................... .................................................................... ................. 36 figure 9.2 bluecore rfcomm stack........................... ..................................................................... .......... 39 figure 9.3 virtual machine ....... ............................................................................................... ..................... 41 figure 9.4 hid stack............................................................................................................ ........................ 42 figure 10.1 circuit for rf_connect ......................... ..................................................................... ............. 44 figure 10.2 circuit rf_in ....................................................................................................... ....................... 45 figure 10.3 tcxo clock accuracy .............................. ................................................................... ............... 46 figure 10.4 actual allowable clock presence delay on xtal_in vs. ps key setting.................................. 47 figure 10.5 crystal driver circuit . ............................................................................................. ..................... 49 figure 10.6 crystal equivalent circuit................. ......................................................................... .................. 49 figure 10.7 crystal load capacitance and series resist ance limits with crystal frequency...................... 53 figure 10.8 crystal driver transconductance vs. driver le vel register setting ........ .............. ............... ...... 54 figure 10.9 crystal driver negative resistance as a func tion of drive level setting . ............ ............... ...... 55 figure 10.10 universal asynchronous receiver ............ ........................................................................ .......... 56 figure 10.11 break signal....................................................................................................... ......................... 57 figure 10.12 uart bypass architecture .................... ....................................................................... .............. 58 figure 10.13 usb connections for self-powered mode..... .............. .............. ............ ........... ........... ........... .... 60 figure 10.14 usb connections for bus-powered mode........ .............. .............. ........... ............ ........... ......... ... 61 figure 10.15 usb_detach and usb_wake_u p signal............... .............. .............. .............. ............... ...... 62 figure 10.16 write operation.................................................................................................... ....................... 65 figure 10.17 read operation....... .............................................................................................. ...................... 65 figure 10.18 bluecore4-rom plug-n-go as pcm interface master ............................................................... 67 figure 10.19 bluecore4-rom plug-n-go as pcm interface sl ave ................................................................. 67 figure 10.20 long frame sync (shown with 8-bit compande d sample) .......... .............. .............. ............ ...... 68 figure 10.21 short frame sync (shown with 16-bit sample) ........................................................................ .. 68 figure 10.22 multi-slot operation with two slots and 8-bit companded sample s ............. ........... ............ ...... 69 figure 10.23 gci interface...................................................................................................... ......................... 69 figure 10.24 16-bit slot length and sample formats ...... ........................................................................ ....... 70 figure 10.25 pcm master timing long frame sync.................................................................................. ..... 72 figure 10.26 pcm master timing short frame sync ......... ........................................................................ ..... 72 figure 10.27 pcm slave timing long frame sync.......... .............. .............. ........... ........... ........... ............ ...... 74 figure 10.28 pcm slave timing short frame sync .................................................................................. ...... 74 figure 10.29 example eeprom connecti on ............. .............. .............. .............. .............. ........... .......... ........ 79 figure 10.30 example txco enable or function........... ......................................................................... ...... 80 figure 13.1 application circuit for radio characteristics specification ......................................................... 86 figure 14.1 bluecore4-rom plug-n-go 96-ball lfbga 1. 6mm package dimensions ................................ 87 list of tables table 10.1 external clock specifications........................................................................................ .............. 46 table 10.2 ps key values for cdma/3g phone tcxo freq uencies ............ .............. .............. ............ ...... 48 table 10.3 crystal specification ................................................................................................ ................... 50 table 10.4 possible uart settings............................................................................................... ............... 56 table 10.5 standard baud rates.................................................................................................. ................ 57 table 10.6 usb interface component values ............... ........................................................................ ....... 60 table 10.7 instruction cycle for an spi transaction............................................................................. ........ 64 table 10.8 pcm master timing .................................................................................................... ................ 71
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 6 of 94 _?`??qjolj=m??j?jd??= data sheet table 10.9 pcm slave timing ..................................................................................................... ................. 73 table 10.10 pskey_pcm_config 32 description ........ .............. .............. .............. .............. ........... ........... .77 table 10.11 pskey_pcm_low_ji tter_config description.... .............. .............. .............. ............... ...... 77 table 10.12 pin states of bluecore4-rom plug-n-go on re set ................................................................... 82 list of equations equation 10.1 load capacitance ......... .............. .............. .............. .............. ........... ........... ........... ..................... 50 equation 10.2 trim capacitance.......... .............. .............. .............. .............. ........... ........... .......... ...................... 51 equation 10.3 frequency trim.......... .............. .............. .............. .............. ........... ........... ............ ....................... 51 equation 10.4 pullability.............. .............. .............. .............. .............. ............ ........... .......... .............................. 51 equation 10.5 transconductance required for oscillation ............ .............. .............. ........... ........... ........... ....... 52 equation 10.6 equivalent negative re sistance ............... .............. .............. .............. .............. ............. ............. 52 equation 10.7 baud rate ............... .............. .............. .............. .............. ........... ............ ........... .......................... 57 equation 10.8 pcm_clk frequency when be ing generated using the internal 48mhz clock..... ............ ...... 75 equation 10.9 pcm_sync frequency relative to pcm_clk ... .............. .............. .............. ........... ............ ...... 75
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 7 of 94 status information _?`??qjolj=m??j?jd??= data sheet 1 status information the status of this data sheet is advance information . csr product data sheets progress according to the following format: advance information information for designers concerning csr product in developm ent. all values specified ar e the target values of the design. minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. all detailed specifications including pinouts and electr ical specifications may be changed by csr without notice. pre-production information pinout and mechanical dimension specifications finalised. all values specified are the tar get values of the design. minimum and maximum values specified are only given as gu idance to the final specific ation limits and must not be considered as the final values. all electrical specifications ma y be changed by csr without notice. production information final data sheet including the guaranteed minimum and ma ximum limits for the electrical specifications. production data sheets supersede all previous document versions. life support policy and use in safety-critical applications csr's products are not authorised for use in life-support or sa fety-critical applications. use in such applications is done at the sole discretion of the cust omer. csr will not warrant the use of its devices in such applications. rohs compliance bluecore4-rom plug-n-go devices meet the requirements of directive 2002/95 /ec of the european parliament and of the council on the restrictio n of hazardous substance (rohs). trademarks, patents and licenses unless otherwise stated, words and logos marked with ? or ? are trademarks registered or owned by cambridge silicon radio limited or its affiliates. bluetooth ? and the bluetooth logos are trademark s owned by bluetooth sig, inc. and licensed to csr. other pr oducts, services and names used in this document may have been trademarked by their respective owners. the publication of this information does not imply that any license is granted under any pat ent or other rights owned by cambridge silicon radio limited. csr reserves the right to make technical changes to its products as part of its development programme. while every care has been taken to ensure the accuracy of the contents of this document, csr cannot accept responsibility for any errors.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 8 of 94 key features _?`??qjolj=m??j?jd??= data sheet 2 key features radio ? direct 50 ? connection to a common tx/rx antenna ? bluetooth v2.0+edr specification compliant ? extensive built-in self-test minimises production test time ? no external trimming is required in production ? antenna matching and filtering within ic transmitter ? +6dbm rf transmit power with level control from on-chip 6-bit dac over a dynamic range >30db ? class 2 and class 3 support without the need for an external power amplifier or tx/rx switch receiver ? integrated channel filters ? digital demodulator for improved sensitivity and co-channel rejection ? real time digitised rssi available on hci interface ? fast agc for enhanced dynamic range synthesiser ? fully integrated synthesiser requires no external vco varactor diode, resonator or loop filter ? compatible with crystals between 8 and 32mhz (in multiples of 250khz) or an external clock ? accepts 7.68, 14.4, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4mhz tcxo frequencies for gsm and cdma devices with sinusoidal or logic level signals auxiliary features ? crystal oscillator with built-in digital trimming ? power management includes digital shutdown, and wake up commands with an integrated low power oscillator for ultra low park/sniff/hold mode ? clock request output to control external clock ? on-chip linear regulator, producing 1.8v output from 2.2v to 4.2v input ? power on reset cell detects low supply voltage ? arbitrary power supply sequencing permitted ? 8-bit adc and dac available to application baseband and software ? internal programmed 4m bit rom for complete system solution ? 48kbyte on-chip ram allows full speed bluetooth data transfer, mixed voice and data, plus full seven slave piconet operation ? logic for forward error correction, header error control, access code correlation, demodulation, crc, encryption bitstream generation, whitening and transmit pulse shaping ? transcoders for a-law, -law and linear voice from host and a-law, -law and cvsd voice over air physical interfaces ? synchronous serial interface up to 4m baud for system debugging ? uart interface with programmable baud rate up to 3m baud with an optional bypass mode ? full speed usb interface supports ohci and uhci host interfaces. compliant with usb v2.0 ? synchronous bi-directional serial programmable audio interface ? optional i 2 c? compatible interface bluetooth stack csr's bluetooth protocol stack runs on-chip in a variety of configurations: ? standard hci (uart or usb) ? fully embedded to rfcomm ? customer specific build s with embedded application code package options ? 96-ball lfbga 10 x 10 x 1.6mm 0.8mm pitch
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 9 of 94 package information _?`??qjolj=m??j?jd??= data sheet 3 package information 3.1 bc41b143a pinout diagram figure 3.1: bluecore4-rom plug-n-go 10 x 10mm lfbga package
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 10 of 94 package information _?`??qjolj=m??j?jd??= data sheet 3.2 bc41b143a-ann-e4 device terminal functions radio ball pad type description rf_in d2 analogue single ended receiver input pio[0]/rxen d3 bi-directional with programmable strength internal pull-up/down programmable input/output line pio[1]/txen c4 bi-directional with programmable strength internal pull-up/down programmable input/output line bal_match a1 analogue tie to vss_radio rf_connect b1 analogue 50 ? rf matched i/o aux_dac c2 analogue voltage dac output synthesiser and oscillator ball pad type description xtal_in l3 analogue for crystal or external clock input xtal_out l4 analogue drive for crystal pcm interface ball pad type description pcm_out g10 cmos output, tristatable with weak internal pull-down synchronous data output pcm_in h11 cmos input, with weak internal pull-down synchronous data input pcm_sync g11 bi-directional with weak internal pull-down synchronous data sync pcm_clk h10 bi-directional with weak internal pull-down synchronous data clock usb and uart ball pad type description uart_tx j10 cmos output, tri-state with weak internal pull-up uart data output active low uart_rx j11 cmos input with weak internal pull-down uart data input active low (idle status high) uart_rts l11 cmos output, tristatable with weak internal pull-up uart request to send active low uart_cts k11 cmos input with weak internal pull-down uart clear to send active low usb_dp l9 bi-directional usb data plus with selectable internal 1.5k ? pull-up resistor usb_dn l8 bi-directional usb data minus
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 11 of 94 package information _?`??qjolj=m??j?jd??= data sheet test and debug ball pad type description reset f9 cmos input with weak internal pull-down reset if high. input debounced so must be high for >5ms to cause a reset resetb g9 cmos input with weak internal pull-up reset if low. input debounced so must be low for >5ms to cause a reset spi_csb c10 cmos input with weak internal pull-up chip select for serial peripheral interface, active low spi_clk d10 cmos input with weak internal pull-down serial peripheral interface clock spi_mosi d11 cmos input with weak internal pull-down serial peripheral interface data input spi_miso c11 cmos output, tristatable with weak internal pull-down serial peripheral interface data output test_en e9 cmos input with strong internal pull-down for test purposes only (leave unconnected) flash_en b10 no connect not available for bluecore4-rom plug-n-go
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 12 of 94 package information _?`??qjolj=m??j?jd??= data sheet pio port ball pad type description pio[2] c3 bi-directional with programmable strength internal pull-up/down programmable input/output line pio[3] b2 bi-directional with programmable strength internal pull-up/down programmable input/output line pio[4] h9 bi-directional with programmable strength internal pull-up/down programmable input/output line pio[5] j8 bi-directional with programmable strength internal pull-up/down programmable input/output line pio[6] k8 bi-directional with programmable strength internal pull-up/down programmable input/output line pio[7] k9 bi-directional with programmable strength internal pull-up/down programmable input/output line pio[8] b3 bi-directional with programmable strength internal pull-up/down programmable input/output line pio[9] b4 bi-directional with programmable strength internal pull-up/down programmable input/output line pio[10] a4 bi-directional with programmable strength internal pull-up/down programmable input/output line pio[11] a5 bi-directional with programmable strength internal pull-up/down programmable input/output line aio[0] k5 bi-directional programmable input/output line aio[1] j6 bi-directional programmable input/output line aio[2] k7 bi-directional programmable input/output line
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 13 of 94 package information _?`??qjolj=m??j?jd??= data sheet (a) positive supply for pio[3:0] and pio[11:8] (b) positive supply for sp i/pcm ports and pio[7:4] power supplies and control ball pad type description vreg_in l7 regulator input linear regulator voltage input vreg_en j2 digital input active high, regulator enable pin with internal pull-up vdd_usb l10 vdd positive supply for uart/usb and aio ports vdd_pio a3 vdd positive supply for pio and aux dac (a) vdd_pads e11 vdd positive supply for all other digital input/output ports (b) vdd_dig l6 regulator output positive 1.8v supply output for vdd_mem and vdd_core vdd_mem b11, k6 vdd positive supply for internal memory vdd_core f11 vdd positive supply for internal digital circuitry vdd_radio e3 vdd positive supply for rf circuitry vdd_ana l5 vdd/regulator output positive supply for analogue circuitry and 1.8v regulated output vdd_balun f1 vdd positive supply for balun vss_pads a2, e10, k10 vss ground connection for input/output vss_mem d9, j9 vss ground connections for aio and extended pio ports vss_core f10 vss ground connection for internal digital circuitry vss_radio e2, f3, g2 vss ground connections for rf circuitry vss_vco g3, h2 h3 vss ground connections for vco and synthesiser vss_ana k4 vss ground connection for analogue circuitry vss_balun g1,j1, k1 vss ground connection for balun unconnected terminals ball description n/c a6, a7, a8, a9, a10, a11, b5, b6, b7, b8, b9, c1, c5, c6, c7, c8, c9, d1, e1, f2, h1, j3, j4, j5, j7, k2, k3, l1, l2 leave unconnected
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 14 of 94 electrical characteristics _?`??qjolj=m??j?jd??= data sheet 4 electrical characteristics (a) typical figures are given for rf performance between -40c and +85c. (b) the device will operate without damage with vreg_in as high as 5.6v, however the rf performance is not guaranteed above 4.2v. absolute maximum ratings rating min max storage temperature -40c +150c supply voltage: vdd_radio, vdd_ana, vdd_bal and vdd_core -0.4v 2.2v supply voltage: vdd_mem, vdd_pads, vdd_pio and vdd_usb -0.4v 3.7v supply voltage: vreg_in -0.4v 5.6v other terminal volt ages vss-0.4v vdd+0.4v recommended operating conditions operating condition min max operating temperature range -40c +85c guaranteed rf performance range (a) -25c +85c supply voltage: vdd_radio, vdd_ana and vdd_core 1.7v 1.9v supply voltage: vdd_mem, vdd_pads, vdd_pio and vdd_usb 1.7v 3.6v supply voltage: vreg_in 2.2v 4.2v (b)
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 15 of 94 electrical characteristics _?`??qjolj=m??j?jd??= data sheet (a) for optimum performance, the vdd_ana ball adjacen t to vreg_in should be used for regulator output, (b) regulator output connected to 47nf pure and 4.7 f 2.2 ? esr capacitors. (c) frequency range is 100hz to 100khz. (d) 1ma to 70ma pulsed load. (e) operation up to 5.6v is permissible without damage and without the output voltage rising sufficiently to damage the rest of bluecore4-rom plug-n-go, but output regulation and other specifications are no longer guaranteed at input voltages in excess of 4.2v. (f) low power mode is entered and exited automatica lly when the chip enters/leaves deep sleep mode. (g) regulator is disabled when vreg_en is pul led low. it is also disabled when vreg_i n is either open circuit or driven to the same voltage as vdd_ana. input/output terminal ch aracteristics (supply) linear regulator min typ max unit normal operation output voltage (a) (i load = 70 ma) 1.70 1.78 1.85 v temperature coefficient -250 - +250 ppm/c output noise (b) (c) -- 1mv rms load regulation (i load < 100 ma) - - 50 mv/a settling time (b) (d) -- 50 s maximum output current 140 - - ma minimum load current 5 - - a input voltage - - 4.2 (e) v dropout voltage (i load = 70 ma) - - 350 mv quiescent current (excluding ioad, i load < 1ma) 25 35 50 a low power mode (f) quiescent current (excluding ioad, i load < 100 a) 4 7 10 a disabled mode (g) quiescent current 1.5 2.5 3.5 a
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 16 of 94 electrical characteristics _?`??qjolj=m??j?jd??= data sheet (a) internal usb pull-up disabled input/output terminal characteristics (digital) digital terminals min typ max unit input voltage levels v il input logic level low 2.7v vdd 3.0v -0.4 - +0.8 v 1.7v vdd 1.9v -0.4 - +0.4 v v ih input logic level high 0.7vdd - vdd+0.4 v output voltage levels v ol output logic level low, --0.2v (l o = 4.0ma), 2.7v vdd 3.0v v ol output logic level low, --0.4v (l o = 4.0ma), 1.7v vdd 1.9v v oh output logic level high, vdd-0.2 - - v (l o = -4.0ma), 2.7v vdd 3.0v v oh output logic level high, vdd-0.4 - - v (l o = -4.0ma), 1.7v vdd 1.9v input and tri-state current with: strong pull-up -100 -40 -10 a strong pull-down +10 +40 +100 a weak pull-up -5.0 -1.0 -0.2 a weak pull-down +0.2 +1.0 +5.0 a i/o pad leakage current -1 0 +1 a c i input capacitance 1.0 - 5.0 pf input/output terminal characteristics (usb) usb terminals min typ max unit vdd_usb for correct usb operation 3.1 3.6 v input threshold v il input logic level low - - 0.3vdd_usb v v ih input logic level high 0.7vdd_usb - - v input leakage current vss_pads < vin < vdd_usb (a) -1 1 5 a c i input capacitance 2.5 - 10.0 pf output voltage levels to correctly terminated usb cable v ol output logic level low 0.0 - 0.2 v v oh output logic level high 2.8 - vdd_usb v
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 17 of 94 electrical characteristics _?`??qjolj=m??j?jd??= data sheet (a) adc is accessed through the vm function. the sample rate given is achieved as part of this function. (a) specified for an output voltage between 0.2v and vdd_pio -0.2v. output is high impedance when chip is in deep sleep mode. input/output terminal characteristics (reset) power-on reset min typ max unit vdd_core falling threshold 1.40 1.50 1.60 v vdd_core rising threshold 1.50 1.60 1.70 v hysteresis 0.05 0.10 0.15 v input/output termi nal characteristics (auxilliary adc) auxiliary adc min typ max unit resolution - - 8 bits input voltage range 0 - vdd_ana v (lsb size = vdd_ana/255) accuracy inl -1 - 1 lsb (guaranteed monotonic) dnl 0 - 1 lsb offset -1 - 1 lsb gain error -0.8 - 0.8 % input bandwidth - 100 - khz conversion time - 2.5 - s sample rate (a) - - 700 samples/s input/output termi nal characteristics (auxilliary dac) auxiliary dac min typ max unit resolution --8bits average output step size (a) 12.5 14.5 17.0 mv output voltage monotonic (a) voltage range (i o =0ma) vss_pads - vdd_pio v current range -10.0 - +0.1 ma minimum output voltage (i o =100 a) 0.0 - 0.2 v maximum output voltage (i o =10ma) vdd_pio-0.3 - vdd_pio v high impedance leakage current -1 - +1 a offset -220 - +120 mv integral non-linearity (a) -2 - +2 lsb settling time (50pf load) - - 10 s
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 18 of 94 electrical characteristics _?`??qjolj=m??j?jd??= data sheet (a) integer multiple of 250khz (b) the difference between the internal capacitance at minimu m and maximum settings of the internal digital trim. (c) xtal frequency = 16mhz; xtal c0 = 0.75pf; xtal load capacitance = 8.5pf. (d) clock input can be any frequency between 8mhz and 40mhz in steps of 250khz plus cdma/3g tcxo frequencies of 7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4mhz. (e) clock input can be either sinusoidal or square wave. if th e peaks of the signal are below vss_ana or above vdd_ana. a dc blocking capacitor is required between the signal and xtal_in. input/output terminal characteristics (clocks) crystal oscillator min typ max unit crystal frequency (a) 8.0 - 32.0 mhz digital trim range (b) 5.0 6.2 8.0 pf trim step size (b) -0.1- pf transconductance 2.0 - - ms negative resistance (c) 870 1500 2400 ? external clock input frequency (d) 7.5 - 40.0 mhz clock input level (e) 0.2 - vdd_ana v pk-pk allowable jitter - - 15 ps rms xtal_in input impedance - - - k ? xtal_in input capacitance - 7 - pf
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 19 of 94 electrical characteristics _?`??qjolj=m??j?jd??= data sheet 4.1 power consumption typical average current consumption vdd=1.8v temperature = +20c output power = +4dbm mode average unit sco connection hv3 (30ms interval sniff mode) (slave) 21 ma sco connection hv3 (30ms interv al sniff mode) (master) 21 ma sco connection hv3 (no sniff mode) (slave) 28 ma sco connection hv1 (slave) 42 ma sco connection hv1 (master) 42 ma acl data transfer 115.2kbps uart no traffic (master) 5 ma acl data transfer 115.2kbps uart no traffic (slave) 22 ma acl data transfer 720kbps uart (master or slave) 45 ma acl data transfer 720kbps usb (master or slave) 45 ma acl connection, sniff mode 40ms interval, 38.4kbps uart 3.2 ma acl connection, sniff mode 1.28s interval, 38.4kbps uart 0.45 ma parked slave, 1.28s beacon interval, 38.4kbps uart 0.55 ma standby mode (connected to host, no rf activity) 47.0 a reset (reset high or resetb low) 15.0 a typical peak current at +20c device activity/state current (ma) peak current during cold boot (100ms sampling interval) - peak tx current average across burst) - peak rx current - average rx current across burst - conditions vreg_in, vdd_pio, vdd_pads - host interface - baud rate - clock source - output power - receive sensitivity - device mode - packet type -
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 20 of 94 radio characteristics - basic data rate _?`??qjolj=m??j?jd??= data sheet 5 radio characteristics - basic data rate 5.1 temperature +20c 5.1.1 transmitter (a) the bluecore4-rom plug-n-go firmware ma intains the transmit power to be within the bluetooth specification v2.0+edr limits. (b) measurement made using a pskey_lc_max_tx_power setting corresponds to a pskey_lc_power_table power table entry of 63 (c) class 2 rf transmit power range, bluetooth specification v2.0+edr (d) to some extent these parameters are dependent on the matc hing circuit used, and its behaviour over temperature. therefore these parameters may be beyond csr's direct control. (e) resolution guaranteed over the range -5db to -25db relative to maximum power for tx level > 20 (f) measured at f 0 = 2441mhz (g) up to three exceptions are allowed in v2.0+edr of the bluetooth specification. bluecor e4-rom plug-n-go is guaranteed to meet the acp performance as specifi ed by the bluetooth specification v2.0+edr radio characteristics vdd = 1.8v temperature = +20c min typ max bluetooth specification unit maximum rf transmit power (a) (b) tbd 2.5 - -6 to +4 (c) dbm rf power variation over temperature range with compensation enabled () (d) -1.5tbd - db rf power variation over temperature range with compensation disabled () (d) -2.5tbd - db rf power control range 25 35 - 16 db rf power range control resolution (e) - 0.5 1.2 - db 20db bandwidth for modulated carrier - 780 1000 1000 khz adjacent channel transmit power - -40 -20 -20 dbm f = f 0 2mhz (f) (g) adjacent channel transmit power - -45 -40 -40 dbm f = f 0 3mhz (f) (g) adjacent channel transmit power -50 -40 -40 dbm f = f 0 > 3mhz (f) (g) ? f1avg maximum modulation 140 165 175 140 BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 21 of 94 radio characteristics - basic data rate _?`??qjolj=m??j?jd??= data sheet (a) integrated in 200khz bandwidth and then normalised to 1hz bandwidth (b) integrated in 1.2mhz bandwidth and then normalised to 1hz bandwidth (c) integrated in 1mhz bandwidth and then normalised to 1hz bandwidth (d) integrated in 30khz bandwidth and then normalised to 1hz bandwidth (e) integrated in 5mhz bandwidth and then normalised to 1hz bandwidth radio characteristics vdd = 1.8v temperature = +20c frequency (ghz) min typ max cellular band unit emitted power in cellular bands measured at rf_connect. output power 4dbm 0.869 - 0.894 (a) - tbd tbd gsm 850 dbm / hz 0.869 - 0.894 (b) - tbd tbd cdma 850 0.925 - 0.960 (a) - tbd tbd gsm 900 1.570 - 1.580 (c) - tbd tbd gps 1.805 - 1.880 (a) -tbdtbd gsm 1800 / dcs 1800 1.930 - 1.990 (d) - tbd tbd pcs 1900 1.930 - 1.990 (b) - tbd tbd gsm 1900 1.930 - 1.990 (a) - tbd tbd cdma 1900 2.110 - 2.170 (b) - tbd tbd w-cdma 2000 2.110 - 2.170 (e) - tbd tbd w-cdma 2000
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 22 of 94 radio characteristics - basic data rate _?`??qjolj=m??j?jd??= data sheet 5.1.2 receiver (a) up to five exceptions are allowed in v2.0+edr of the bluetooth specification. bluecor e4-rom plug-n-go is guaranteed to meet the c/i performance as specified by the bluetooth specification v2.0+edr. (b) measured at f = 2441mhz (c) measured at f1 - f2 = 5mhz. measurement is performed in accordance with bluetooth rf test rcv/ca/05/c., i.e., wanted signal at -64dbm. (d) measured at rf_connect. integrated in 100khz bandwidth and normalised to 1hz. figure is typically below tbddbm/hz except for peaks of tbddbm at 1.6ghz , tbddbm inband at 2.4ghz and tbddbm at 3.2ghz. radio characteristics vdd = 1.8v temperature = +20c frequency (ghz) min typ max bluetooth specification unit sensitivity at 0.1% ber for all packet types 2.402 - -84 tbd -70 dbm 2.441 - -84 tbd 2.480 - -86 tbd maximum received signal at 0.1% ber -20 tbd - -20 dbm frequency (mhz) min typ max bluetooth specification unit continuous power required to block bluetooth reception (for input power of -67dbm with 0.1% ber) measured at the unbalanced port of the balun. 30-2000 -10 tbd - -10 dbm 2000-2400 -27 tbd - -27 2500-3000 -27 tbd - -27 3000-3300 -10 tbd - -10 c/i co-channel - 6 11 11 db adjacent channel selectivity c/i - -5 0 0 db f = f 0 + 1mhz (a) (b) adjacent channel selectivity c/i - -4 0 0 db f = f 0 - 1mhz (a) (b) adjacent channel selectivity c/i - -38 -30 -30 db f = f 0 + 2mhz (a) (b) adjacent channel selectivity c/i - -23 -20 -20 db f = f 0 - 2mhz (a) (b) adjacent channel selectivity c/i - -45 -40 -40 db f f 0 + 3mhz (a) (b) adjacent channel selectivity c/i - -44 -40 -40 db f f 0 -5mhz (a) (b) adjacent channel selectivity c/i - -22 -9 -9 db f = f image (a) (b) maximum level of intermodulation interferers (c) -39 tbd - -39 dbm spurious output level (d) - tbd - - dbm/hz
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 23 of 94 radio characteristics - basic data rate _?`??qjolj=m??j?jd??= data sheet (a) tbd dbm if f blocking < 0.831ghz radio characteristics vdd = 1.8v temperature = +20c frequency (ghz) min typ max cellular band unit continuous power in cellular bands required to block bluetooth reception (for input power of -67dbm with 0.1% ber) measured at rf_connect. 0.824 - 0.849 - tbd (a) - gsm 850 dbm 0.824 - 0.849 - tbd - cdma 850 0.880 - 0.915 - tbd - gsm 900 1.710 - 1.785 - tbd - gsm 1800 / dcs 1800 1.850 - 1.910 - tbd - gsm 1900 / pcs 1900 1.850 - 1.910 - tbd - cdma 1900 1.920 - 1.980 - tbd - w-cdma 2000 continuous power in cellular bands required to block bluetooth reception (for input power of -72dbm with 0.1% ber) measured at rf_connect. tbd 0.824 - 0.849 - tbd - gsm 850 dbm 0.824 - 0.849 - tbd - cdma 850 0.880 - 0.915 - tbd - gsm 900 1.710 - 1.785 - tbd - gsm 1800 / dcs 1800 1.850 - 1.910 - tbd - gsm 1900 / pcs 1900 1.850 - 1.910 - tbd - cdma 1900 1.920 - 1.980 - tbd - w-cdma 2000
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 24 of 94 radio characteristics - basic data rate _?`??qjolj=m??j?jd??= data sheet 5.2 temperature -40c 5.2.1 transmitter (a) bluecore4-rom plug-n-go firmware maintains the transmit po wer to be within the bluetooth specification v2.0+edr limits. (b) class 2 rf transmit power range, bluetooth specification v2.0+edr (c) measured at f 0 = 2441mhz (d) up to three exceptions are allowed in v2.0+edr of the bluetooth specification. 5.2.2 receiver radio characteristics vdd = 1.8v temperature = -40c min typ max bluetooth specification unit maximum rf transmit power (a) tbd 3.5 - -6 to +4 (b) dbm rf power control range 25 35 - 16 db rf power range control resolution - 0.5 - - db 20db bandwidth for modulated carrier - 780 1000 1000 khz adjacent channel transmit power - -40 -20 -20 dbm f = f 0 2mhz (c) (d) adjacent channel transmit power - -45 -40 -40 dbm f = f 0 3mhz (c) (d) ? f1avg maximum modulation 140 165 175 140< ? f1avg<175 khz ? f2max minimum modulation 115 151 - 115 khz ? f2avg/ ? f1avg 0.8 0.97 - 0.80 - initial carrier frequency tolerance - 10 75 75 khz drift rate - 7 20 20 khz/50 s drift (single slot packet) - 8 25 25 khz drift (five slot packet) - 12 40 40 khz radio characteristics vdd = 1.8v temperature = -40c frequency (ghz) min typ max bluetooth specification unit sensitivity at 0.1% ber for all packet types 2.402 - -86 tbd -70 dbm 2.441 - -86 tbd 2.480 - -88 tbd maximum received signal at 0.1% ber -20 tbd - -20 dbm
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 25 of 94 radio characteristics - basic data rate _?`??qjolj=m??j?jd??= data sheet 5.3 temperature -25c 5.3.1 transmitter (a) bluecore4-rom plug-n-go firmware maintains the transmit po wer to be within the bluetooth specification v2.0+edr limits. (b) class 2 rf transmit power range, bluetooth specification v2.0+edr (c) measured at f 0 = 2441mhz (d) up to three exceptions are allowed in v2.0+edr of the bluetooth specification. 5.3.2 receiver radio characteristics vdd = 1.8v temperature = -25c min typ max bluetooth specification unit maximum rf transmit power (a) tbd 3.0 - -6 to +4 (b) dbm rf power control range 25 35 - 16 db rf power range control resolution - 0.5 - - db 20db bandwidth for modulated carrier - 780 1000 1000 khz adjacent channel transmit power - -40 -20 -20 dbm f = f 0 2mhz (c) (d) adjacent channel transmit power - -45 -40 -40 dbm f = f 0 3mhz (c) (d) ? f1avg maximum modulation 140 165 175 140< ? f1avg<175 khz ? f2max minimum modulation 115 151 - 115 khz ? f2avg/ ? f1avg 0.8 0.97 - 0.80 - initial carrier frequency tolerance - 8 75 75 khz drift rate - 7 20 20 khz/50 s drift (single slot packet) - 8 25 25 khz drift (five slot packet) - 12 25 40 khz radio characteristics vdd = 1.8v temperature = -25c frequency (ghz) min typ max bluetooth specification unit sensitivity at 0.1% ber for all packet types 2.402 - -86 tbd -70 dbm 2.441 - -86 tbd 2.480 - -87 tbd maximum received signal at 0.1% ber -2 0 tbd - -20 dbm
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 26 of 94 radio characteristics - basic data rate _?`??qjolj=m??j?jd??= data sheet 5.4 temperature +85c 5.4.1 transmitter (a) bluecore4-rom plug-n-go firmware maintains the transmit po wer to be within the bluetooth specification v2.0+edr limits (b) class 2 rf transmit power range, bluetooth specification v2.0+edr (c) measured at f 0 = 2441mhz (d) up to three exceptions are allowed in v2.0+edr of the bluetooth specification 5.4.2 receiver radio characteristics vdd = 1.8v temperature = +85c min typ max bluetooth specification unit maximum rf transmit power (a) tbd 0 - -6 to +4 (b) dbm rf power control range 25 35 - 16 db rf power range control resolution - 0.5 - - db 20db bandwidth for modulated carrier - 780 1000 1000 khz adjacent channel transmit power - -40 -20 -20 dbm f = f 0 2mhz (c) (d) adjacent channel transmit power - -45 -40 -40 dbm f = f 0 3mhz (c) (d) ? f1avg maximum modulation 140 165 175 140< ? f1avg<175 khz ? f2max minimum modulation 115 148 - 115 khz ? f2avg/ ? f1avg 0.8 0.97 - 0.80 - initial carrier frequency tolerance - 7 75 75 khz drift rate - 7 20 20 khz/50 s drift (single slot packet) - 8 25 25 khz drift (five slot packet) - 9 40 40 khz radio characteristics vdd = 1.8v temperature = +85c frequency (ghz) min typ max bluetooth specification unit sensitivity at 0.1% ber for all packet types 2.402 - -81 tbd -70 dbm 2.441 - -81 tbd 2.480 - -82 tbd maximum received signal at 0.1% ber -20 tbd - -20 dbm
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 27 of 94 radio characteristics - enhanced data rate _?`??qjolj=m??j?jd??= data sheet 6 radio characteristics - enhanced data rate 6.1 temperature +20c 6.1.1 transmitter (a) bluecore4-rom plug-n-go firmware keeps rf transmit power within the bluetooth v2.0+edr specification limits (b) class 2 rf transmit power range, bluetooth v2.0+edr specification (c) measurement methods are in accordance with t he bluetooth v2.0+edr rf test specification (d) modulation accuracy utilises differential error vector m agnitude (devm) with tracking of the carrier frequency drift. (e) the bluetooth specification values ar e for 8dpsk modulation (values for the /4 dqpsk modulation are less stringent) notes: results shown are referenced to the unbalanced port of the balun. radio characteristics vdd = 1.8v temperature = +20c min typ max bluetooth specification unit maximum rf transmit power (a) - 6 - -6 to +4 (b) dbm relative transmit power (c) - -1 - -4 to +1 db carrier frequency stability (c) -3- 10 khz modulation accuracy (c) (d) rms devm - 10 - 13 (e) % 99% devm - 15 - 20 (e) % peak devm - 20 - 25 (e) %
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 28 of 94 radio characteristics - enhanced data rate _?`??qjolj=m??j?jd??= data sheet 6.1.2 receiver (a) measurements methods are in accordance with t he bluetooth v2.0+edr rf test specification (b) up to five exceptions are allowed in the bluetooth v2.0 +edr rf test specification.bluecore4-rom plug-n-go is guaranteed to meet the c/i performance as specified by the bluetooth v2.0 +edr rf test specification (c) measured at f 0 = 2405mhz, 2441mhz, 2477mhz notes: results shown are referenced to the unbalanced port of the balun. radio characteristics vdd = 1.8v temperature = +20c modulation min typ max bluetooth specification unit sensitivity at 0.01% ber (a) /4 dqpsk - -86 - -70 dbm 8dpsk - -79 - -70 dbm maximum received signal at 0.1% ber (a) /4 dqpsk - -6 - -20 dbm 8dpsk - -7 - -20 dbm c/i co-channel at 0.1% ber (a) /4 dqpsk - +11 - +13 db 8dpsk - +19 - +21 db adjacent channel selectivity /4 dqpsk - -8 - 0db c/i f=f 0 +1mhz (a) (b) (c) 8dpsk - -2 - +5 db adjacent channel selectivity /4 dqpsk - -8 - 0db c/i f=f 0 -1mhz (a) (b) (c) 8dpsk - -2 - +5 db adjacent channel selectivity /4 dqpsk - -35 - -30 db c/i f=f 0 +2mhz (a) (b) (c) 8dpsk - -35 - -25 db adjacent channel selectivity /4 dqpsk - -23 - -20 db c/i f=f 0 -2mhz (a) (b) (c) 8dpsk - -19 - -13 db adjacent channel selectivity /4 dqpsk - -43 - -40 db c/i f f 0 +3mhz (a) (b) (c) 8dpsk - -40 - -33 db adjacent channel selectivity /4 dqpsk - -43 - -40 db c/i f f 0 5mhz (a) (b) (c) 8dpsk - -38 - -33 db adjacent channel selectivity /4 dqpsk - -17 - -7 db c/i f=f image (a) (b) (c) 8dpsk - -10 - 0db
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 29 of 94 radio characteristics - enhanced data rate _?`??qjolj=m??j?jd??= data sheet 6.2 temperature -40c 6.2.1 transmitter (a) bluecore4-rom plug-n-go firmware keeps rf transmit power within the bluetooth v2.0+edr specification limits (b) class 2 rf transmit power range, bluetooth v2.0+edr specification (c) measurements methods are in accordance with t he bluetooth v2.0+edr rf test specification (d) modulation accuracy utilises differential error vector m agnitude (devm) with tracking of the carrier frequency drift. (e) the bluetooth specification values ar e for 8dpsk modulation (values for the /4 dqpsk modulation are less stringent) notes: results shown are referenced to the unbalanced port of the balun. 6.2.2 receiver (a) measurements methods are in accordance with t he bluetooth v2.0 + edr rf test specification notes: results shown are referenced to the unbalanced port of the balun. radio characteristics vdd = 1.8v temperature = -40c min typ max bluetooth specification unit maximum rf transmit power (a) - 8 - -6 to +4 (b) dbm relative transmit power (c) - -1 - -4 to +1 db carrier frequency stability (c) -3- 10 khz modulation accuracy (c) (d) rms devm - 10 - 13 (e) % 99% devm - 15 - 20 (e) % peak devm - 20 - 25 (e) % radio characteristics vdd = 1.8v temperature = -40c modulation min typ max bluetooth specification unit sensitivity at 0.01% ber (a) /4 dqpsk - -89 - -70 dbm 8dpsk - -82 - -70 dbm maximum received signal at 0.1% ber (a) /4 dqpsk - -10 - -20 dbm 8dpsk - -10 - -20 dbm
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 30 of 94 radio characteristics - enhanced data rate _?`??qjolj=m??j?jd??= data sheet 6.3 temperature -25c 6.3.1 transmitter (a) bluecore4-rom plug-n-go firmware keeps rf transmit power within the bluetooth v2.0+edr specification limits (b) class 2 rf transmit power range, bluetooth v2.0+edr specification (c) measurement methods are in accordance with t he bluetooth v2.0+edr rf test specification (d) modulation accuracy utilises differential error vector m agnitude (devm) with tracking of the carrier frequency drift. (e) the bluetooth specification values ar e for 8dpsk modulation (values for the /4 dqpsk modulation are less stringent) notes: results shown are referenced to the unbalanced port of the balun. 6.3.2 receiver (a) measurements methods are in accordance with t he bluetooth v2.0 +edr rf test specification notes: results shown are referenced to the unbalanced port of the balun. radio characteristics vdd = 1.8v temperature = -25c min typ max bluetooth specification unit maximum rf transmit power (a) - 7 - -6 to +4 (b) dbm relative transmit power (c) - -1 - -4 to +1 db carrier frequency stability (c) -3- 10 khz modulation accuracy (c) (d) rms devm - 10 - 13 (e) % 99% devm - 15 - 20 (e) % peak devm - 20 - 25 (e) % radio characteristics vdd = 1.8v temperature =-25c modulation min typ max bluetooth specification unit sensitivity at 0.01% ber (a) /4 dqpsk - -87 - -70 dbm 8dpsk - -80 - -70 dbm maximum received signal at 0.1% ber (a) /4 dqpsk - -10 - -20 dbm 8dpsk - -10 - 20 dbm
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 31 of 94 radio characteristics - enhanced data rate _?`??qjolj=m??j?jd??= data sheet 6.4 temperature +85c 6.4.1 transmitter (a) bluecore4-rom plug-n-go firmware keeps rf transmit power within the bluetooth v2.0+edr specification limits (b) class 2 rf transmit power range, bluetooth v2.0+edr specification (c) measurement methods are in accordance with the bluetooth v2.0 + edr rf test specification (d) modulation accuracy utilises differential error vector m agnitude (devm) with tracking of the carrier frequency drift. (e) the bluetooth specification values ar e for 8dpsk modulation (values for the /4 dqpsk modulation are less stringent) notes: results shown are referenced to the unbalanced port of the balun. 6.4.2 receiver (a) measurements methods are in accordance with t he bluetooth v2.0 + edr rf test specification notes: results shown are referenced to the unbalanced port of the balun. radio characteristics vdd = 1.8v temperature = +85c min typ max bluetooth specification unit maximum rf transmit power (a) - 1 - -6 to +4 (b) dbm relative transmit power (c) - -1 - -4 to +1 db carrier frequency stability (c) -3- 10 khz modulation accuracy (c) (d) rms devm - 10 - 13 (e) % 99% devm - 15 - 20 (e) % peak devm - 20 - 25 (e) % radio characteristics vdd = 1.8v temperature = +85c modulation min typ max bluetooth specification unit sensitivity at 0.01% ber (a) /4 dqpsk - -84 - -70 dbm 8dpsk - -77 - -70 dbm maximum received signal at 0.1% ber (a) /4 dqpsk - 0 - -20 dbm 8dpsk - -3 - -20 dbm
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 32 of 94 device diagram _?`??qjolj=m??j?jd??= data sheet 7 device diagram figure 7.1: blue core4-rom plug-n-g o device diagram clock generation baseband and logic ram memory mapped control status physical layer hardware engine burst mode controller microcontroller risc microcontroller interrupt controller event timer dac iq mod internal rom memory management unit pa aux_dac pio[1]/txen aux dac rf_in pio[0]/rxen rf transmitter xtal_out xtal_in fref -45 +45 rf synthesiser rf synthesiser /n/n+1 loop filter tune vreg_in vdd_ana vreg in out vdd_core vss_core test_en vdd_pads reset resetb vdd_pio vdd_usb vss_ana vss_vco vss_radio vss_mem vdd_mem iq demod rf receiver lna usb usb_dp usb_dn synchronous serial interface spi_csb spi_clk spi_mosi spi_miso uart_tx uart_rx uart_rts uart_cts pcm_out pcm_in pcm_sync pcm_clk uart audio pcm interface vdd_radio vss_pads flash_en pio[2] aio[0] aio[1] aio[2] programmable i/o aio pio[3] pio[4] pio[5] pio[6] pio[7] pio[8] pio[9] pio[10] pio[11] vdd_balun vss_balun vss_balun bal_match rf_connect balun and filter vdd_dig rssi attenuator demodulator adc adc vreg_en
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 33 of 94 description of functional blocks _?`??qjolj=m??j?jd??= data sheet 8 description of functional blocks 8.1 rf receiver the receiver features a near-zero intermediate frequency (if) architecture that allows the channel filters to be integrated onto the die. sufficient out-o f-band blocking specification at the low noise amplifier (lna) input allows the radio to be used in close proximity to global system fo r mobile communications (gsm) and wideband code division multiple access (w-cdma) cellular phone tr ansmitters without being desensitised. the use of a digital frequency shift keying (fsk) discriminator means that no discriminator tank is needed and its e xcellent performance in the presence of noise allows bluecore4-rom plug-n-go to exceed the bl uetooth requirements for co-channel and adjacent channel rejection. for edr, an adc is used to digitise the if received signal. 8.1.1 low noise amplifier the lna can be configured to operate in single-ended or differential mode. single-ended mode is used for class 1 (1) bluetooth operation; differential mode is used for class 2 operation. 8.1.2 analogue to digital converter the analogue to digital converter (adc) is used to implem ent fast automatic gain control (agc). the adc samples the received signal strength indicator (rssi) voltage on a slot-by-slot basis. the front-end lna gain is changed according to the measured rssi value, keeping the first mixe r input signal within a limited range. this improves the dynamic range of the receiver , improving performance in inte rference limited environments. 8.2 rf transmitter 8.2.1 iq modulator the transmitter features a direct iq mo dulator to minimise the frequency drift during a transmit timeslot, which results in a controlled modulation index. digital baseband transmit circuitry provides the required spectral shaping. 8.2.2 power amplifier the internal power amplifier (pa) has a maximum output po wer of +6dbm. this allows bluecore4-rom plug-n-go to be used in class 2 and class 3 radios without an external rf pa. 8.2.3 auxiliary dac an 8-bit voltage auxiliary dac is provided for power cont rol of an external pa for class 1 operation or any other customer specific application. 8.3 balun and filter the plug-n-go device incorporates a balun and filter to provide a 50 ? unbalanced antenna port. 8.4 rf synthesiser the radio synthesiser is fully integrated onto the die wit h no requirement for an external voltage controlled oscillator (vco) screening can, varactor tuning diodes, lc resonators or loop filter. the synthesiser is guaranteed to lock in sufficient time across the guaranteed temperature ran ge to meet the bluetooth v2.0 + edr specification. 8.5 clock input and generation the reference clock for the system is gen erated from a tcxo or crystal input between 8mhz and 40mhz. all internal reference clocks are generated using a phase locked loop, which is locked to the external reference frequency. (1) class 1 operation is not recommended for pl ug-n-go devices and therefore is not recommended for bluecore4-rom plug-n-go.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 34 of 94 description of functional blocks _?`??qjolj=m??j?jd??= data sheet 8.6 baseband and logic 8.6.1 memory management unit the memory management unit (mmu) provi des a number of dynamically allocated ri ng buffers that hold the data that is in transit between the host and the ai r. the dynamic allocation of memory ensures efficient use of the available random access memory (ram) and is performed by a hard ware mmu to minimise the overheads on the processor during data/voice transfers. 8.6.2 burst mode controller during radio transmission the burst mode controller (bmc) constructs a packet from header information previously loaded into memory-mapped registers by the software and pa yload data/voice taken from the appropriate ring buffer in the ram. during radio reception, the bmc stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer in ram. this architecture minimises the intervention required by the processor during transmission and reception. 8.6.3 physical layer hardware engine dsp dedicated logic is used to perform the following: ? forward error correction ? header error control ? cyclic redundancy check ? encryption ? data whitening ? access code correlation ? audio transcoding the following voice data translations and operations are performed by firmware: ? a-law/ -law/linear voice data (from host) ? a-law/ -law/continuously variable slope delta (cvsd) (over the air) ? voice interpolation for lost packets ? rate mismatches the hardware suports all optional and mandatory featur es of bluetooth v2.0 + edr including afh and esco. 8.6.4 ram (48kbytes) 48kbytes of on-chip ram is provided to support the risc m cu and is shared between the ring buffers used to hold voice/data for each active connection and the general purpose memory required by the bluetooth stack. 8.6.5 rom 4mbits of metal programmable rom is prov ided for system firmware implementation. 8.6.6 usb this is a full speed universal serial bus (usb) interfac e for communicating with other compatible digital devices. bluecore4-rom plug-n-go acts as a usb peripheral, respondi ng to requests from a master host controller such as a pc. 8.6.7 synchronous serial interface this is a synchronous serial port interface (spi) for interfac ing with other digital devices. the spi port can be used for system debugging. it can also be us ed for programming the flash memory. 8.6.8 uart this is a standard universal asynchronous receiver transmit ter (uart) interface for comm unicating with other serial devices.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 35 of 94 description of functional blocks _?`??qjolj=m??j?jd??= data sheet 8.7 microcontroller the microcontroller (mcu), interrupt controller and event ti mer run the bluetooth software stack and control the radio and host interfaces. a 16-bit reduced instruction set co mputer (risc) microcontroller is used for low power consumption and efficient use of memory. 8.7.1 programmable i/o 8.7.2 802.11 co-existence interface dedicated hardware is provided to impl ement a variety of co-existence schem es. channel skipping afh, priority signalling, channel signalling and host passing of channel inst ructions are all supported. t he features are configured in firmware. the details of some methods are prop rietary (e.g., intel wcs). contact csr for details.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 36 of 94 csr bluetooth software stacks _?`??qjolj=m??j?jd??= data sheet 9 csr bluetooth software stacks bluecore4-rom plug-n-go is supplied with bluetooth v2.0 + edr compliant stack fi rmware, which runs on the internal risc microcontroller. the bluecore4-rom plug-n-go software architecture allows bluetooth processing and the application program to be shared in different ways between the internal risc microc ontroller and an external host processor (if any). the upper layers of the bluetooth stack (above hci) can be run either on-chip or on the host processor. 9.1 bluecore hci stack in the implementation shown in figure 9. 1 the internal processor runs the bluetooth stack up to the host controller interface (hci). the ho st processor must provide all u pper layers including the application. figure 9.1: bluecore hci stack hci lm lc internal rom 48kb ram baseband mcu host i/o radio pcm i/o usb uart host
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 37 of 94 csr bluetooth software stacks _?`??qjolj=m??j?jd??= data sheet 9.1.1 key features of the hci stack: standard bluetooth functionality bluetooth v2.0 + edr mandatory functionality: ? adaptive frequency hopping (afh), including classifier ? faster connection - enhanced inquiry scan (immediate fhs response) ? lmp improvements ? parameter ranges optional bluetooth v2.0 + edr functionality supported: ? adaptive frequency hopping (afh) as master and automatic channel classification ? fast connect - interlaced inquiry and page scan plus rssi during inquiry ? extended sco (esco), ev3 +crc, ev4, ev5 ? sco handle ? synchronisation the firmware was written against the bluetooth v2.0 + edr specification. ? bluetooth components: ? baseband (including lc) ? lm ? hci ? standard usb v1.1 and uart hci transport layers ? all standard radio packet types ? full bluetooth data rate, enhanced data rates of 2 and 3mbps (1) ? operation with up to seven active slaves (1) ? scatternet v2.5 operation ? maximum number of simultaneous active acl connections: 7 (2) ? maximum number of simultaneous active sco connections: 3 (2) ? operation with up to three sco links, routed to one or more slaves ? all standard sco voice coding, plus transparent sco ? standard operating modes: page, i nquiry, page-scan and inquiry-scan ? all standard pairing, authentication, link key and encryption operations ? standard bluetooth power saving mechanisms: hold, sniff and park modes, including forced hold ? dynamic control of peers' transmit power via lmp ? master/slave switch ? broadcast ? channel quality driven data rate ? all standard bluetooth test modes the firmware's supported bluetooth feat ures are detailed in the standard pr otocol implementation conformance statement (pics) documents, available from www.csr.com. (1) this is the maximum allowed by bluetooth v2.0 + edr specification. (2) bluecore4-rom plug-n-go supports all combinations of active acl and sco channels for both master and slave operation, as specif ied by the bluetooth v2.0 + edr specification.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 38 of 94 csr bluetooth software stacks _?`??qjolj=m??j?jd??= data sheet 9.1.2 key features of the hc i stack: extra functionality the firmware extends the standard bluetooth functionality with the following features: ? supports bluecore serial protocol (bcsp), a proprietar y, reliable alternative to the standard bluetooth uart host transport ? provides a set of approximately 50 manufacturer-s pecific hci extension commands. this command set, called bluecore command (bccmd), provides: ? access to the chip's general-purpose pio port ? the negotiated effective encryption key le ngth on established bluetooth links ? access to the firmware's random number generator ? controls to set the default and maximum transmit powers; these can help minimise interference between overlapping, fixed-location piconets ? dynamic uart configuration ? radio transmitter enable/disable. a simple command connects to a dedicated hardware switch that determines whether the radio can transmit. ? the firmware can read the voltage on a pair of the chip's external pins. this is normally used to build a battery monitor, using either vm or host code ? a block of bccmd commands provides access to the ch ip's persistent store c onfiguration database (ps). the database sets the device's bluetooth address, class of device, radio (transmit class) configuration, sco routing, lm, usb and dfu constants, etc. ? a uart break condition can be used in three ways: 1. presenting a uart break condition to the chip can force the chip to perform a hardware reboot 2. presenting a break condition at boot time can hold the chip in a low power state, preventing normal initialisation while the condition exists 3. with bcsp, the firmware can be configured to s end a break to the host before sending data. (this is normally used to wake the host from a deep sleep state.) ? the dfu standard has been extended with public/priva te key authentication, al lowing manufacturers to control the firmware that can be loaded onto their bluetooth modules ? a modified version of the dfu protocol allows firmware upgrade via the chip's uart ? a block of radio test or bist command s allows direct control of the chip's radio. this aids the development of modules' radio designs, and can be used to support bluetooth qualification. ? virtual machine (vm). the firmware provides the vm en vironment in which to run application-specific code. although the vm is mainly used with bluelab and rfcomm builds (alternative firmware builds providing l2cap, sdp and rfcomm), the vm can be used with this build to perform simple tasks such as flashing leds via the chip's pio port. ? hardware low power modes: shallow sleep and deep sl eep. the chip drops into modes that significantly reduce power consumption when the software goes idle. ? sco channels are normally routed via hci (over bcsp). however, up to three sco channels can be routed over the chip's single pcm port (at the same time as routing any remaining sco channels over hci). note: always refer to the firmware release note for th e specific functionality of a particular build.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 39 of 94 csr bluetooth software stacks _?`??qjolj=m??j?jd??= data sheet 9.2 bluecore rfcomm stack in the version of the firmware, shown in figure 9.2 the upper layers of th e bluetooth stack up to rfcomm are run on-chip. this reduces host-side softwa re and hardware requirements at the expense of some of the power and flexibility of the hci only stack. figure 9.2: bluecore rfcomm stack lc internal rom 48kb ram baseband mcu host i/o radio pcm i/o usb uart host rfcomm sdp lm l2cap hci
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 40 of 94 csr bluetooth software stacks _?`??qjolj=m??j?jd??= data sheet 9.2.1 key features of the blueco re4-rom plug-n-go rfcomm stack interfaces to host: ? rfcomm, an rs-232 serial cable emulation protocol ? sdp, a service database look-up protocol connectivity: ? maximum number of active slaves: three ? maximum number of simultaneous active acl connections: three ? maximum number of simultaneous active sco connections: three ? data rate: up to 350kbps (1) security: ? full support for all bluetooth security featur es up to and including strong (128-bit) encryption. power saving: ? full support for all bluetooth power saving modes (park, sniff and hold). data integrity: ? cqddr increases the effective data rate in noisy environments. ? rssi used to minimise interference to other radio devices using the ism band. (1) the data rate is with respect to bluecore4-rom plug-n-go with basic data rate packets.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 41 of 94 csr bluetooth software stacks _?`??qjolj=m??j?jd??= data sheet 9.3 bluecore virtual machine stack in figure 9.3, this version of the st ack firmware shown requires no host processor (but it can use a host processor for debugging, etc.). all software layers, including application so ftware, run on the internal ri sc processor in a protected user software execution environmen t known as a virtual machine (vm). the user may write custom application code to run on the bluecore vm using bluelab sdk supplied with the bluelab multimedia and casira development kits, available separately from csr. this code will then execute alongside the main bluecore firmware. the user is able to make ca lls to the bluecore firmware for various operations. the execution environment is structured so the user applicatio n does not adversely affect the main software routines, thus ensuring that the bluetooth stack software component does not need re-qualification when the application is changed. using the vm and the bluelab sdk the user is able to devel op applications such as a cordless handsfree kit or other profiles without the requir ement of a host controller. bluelab is supplied with example code including a full implementation of the handsfree profile. note: sample applications to control pio lines can also be written with bluelab sdk and the vm for the hci stack. figure 9.3: virtual machine lc internal rom 48kb ram baseband mcu host i/o radio pcm i/o usb uart host (optional) rfcomm sdp vm application software lm l2cap hci
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 42 of 94 csr bluetooth software stacks _?`??qjolj=m??j?jd??= data sheet 9.4 bluecore hid stack this version of the stack firmware requires no host processor. all software layers, including application software, run on the internal risc microcontroller in a protected user software execution env ironment known as a virtual machine (vm). the user may write custom application code to run on the bluecore vm using bluelab professional sdk supplied with the bluelab professional and casira development kits, avail able separately from csr. th is code will then execute alongside the main bluecore firmware. the user is able to make calls to the bluecore firmware for various operations. the execution environment is structured so the user applicatio n does not adversely affect the main software routines, thus ensuring that the bluetooth stack software component does not need re-qualification when the application is changed. using the vm and the bluelab professional sdk the user is able to develop bluetooth hid devices such as an optical mouse or keyboard. the user is abl e to customise features such as power management and connect/reconnect behaviour. the hid i/o component in the hid stack controls low laten cy data acquisition from external sensor hardware. with this component running in native code, it does not incur the overhead of the vm code interpreter. supported external sensors include five mouse buttons, the agilent adns-203 0 optical sensor, quadrature scroll wheel, direct coupling to a keyboard matrix and a uart interface to custom hardware. a reference schematic for implementing a three button, optical mouse with scroll wheel is available from csr. figure 9.4: hid stack lc internal rom 48kb ram baseband mcu hid i/o radio pio/uart sensing hardware (optical sensor etc.) hid sdp vm application software lm l2cap hci
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 43 of 94 csr bluetooth software stacks _?`??qjolj=m??j?jd??= data sheet 9.5 host-side software bluecore4-rom plug-n-go can be ordered with companion host-side software: ? bluecore3-pc includes software for a full windows 98/me, windows 2000 or windows xp bluetooth host-side stack together with ic hardware described in this document. ? bluecore3-mobile includes software for a full host-side stack designed for modern arm chip-based mobile handsets together with ic hardw are described in this document. 9.6 device firmware upgrade bluecore4-rom plug-n-go is supplied with boot loader soft ware, which implements a device firmware upgrade (dfu) capability. this allows new firmware to be uploaded to the flash memory through bluecore4-rom plug-n-go uart or usb ports. 9.7 bchs software bluecore embedded host software is designed to enable cs r customers to implement bl uetooth functionality into embedded products quickly, cheaply and with low risk. bchs is developed to work with csr's family of bluecore ic s. bchs is intended for em bedded products that have a host processor for running bchs and the bluetooth applicat ion, e.g., a mobile phone or a pda. bchs together with the bluecore ic with embedded bluetooth core stack (l2c ap, rfcomm and sdp) is a complete bluetooth system solution from rf to profiles. bchs includes most of the bluetooth intelligence and give s the user a simple api. this makes it possible to develop a bluetooth product without in -depth bluetooth knowledge. the bluecore embedded host software contains three elements: ? example drivers (bcsp and proxies) ? bluetooth profile managers ? example applications the profiles are qualified which makes t he qualification of the final product very easy. bchs is delivered with source code (ansi c). bchs also comes with example applications in ansi c, which makes the process of writing the application easier. 9.8 additional software for ot her embedded applications when the upper layers of the bluetooth protocol stack are run as firmware on bluecore4-rom plug-n-go, a uart software driver is supplied that pr esents the l2cap, rfcomm and service disco very protocol (sdp) apis to higher bluetooth stack layers running on the host. the code is provided as c source or object code. 9.9 csr development systems csr?s bluelab multimedia and casira deve lopment kits are available to allow the evaluation of the bluecore4-rom plug-n-go hardware and software, and as toolki ts for developing on-chip and host software.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 44 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10 device terminal descriptions 10.1 rf ports the bluecore4-rom plug-n-go rf_in terminal can be config ured as either a single-ended or differential input. the operational mode is determined by setting the ps key pskey_txrx_pio_control (0x20). 10.1.1 rf plug-n-go the 10 x 10mm 96-ball lfbga package used on the bluecore4- rom plug-n-go device is an rf plug-n-go package, where the terminal rf_connect forms an unbalanced ouput with a nominal 50 ? impedance. this terminal can be directly connected to an antenna requiring no imped ance matching network as figure 10.1 indicates. figure 10.1: circuit for rf_connect rf_connect bluecore r1 50 ?
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 45 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.1.2 single-ended input (rf_in) this is the single-ended rf input from the antenna. the input presents a complex impedan ce that requires a matching network between the terminal and the ante nna. starting from the substrate (chi p) side, the input can be modelled as a lossy capacitor with th e bond wire to the ba ll grid represented as a series inductance. the terminal is dc blocked. the dc level must not exceed (vss_radi o -0.3v to vdd_ radio + 0.3v). note: both terminals must be externally dc biased to vdd_radio figure 10.2: circuit rf_in bluecore rf_in r1 6.8 ? c1 0.68pf l1 1.5nh
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 46 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.2 external reference clock input (xtal_in) the bluecore4-rom plug-n-go rf local osc illator and internal digita l clocks are derived from the reference clock at the bluecore4-rom plug-n-go xtal_in input. this reference may be either an external clock or from a crystal connected between xtal_in and xtal_out. the crystal mode is described in section 10.3. 10.2.1 external mode bluecore4-rom plug-n-go can be configured to accept an external refere nce clock from another device (such as tcxo) at xtal_in by connectin g xtal_out to ground. the external clock can be either a digital level square wave or sinusoidal, and this may be directly coupled to xtal_i n without the need for additional components. if the peaks of the reference clock are below vss_an a or above vdd_ana, it must be dr iven through a dc bl ocking capacitor (approximately 33pf) connected to xtal_in. a digital level reference clock gives superior noise immunity, as the high slew rate clock edges have lower voltage to phase conversion. the external clock signal should meet the specifications in table 10.1: table 10.1: external clock specifications (a) the frequency should be an integer multiple of 250khz except for the cdma/3g frequencies (b) vdd_ana is 1.8v nominal (c) if the external clock is driven through a dc blocking capa citor, then maximum allowable amplitude is reduced from vdd_ana to 800mv pk-pk. 10.2.2 xtal_in impedance in external mode the impedance of the xtal _in will not change signific antly between operating modes, typically 10ff. when transitioning from deep sleep to an active state a spike of up to 1pc may be measured. for this reason it is recommended that a buffered clock input be used. 10.2.3 clock timing accuracy as figure 10.3 indicates, the 250ppm timing accuracy on the external clock is required 7ms after the assertion of the system clock request line. this is to guarantee that the firmware can maintain timing accuracy in accordance with the bluetooth v2.0 + edr specification. radio activity may occu r after 11ms, therefore, at this point the timing accuracy of the external clock source must be within 20ppm. min typ max frequency (a) 7.5mhz 16mhz 40mhz duty cycle 20:80 50:50 80:20 edge jitter (at zero crossing) - - 15ps rms signal level 400mv pk-pk - vdd_ana (b) (c) figure 10.3: tcxo clock accuracy
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 47 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.2.4 clock start-up delay bluecore4-rom plug-n-go hardware incorp orates an automatic 5ms delay afte r the assertion of the system clock request signal before running firmware. this is suitable fo r most applications using an external clock source. however, there may be scenarios where the clock cannot be guaranteed to either exist or be stable after this period. under these conditions, bluecore4-rom plug-n-go firmware provides a software function which will extend the system clock request signal by a period stored in pskey_clock_startu p_delay. this value is set in milliseconds from 5-31ms. this ps key allows the designer to optimise a system where cl ock latencies may be longer than 5ms while still keeping the current consumption of bluecore4-rom plug-n-go as low as possible. bluecore4-rom plug-n-go will consume about 2ma of current for the dura tion of pskey_clock_startup_delay before activati ng the firmware. figure 10.4: actual allowable clock pres ence delay on xtal_in vs. ps key setting actual allowable clock presence delay on xtal_in vs. pskey setting 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 pskey_clock_startup_delay delay (ms)
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 48 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.2.5 input frequenci es and ps key settings bluecore4-rom plug-n-go should be conf igured to operate with the chosen reference frequency. this is accomplished by setting the ps key pskey_ana_freq (0x1fe ) for all frequencies with an integer multiple of 250khz. the input frequency default settin g in bluecore4-rom plug-n-go is 26mhz. the following cdma/3g tcxo frequencies are also catered for: 7.68, 14.4, 15.36, 16.2, 16. 8, 19.2, 19.44, 19.68, 19.8 and 38.4mhz. table 10.2: ps key values for cdma/3g phone tcxo frequencies reference crystal frequency (mhz) pskey_ana_freq (0x1fe) (units of 1khz) 7.68 7680 14.40 14400 15.36 15360 16.20 16200 16.80 16800 19.20 19200 19.44 19440 19.68 19680 19.80 19800 38.40 38400 n x 250khz - +26.00 default 26000
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 49 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.3 crystal oscillator (xtal_in, xtal_out) this section describes the crystal mode . see section 10.2 for the description of the external reference clock mode. 10.3.1 xtal mode bluecore4-rom plug-n-go contains a crystal driver circuit. this operates with an external crystal and capacitors to form a pierce oscillator. figure 10.6 shows an electrical equivalent circuit for a crystal. the crystal appears i nductive near its resonant frequency. it forms a resonant circuit with its load capacitors. the resonant frequency may be trimmed with the crystal load capacitance. bluecore4-rom plug-n-go contains variable internal capacitors to provide a fine trim. figure 10.5: crystal driver circuit figure 10.6: crystal equivalent circuit - g m bluecore c trim c int c trim c t2 c t1 xtal_in xtal_out
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 50 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet table 10.3: crystal specification the bluecore4-rom plug-n-go driver circuit is a transc onductance amplifier. a voltage at xtal_in generates a current at xtal_out. the value of transconductance is variable and may be set for optimum performance. 10.3.2 load capacitance for resonance at the correct frequency the crystal shoul d be loaded with its specified load capacitance, which is defined for the crystal. this is the total capacitance across the crystal vi ewed from its terminals. bluecore4-rom plug-n-go provides some of this load with the capacitors c trim and c int . the remainder should be from the external capacitors labelled c t1 and c t2 . c t1 should be three times the value of c t2 for best noise performance. this maximises the signal swing, henc e, slew rate at xtal _in (to which all on-chip clocks are referred). crystal load capacitance, c l is calculated with equation 10.1: where: c trim = 3.4pf nominal (mid-range setting) c int = 1.5pf note: c int does not include the crystal internal self capa citance; it is the driver self capacitance. min typ max frequency 8mhz 16mhz 32mhz initial tolerance - 25ppm - pullability - 20ppm/pf - equation 10.1: load capacitance 2 t 1 t 2 t 1 t trim int i c c c c 2 c c c + + + = ?
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 51 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.3.3 frequency trim bluecore4-rom plug-n-go enables frequency adjustments to be made. this feature is typica lly used to remove initial tolerance frequency errors associated with the crystal. fr equency trim is achieved by adjusting the crystal load capacitance with on-chip trim capacitors, c trim . the value of c trim is set by a 6-bit word in the ps key pskey_ana_ftrim (0x1f6). its value is calc ulated thus: there are two c trim capacitors, which are both connected to ground. when viewed from the crystal terminals, they appear in series so each least significant bit (lsb) increment of frequency trim presents a load across the crystal of 55ff. the frequency trim is described by equation 10.3. where fx is the crystal frequency and pullability is a crysta l parameter with unit s of ppm/pf. total trim range is 63 times the value above. if not specified, the pullability of a crystal may be calc ulated from its motional capacitance with equation 10.4. where: c 0 = crystal self capaci tance (shunt capacitance) c m = crystal motional capacitance (series branch capacitance in crystal model). see figure 10.6. note: it is a bluetooth requirement that the frequency is always within 20ppm. the trim range should be sufficient to pull the crystal within 5ppm of the exact frequency. this l eaves a margin of 15ppm for frequency drift with ageing and temperature. a crystal with an age ing and temperature drift specificati on of better than 15ppm is required. equation 10.2: trim capacitance equation 10.3: frequency trim equation 10.4: pullability ftrim _ ana _ pskey ff 110 c trim = () () lsb / ppm 10 55 y pullabilit f f 3 x x ? = ? ( ) () () 2 0 i m x x x c c 4 c f f f + = ? ? ?
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 52 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.3.4 transconductance driver model the crystal and its load capacitors should be viewed as a transimpedance element, whereby a current applied to one terminal generates a voltage at the other. the transconductance amplifier in bluecore4-rom plug-n-go uses the voltage at its input, xtal_in, to generate a current at its ou tput, xtal_out. therefore, the circuit will oscillate if the transconductance, transimpedance product is greater than un ity. for sufficient oscillation amplitude, the product should be greater than three. the transconductance required for oscillation is defined by the relationship shown in equation 10.5: bluecore4-rom plug-n-go guarantees a tr ansconductance value of at least 2ma/v at maximum drive level. notes: more drive strength is required for higher fre quency crystals, higher loss crystals (larger r m ) or higher capacitance loading. optimum drive level is attained when the level at xt al_in is approximately 1v pk-pk. the drive level is determined by the crystal driver transconductance, by setting the ps key pskey_xtal_lvl (0x241). 10.3.5 negative resistance model an alternative representation of the cr ystal and its load capacitors is a fre quency dependent resistive element. the driver amplifier may be considered as a circuit that prov ides negative resistance. for oscillation, the value of the negative resistance must be greater than that of the crysta l circuit equivalent resistance. although the bluecore4-rom plug-n-go crystal driver circuit is based on a transim pedance amplifier, an equivale nt negative resistance may be calculated for it with the following formula in equation 10.6: this formula shows the negative resistance of the bluecore4- rom plug-n-go driver as a function of its drive strength. the value of the driver negative resistance may be easily m easured by placing an additional resistance in series with the crystal. the maximum value of this resistor (oscillati on occurs) is the equivalent negative resistance of the oscillator. equation 10.5: transconductance required for oscillation equation 10.6: equivalent negative resistance ( ) ( ) ()( )( )( )( ) () 2 trim 2 t trim 1 t trim 2 t 1 t int 0 m 2 x trim 2 t trim 1 t m c c c c c 2 c c c c r f 2 c c c c 3 g + + + + + + + + > ( ) ( ) ()( )( )( )( ) () 2 trim 2 t trim 1 t trim 2 t 1 t int 0 2 x m trim 2 t trim 1 t neg c c c c c 2 c c c c f 2 g c c c c 3 r + + + + + + + + >
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 53 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.3.6 crystal ps key settings see tables in section 10.2.5. 10.3.7 crystal oscill ator characteristics note: graph shows results for bluecore4-rom plug-n-g o crystal driver at maximum drive level. conditions: c trim = 3.4pf centre value crystal c o = 2pf transconductance setting = 2ma/v loop gain = 3 c t1 /c t2 = 3 figure 10.7: crystal load capacitance and series resistance limits with crystal frequency crystal load capacitance and series resistance limits with crystal frequency 10.0 100.0 1000.0 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 load capacitance (pf) max xtal rm value (esr), (ohm) 8 mhz 12 mhz 16 mhz 20 mhz 24 mhz 28 mhz 32 mhz
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 54 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet note: drive level is set by ps key pskey_xtal_lvl (0x241). figure 10.8: crystal driver transconduct ance vs. driver level register setting
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 55 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet crystal parameters: crystal frequency 16mhz (refer to your software build release note for supported frequencies ). crystal c 0 = 0.75pf circuit parameters: c trim = 8pf, maximum value c t1 ,c t2 = 5pf (3.9pf plus 1.1 pf stray) (crystal total load capacitance 8.5pf) note: this is for a specific crystal and load capacitance. figure 10.9: crystal driver negative resist ance as a function of drive level setting
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 56 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.4 uart interface bluecore4-rom plug-n-go uart interface provides a simple mechanism for communicating with other serial devices using the rs232 protocol. (1) four signals are used to implement the uart function, as shown in figure 10.10. when bluecore4-rom plug-n-go is connected to another digital device, uart_rx and ua rt_tx transfer data between the two devices. the remaining two signals, uart_cts and uart_rts, can be us ed to implement rs232 hardware flow control where both are active low indicators. all uart connections are implemented using cmos te chnology and have signalling levels of 0v and vdd_usb. uart configuration parameters, such as baud rate and packet format, are set using bluecore4-rom plug-n-go software. note: in order to communicate with the uart at its maximum data rate using a standard pc, an accelerated serial port adapter card is required for the pc. table 10.4: possible uart settings (1) uses rs232 protocol, but voltage levels are 0v to vdd_usb (requires external rs232 transceiver chip). figure 10.10: universal asynchronous receiver parameter possible values baud rate minimum 1200 baud ( 2%error) 9600 baud ( 1%error) maximum 3m baud ( 1%error) flow control rts/cts or none parity none, odd or even number of stop bits 1 or 2 bits per channel 8 uart_tx uart_rx uart_rts uart_cts bluecore
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 57 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet the uart interface is capable of re setting bluecore4-rom plug-n-go upon rece ption of a break signal. a break is identified by a continuous logic low (0v) on the uart_rx terminal, as shown in figure 10.11. if t brk is longer than the value, defined by the ps key pskey_host_io_uart_r eset_timeout, (0x1a4), a reset will occur. this feature allows a host to in itialise the system to a know n state. also, bluecore4-rom plug-n-go can emit a break character that may be used to wake the host. note: the dfu boot loader must be loaded into the flash device before the uart or usb inte rfaces can be used. this initial flash programming can be done via the spi. table 10.5 shows a list of commonly used baud rates and their associated values for the ps key pskey_uart_baud_rate (0x204). there is no requiremen t to use these standard values. any baud rate within the supported range can be set in the ps key according to the formula in equation 10.7. table 10.5: standard baud rates figure 10.11: break signal equation 10.7: baud rate baud rate persistent store value error hex dec 1200 0x0005 5 1.73% 2400 0x000a 10 1.73% 4800 0x0014 20 1.73% 9600 0x0027 39 -0.82% 19200 0x004f 79 0.45% 38400 0x009d 157 -0.18% 57600 0x00ec 236 0.03% 76800 0x013b 315 0.14% 115200 0x01d8 472 0.03% 230400 0x03b0 944 0.03% 460800 0x075f 1887 -0.02% 921600 0x0ebf 3775 0.00% 1382400 0x161e 5662 -0.01% 1843200 0x1d7e 7550 0.00% 2764800 0x2c3d 11325 0.00% 004096 . 0 rate _ baud _ uart _ pskey rate baud =
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 58 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.4.1 uart bypass 10.4.2 uart configuration while reset is active the uart interface for bluecore4-rom plug-n-go while the chip is being held in reset is tri-state. this will allow the user to daisy chain devices onto the physical uart bus. the co nstraint on this method is that any devices connected to this bus must tri-state when bluecore4-rom plug-n-go reset is de-asserted and the firmware begins to run. 10.4.3 uart bypass mode alternatively, for devices that do not tri-state the ua rt bus, the uart bypass mode on bluecore4-rom plug-n-go can be used. the default state of bluecore4-rom plug-n-go af ter reset is de-asserted; this is for the host uart bus to be connected to the bluecore4-rom plug-n-go uart , thereby allowing communication to bluecore4-rom plug-n-go via the uart. all uart bypass mode connecti ons are implemented using cmos technology and have signalling levels of 0v and vdd_pads. (1) in order to apply the uart bypass mode, a bccmd command will be issued to bluecore4-rom plug-n-go. upon this issue, it will switch the bypass to pio[7:4] as figur e 10.12 indicates. once the bypass mode has been invoked, bluecore4-rom plug-n-go will enter the deep sleep state indefinitely. in order to re-establish communication with bluecore4-rom pl ug-n-go, the chip must be reset so that the default configuration takes effect. it is important for the host to ensure a clean bluetooth disconnection of any active links before the bypass mode is invoked. therefore, it is not possible to have active bluetooth links while operating the bypass mode. 10.4.4 current consumpt ion in uart bypass mode the current consumption for a device in uart bypass mode is equal to the values quoted for a device in standby mode. figure 10.12: uart bypass architecture (1) the range of the signalling level for the standard uart described in section 10.4 and the uart bypass may differ between csr bl uecore devices, as the power supply configurations are chip dependent. for bluecore4-rom plug-n-go, the standard uart is supplied by vdd_usb, so has signalling levels of 0v and vdd_usb. whereas in the uart bypass mode, the signals appear on pio[4:7] which are supplied by vdd_pads, therefore the signalling levels are 0v and vdd_pads. host processor bluecore another device reset uart rxd cts test interface rts uart_rx uart_cts uart_rts uart_tx pio4 pio5 pio6 pio7 txd tx rts cts rx
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 59 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.5 usb interface bluecore4-rom plug-n-go devices contain a full speed (12mbits/s) usb interface that is capable of driving a usb cable directly. no external usb transceiver is required . the device operates as a usb peripheral, responding to requests from a master host controller such as a pc. bo th the ohci and the uhci standar ds are supported. the set of usb endpoints implemented can behav e as specified in the usb section of the bluetooth specification v2.0+edr or alternatively can appear as a set of endpoints appropriate to usb audio devices such as speakers. as usb is a master/slave oriented system (in common with other usb peripherals), bluecore4-rom plug-n-go only supports usb slave operation. 10.5.1 usb data connections the usb data lines emerge as pins usb_dp and usb_dn. these terminals are connected to the internal usb i/o buffers of the bluecore4-rom plug-n-go, therefore, have a low output impedanc e. to match the connection to the characteristic impedance of the usb cable, resistors must be placed in series with usb_dp/usb_dn and the cable. 10.5.2 usb pull-up resistor bluecore4-rom plug-n-go features an internal usb pull-up resistor. this pulls the usb_dp pin weakly high when bluecore4-rom plug-n-go is ready to enumer ate. it signals to the pc that it is a full speed (12mbit/s) usb device. the usb internal pull-up is implemented as a current so urce, and is compliant with section 7.1.5 of the usb specification v1.2. the internal pull-up pulls u sb_dp high to at least 2.8v when loaded with a 15k ? 5% pull-down resistor (in the hub/host) when vdd_pads =3.1v. this presents a thevenin resi stance to the host of at least 900 ? . alternatively, an external 1.5k ? pull-up resistor can be placed between a pio line and d+ on the usb cable. the firmware must be alerted to which mode is used by setting ps ke y pskey_usb_pio_pullup appropriate ly. the default setting uses the internal pull-up resistor. 10.5.3 power supply the usb specification dictates that t he minimum output high voltage for usb dat a lines is 2.8v. to safely meet the usb specification, the voltage on the vdd_usb suppl y terminals must be an absolute minimum of 3.1v. csr recommends 3.3v for optimal usb signal quality.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 60 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.5.4 self-powered mode in self-powered mode, the circuit is powered from its ow n power supply and not from the vbus (5v) line of the usb cable. it draws only a small leakage cu rrent (below 0.5ma) from vbus on the us b cable. this is the easier mode for which to design, as the design is not limited by the power th at can be drawn from the usb hub or root port. however, it requires that vbus be co nnected to bluecore4-rom plug-n-go via a resistor network (r vb1 and r vb2 ), so bluecore4-rom plug-n-go can detect when vbus is powe red up. bluecore4-rom plug- n-go will not pull usb_dp high when vbus is off. self-powered usb designs (powered from a battery or psu) must ensure that a pio line is allocated for usb pull-up purposes. a 1.5k ? 5% pull-up resistor between usb_dp and the selected pio line should be fitted to the design. failure to fit this resistor may result in the design failing to be usb compliant in self-powered mode. the internal pull-up in bluecore is only suitable for bus-powered usb devices, e.g., dongles. the terminal marked usb_on can be any free pio pin. the pio pin selected must be registered by setting pskey_usb_pio_vbus to the corresponding pin number. note: usb_on is shared with bluecore4-rom plug-n-go pio terminals. table 10.6: usb interface component values figure 10.13: usb connections for self-powered mode identifier value function r s 27 ? nominal impedance matching to usb cable r vb1 22k ? 5% vbus on sense divider r vb2 47k ? 5% vbus on sense divider d- vbus d+ gnd r s r s r vb1 r vb2 bluecore 1.5k ? 5% pio usb_dp usb_dn usb_on
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 61 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.5.5 bus-powered mode in bus-powered mode, the application circuit draws its current from the 5v vbus supply on the usb cable. bluecore4-rom plug-n-go negotiates with the pc during the usb enumeration stage about how much current it is allowed to consume. for class 2 bluetooth applications, csr re commends that the regulator used to de rive 3.3v from vbus is rated at 100ma average current and should be able to handle peaks of 120ma without foldback or limiting. in bus-powered mode, bluecore4-rom plug-n-go requests 100ma during enumeration. for class 1 bluetooth applications, the usb power descripto r should be altered to reflect the amount of power required. this is accomplished by setting the ps key pskey_usb_max_power (0x2c6). this is higher than for a class 2 application due to the extra curr ent drawn by the transmit rf pa. when selecting a regulator, be aware that vbus may go as low as 4.4v. the inrush current (when charging reservoir and supply decoupling capacitors) is lim ited by the usb specification. see usb specification v1.1, section 7.2.4.1. some applications may require soft start circui try to limit inrush current if more than 10 f is present between vbus and gnd. the 5v vbus line emerging from a pc is often electrica lly noisy. as well as regulation down to 3.3v and 1.8v, applications should include careful filtering of the 5v line to attenuate noise that is above the voltage regulator bandwidth. excessive noise on the 1.8v supply to the anal ogue supply pins of bluecore4-rom plug-n-go will result in reduced receive sensitivity and a distorted rf transmit signal. figure 10.14: usb connections for bus-powered mode bluecore d- vbus d+ gnd r s r s r vb1 voltage regulator usb_dp usb_dn usb_on
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 62 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.5.6 suspend current all usb devices must permit the usb controller to plac e them in a usb suspend mode. while in usb suspend, bus-powered devices must not draw more than 0.5ma from usb vbus (self-powered devices may draw more than 0.5ma from their own supply). this current draw requirem ent prevents operation of the radio by bus-powered devices during usb suspend. the voltage regulator circuit itself should draw on ly a small quiescent current (typically less than 100 a) to ensure adherence to the suspend current requirement of the usb sp ecification. this is not normally a problem with modern regulators. ensure that external leds and/or amplifiers can be turned off by bluecore4-rom plug-n-go. the entire circuit must be able to enter the suspend mode. refer to separate csr documentation for more details on usb suspend. 10.5.7 detach and wake_up signalling bluecore4-rom plug-n-go can provide out-o f-band signalling to a host controller by using the control lines called usb_detach and usb_wake_up. these ar e outside the usb specif ication (no wires exist for them inside the usb cable), but can be useful when embedding bluecore4-rom plug- n-go into a circuit where no external usb is visible to the user. both control lines are shared with pio pins and can be assigned to any pio pin by setting the ps keys pskey_usb_pio_detach and pskey_usb_pio_wakeup to the selected pio number. usb_detach is an input which, when asserted high, causes bluecore4-rom plug-n-go to put usb_dn and usb_dp in a high impedance state and turns off the pull-up resistor on dp. this detaches the device from the bus and is logically equivalent to unplugging the device. when usb_detach is taken low, bluecore4-rom plug-n-go will connect back to usb and await enumeration by the usb host. usb_wake_up is an active high output (used only when usb_detach is active ) to wake up the host and allow usb communication to recommence. it replaces the function of the software usb wake_up message (which runs over the usb cable) and cannot be sent while bluecore4-rom plug-n-go is effectively disconnected from the bus. 10.5.8 usb driver a usb bluetooth device driver is required to provide a software interface between bluecore4-rom plug-n-go and bluetooth software running on the host computer. suitabl e drivers are available from http://www.csrsupport.com. figure 10.15: usb_det ach and usb_wake_up signal
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 63 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.5.9 usb 1.1 compliance bluecore4-rom plug-n-go is qualified to th e usb specification v1.1, details of which are available from www.usb.org. the specification contains valuable information on aspects such as pcb track impedance, supply inrush current and product labelling. although bluecore4-rom plug-n-go meets the usb specificat ion, csr cannot guarantee that an application circuit designed around the chip is usb compliant. the choice of application circuit, component choice and pcb layout all affect usb signal quality and electrical characteristics. the information in this document is intended as a guide and should be read in association with the usb specification, with particular attention being giv en to chapter 7. independent usb qualification must be sough t before an application is deemed usb compliant and can bear the usb logo. such qualification can be obtained from a us b plugfest or from an independent usb test house. terminals usb_dp and usb_dn adhere to the usb specif ication v2.0 (chapter 7) electrical requirements. 10.5.10 usb 2.0 compatibility bluecore4-rom plug-n-go is compatible with usb v2.0 host controllers; under these circumstances the two ends agree the mutually acceptable rate of 12mbits /s according to the usb v2.0 specification.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 64 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.6 serial peripheral interface bluecore4-rom plug-n-go uses 16-bit dat a and 16-bit address serial peripheral interface, where transactions may occur when the internal processor is running or is sto pped. this section details the considerations required when interfacing to bluecore4-rom plug-n-go via the four dedica ted serial peripheral interface terminals. data may be written or read one word at a time or the au to increment feature may be used to access blocks. 10.6.1 instruction cycle the bluecore4-rom plug-n-go is the slave and receives commands on spi_mosi and outputs data on spi_miso. table 10.7 shows the instruct ion cycle for an spi transaction. table 10.7: instruction cycl e for an spi transaction with the exception of reset, spi_csb must be held low duri ng the transaction. data on spi_mosi is clocked into the bluecore4-rom plug-n-go on the rising edge of the clock line spi_clk. when reading, bluecore4-rom plug-n-go will reply to the master on spi_miso with the data changing on the falling edge of the spi_clk. the master provides the clock on spi_clk. the transaction is teminated by taking spi_csb high. sending a command word and the address of a register for every time it is to be read or written is a significant overhead, especially when large amounts of data are to be transferred. to ov ercome this bluecore4-rom plug-n-go offers increased data transfe r efficiency via an auto increment operation. to invoke auto increment, spi_csb is kept low, which auto increments the address, while providing an extra 16 clock cycles for each extra word to be written or read. 1 reset the spi interface hold spi_csb high for two spi_clk cycles 2 write the command word take spi_csb low and clock in the 8 bit command 3 write the address clock in the 16-bit address word 4 write or read data words clock in or out 16-bit data word(s) 5 termination take spi_csb high
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 65 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.6.2 writing to blue core4-rom plug-n-go to write to bluecore4-rom plug-n-go, the 8-bit write command (00000010) is sent first (c[7:0]) followed by a 16-bit address (a[15:0]). the next 16-bits (d[15:0]) clocked in on spi_mosi are written to the location set by the address (a). thereafter for each subsequent 16-bits clocked in, the address (a) is incremented and the data written to consecutive locations until the transaction terminates when spi_csb is taken high. 10.6.3 reading from bluecore4-rom plug-n-go reading from bluecore4-rom plug-n-go is similar to writin g to it. an 8-bit read command (00000011) is sent first (c[7:0]), followed by the address of the location to be read (a[15:0]). bluecore4- rom plug-n-go then outputs on spi_miso a check word during t[15:0] followed by the 16-bit contents of the addressed lo cation during bits d[15:0]. the check word is composed of {command, address [15:8]}. the check word may be used to confirm a read operation to a memory location. this overcomes the problems enc ountered with typical serial peripheral interface slaves, whereby it is impossible to determine whether the data retur ned by a read operation is vali d data or the result of the slave device not responding. if spi_csb is kept low, data from cons ecutive locations is read out on spi_mis o for each subsequent 16 clocks, until the transaction terminates when spi_csb is taken high. 10.6.4 multi-slave operation bluecore4-rom plug-n-go should not be connected in a mult i-slave arrangement by simple parallel connection of slave miso lines. when bluecore4-rom plug-n-go is dese lected (spi_csb = 1), the spi_miso line does not float. instead, bluecore4-rom plug-n-go outputs 0 if the processor is running or 1 if it is stopped. figure 10.16: write operation figure 10.17: read operation
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 66 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.7 pcm codec interface pulse code modulation (pcm) is a standard method used to digitise audio (particularly voice) for transmission over digital communication channels. through its pcm interfac e, bluecore4-rom plug-n-go has hardware support for continual transmission and reception of pcm data, t hus reducing processor overhead for wireless headset applications. bluecore4-rom plug-n-go offers a bi-directiona l digital audio interface that routes directly into the baseband layer of the on-chip firmware. it do es not pass through the hci protocol layer. hardware on bluecore4-rom plug-n-go allows the data to be sent to and received from a sco connection. (1) up to three sco connections can be supported by the pcm interface at any one time. bluecore4-rom plug-n-go can operate as the pcm interfac e master generating an output clock of 128, 256 or 512khz. when configured as pcm interf ace slave, it can operate with an in put clock up to 2048khz. bluecore4-rom plug-n-go is compatible with a variety of clock formats, including long frame sync, short frame sync and gci timing environments. it supports 13-bit or 16-bit linear, 8-bit -law or a-law companded sample formats at 8ksamples/s and can receive and transmit on any selection of three of the first four slots following pcm_sy nc. the pcm configuration options are enabled by setting the ps key ps key_pcm_config32 (0x1b3). bluecore4-rom plug-n-go interfaces directly to pcm audio devices including the following: ? qualcomm msm 3000 series and msm 5000 series cdma baseband devices ? oki msm7705 four channel a-law and -law codec ? motorola mc145481 8-bit a-law and -law codec ? motorola mc145483 13-bit linear codec ? stw 5093 and 5094 14-bit linear codecs ? bluecore4-rom plug-n-go is also compat ible with the motorola ssi? interface (1) subject to firmware support. c ontact csr for current status.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 67 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.7.1 pcm interface master/slave when configured as the master of the pcm interf ace, bluecore4-rom plug-n-go generates pcm_clk and pcm_sync. when configured as the slave of the pcm interface, bluecore4-rom plug-n-go a ccepts pcm_clk rates up to 2048khz. figure 10.18: bluecore4-rom plug-n-go as pcm interface master figure 10.19: bluecore4-rom pl ug-n-go as pcm interface slave bluecore pcm_sync pcm_out pcm_in pcm_clk 128/256/512khz 8khz upto 2048khz 8khz bluecore pcm_out pcm_in pcm_clk pcm_sync
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 68 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.7.2 long frame sync long frame sync is the name given to a clocking format that controls the transfer of pcm data words or samples. in long frame sync, the rising edge of pcm_sync indicates the start of the pcm word. when bluecore4-rom plug-n-go is configured as pcm ma ster, generating pcm_sync and pcm_cl k, then pcm_sync is 8-bits long. when bluecore4-rom plug-n-go is configured as pcm slave, pcm_sync may be fr om two consecutive falling edges of pcm_clk to half the pcm_sync rate, i.e., 62.5 s long. bluecore4-rom plug-n-go samples pcm_in on the falling e dge of pcm_clk and transmits pcm_out on the rising edge. pcm_out may be configured to be high impedance on the falling edge of pcm_clk in the lsb position or on the rising edge. 10.7.3 short frame sync in short frame sync, the falling edge of pcm_sync indicates the start of the pcm word. pcm_sync is always one clock cycle long. as with long frame sync, bluecore4-rom plug-n-go samples pcm_in on the falling edge of pcm_clk and transmits pcm_out on the rising edge. pcm_out may be configured to be high impedance on the falling edge of pcm_clk in the lsb position or on the rising edge. figure 10.20: long frame sync (shown with 8-bit companded sample) figure 10.21: short frame sync (shown with 16-bit sample) pcm_sync pcm_clk pcm_out pcm_in 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 undefined undefined pcm_sync pcm_clk pcm_out pcm_in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 undefined undefined
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 69 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.7.4 multi-slot operation more than one sco connection over the pcm interface is sup ported using multiple slots. up to three sco connections can be carried over any of the first four slots. 10.7.5 gci interface bluecore4-rom plug-n-go is compatible with the general circuit interface (gci), a st andard synchronous 2b+d isdn timing interface. the two 64kbps b channels c an be accessed when this mode is configured. the start of frame is indicated by the rising edge of pcm_sync and runs at 8khz. with bluecore4-rom plug-n-go in slave mode, the frequency of pcm_clk can be up to 4.096mhz. figure 10.22: multi-slot operation with two slots and 8-bit companded samples figure 10.23: gci interface long_pcm_sync or short_pcm_sync pcm_clk pcm_out pcm_in 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 do not care do not care pcm_sync pcm_clk pcm_out pcm_in 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 do not care do not care b1 channel b2 channel
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 70 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.7.6 slots and sample formats bluecore4-rom plug-n-go can receive and transmit on any select ion of the first four slots following each sync pulse. slot durations can be either 8 or 16 clock cycles. durations of 8 clock cycles may only be used with 8-bit sample formats. durations of 16 clocks may be used with 8-bit, 13-bit or 16-bit sample formats. bluecore4-rom plug-n-go supports 13-bi t linear, 16-bit linear and 8-bit -law or a-law sample formats. the sample rate is 8ksamples/s. the bit order may be little or big endian. when 16-bit slots are used, th e 3 or 8 unused bits in each slot may be filled with sign extensi on, padded with zeros or a programmable 3- bit audio attenuation compatible with some motorola codecs. 10.7.7 additional features bluecore4-rom plug-n-go has a mute faci lity that forces pcm_out to be 0. in master mode, pcm_sync may also be forced to 0 while keeping pcm_clk running which some codecs use to control power down. figure 10.24: 16-bit slot length and sample formats pcm_out pcm_out pcm_out pcm_out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sign extension 8-bit sample 8-bit sample zeros padding sign extension 13-bit sample 13-bit sample audio gain a 16-bit slot with 8-bit companded sample and sign extension selected. a 16-bit slot with 8-bit companded sample and zeros padding selected. a 16-bit slot with 13-bit linear sample and sign extension selected. a 16-bit slot with 13-bit linear sample and audio gain selected.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 71 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.7.8 pcm timing information table 10.8: pcm master timing (a) assumes normal system clock operation. figures will vary during low power modes, when system clock speeds are reduced. symbol parameter min typ max unit f mclk pcm_clk frequency 4mhz dds generation. selection of frequency is programmable. see table 10.10. - 128 -khz 256 512 48mhz dds generation. selection of frequency is programmable. see table 10.11 and pcm_clk and pcm_sync generation on page 75. 2.9 - khz - pcm_sync frequency - 8 khz t mclkh (a) pcm_clk high 4mhz dds generation 980 - - ns t mclkl (a) pcm_clk low 4mhz dds generation 730 - ns - pcm_clk jitter 48mhz dds generation 21 ns pk-pk t dmclksynch delay time from pcm_clk high to pcm_sync high --20ns t dmclkpout delay time from pcm_ clk high to valid pcm_out --20ns t dmclklsyncl delay time from pcm_clk low to pcm_sync low (long frame sync only) --20ns t dmclkhsyncl delay time from pcm_clk high to pcm_sync low --20ns t dmclklpoutz delay time from pcm_ clk low to pcm_out high impedance --20ns t dmclkhpoutz delay time from pcm_ clk high to pcm_out high impedance --20ns t supinclkl set-up time for pcm_in va lid to pcm_clk low 30 - - ns t hpinclkl hold time for pcm_clk low to pcm_in invalid 10 - - ns
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 72 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet figure 10.25: pcm master timing long frame sync figure 10.26: pcm master timing short frame sync pcm_sync pcm_clk pcm_out pcm_in msb (lsb) lsb (msb) msb (lsb) lsb (msb) f mlk t mclkh t mclkl t supinclkl t dmclksynch t dmclkpout t hpinclkl t dmclklsyncl t dmclkhsyncl t dmclklpoutz t dmclkhpoutz t r ,t f pcm_sync pcm_clk pcm_out pcm_in msb (lsb) lsb (msb) msb (lsb) lsb (msb) f mlk t mclkh t mclkl t supinclkl t t dmclkpout t hpinclkl dmclkhsyncl t dmclklpoutz t dmclkhpoutz t r ,t f t dmclksynch
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 73 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet table 10.9: pcm slave timing symbol parameter min typ max unit f sclk pcm clock frequency (slave mode: input) 64 - 2048 khz f sclk pcm clock frequency (gci mode) 128 - 4096 khz t sclkl pcm_clk low time 200 - - ns t sclkh pcm_clk high time 200 - - ns t hsclksynch hold time from pcm_clk low to pcm_sync high 30 - - ns t susclksync h set-up time for pcm_sync hi gh to pcm_clk low 30 - - ns t dpout delay time from pcm_sync or pcm_clk whichever is later, to valid pcm_out data (long frame sync only) --20ns t dsclkhpout delay time from clk high to pcm_out valid data - - 20 ns t dpoutz delay time from pcm_sync or pcm_clk low, whichever is later, to pcm_out data line high impedance --20ns t supinsclkl set-up time for pcm_in valid to clk low 30 - - ns t hpinsclkl hold time for pcm_clk low to pcm_in invalid 30 - - ns
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 74 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet figure 10.27: pcm slave timing long frame sync figure 10.28: pcm slave timing short frame sync pcm_clk pcm_sync pcm_out pcm_in msb (lsb) lsb (msb) f sclk t sclkh t tsclkl t hsclksynch t susclksynch t dpout t dsclkhpout t dpoutz t dpoutz t supinsclkl t hpinsclkl t r ,t f lsb (msb) msb (lsb) pcm_clk pcm_sync pcm_out pcm_in msb (lsb) lsb (msb) f sclk t sclkh t tsclkl t hsclksynch t susclksynch t dpoutz t dpoutz t supinsclkl t hpinsclkl t r ,t f lsb (msb) msb (lsb) t dsclkhpout
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 75 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet pcm_clk and pcm_ sync generation bluecore4-rom plug-n-go has two methods of generating pc m_clk and pcm_sync in master mode. the first is generating these signals by direct digit al synthesis (dds) from bluecore4-rom plug-n-go internal 4mhz clock (which is used in bluecore2-external). using this mode limits pcm_clk to 128, 256 or 512khz and pcm_sync to 8khz. the second is generating pcm_clk and pcm_sync by dds from an internal 48mhz clock (which allows a greater range of frequencies to be gener ated with low jitter but consumes more power). this second method is selected by setting bit 48m_pcm_clk_gen_en in pskey_pc m_config32. when in th is mode and with long frame sync, the length of pcm_sync can be either 8 or 16 cycles of pcm_clk, determined by long_length_sync_en in pskey_pcm_config32. the equation 10.8 describes pcm_clk frequency when being generated using the internal 48mhz clock: the frequency of pcm_sync relative to pcm_clk can be set using equation 10.9: cnt_rate, cnt_limit and sync_limi t are set using pskey_pcm_low_jitt er_config. as an example, to generate pcm_clk at 512 khz with pcm_sync at 8khz, set pskey_pc m_low_jitter_conf ig to 0x08080177. equation 10.8: pcm_clk frequency when being generated using the internal 48mhz clock equation 10.9: pcm_sync frequency relative to pcm_clk mhz 24 limit _ cnt rate _ cnt f = 8 limit _ sync clk _ pcm f =
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 76 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.7.9 pcm configuration the pcm configuration is set using two ps keys, pskey_pcm_config32 detaile d in table 10.10 and pskey_pcm_low_jitter_config in table 10.11. the de fault for pskey_pcm_config32 is 0x00800000, i.e., first slot following sync is active, 13-bit linear voice forma t, long frame sync and interface master generating 256khz pcm_clk from 4mhz internal clo ck with no tri-state of pcm_out. name bit position description - 0 set to 0 slave_mode_en 1 0 = master mode with internal generation of pcm_clk and pcm_sync. 1 = slave mode requiring externally generated pcm_clk and pcm_sync. short_sync_en 2 0 = long frame sync (rising edge indicates start of frame). 1 = short frame sync (falling edge indicates start of frame). - 3 set to 0. sign_extend_en 4 0 = padding of 8 or 13-bit voice sample into a 16-bit slot by inserting extra lsbs. when padding is selected with 13-bit voice sample, the 3 padding bits are the audio gain setting; with 8-bit sample the 8 padding bits are zeroes. 1 = sign-extension. lsb_first_en 5 0 = msb first of transmit and receive voice samples. 1 = lsb first of transmit and receive voice samples. tx_tristate_en 6 0 = drive pcm_out continuously. 1 = tri-state pcm_out immediately after falling edge of pcm_clk in the last bit of an active slot, assuming the next slot is not active. tx_tristate_rising_edge_en 7 0 = tri-state pcm_out immediately after falling edge of pcm_clk in last bit of an active slot, assuming the next slot is also not active. 1 = tri-state pcm_out after rising edge of pcm_clk. sync_suppress_en 8 0 = enable pcm_sync output when master. 1 = suppress pcm_sync whilst keeping pcm_clk running. some codecs utilise this to enter a low power state. gci_mode_en 9 1 = enable gci mode mute_en 10 1 = force pcm_out to 0 48m_pcm_clk_gen_en 11 0 = set pcm_clk and pcm_sync generation via dds from internal 4 mhz clock. 1 = set pcm_clk and pcm_sync generation via dds from internal 48 mhz clock. long_length_sync_en 12 0 = set pcm_sync length to 8 pcm_clk cycles. 1 = set length to 16 pcm_clk cycles. only applies for long frame sync and with 48m_pcm_clk_gen_en set to 1. - [20:16] set to 0b00000
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 77 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet table 10.10: pskey_pcm_ config32 description table 10.11: pskey_pcm_low_jitter_config description master_clk_rate [22:21] selects 128 (0b01), 256 (0b00), 512 (0b10) khz pcm_clk frequency when master and 48m_pcm_clk_gen_en (bit 11) is low. active_slot [26:23] default is 0001. ignored by firmware. sample_format [28:27] selects between 13 (0b00), 16 (0b01), 8 (0b10) bit sample with 16 cycle slot duration or 8 (0b11) bit sample with 8 cycle slot duration. name bit position description cnt_limit [12:0] sets pc m_clk counter limit cnt_rate [23:16] sets pcm_clk count rate sync_limit [31:24] sets pcm_sync division relative to pcm_clk name bit position description
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 78 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.8 i/o parallel ports fifteen lines of programmable bi-directi onal input/outputs (i/o) are provided. pi o[11:8] and pio[3:0] are powered from vdd_pio. pio[7:4] are powered from vdd_ pads. aio [2:0] are powered from vdd_mem. fifteen lines of programmable bi-directi onal input/outputs (i/o) are provided. pi o[11:8] and pio[3:0] are powered from vdd_pio. pio[7:4] are powered from vdd_ pads. aio [2:0] are powered from vdd_usb. pio lines can be configured through software to have eit her weak or strong pull-ups or pull-downs. all pio lines are configured as inputs with weak pull-downs at reset. pio[0] and pio[1] are normally dedicated to rxen and txen respectively, but they are available for general use. any of the pio lines can be configured as interrupt request lines or as wake-up lines fr om sleep modes. pio[6] or pio[2] can be configured as a request line for an external clock source. this is useful when the clock to bluecore4-rom plug-n-go is provided from a system application specific integrated circuit (asic). using pskey_clock_request_enable (0 x246), this terminal can be confi gured to be low when bluecore4-rom plug-n-go is in deep sleep and high when a clock is requ ired. the clock must be suppl ied within 4ms of the rising edge of pio[6] or pio[2] to avoid losing timing accuracy in certain bluetooth operating modes. bluecore4-rom plug-n-go has three general purpose analogue interface pins, aio[0], aio[1] and aio[2] also known as the extended pio lines. these are used to access intern al circuitry and control signals. one pin is allocated to decoupling for the on-chip band gap reference voltage; th e other two may be configured to provide additional functionality. auxiliary functions available via these pins include an 8-bit adc and an 8-bit dac. typically the adc is used for battery voltage measurement. signals selectable at these pins include the band gap re ference voltage and a variety of clock signals: 48, 24, 16, 8mhz and the xtal clock frequency. when used with analogue signals, the voltage range is constrained by the analogue supply voltage (1.8v). when configur ed to drive out digital level signals (e.g., clocks), the output voltage level is determined by vdd_usb. 10.8.1 pio defaults for bluecore4-rom plug-n-go csr cannot guarantee that thes e terminal functions remain the same. refer to the software release note for the implementation of these pio lines, as they are firmware build-specific.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 79 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.9 i 2 c interface pio[8:6] can be used to form a master i 2 c interface. the interface is formed using software to drive these lines. therefore, it is suited only to relatively slow functions such as driving a dot matrix liquid crystal display (lcd), keyboard scanner or eeprom. notes: pio lines need to be pulled-up through 2.2k ? resistors. pio[7:6] dual functions, uart bypass and eeprom sup port, therefore, devices using an eeprom cannot support uart bypass mode. for connection to eeproms, refer to csr documentation on i 2 c eeproms for use with bluec ore. this provides information on the type of devices currently supported. figure 10.29: example eeprom connection serial eeprom (at24c16a) 4 3 2 1 5 6 7 8 pio[8] pio[7] pio[6] u2 vcc wp scl sda a0 a1 a2 gnd 2.2k ? 2.2k ? 2.2k ? +1.8v 10nf
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 80 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.10 tcxo enable or function an or function exists for clock enable signals from a ho st controller and bluecore4-rom plug-n-go where either device can turn on the clock without having to wake up the ot her device. pio[3] can be used as the host clock enables input and pio[2] can be used as the or output with the tcxo enable signal from bluecore4-rom plug-n-go. on reset and up to the time the pio has been configured, pio[ 2] will be tri-state. therefore, the de veloper must ensure that the circuitry connected to this pin is pulled via a 470k ? resistor to the appropriate power rail. this ensures that the tcxo is oscillating at start up. figure 10.30: example txco enable or function bluecore system gsm system tcxo vdd enable clk in clk in clk req in/ pio[3] clk req out/ pio[2] clk req out
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 81 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.11 reset and resetb bluecore4-rom plug-n-go may be reset from several sources: ? reset or resetb pins ? power on reset ? a uart break character ? via a software configured watchdog timer the reset pin is an active high reset and is internally filtered using the internal low frequency clock oscillator. a reset will be performed between 1.5ms and 4.0ms following reset being active. it is recommended that reset be applied for a period greater than 5ms. the resetb pin is the active low version of reset a nd is or'd on-chip with the active high reset, with either causing the reset function. the power on reset occurs when the vdd_core supply fa lls below typically 1.5v and is released when vdd_core rises above typically 1.6v. at reset the digital i/o pins are set to inputs for bi-direc tional pins and outputs are tr i-state. the pios have weak pull-downs. following a reset, bluecore4-rom plug-n-go assumes t he maximum xtal_in frequency, which ensures that the internal clocks run at a safe (low) frequency until bluecore4-rom plug-n-go is configured for the actual xtal_in frequency. if no clock is present at xt al_in, the oscillator in bluecore4-rom plug-n-go free runs, again at a safe frequency.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 82 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.11.1 pin states on reset table 10.12 shows the pin states of bluecore4-rom plug-n-go on reset. table 10.12: pin states of blue core4-rom plug-n -go on reset 10.11.2 status after reset the chip status after a reset is as follows: ? warm reset: baud rate and ram data remain available ? cold reset (1) : baud rate and ram data not available pin name state: blue core4-rom plug-n-go pio[11:0] input with weak pull-down pcm_out tri-state with weak pull-down pcm_in input with weak pull-down pcm_sync input with weak pull-down pcm_clk input with weak pull-down uart_tx output tri-state with weak pull-up uart_rx input with weak pull-down uart_rts output tri-state with weak pull-up uart_cts input with weak pull-down usb_dp input with weak pull-down usb_dn input with weak pull-down spi_csb input with weak pull-up spi_clk input with weak pull-down spi_mosi input with weak pull-down spi_miso output tri-state with weak pull-down aio[2:0] output, driving low reset input with weak pull-down resetb input with weak pull-up test_en input with strong pull-down aux_dac high impedance rf_in high impedance xtal_in high impedance, 250k to xtal_out xtal_out high impedance, 250k to xtal_in (1) a cold reset is either power cycle, system reset (firmware fault code) or reset signal. see section 10.11.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 83 of 94 device terminal descriptions _?`??qjolj=m??j?jd??= data sheet 10.12 power supply 10.12.1 voltage regulator (plug-n-go) an on-chip linear voltage regulator can be used to power th e 1.8v dependent supplies. it is advised that a smoothing circuit using a 2.2 f low esr capacitor and 2.2 ? resistor be placed on the output vdd_ana. in the plug-n-go package, an internal 2.2 ? resistor is provided between the regulator output vdd_ana and vdd_dig. the regulator is switched into a low power mode when t he device is sent into deep sleep mode. when the on-chip regulator is not required vdd_ana is a 1.8v input and vr eg_in must be either open circuit or tied to vdd_ana. 10.12.2 sequencing it is recommended that vdd_core, vdd_radio and vdd_ana be powered at the same time. the order of powering supplies for vdd_core, vdd_pio, vdd_pads and vdd_usb is not important. however, if vdd_core is not present, all inputs have a weak pull-down irrespective of the reset state. 10.12.3 sensitivity to disturbances csr recommends if supplying bluecore4-rom plug-n-go from an external voltage source that vdd_ana and vdd_radio should have less than 10mv rms noise levels between 0 to 10mhz. in addition, avoid single tone frequencies. csr recommends a simple rc filter for vdd_core, as this redu ces transients put back onto the power supply rails. the remaining supplies vdd_mem, vdd_pio, vdd_pad s and vdd_usb can be conn ected together with the vreg_in to the 3.3v supply and simply decoupled as shown in figure 13.1. the transient response of the regulator is also important. at the start of a packe t, power consumption will jump to high levels. see the average current consumption section. the regulator should have a response time of 20 s or less; it is essential that the power rail recovers quickly. 10.12.4 vreg_en pin the regulator enable pin, vreg_en, can be used to enabl e and disable the bluecore4-rom plug-n-go device if the on-chip regulator is being used. the pin is active high and has an internal weak pull-up to enable the regulator if vreg_en is not connected.
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 84 of 94 product reliability tests _?`??qjolj=m??j?jd??= data sheet 11 product reliability tests die test conditions specification sample size esd human body model jedec 36 latch-up 200ma jedec 6 early life 125c 48 ? 168 hours 240 hot life test 125c 1000 hours 320 (240 fits) package test conditions specification sample size moisture sensitivity precon jedec level 3 (125c 24 hours) 192 hours five re-flow simulation cycles 308 30c/60%rh temperature cycling -65c to +150c 500 cycles 77 autoclave (steam) 121c at 100% rh 96 hours 77 hast 130c/85% rh 96 hours 77 thermal shock -55 /125c 100 cycles 77 high temperature storage 150c 1000 hours 77
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 85 of 94 product reliability tests for blue core4-rom plug-n-go automotive _?`??qjolj=m??j?jd??= data sheet 12 product reliability tests for bluecore4-rom plug-n-go automotive 12.1 aec-q100 the reliability tests in this section follow the tests out lined in the aec-q100 and were performed on bluecore4-rom plug-n-go in vfbga 10 x 10mm 96 i/o (lead-free solder balls). samples are electrically tested at ambient temperature. this package qualification will (where moisture sensitivity preconditioning is required) us e ipc/jedec msl3, i.e., the finished product is allowed a maximum exposure to a 30c/60%rh environment for 168 hours before mounting. as part of csr's automotive test program, customers will have access to the initia l device reliability test report. they will also have access to a quarterly reliability test report update for automotive parts. die test conditions speci fication sample size esd human body model jedec 24 early life 125c vdd max 48 hours 2400 hot life test 125c vdd max 1000 hours 90, 77, 77 package test conditions specification sample size moisture (125c 24 hours) 192 hours five reflow simulation cycles 783 sensitivity precon 30c/60%rh jedec level 3 temperature cycling -65/150 c 500 cycles 231 from precon autoclave (steam) 121c/100%rh 96 hours 231 from precon temperature humidity bias 85c/85%rh vdd max 1000 hours 231 from precon thermal shock -55/125c 100 cycles 77 from precon high temperature storage 150c 1000 hours 77 other test conditions sample size bond shear acid decapsulation of finished product 30 bonds wire pull acid decapsulation of finished product 60 wires from precon and temperature cycling solder ball shear two reflow cycles 150 balls visual inspection and dimensions n/a 30 devices
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 86 of 94 application schematic _?`??qjolj=m??j?jd??= data sheet 13 application schematic figure 13.1: application circuit fo r radio characteristics specification rf_in d2 pio[0]/rxen d3 pio[1]/txen c4 bal_match a1 rf_connect b1 aux_dac c2 xtal_in l3 xtal_out l4 vreg_en j2 pcm_out g10 pcm_in h11 pcm_sync g11 pcm_clk h10 uart_tx j10 uart_rx j11 uart_rts l11 uart_cts k11 usb_dp l9 usb_dn l8 reset f9 resetb g9 spi_csb c10 spi_clk d10 spi_mosi d11 spi_miso c11 test_en e9 flash_en b10 pio[2] c3 pio[3] b2 pio[4] h9 pio[5] j8 pio[6] k8 pio[7] k9 pio[8] b3 pio[9] b4 pio[10] a4 pio[11] a5 aio[0] k5 aio[1] j6 aio[2] k7 vreg_in l7 vdd_usb l10 vdd_pio a3 vdd_pads e11 vdd_dig l6 vdd_mem b11 vdd_mem k6 vdd_core f11 vdd_radio e3 vdd_ana l5 vdd_balun f1 vss_pads a2 vss_pads e10 vss_pads k10 vss_mem d9 vss_mem j9 vss_core f10 vss_radio e2 vss_radio f3 vss_radio g2 vss_vco g3 vss_vco h2 vss_vco h3 vss_ana k4 vss_balun g1 vss_balun j1 vss_balun k1 1.8v regulator 2r2 xt1 xtal c8 3p3 c9 10p c2 10n c1 10n c3 2u2 vi o vin c4 2u2 tp1 tp2 tp3 tp4 r1 22r r2 22r usb_d+ usb_d- tp5 tp6 tp7 tp8 general purpose i/ o 8 bit adc inputs 50 ohms antenna nc dac output nc nc u1 bc41b143a bluecore4-rom plug-n-go
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 87 of 94 package dimensions _?`??qjolj=m??j?jd??= data sheet 14 package dimensions 14.1 10 x 10 lfbga 96-ball 1.6mm package figure 14.1: bluecore4-ro m plug-n-go 96-ball lfbg a 1.6mm package dimensions d d1 e a b c d e f g h j k l a x y b c d e f g h j k l 7 8 10 11 11 6 5 4 3 21 78 10 6 5 4 3 2 1 a a1 a2 se sd a3 seating plane z 2 0.08 z 3 0.1 z ? b 1 t op vi ew bottom view 1 2 3 4 5 f g j h 4 px py scale = 1mm e1 e
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 88 of 94 ordering information _?`??qjolj=m??j?jd??= data sheet 15 ordering information 15.1 bluecore4-rom plug-n-go (a) until bluecore4-rom plug-n-go reaches production status order number is bc41b143aes-ann-e4. minimum order quantity 2kpcs taped and reeled interface version package order number type size shipment method uart and usb 96-ball lfbga 10 x 10 x 1.6mm tape and reel bc41b143a-ann-e4 (a) (pb free)
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 89 of 94 contact information _?`??qjolj=m??j?jd??= data sheet 16 contact information csr uk csr denmark csr japan churchill house novi science park csr kk cambridge business park niels jernes vej 10 9f kojimachi ks square 5-3-3, cowley road 9220 aalborg east kojimachi, cambridge, cb4 0wz denmark chiyoda-ku, united kingdom tel: +45 72 200 380 tokyo 102-0083 tel: +44 (0) 1223 692 000 fax: +45 96 354 599 japan fax: +44 (0) 1223 692 001 e-mail: sales@csr.com tel: +81-3-5276-2911 e-mail: sales@csr.com fax: +81-3-5276-2915 e-mail: sales@csr.com csr korea csr taiwan csr u.s. 2nd floor, hyo-bong building, 6th floor , no. 407, 2425 n. central expressway 1364-1, seocho-dong, rui guang road, suite 1000 seocho-gu, neihu, richardson seoul 137-863, taipei 114, texas 75080 korea taiwan, r.o.c. usa tel: +82 2 3473 2372-5 tel: +886 2 7721 5588 tel: +1 (972) 238 2300 fax : +82 2 3473 2205 fax: +886 2 7721 5589 fax: +1 (972) 231 1440 e-mail: sales@csr.com e-mail: sale s@csr.com e-mail: sales@csr.com to contact a csr representative, go to www.csr.com/contacts.htm
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 90 of 94 document references _?`??qjolj=m??j?jd??= data sheet 17 document references document: reference specification of the bluetoot h system v1.1, 22 february 2001 and v1.2, 05 november 2003 bluetooth core specification v2.0 + edr v2.0+edr, 8 november 2004 bluetooth test document v2.0+edr v2.0.e.0, 5 november 2004 universal serial bus specific ation v1.1, 23 september 1998 selection of flash memory for use with bluecore csr document bcore-an-001p selection of i 2 c eeproms for use with bluecore csr document bcore-an-008p ia-481-2 16mm, 24mm, 32mm, 44mm and 56mm embossed carrier taping of surface mount components for automatic handling eia-541 packaging material standards for esd sensitive items eia-583 packaging material standards for electrostatic discharge (esd) sensitive items ipc / jedec standard for handling, packing, shipping and use of moisture / reflow sensitive surface mount devices j-std-033
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 91 of 94 terms and definitions _?`??qjolj=m??j?jd??= data sheet 18 terms and definitions 8dpsk 8 phase differential phase shift keying /4 dqpsk pi/4 rotated differential quaternary phase shift keying bluecore? group term for csr?s range of bluetooth chips bluetooth? set of technologies providing audio and data transfer over short-range radio connections acl asynchronous connection-less. bluetooth data packet adc analogue to digital converter afh adaptive frequency hopping agc automatic gain control a-law audio encoding standard alu arithmetic logic unit api application programming interface asic application specific integrated circuit bcsp bluecore? serial protocol ber bit error rate. used to measure the quality of a link bist built-in self-test bmc burst mode controller cdma code division multiple access cmos complementary metal oxide semiconductor codec coder decoder cqddr channel quality driven data rate crc cyclic redundancy check csb chip select (active low) csr cambridge silicon radio cts clear to send cvsd continuous variable slope delta modulation dac digital to analogue converter dbm decibels relative to 1mw dds direct digital synthesis dc direct current dfu device firmware upgrade dnl differential linearity error dsp digital signal processor edr enhanced data rate esco extended sco esr equivalent series resistance fir finite impulse response
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 92 of 94 terms and definitions _?`??qjolj=m??j?jd??= data sheet fsk frequency shift keying gci general circuit interface gfsk gaussian frequency shift keying gsm global system for mobile communications hci host controller interface i 2 c? inter-integrated circuit if intermediate frequency iir infinite impulse response inl integral linearity error iq modulation in-phase and quadrature modulation isdn integrated services digital network ism industrial, scientific and medical kalimba dsp core for csr?s range of chips ksps kilosamples per second l2cap logical link control and adaptation protocol (protocol layer) lc link controller lcd liquid crystal display lfbga low profile fine ball grid array lmp link manager protocol lna low noise amplifier lpf low pass filter lsb least-significant bit mcu microcontroller unit -law audio encoding standard mips million instructions per second mmu memory management unit miso master in serial out nob number of bits ohci open host controller interface pa power amplifier pcm pulse code modulation. refers to digital voice data pda personal digital assistant persistent store storage of bluecore?s conf iguration values in non-volatile memory pio parallel input output pics profile implementation confirmation statement pk-pk peak to peak pll phase lock loop ppm parts per million ps key persistent store key
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 93 of 94 terms and definitions _?`??qjolj=m??j?jd??= data sheet ram random access memory reb read enable (active low) ref reference. represents dimension for reference use only. rf radio frequency rfcomm protocol layer providing serial port emulation over l2cap risc reduced instruction set computer rms root mean squared rssi receive signal strength indication rts ready to send rx receive or receiver sco synchronous connection-oriented. voice oriented bluetooth packet sdk software development kit sdp service discovery protocol sig special interest group sinad signal to noise ratio and distortion snr signal to noise ratio spdif sony and philips interface specification spi serial peripheral interface ssi synchronous serial interface tbd to be defined tcxo temperature controlled crystal oscillator tx transmit or transmitter uart universal asynchronous receiver transmitter uhci upper host control interface usb universal serial bus or upper side band (depending on context) vco voltage controlled oscillator vfbga very fine ball grid array vm virtual machine w-cdma wideband code division multiple access web write enable (active low)
BC41B143A-DS-003PC advance information ? cambridge silicon radio limited 2005 page 94 of 94 document history _?`??qjolj=m??j?jd??= data sheet 19 document history date revision reason for change feb 05 a original publication of this docu ment. (csr reference: bc41b143a-ds-001pa) mar 05 a document identification number revised to bc41b143a-ds-003pa. amended device diagram. amended vdd_usb terminal function description. added balun and filter block description. minor amends. apr 05 b amended maximum baud rate to 3m baud and added additional data rates. jul 05 c electrical characteristics and radio characteristics - basic data rate updated to reflect a radio performance temperature range of -40c to +85c. updated auxilliary dac in description of functional blocks amendment to note (a) concerning specifie d output voltage in the auxilliary dac table (input/output terminal characteristi cs) in electrical characteristics. amendment to note (g) concerning vreg_en and vreg_in in linear regulator table in electrical characteristics. power consumption moved from radio charac teristics to electrical characteristics section. changed title of record of changes to do cument history; chang ed title of acronyms and abbreviations to terms and definitions. _?`? ? qjolj=m??j?jd? ? product data sheet BC41B143A-DS-003PC july 2005

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