frequency multiplying, peak reducing emi solution w530 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 november 22, 2000 features ? cypress premis? family offering generates an emi optimized clocking signal at the out- put selectable output frequency range single 1.25%, 2.5%, 5% or 10% down or center spread output integrated loop filter components operates with a 3.3 or 5v supply low power cmos design available in 20-pin ssop (small shrunk outline package) key specifications supply voltages:......................................... v dd = 3.3v0.3v or v dd = 5v10% frequency range: ............................13 mhz f in 120 mhz cycle to cycle jitter: .........................................250 ps (max) output duty cycle: ................................. 40/60% (worst case) premis is a trademark of cypress semiconductor. w530 20 19 18 17 1 2 3 4 x1 x2 avdd mw0^ refout vdd gnd ir1* 5 6 7 14 15 16 ir2* ssout mw1* stop^ or1^ nc 8 9 10 11 12 13 vdd mw2^ or2* sson#^ gnd gnd simplified block diagram pin configuration ssop spread spectrum w530 (emi suppressed) 3.3v or 5.0v oscillator or spread spectrum w530 (emi suppressed) 3.3v or 5.0v xtal x1 x2 reference input input output output x1 note: 1. pins marked with ^ are internal pull-down resistors with weak 250 ?. pins marked with * are internal pull-up resistors with weak 250 ?. [1]
w530 2 pin definitions pin name pin no. pin type pin description ssout 15 i spread spectrum control. refout 20 o non-modulated output: this pin provides a copy of the reference frequency. this output will not have the spread spectrum feature enabled regardless of the state of logic input sson#. x1 1 i crystal connection or external reference frequency input: this pin has dual functions. it may either be connected to an external crystal, or to an external reference clock. x2 2 i crystal connection: input connection for an external crystal. if using an ex- ternal reference, this pin must be left unconnected. sson# 10 i spread spectrum control (active low): asserting this signal (active low) turns the internal modulation waveform on. this pin has an internal pull-down resistor. mw0:2 4, 14, 11 i modulation width selection: when the spread spectrum feature is turned on, these pins are used to select the amount of variation and peak emi reduc- tion that is desired on the output signal. mw0: down, mw1: up, mw2: down. (see ta b l e 2 .) ir1:2 17, 16 i reference frequency selection: logic level provided at this input indicates to the internal logic what range the reference frequency is in and determines the factor by which the device multiplies the input frequency. refer to ta b l e 1 . these pins have internal pull-up resistors. or1:2 6, 9 i output frequency selection bits: these pins select the frequency operation for the output. refer to ta b l e 1 . or1: down, or2: up. nc 7 nc no connection: leave this pin unconnected. stop 5 i output disable: when pulled high, stops all outputs at logic low voltage level. this pin has an internal pull-down. vdd 12, 19 p power connection: connected to 3.3v or 5v power supply. avdd 3 p analog power connection: connected to 3.3v or 5v power supply. gnd 8, 13, 18 g ground connection: connect all ground pins to the common ground plane.
w530 3 table 1. frequency configuration table table 2. modulation percentage selection table overview the w530 product is one of a series of devices in the cypress premis family. the premis family incorporates the latest advances in pll spread spectrum frequency synthesizer tech- niques. by frequency modulating the output with a low fre- quency carrier, peak emi is greatly reduced. use of this tech- nology allows systems to pass increasingly difficult emi testing without resorting to costly shielding or redesign. in a system, not only is emi reduced in the various clock lines, but also in all signals which are synchronized to the clock. therefore, the benefits of using this technology increase with the number of address and data lines in the system. the sim- plified block diagram shows a simple implementation. functional description the w530 uses a phase locked loop (pll) to frequency modulate an input clock. the result is an output clock whose frequency is slowly swept over a narrow band near the input signal. the basic circuit topology is shown in figure 1 . the input reference signal is divided by q and fed to the phase detector. a signal from the vco is divided by p and fed back to the phase detector also. the pll will force the frequency of the vco output signal to change until the divided output signal and the divided reference signal match at the phase detector input. the output frequency is then equal to the ratio of p/q times the reference frequency. (note: for the w530 the output frequency is nominally equal to the input frequency.) the unique feature of the spread spectrum frequency timing generator is that a modulating waveform is superimposed at the input to the vco. this causes the vco output to be slowly swept across a predetermined frequency band. because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum pro- cess has little impact on system performance. frequency selection with ssftg in spread spectrum frequency timing generation, emi re- duction depends on the shape, modulation percentage, and frequency of the modulating waveform. while the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. using frequency select bits (fs2:1 pins), the frequency range can be set (see ta b l e 2 ). spreading percentage is set with pins mw as shown in table 2 . a larger spreading percentage improves emi reduction. how- ever, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. for these reasons, spreading percentage options are provided. range of fin frequency multiplier set- tings output / input range of fout required r set- tings modulation & power down settings min. max. or2 or1 min. max. ir2 ir1 mw2 mw1 14 30 0 1 1 14 30 0 1 ta b l e 2 14 30 1 0 2 28 60 0 1 ta b l e 2 14 30 1 1 4 56 120 0 1 ta b l e 2 25 60 0 1 0.5 13 30 1 0 ta b l e 2 25 60 1 0 1 25 60 1 0 ta b l e 2 25 60 1 1 2 50 120 1 0 ta b l e 2 50 120 0 1 0.25 13 30 1 1 ta b l e 2 50 120 1 0 0.5 25 60 1 1 ta b l e 2 50 120 1 1 1 50 120 1 1 ta b l e 2 reserved 0 0 n/a n/a n/a as set as set 1 0 power down hi-z 0 0 n/a n/a n/a as set as set 1 1 power down 0 0 0 n/a n/a n/a as set as set 0 0 power down 1 0 0 n/a n/a n/a as set as set 0 1 emi reduction modulation setting bandwith limit frequencies as a % value of fout mw0 = 0 mw0 = 1 mw2 mw1 low high low high minimum emi control 0 0 98.75% 100% 99.375% 100.625% suggested setting 0 1 97.5% 100% 98.75% 101.25% alternate setting 1 0 95.0% 100% 97.5% 102.5% maximum emi reduction 1 1 90.0% 100% 95% 105%
w530 4 spread spectrum frequency timing generator the device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. by increasing the bandwidth of the fundamental and its harmonics, the am- plitudes of the radiated electromagnetic emissions are re- duced. this effect is depicted in ta b l e 2 . as shown in ta b l e 2 , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. the equation for the reduction is: db = 6.5 + 9*log 10 (p) + 9*log 10 (f) where p is the percentage of deviation and f is the frequency in mhz where the reduction is measured. the output clock is modulated with a waveform depicted in figure 3 . this waveform, as discussed in ? spread spectrum clock generation for the reduction of radiated emissions ? by bush, fessler, and hardin, produces the maximum reduction in the amplitude of radiated electromagnetic emissions. the deviation selected for this chip is described in ta b l e 2 . figure 3 details the cypress spreading pattern. cypress does offer options with more spread and greater emi reduction. contact your local sales representative for details on these devices. freq. phase modulating vco post ssout detector charge pump waveform dividers divider feedback divider pll gnd v dd q p clock input reference input (emi suppressed) figure 1. functional block diagram
w530 5 ssftg typical clock frequency span (mhz) amplitude (db) spread spectrum enabled emi reduction spread spectrum non- frequency span (mhz) down spread amplitude (db) center spread figure 2. clock harmonic with and without sscg modulation frequency domain representation max. min. 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% frequency figure 3. typical modulation profile
w530 6 absolute maximum ratings stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. . parameter description rating unit v dd , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t a operating temperature 0 to +70 c t b ambient temperature under bias ? 55 to +125 c p d power dissipation 0.5 w dc electrical characteristics : 0 c < t a < 70 c, v dd = 3.3v 0.3v parameter description test condition min. typ. max. unit i dd supply current 18 32 ma t on power up time first locked clock cycle after power good 5ms v il input low voltage 0.8 v v ih input high voltage 2.4 v v ol output low voltage 0.4 v v oh output high voltage 2.4 v i il input low current note 2 ? 100 a i ih input high current note 2 10 a i ol output low current @ 0.4v, v dd = 3.3v 15 ma i oh output high current @ 2.4v, v dd = 3.3v 15 ma c i input capacitance 7pf r p input pull-up resistor 250 k ? z out clock output impedance 25 ? note: 2. inputs or1:2 and ir1:2 have a pull-up resistor, input sson# has a pull-down resistor.
w530 7 document #: 38-00913-*a dc electrical characteristics: 0 c < t a < 70 c, v dd = 5v 10% parameter description test condition min. typ. max. unit i dd supply current 30 50 ma t on power up time first locked clock cycle after power good 5ms v il input low voltage 0.15v dd v v ih input high voltage 0.7v dd v v ol output low voltage 0.4 v v oh output high voltage 2.4 v i il input low current note 2 ? 100 a i ih input high current note 2 10 a i ol output low current @ 0.4v, v dd = 5v 24 ma i oh output high current @ 2.4v, v dd = 5v 24 ma c i input capacitance 7pf r p input pull-up resistor 250 k ? z out clock output impedance 25 ? ac electrical characteristics: t a = 0 c to +70 c, v dd = 3.3v 0.3v or 5v10% symbol parameter test condition min. typ. max. unit f in input frequency input clock 14 120 mhz f out output frequency spread off 13 120 mhz t r output rise time 15-pf load, 0.8v ? 2.4v 2 5 ns t f output fall time 15-pf load, 2.4 ? 0.8v 2 5 ns t od output duty cycle 15-pf load 40 60 % t id input duty cycle 40 60 % t jcyc jitter, cycle-to-cycle 250 300 ps ordering information ordering code package name package type w530 h 20-pin plastic ssop (209-mil)
w530 ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagram 20-pin small shrink outline package (ssop, 209-mil)
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