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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1997 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs5542 cs5543 22-bit, multi-channel ds adc chip set features l delta-sigma architecture: - 5th order modulator - 22-bit resolution l dc accuracy (f bw = 250hz): - integral linearity: 0.001 % f.s. - differential linearity: 0.5 lsbs - rms noise: 1.1 pa rms l pin selectable input range: - 400 na to 2.5 a full scale l 8-channel digital fir filter l self-calibration of offset and gain l low power: 50 mw /ch for 8-ch system description the cs5542 / cs5543 chip set is designed to be a com- plete current measurement data acquisition system. the cs5542 is a 22-bit, 2-channel, 5th-order delta sig- ma modulator. the cs5543 is a monolithic cmos, 8- channel digital fir filter designed to be used with up to four cs5542s forming an 8-channel system. the com- plete system is capable of cascading up to 1024 channels. the system supports 22-bit measurement resolution with output conversion rates up to 1 khz per channel. jtag boundary-scan capability is available to facilitate self-test at the system level. potential applications for the cs5542/cs5543 system are environmental monitoring, process control systems, color sensing, light measurement, chemical analyzers and photo-diode transducer applications. ordering information cs5542-kl 0 to 70c 28-pin plcc CS5543-KL 0 to 70c 28-pin plcc refgndl inl ical inr refgndr va+ va- gndl vd+ dgnd vref+ vref- gndr sel0 sel1 capsize pdn mclk fsync cal[1:0] mdata[3:0] c[2:0] calibra- and digital control logic 5th order bias ical mux delta-sigma modulator right 5th order delta-sigma modulator left capsize mclk fsync pdn c[2.0] cal[1:0] tck tms tdi tdo vd1+ gnd1 vd2+ gnd2 vd3+ gnd3 channel channel regulator tion control/sequencing 3 2 dmode[2:0] rst clkin fegain oe datsel[3:0] 3 4 te st access port mdata 4 data decode fir filter noise calibration system offset calibration offset/gain registers system or itest gain calibration serial i/o datain[3:0] 4 dataout 4 [3:0] dataclk frame [3:0] cs5543 cs5542 sep 96 ds109pp2
cs5542 cs5543 2 ds109pp2 analog characteristics: (t a = 25 c; va+, vd+ = 5 v 5%; va- = -5 v 5%; gndl,gndr, & dgnd= 0v;vref+ = 4v, vref- = -4 v; mclk frequency as noted.) notes: 1. full scale current is tested under two conditions: capsize = 0 (cdac = 1.6 pf) with mclk at 1.024 mhz and capsize = 1 (cdac = 4.8 pf) with mclk at 2.048 mhz. dynamic range (signal-to-noise) is tested with 101 hz sine wave voltage driven into a 5 m w input resistor with a 470 pf capacitor connected from inr or inl to refgndr or refgndl respectively, to test each modulator. s/n and integral nonlinearity are tested with capsize = 0 (cdac = 1.6 pf) with mclk at 2.048 mhz and capsize = 1 (cdac = 4.8 pf) with mclk at 1.024 mhz. 2. guaranteed by design or characterization. 3. specification applies after a complete calibration sequence using the cs5542/cs5543 combination. drift specification is for the cs5542/cs5543 only and does not include drift due to the input components, the vref voltage, or a frequency change of clkin. 4. specification applies only to system offset calibration using the cs5542/cs5543 chip combination after input offset voltage calibration has been completed with no external offset applied to the input. 5. the va+ and va- supplies should be quiet supplies (see data sheet text). power supply sequence is important. the va+ and va- supplies should be applied to the cs5542 prior to or at the same time as the vd+ supply. 6. power supply rejection is tested with a 100 mvp-p sine wave applied to each supply. see data sheet text for power supply noise requirements. parameter min typ max units specified temperature range 0 - 70 c accuracy full scale input current (bipolar) capsize=0 (note 1) capsize=1 (note 1) - - 400 2500 - - na na dynamic range capsize=0 (note 1) capsize=1 (note 1) 106 113 109 116 - - db db differential nonlinearity (no missing codes) (note 2) 22 - - bits integral nonlinearity (note 1) - - 0.001 %fs full scale error (note 3) - - 0.1 %fs full scale drift (note 3) - 30 - ppm/c system offset calibration range (note 4) - - 10 %fs offset drift (note 1) - 0.3 - lsb/c power supplies (note 5) consumption active powerdown - - - - 80 10 mw mw 50, 60 hz power supply rejection: va+ or va- (notes 1, 6) - tbd - db fullscale current = 400 na 60 hz 500 hz fullscale current = 2500 na 60 hz 500 hz - - - - 1.85 13.5 1.88 15.3 - - - - na/v na/v na/v na/v
cs5542 cs5543 ds109pp2 3 mdata3:0 chip #4 active (previous frame) chip #1 active slot pair #1 chip #2 active slot pair #2 chip #3 active slot pair #3 chip #4 active slot pair #4 inter-chip handoff point slot6 slot7 slot0 slot1 slot2 slot3 slot4 slot5 slot7 slot6 (previous frame) (previous frame) l r l r l r l r l r mclk (2048 x owr) fsync (modulator fs rate) one frame 8 channels 4 slot-pairs cs5542 frame timing overview left data mclk mdata[3:0] right data one slot pair hi-z state (note 1) hi-z state (note 1) notes hi-z state shown as intermediate level for clarity only. bus capacitance would normally maintain valid logic one level during hi-z until next time slot pair becomes active. 1 cs5542 mdata3-mdata0 output timing characteristics
cs5542 cs5543 4 ds109pp2 cs5542 / cs5543 system switching characteristics: (t a = 25c, vd1+ = vd2+ = vd3+ = 5 v 5%; gnd1 = gnd2 = gnd3 = 0 v; for timing parameters: clkin= 2.048 mhz; dataclk = 6.144 mhz; mclk = 2.048 mhz; outputs loaded with 50 pf.) parameter number min typ max units cs5542 modulator timing mclk frequency 0 1.024 - 2.048 mhz mclk duty cycle 1 40 - 60 % fsync frequency 2 - mclk/ 16 -hz fsync set-up before mclk rising edge 3 70 - - ns fsync hold time after mclk rising edge 4 70 - - ns mclk rising to mdata[3:0] valid 5 70 ns mclk rising to mdata[3:0] high 6 70 ns mclk falling to mdata[3:0] to hi-z 7 70 ns mclk falling to mdata[3:0] active 8 70 ns cs5543 system timing clkin frequency (1/clock period) 9 1.024 - 2.048 mhz clkin duty cycle 10 40 - 60 % dataclk frequency (1/clock period) 11 3.072 - 6.144 mhz dataclk duty cycle 12 40 - 60 % frame rising to clkin rising 13 20 ns frame rising to next dataclk rising 14 20 ns frame period 15 1 ms clkin rising to mclk rising 16 0 50 ns clkin falling to mclk falling 17 0 50 ns cs5542 /cs5543 interface fsync period 18 - 7.81 - s mclk falling to fsync rising or falling 19 0 70 ns cs5543 to cs5543 interface dataclk rising to dataout valid 20 65 ns datain set-up time before dataclk rising 21 0 15 ns datain hold time after dataclk rising 22 15 15 ns
cs5542 cs5543 ds109pp2 5 mclk fsync valid data dataclk tck, clkin frame dataout [3:0] dmode [2:0], datsel[3:0], jtag pins, oe, fegain 11 valid data datain [3:0] 15 14 13 20 9 16 17 19 3 18 19 4 21 22 cs5542/cs5543 system timing diagram clkin dataout [3:0] sign bit from "nearest" channel (beginning of frame n-2) parity bit from "most remote" channel (end of frame n-3) dataclk clkin frame dataout [3:0] frame 1 filter output time output word cycle n - 1 n n + 1 n + 2 n + 3 dataclk n - 1 n - 2 n - 3 expanded inter-view timing n multi-frame system timing diagram
cs5542 cs5543 6 ds109pp2 cs5543 filter characteristics: (t a = 25c, vd1+ = vd2+ = vd3+ = 5 v 5%; gnd1 = gnd2 = gnd3 = 0 v; output word rate (owr) = clkin/2048) parameter min typ max units passband - - 0.5 owr -3 db frequency - 0.536 - owr equivalent noise bandwidth 0.536 owr stop band 0.016 0.5 128 x owr stop band rejection (cs5543 only) 120 db stop band rejection (cs5542/43 combination) 127 db group delay 3/owr s group delay vs. frequency (linear phase) 0 s decimation ratio (cs5543 input to output) 128
cs5542 cs5543 ds109pp2 7 0.0 0.1 0.2 0.3 0.4 0.5 normalized to output word rate -3.0 -2.7 -2.4 -2.1 -1.8 -1.5 -1.2 -0.9 -0.6 -0.3 -0.0 h(z), db 0.0 0.1 0.2 0.3 0.4 0.5 normalized to modulator sample frequency -300 -270 -240 -210 -180 -150 -120 -90 -60 -30 0 h(z), db modulator sample frequency = mclk/16; output word rate = mclk/2048 hz digital filter total response cs5543 digital filter passband response
cs5542 cs5543 8 ds109pp2 cs5542 digital characteristics: (t a = 25c, vd+ = 5 v 5%; dgnd = 0v; output loaded with 50 pf) cs5542 recommended operating conditions: (gndr = gndl = refgndr = refgndl = dgnd = 0v) cs5542 absolute maximum ratings*: (voltages with respect to gnd = 0v) notes: 7. transient model is 100 pf through a 1500 ohm source resistance. *warning: operation beyond these limits may result in permanent damage to the device normal operations not guaranteed at these extremes parameter symbol min typ max units high-level input voltage v ih vd+ -1.0 - - v low-level input voltage v il --1v high-level output voltage (i out = 600 m a) v oh vd+ -0.4 - - v low-level output voltage (i out = 800 m a) v ol --0.4v input leakage current (all pins except oe = logic 0) i in --10 m a input leakage current (oe pin only, oe pin = logic 0) i in --25 m a output leakage current i out --10 m a digital input capacitance c in -7-pf digital output capacitance c out -7-pf parameter symbol min typ max units operating voltages positive analog va+ 4.75 5.0 +5.25 v negative analog va- -4.75 -5.0 -5.25 v positive digital vd+ 4.75 5.0 +5.25 v vref+ vref+ 2.0 4.0 4.1 v vref- vref- -2.0 -4.0 -4.1 v parameter symbol min typ max units source transient voltage into inl and inr inputs (note 7) - - 1000 v source transient current into inl and inr inputs - - 100 ma operating voltages positive analog negative analog positive digital va+ va- vd+ -0.3 +0.3 0.3 - - - 6.0 -6.0 (va+)+0.3 v v v input current, any pin except supplies i in --10ma digital input voltage v ind -0.3 - (vd+)+0.3 v storage temperature t stg -65 150 c
cs5542 cs5543 ds109pp2 9 cs5543 power supply: (t a = 25c; clkin = 2.048 mhz; dataclk = 6.144 mhz, vd+ = 5.25 v; gnd1 = gnd2 = gnd3 = 0v) cs5543 digital characteristics: (t a = 25c, v d + = 5 v 5%; gnd1 = gnd2 = gnd3 = 0v; output loaded with 50 pf) cs5543 recommended operating conditions: (gnd1 = gnd2 = gnd3 = 0v, all voltages with respect to 0v.) cs5543 absolute maximum ratings*: (gnd = 0v, all voltages with respect to 0v.) *warning: operation beyond these limits may result in permanent damage to the device normal operations not guaranteed at these extremes parameter symbol min typ max units consumption active powerdown 75 - 95 1700 mw uw parameter symbol min typ max units high-level input voltage v ih vd+-1.0 - - v low-level input voltage v il --1v high-level output voltage (i out = -600 m a) v oh vd+-0.4 - - v low-level output voltage (i out = 800 m a) v ol --0.4v input leakage current i in --10 m a output leakage current i out --10 m a digital input capacitance c in -7-pf digital output capacitance c out -7-pf parameter symbol min typ max units digital dc supply vd+ 4.75 5.0 5.25 v supply voltage required to maintain calibration information 4.0 - - v parameter symbol min typ max units power supplies: vd1+ vd2+ vd3+ -0.3 6.0 v input current (except supply pins) i in 10.0 ma digital input voltage v inp -0.3 (vd+)+0.3 v storage temperature t stg -65 150 c
cs5542 cs5543 10 ds109pp2 general description the cs5542 is a monolithic cmos dual delta-sig- ma modulator. each modulator in the cs5542 ac- cepts a low level current input, usually supplied by a photodiode (see figure 1). this current is digi- tized by the cs5542 modulator and filtered by the cs5543 digital fir decimation filter. four cs5542 modulator chips can be combined with one cs5543 filter chip to provide eight channels of data conver- sion as shown in figure 2. up to 128 8-channel blocks of cs5542/cs5543 chip sets can be con- nected to build a 1024 channel system as shown in figure 3. the cs5542/cs5543 combination sup- ports several calibration modes for the data acqui- sition system. theory of operation the cs5542/cs5543 chip set is designed to con- struct multi-channel current input digitizer sys- tems. the conversion clock input (clkin) into the cs5543 provides the master clock for the digi- tal filter. this clock can be as fast as 2.048 mhz. clkin is buffered inside the cs5543 and is passed to each of the cs5542 modulator chips as the mclk (modulator clock) signal. the cs5542/ cs5543 combination provides output conversion data at a word rate equal to clkin/2048. inl refgndl gndl ical inr refgndr gndr va- va+ vd+ dgnd mdata [3:0] c [2:0] cal [1:0] fsync mclk pdn capsize vref+ vref- sel0 sel1 cs5542 +4.0 v -4.0 v .1 m f photodiode reference 8 meg +5 v -5v 5 6 4 10 8 7 9 13 12 23 22 25,24,21,20 28,27,26 19, 18 16 17 11 1 32 14 15 2 3 4 to cs5543 decimator photodiode -4.0 v i fs i r 10 m f .1 m f .1 m f10 m f .1 m f 10 w differential reference voltage .1 m f note 1 note 1: diodes can be connected with either polarity. as shown the cs5542/43 will generate a more negative code as the photodiode outputs more current. 2: the ical current can be of either polarity. its magnitude will determine the full scale measurement range. note 1 note 2 dgnd agnd figure 1. cs5542 typical connection diagram
cs5542 cs5543 ds109pp2 11 inl inr ical cs5542 inl0 inr0 inl inr ical sel1 sel0 cs5542 inl1 inr1 inl inr ical mdata[3:0] c[2:0] cal[1:0] fsync mclk pdn sel1 sel0 cs5542 inl2 inr2 inl inr ical mdata[3:0] c[2:0] cal[1:0] fsync mclk pdn sel1 sel0 cs5542 inl3 inr3 ical pdn mclk fsync cal[1:0] c[2:0] mdata[3:0] rst tck tms tdi tdo frame datclk clkin dataout[3:0] datain[3:0] datsel[3:0] dmode[2:0] rst tck tms tdi tdo frame datclk clkin dataout[3:0] datain[3:0] datsel[3:0] dmode[2:0] cs5543 caps mclk pdn mdata[3:0] c[2:0] cal[1:0] fsync mdata[3:0] c[2:0] cal[1:0] fsync mclk pdn sel1 sel0 capsize capsize capsize capsize fegain fegain oe oe supplies omitted for clarity vd+ vd+ vd+ dgnd dgnd vd+ dgnd dgnd figure 2. typical 8-channel connection diagram
cs5542 cs5543 12 ds109pp2 in0 in1 in2 in3 in4 in5 in6 in7 ical0 8-channel block 0 inl0 inr0 inr1 inl2 inr2 inl3 inr3 ical inl1 in8 in9 in10 in11 in12 in13 in14 in15 ical1 8-channel block 1 inl0 inr0 inr1 inl2 inr2 inl3 inr3 ical inl1 in1016 in1017 in1018 in1019 in1020 in1021 in1022 in1023 ical127 8-channel block 127 inl0 inr0 inr1 inl2 inr2 inl3 inr3 ical inl1 to tdi of next ieee 1149.1 - compliant device in system dataout[3:0] current inputs host system interface rst tck tms frame dataclk clkin datsel[3:0] dmode[2:0] dataout[3:0] tdo tdi datain[3:0] tdi datain[3:0] rst tck tms frame dataclk clkin datsel[3:0] dmode[2:0] dataout[3:0] tdo fegain from tdo of previous ieee 1149.1 - compliant device in syste m tdi datain[3:0] oe rst* tck tms frame dataclk clkin datsel[3:0] dmode[2:0] fegain datain[3:0] oe rst tck tms frame dataclk clkin datsel[3:0] dmode[2:0] dataout[3:0] tdo oe fegain oe fegain figure 3. typical 1024 connection diagram
cs5542 cs5543 ds109pp2 13 the cs5542 includes two modulators. the input current into each of the modulators is set by the fol- lowing factors: the mclk (modulator clock) fre- quency, the value of the vref voltage to modulator chip, and the logic value of the cap- size input to the cs5542 modulator (this selects either a 1.6 pf or a 4.8 pf transimpedance feedback capacitor). mclk is typically set as some frequen- cy between 1.024 mhz and 2.048 mhz. the vref voltage is optimally set to 4.0 volts. the voltage reference for the modulator is actually in- put into both the vref+ and vref- pins as +4.0 and -4.0 volts. the full scale input current is defined by the fol- lowing equation: (v ref ) x (c dac ) x (mclk/16) = i fs with vref = 4.0, mclk = 2.048 mhz, and cdac set to select 1.6 pf, the nominal full scale current will be set at 819 na. the value of the off- set and gain register contents will affect the actual conversion words which are output from the con- verter with a specific input current. several calibra- tion steps (to be discussed later) are necessary to ensure that the chip converts accurately. the cs5542 dual modulator and cs5543 multi- channel filter are designed to interface together. the cs5542 modulator uses a tri-level modulator. the modulator thresholds must be calibrated before accurate measurements can be accomplished. the threshold values are measured and digitally cor- rected inside the cs5543 digital filter. the cs5543 digital filter functions as a digital calibra- tion engine and a communications interface in ad- dition to being an fir filter. the cs5543 digital filter collects the multi-bit quantized data from four dual modulator cs5542s and computes offset and gain corrections to the da- ta, yielding a 24-bit output word. the 24-bit output data word includes an overflow bit, a parity bit, and 22 data bits (21 bits plus sign). there are several clocks which control the timing to the multi-channel system. clkin (master clock) is the primary clock to the system. clkin (typically 2.048 mhz) is input to the cs5543 filter. inside the filter clkin is buffered and passed to the cs5542s as mclk. for each two clock cycles of mclk to the modulator, a four bit modulator sample is passed to the cs5543 digital filter. the digital filter computes an output conversion word for each set of 1024 modulator samples. the out- put word rate of the filter is therefore related to the clkin or mclk frequency by the ratio clkin/2048 = owr (output word rate). the con- version data for eight cs5542 modulator channels is output from the four cs5543 dataout pins in a serial-formatted, time-multiplexed fashion. the dataclk controls the rate at which data is output from the dataout pins. dataclk is three times the frequency of clkin. the cs5542/cs5543 chip set is designed to sup- port constructing a serially-connected current digi- tization system with up to 1024 channels. system initialization and calibration after power is applied to the cs5542/cs5543 sys- tem, a reset must be issued to the cs5543 device by taking the rst pin low. this resets the gain regis- ter to 0.8 (199998(h)) and all other registers to 0.0. after rst is returned high, the release of the rst state is not recognized until the next rising edge of the frame signal. after a reset is recognized, the cs5542/cs5543 system must complete a full set of calibration steps before being used for measurement. cali- brations are performed by controlling the states of the dtest (digital test mode select) pins with the datsel (data select mode) pins held as logic 0s. tables 1 and 2 illustrate the com- mands available via the dtest and datsel
cs5542 cs5543 14 ds109pp2 pins. when entering calibration commands via the dtest lines, the calibration steps must follow a specific sequence for the cs5542/cs5543 pair to be properly calibrated. figure 4 illustrates the cal- ibration sequence for the cs5542/cs5543 chip set. after the rst is issued, the chip set will be in the normal mode. the first calibration step is the input offset voltage cal mode. the cs5542 is designed to digitize an input cur- rent. this current is normally sourced from a pho- todiode at the input of the chip. the input offset voltage cal step is intended to remove any offset at the front end of the modulator. this should be cal- ibrated with no photodiode current present. if the phototdiode is replaced with a resistor, the voltage table 1. operation modes notes: 1. msw = most significant word 2. lsw = least significant word table 2. control modes datsel[3:0] dtest[2:0] function 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 normal operation input offset voltage cal noise cal system offset cal full-scale gain cal (uses ical input) full-scale gain cal (uses inl(inr) input) decimator and modulator power-down modular power down dtest[2:0] datsel[3:0] function data type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 x x normal operation tri-state dataout [3:0] pins test pattern #1 test pattern #2 offset cal register load offset cal register load gain cal register load noise cal register load offset cal register read offset cal register read gain cal register read noise cal register read reserved (sign, msb first) (- - -) (msw) (note 1) (lsw) (note 2) (msw) (lsw) note: main current input must be idle for all calibration modes except for gain cal using inl(inr). normal system reset input offset voltage cal noise cal system offset cal inr(inl) or ical gain cal normal figure 4. calibration sequence cs5542/cs5543
cs5542 cs5543 ds109pp2 15 should be zeroed before calibrating the input offset voltage cal step. the input offset voltage cal mode will require 23 filter cycles (a filter cycle is one output conversion word) to complete. the cs5543 will not accept new mode commands until the 23 filter cycles have been completed, even if the dtest pins are changed. after the 23 filter cy- cles, the calibration step is complete. note that when the input offset voltage cal command is ini- tiated inside the cs5543 decimator, the modulators of all of the cs5542 chips connected to the cs5543 will execute the calibration step at the same time. there is no calibration word or register inside the cs5543 which contains the calibration data for this calibration step. the next calibration to be performed is the noise cal. this calibration step is necessary to calibrate the quantizer threshold of the modulators. this en- sures linearity in the multi-bit quantizer. the noise cal lasts 409 filter cycles. upon entering the noise cal mode, the system offset registers are set to 0; all gain registers are unaffected. the noise cal step can be performed at any time and it can be per- formed independent of the other calibration steps. when this step is executed, all eight modulators as- sociated with a cs5543 calibrate at the same time. at the end of the noise cal step, a 24-bit calibration word is placed into the noise cal register inside the cs5543. after the modulators have been calibrated by the noise cal step, the system offset cal step is per- formed. the current present at the inl (inr) input at the time the system offset cal is performed will treated as the zero point of the converter transfer function. the system offset cal step lasts 1028 fil- ter cycles. at the end of the system offset cal, a signed 43-bit result is placed into two system off- set cal registers (msw and lsw; most significant word and least significant word) inside the cs5543. after the system offset cal is complete, the next calibration step is a gain calibration. to perform a gain calibration, an input signal must be 2 23 2 22 2 1 2 0 noise calibration register lsb parity (note 1) msb r0 0 0 0 2 23 2 22 2 1 2 0 system offset registers lsb parity (note 1) sign msw 2 21 2 20 sign sign upper 20 bits 2 23 2 22 2 1 2 0 lsb parity (note 1) 0 lsw 2 21 2 20 lower 22 bits 2 2 2 1 2 -19 lsb gain registers lsb parity (note 1) 2 0 2 0 decimal integer 2 -1 2 -2 reset to binary 000.11001100110011001000 or 199998(h) note 1: all parity bits are odd. table 3. calibration registers
cs5542 cs5543 16 ds109pp2 provided into the cs5542. the cs5542 dual mod- ulator is designed to allow for two possible means of inputting the signal necessary to perform this calibration step. the input method chosen will dic- tate whether an ical full-scale gain cal or a sys- tem full-scale gain cal is to be performed. at the input of the cs5542 is an ical pin. a cur- rent can be sourced into this pin to provide a cali- bration current to set the full scale point (actually 97% of the full scale value as will be discussed lat- er) of the system. the current into the ical pin will be used to calibrate the gain if the full-scale gain cal mode (using the ical input) is selected. note that the ical pin on the cs5542 is shared be- tween the two modulators. each modulator will be calibrated sequentially (only one of eight channels will be active at a time during the calibration if the ical full-scale gain cal mode is executed. the cs5543 will sequentially calibrate each one of the eight modulators associated with it. each gain cal requires 5 filter cycles; therefore 40 filter cycles will elapse for the ical full-scale gain cal. at the end of the gain cal, a 24-bit calibration word is placed into the gain register of the cs5543. selection of the ical full-scale gain cal mode enables the ical input switch (note that the normal current input remains active and its current will be summed with the ical current when using this mode). during an ical full-scale gain cal cycle, only one ical input is active at any one time, therefore a single external resistor and a voltage source can supply a current which can be used to calibrate all eight channels associated with a single cs5543. alternatively, four individual resistors can be supplied, one for each cs5542 dual channel ical input. the magnitude of the calibration current should be 3% less than the desired full scale current. recall that the nominal full scale input current magnitude is set by the size of the internal transimpedance ca- pacitor, the clock rate, and the vref voltage. the output code produced by this current will be 2 21 - 2 16 -1 or approximately 97% of full scale. the 97% gain point can be calibrated with currents as low as 40% below the nominal full scale value set by the clock rate, cap size, and vref voltage. it is preferable to keep the input current for calibration within 20% of the nominal full scale value as lower levels of input calibration magnitude will exhibit a slight reduction in dynamic range. if the full-scale gain cal mode using inl (inr) is selected, the ical input mux at the front of each cs5542 is not used. instead, the gain is calibrated using the current input into the inl and inr pins. again, the current supplied should be 3% less than the desired full scale value. the output code due to this current will be set to 2 21 - 2 16 -1 or approxi- mately 97% of full scale. for either gain calibration mode (ical or inl (inr)) the magnitude of the input current should be 97% of the nominal full scale, but the polarity is not important. the current can be sinked or sourced. in either case the cs5543 will calibrate the positive full scale point. once calibrated, currents into the inl or inr pins will result in a positive output code, while currents out of the pins will yield a neg- ative output code. calibration register readability the cs5543 has registers which hold the digital calibration words for each of the eight channels. for each of the channels, there are four 24-bit reg- isters. the noise cal and gain cal functions each result in a 24-bit digital calibration word, whereas the system offset cal function produces a 48-bit calibration word which is split into two 24-bit reg- isters. these registers can be read and their contents stored into some nonvolatile storage from which they can be recalled and reloaded if so desired. the 48-bit offset register contents must be read or
cs5542 cs5543 ds109pp2 17 written with two read cycles using different com- mands to read either the msw (most significant word) or the lsw (least significant word). when reading or writing to the calibration regis- ters, the register contents are time-division multi- plexed into or out of the cs5543 in the same manner as conversion data as shown in figure 5. in addition to writing or reading the calibration reg- isters, the cs5543 provides several test modes. some of these test modes are as follows: the dataout [3:0] pins can be set to a high imped- ance output state; or either of two different test pat- terns can be requested to be output on the dataout [3:0] pins of the cs5543. see table 4 for the test pattern information. commands to change calibration modes or control modes should not be issued to the system while a calibration is in progress. new data for the calibra- tion or control modes is latched on every falling edge of clkin and takes effect on the following rising edge of frame. test pattern #1: (all channels) table 4. test patterns parity msb sign lsb sign parity msb channel 0 channel 4 parity msb sign sign parity msb channel 2 channel 6 parity msb sign sign parity msb channel 1 channel 5 parity msb sign sign parity msb channel 3 channel 7 dataout [0] dataout [1] dataout [2] dataout [3] od od od od lsb lsb lsb lsb lsb lsb lsb od od od od figure 5. data transfer timing hex binary test pattern #1: (all channels) a00001 0001 0000 0000 0000 0000 0001 sign, msb lsb, parity test pattern #2: (unique for each channel) channel hex binary 0 1 2 3 4 5 6 7 1000a0 000a01 20a000 0a0001 450000 005001 800500 000051 0001 0000 0000 0000 0000 0001 0000 0000 0000 1010 0000 0001 0010 0000 1010 0000 0000 0000 0000 1010 0000 0000 0000 0001 0100 0101 0000 0000 0000 0000 0000 0000 0101 0000 0000 0001 1000 0000 0000 0101 0000 0000 0000 0000 0000 0000 0101 0001 sign, msb lsb, parity
cs5542 cs5543 18 ds109pp2 conversion coding each of the channels of the cs5543 outputs a 24- bit conversion data word. the word includes a sign bit along with 21 additional data bits, an oscillation detect flag (od), and an odd parity bit. the format of the data conversion word is shown in figure 6. the od bit is set whenever the modulator in the cs5542 is overranged to the point of making it lose stability. under this condition the output data can be erroneous. the od bit can be set whenever the input magnitude exceeds the full scale point by greater than 5%. the od bit will be cleared when- ever the modulator input comes back into proper range. table 5 illustrates the output coding for the cs5542/cs5543 chip set. positive current means that current is flowing into the inl (inr) pin and produces a positive output code. cs5543 serial data interface the serial data interface on the cs5543 has four in- put signals and four output signals. data read from the cs5543 is output from the dataout[3:0] pins. dataout[0] outputs data from channels 0 and 4; dataout[1] outputs data from channels 1 and 5; dataout[2] outputs data from channels 2 and 6; and dataout[3] outputs data from chan- nels 3 and 7. information from dataout[0] is output beginning with the sign bit of channel 0 and ends with the parity (odd) bit of channel 4. data out of the other dataout pins follows the same convention. in a system, multiple cs5543s are connected with the dataout pins of one cs5543 connected to the datain pins of the next cs5543. dataout[3:0] lines will change immediately af- ter the rising edge of dataclk, and be latched into the datain[3:0] pins on the next rising edge of dataclk. a timing diagram which shows eight channels of data transfer from one cs5543 to another is shown in figure 5. the data which is transmitted either to or from the series-connected cs5543s is synchronized by the frame signal. frame should be a pulse, one clkin cycle wide, generated by falling edges of 2 23 2 22 2 1 2 0 sign 2 21 2 20 msb lsb od parit y 2 2 figure 6. data conversion word format note 1 positive full scale is current going into the modulator. d out = 2,097,151 [(i in - i of )/(i fs - i of )] where d out is the digital output code from the cs5543; i of is the current going into the modulator during system offset voltage calibration; i fs is the full scale input current which is always positive in magnitude and w ill be the absolute value of the current going into either inl/inr or ical pin, divided by 0.97; and i in is the current going into the modulator during the conversion. 2,097,151 is 2 21 - 1. table 5. output coding for cs5542/cs5543. bipolar input current output code (sign and 21 data bits) positive full scale 1 1 0 0000 0000 0000 0000 0000 zero input 0 0 0000 0000 0000 0000 0000 negative full scale 1 1 1111 1111 1111 1111 1111
cs5542 cs5543 ds109pp2 19 clkin. frame will be latched into the cs5543 by the rising edge of clkin. this will subse- quently generate an fsync signal to synchronize the cs5542 modulators. system connections an eight channel digitizer system can be construct- ed using four cs5542 dual modulators with one cs5543 eight-channel decimator. figure 2 illus- trates the hardware signal connections for an eight channel system. digitizer blocks of eight channels each can be cas- caded to connect 128 blocks together for a total of 1024 digitizer channels. all clocks in the system are related to the clkin master clock. assuming that clkin= 2.048 mhz, the converter output word rate will be clkin/2048. a data framing signal, frame, synchronizes the digital output data and the modulator data. the frame signal must occur at the output word rate. the data- clk must be three times faster than the clkin rate, 6.144 mhz in this example. the cs5543 has four dataout lines. each of the lines provides an output for the data from two of the eight channels associated with a single cs5543. data from any one dataout line is se- rially transferred out of the dataout pin in 48- bit blocks, consisting of two 24-bit words. with 128 cs5543 linked together, each of the four serial lines linking dataout pins to datain pins is in effect a serial shift register 6144 (48 x 128) bits long. the dataclk is used to shift data out of each cs5543 in 48 bit blocks. for a 1024 channel system with an clkin rate of 2.048 mhz, the 6.144 mhz dataclk will shift out the data for all 1024 channels in one millisecond. analog input the cs5542 modulator is optimized to be driven by a photodiode current source. photodiodes have large output impedances. a photodiode also has a capacitance which is a function of its size. the cs5542 relies on this capacitance to ensure the sta- bility of its input stage. the capacitance also af- fects the bandwidth of the input circuit. in all cases the modulator assumes that the external shunt capacitance of the photodiode is at least 220pf. if the input source is actually a voltage source and a resistor is used to generate the input current, a 220 pf capacitor should be connected between the in- put pin and ground. the resistor will add additional current noise into the circuit and will degrade the dynamic range somewhat. voltage reference the voltages supplied to the vref+ and vref- pins can range from 2.0 volts to 4.1 volts with 4. 0 volts being preferred. vref+ and vref- voltages should be balanced and have low noise. figure 7 illustrates how a bandgap voltage refer- ence can be well filtered to provide a low noise source for +4.0 volts. >9v 10 m f + lt1019- 5 10 1k 4.02k 1k 10k 100 m f + 100 m f + >9v op27 1k 47k 0.01 m f 22 + 15 m f + 0.1 m f +4.0 figure 7. noise-filtered bandgap reference
cs5542 cs5543 20 ds109pp2 each vref+ or vref- input on a cs5542 may re- quire up to 1 microamp of reference current. the number of channels which can be supplied from one voltage reference buffer will depend upon the buffers output impedance and the distance be- tween the cs5542 and the reference circuitry. a well-designed voltage reference should be able to supply 32 channels (16 cs5542s) in a system. board layout the circuit board containing the cs5542 modulator should have a ground plane split through middle of the modulator with pins 2 through 13 over a quiet analog ground plane. in addition, guarding tech- niques should be used around the low level inputs inl, inr, and ical. care must also be exercised to ensure that the circuit card is manufactured with good quality to ensure low leakage. after assem- bly, the card should be cleaned to ensure it is free from all surface contaminants. clock source clkin must have low jitter; less than 20 psec rms. note that any drift in clkin over time or temperature will show up as a gain error in the cs5542/cs5543 measurement system; therefore a stable clock source is highly desirable. power supply power supply noise and ripple must be very low within the passband of the cs5543 digital filter. this noise and ripple can pass through the esd (electrostatic discharge) protection diodes at the inl (inr) pin into the transimpedance stage of the cs5542 modulator. with the capacitance of this diode at about 5 pf, and the transimpedance resis- tor of the first stage at about 2-10 megohm, cou- pling of supply ripple is going to occur. for this reason, the noise and ripple on the power supplies should be low enough that the noise coupled into the transimpedance stage should remain below the noise floor of the converter across the bandwidth of the digital filter. to achieve this, 60 hz related noise and ripple should remain below 50 micro- volts peak-to-peak. digital filter the digital filter is a linear phase fir filter. the filter has a group delay of three conversion words and an equivalent noise bandwidth of 0.536 of the output word frequency. plots for the filter are shown in the data sheet tables. coefficients are tab- ulated in the appendix of this data sheet. joint test action group (jtag) boundary-scan interface the cs5543 is designed for large multi-channel systems. for this reason the chip is designed to sup- port the ieee standard access port and boundary- scan architecture as defined in ieee std. 1149.1- 1990, or p1149.1. this standard defines circuitry which is built into the an integrated circuit to assist in the test, maintenance, and support of a system at the printed circuit board level. the cs5543 in- cludes circuitry which supports this standard. it is highly recommended that if this type of test ca- pability is desired in your system, that you acquire a copy of the ieee standard which thoroughly dis- cusses the ieee standard access port and bound- ary-scan architecture as it will only be discussed briefly here. the cs5543 includes a tap (test access port) made of the following connections: tck (test clock), tms (test mode select input), tdi (test data input), and tdo (test data output). in ad- dition to the tap, the test logic includes a tap controller, an instruction register, and a set of test registers. the tap controller is a synchronous fi- nite state machine which controls the sequence of operations necessary to implement the boundary- scan architecture. figure 8 illustrates the tap con- troller state diagram. the instruction register al- lows an instruction to be shifted into the design.
cs5542 cs5543 ds109pp2 21 the instruction register is used to select the test to be performed or to select the test data register to be accessed. the 3-bit instructions available in the in- struction register are illustrated in table 6. the lsb of the 3-bit instruction is shifted in first. table 6. boundary scan instructions several test registers are in the design including the boundary-scan register (bsr), the device identi- fication register (dir), the operating mode reg- ister (omr), and the bypass register (br). the boundary-scan register allows for the testing of board interconnects. the bit ordering for the bsr is the same as the top-view packaged pinout, clockwise beginning with the mdata[3], and ending with rst . the tap, power and gnd pins are not included as part of the boundary-scan regis- ter. the bsr is 47 bits long. inputs can be set via the bsr, bypassing the actual pin. all outputs are 3-state (logic high, low and or high impedance) outputs. their states during test can be controlled via the preload instruction. in the boundary- scan register, each input pin of the device is repre- sented by one bit position of the boundary scan reg- ister, whereas each of the outputs, having the possibility of any one of three states, require two bits each in the boundary-scan register. the device identification register is designed to identify the manufacturer, the part number, and the version number of the cs5543. the format of the dir is illustrated in table 7. data from the dir is shifted out of the tdo lsb first. note that when the cs5543 is reset, the instruction register is set to select idcode. ir code instruction 000 001 010 011 100 101 110 111 extest sample/preload idcode operating mode register reserved reserved reserved bypass test-logic-reset 1 0 run-test/idle capture-dr select-dr-scan shift-dr exit1-dr pause-dr exit2-dr update-dr capture-ir select-ir-scan shift-ir exit1-ir pause-ir exit2-ir update-ir 0 0 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 1 0 1 0 figure 8. tpa controller state diagram
cs5542 cs5543 22 ds109pp2 the operating mode register (omr) allows ac- cess to the device operating modes via the data- sel and dmode pins as shown in figure 9. the bypass register allows a minimum length path between the tdi and tdo pins on the device. this register can be selected whenever the device does not need to be tested during board-level test opera- tion. tap operation for extest before execution of the instruction extest, the sample/preload instruction must be used to load testing data to all output pins through tdi. each output pin requires two bits. the first bit to be shifted in controls the output enable function. if a logic 1 is entered, the output is enabled; if a logic 0 is entered, the output is disabled. the second bit shifted in after the first bit is the test data. there- fore, two tck cycles are required to load testing data into the boundary-scan register for each output pin. device identification register table 7. device identification register tdi datsel dmode 3 2 1 0 2 1 0 6 5 4 3 2 1 0 tdo omr bit # figure 9. operating mode register msb 31 16 v3 v2 v1 v0 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 15 lsb 0 p3 p2 p1 p0m10m9m8m7m6m5m4m3m2m1m0 1 bit name value function v3-v0 version bits 0000 version number of device p15-p0 part number bits 0101010101000011 part number of device m10-m0 manufacture number bits 00001100100 manufacture number l0 logic 1 1 always logic 1
cs5542 cs5543 ds109pp2 23 cs5542 pin descriptions power supplies gndl - ground left, pin 4. left modulator analog ground for integrators 2 through 5. refgndl - reference ground left, pin 6. analog ground for left modulator integrator 1 and summing node. gndr - ground right, pin 9. right modulator analog ground for integrators 2 through 5. refgndr - reference ground right, pin 7 analog ground for right modulator integrator 1 and summing node. va+ - positive analog supply, pin 12. positive analog supply voltage. nominally +5 volts. va- - negative analog supply, pin 13. negative analog supply voltage. nominally -5 volts. vd+ - digital supply, pin 23. digital supply voltage. nominally +5 volts. top view 22 20 24 19 21 23 25 3 27 2 4 26 28 1 12 14 16 18 13 15 17 8 6 10 5 7 9 11 capsize vref- vref+ gndl inl refgndl refgndr inr gndr ical pdn va+ va- sel0 c2 c1 c0 mdata3 mdata2 vd+ dgnd mdata1 mdata0 cal1 cal0 mclk fsync sel1 cs5542
cs5542 cs5543 24 ds109pp2 cs5542 pin descriptions dgnd - digital ground, pin 22. digital ground. digital input pins- mclk - modulator clock input, pin 17. the modulator clock input provides the necessary clock for operation of the modulator. mclk operates at 16 times the modulator sample rate. mclk is 2048 times the output word rate. fsync - frame sync, pin 16. the transition from a low to high level on this input supplied by the cs5543, will reset the internal master timing of the cs5542 and synchronize its data with each output word. cal[1:0] - calibration control, pins 19, 18. the mode of operation for the cs5542 is selected through the calibration control pins via the cs5543 and is summarized in the table below. cal1 cal0 mode selected 0 0 normal operation, noise cal, offset cal 0 1 input offset voltage calibrate 1 0 unused code 1 1 full scale gain calibrate normal calibration sequence 01 input offset 00 noise cal(dark) 00 offset cal(dark) 11 gain cal 00 normal operation sel[1:0] - time slot selections, pins 15,14 the binary code applied to sel0 and sel1 will determine the time slot pair associated with the cs5542. each of the up to four cs5542's connected to a single cs5543 must have a unique code assigned to the combination of sel0 and sel1. capsize - full scale input range select, pin 1. when capsize = 0, c dac = 1.6 pf; when capsize = 1, c dac = 4.8 pf
cs5542 cs5543 ds109pp2 25 cs5542 pin descriptions pdn - power down, pin 11. when asserted the cs5542 will enter the power-down state. c[2:0] - ical input select, pins 28, 27, 26. in an array of 4 cs5542's (eight channels), c2-c0 will select which channel is to receive the d.c. current applied to the ical pins. digital outputs pins- mdata[3:0] - modulator data outputs, pins 25, 24, 21, 20. the tri-level modulator data is output on mdata3 - mdata0 for decimation by the cs5543. modulator output coding table overload -1 zero +1 mdata3 mdata2 mdata_1 mdata0 value / meaning 1 0 0 1 +1 / normal operation 1 0 1 0 0 / normal operation 1 1 0 0 -1 / normal operation 0 1 1 0 +1 / modulator overload 0 1 0 1 0 / modulator overload 0 0 1 1 -1 / modulator overload as shown in the table above, a constant number of zeros and ones exist for all output states. this provides a data-independent noise invariant coding to maximize isolation between channels. analog input pins - vref-,vref+ - differential voltage reference inputs, pins 2, 3. a differential voltage reference on these pins operates as the voltage reference for the cs5542. nominally, it is -4.0 v and + 4.0 respectively. ical - full-scale current calibration input, pin 10. ical needs to be supplied for full-scale gain calibration. inl, inr - input left and input right, pins 5, 8. inl and inr are the left and right modulator current input pins.
cs5542 cs5543 26 ds109pp2 cs5543 pin descriptions power supply vd1+, vd2+, vd3+ - digital power supplies, pins 13, 25, 39. digital supply voltages. nominally +5 volts. gnd1, gnd2, gnd3 - digital ground, pins 12, 24, 40. digital grounds. dsm-dsd interface pins c[2:0] - ical channel select (outputs), pins 7, 6, 5. in an array of 4 cs5542's (eight channels), c2-c0 will select which channel is to receive the d.c. current applied to the ical pins during full-scale gain calibration. top view 18 20 22 24 26 28 1 2 4 6 40 42 44 12 8 10 14 16 7 9 11 13 15 17 29 31 33 35 37 39 34 30 32 36 38 cs5543 datain[0] datain[1] datain[2] datain[3] c0 c1 c2 cal[0] cal[1] fsync mclk gnd1 vd1+ caps pdn mdata[0] mdata[1] mdata[2] mdata[3] tms tdi tdo dataout[0] dataout[1] dataout[2] dataout[3] gnd3 vd3+ dataclk frame clkin datsel[0] datsel[1] datsel[2] datsel[3] dtest[0] dtest[1] dtest[2] fegain oe rst vd2+ gnd2 tck
cs5542 cs5543 ds109pp2 27 cs5543 pin descriptions cal[1:0] - calibration control (outputs), pins 8, 9. the mode of operation for the cs5542 is selected through the calibration control pins. see the table in the pin-out section of the cs5542 data sheet for details. fsync - frame sync (output), pin 10. the transition from a low to high level at the cs5542's input will reset the internal master timing of the cs5542 and synchronize its data with each output word from the cs5543. mclk - modulator clock (output), pin 11. the modulator clock output provides the necessary clock for operation of the modulator. capsize - full scale input range select (output), pin 14. controls the capsize input to the cs5542. this determines the size of the sampling capacitor used by the cs5542. pdn - power down (output), pin 15. when asserted the cs5542 will enter the power-down state. mdata[3:0] - modulator data inputs (inputs), pins 16, 17, 18, 19. the tri-level modulator data is input to the cs5543 via mdata3 - mdata0 for decimation. see the table in the pin-out section of the cs5542 data sheet for details. test access port pins tms -test mode select (input), pin 20. controls the state-to-state operation of the tap controller. tdi - test data input (input) , pin 21. serially inputs data to the test access port. tdo - test data output (output), pin 22. serially outputs data from the test access port. tck - test clock (input), pin 23. the clock for the test access port, shorted to mclk control pins oe - output enable (input), pin 27. enables or disables (tri-states) all output pins on the cs5543. fegain - front-end gain select (input), pin 28. selects the front-end capacitor gain ratio. a full calibration is necessary following any change to this input.
cs5542 cs5543 28 ds109pp2 cs5543 pin descriptions dmode[2:0] - digital mode select (inputs), pins 29, 30, 31. selects the operation mode of the cs5543. datsel[3:0] - data selection mode (inputs), pins 32, 33, 34, 35. selects the data to be placed on the dataout[3:0] pins. rst - chip reset (input), pin 26 resets all internal logic and registers. dsd-system interface pins dataclk - serial data clock (input), pin 38. clock signal generated by the system controller which governs all serial output data timing from the cs5543. clkin - master system clock (input), pin 36. a cmos compatible clock input to this pin governs all non-serial data timing. frame - framing signal (input), pin 37. synchronizes dataclk and mclk for each frame of output data from the cs5543. dataout[3:0] - serial output data (outputs), pins 41-44. cs5543 serial output data. datain[3:0] - serial data inputs (inputs), pins 1-4. cs5543 serial input data from the serial output of the adjacent cs5543 in a multi-decimator system.
cs5542 cs5543 ds109pp2 29 filter coefficients h(0)=h(383)= -6 h(32)=h(351)= -2988 h(64)=h(319)= -32337 h(96)=h(287)= -6663 h(128)=h(255)= 613898 h(160)=h(223)= 2079544 h(1)=h(382)= -7 h(33)=h(350)= -3327 h(65)=h(318)= -33741 h(97)=h(286)= -229 h(129)=h(254)= 649637 h(161)=h(222)= 2126869 h(2)=h(381)= -10 h(34)=h(349)= -3695 h(66)=h(317)= -35134 h(98)=h(285)= 6812 h(130)=h(253)= 686379 h(162)=h(221)= 2173544 h(3)=h(380)= -15 h(35)=h(348)= -4094 h(67)=h(316)= -36508 h(99)=h(284)= 14489 h(131)=h(252)= 724107 h(163)=h(220)= 2219496 h(4)=h(379)= -21 h(36)=h(347)= -4524 h(68)=h(315)= -37856 h(100)=h(283)= 22828 h(132)=h(251)= 762800 h(164)=h(219)= 2264653 h(5)=h(378)= -29 h(37)=h(346)= -4988 h(69)=h(314)= -39167 h(101)=h(282)= 31855 h(133)=h(250)= 802436 h(165)=h(218)= 2308943 h(6)=h(377)= -39 h(38)=h(345)= -5487 h(70)=h(313)= -40431 h(102)=h(281)= 41596 h(134)=h(249)= 842990 h(166)=h(217)= 2352295 h(7)=h(376)= -52 h(39)=h(344)= -6021 h(71)=h(312)= -41638 h(103)=h(280)= 52077 h(135)=h(248)= 884434 h(167)=h(216)= 2394640 h(8)=h(375)= -67 h(40)=h(343)= -6594 h(72)=h(311)= -42777 h(104)=h(279)= 63323 h(136)=h(247)= 926737 h(168)=h(215)= 2435908 h(9)=h(374)= -85 h(41)=h(342)= -7205 h(73)=h(310)= -43834 h(105)=h(278)= 75361 h(137)=h(246)= 969867 h(169)=h(214)= 2476030 h(10)=h(373)= -107 h(42)=h(341)= -7856 h(74)=h(309)= -44798 h(106)=h(277)= 88214 h(138)=h(245)= 1013788 h(170)=h(213)= 2514942 h(11)=h(372)= -133 h(43)=h(340)= -8549 h(75)=h(308)= -45655 h(107)=h(276)= 101906 h(139)=h(244)= 1058463 h(171)=h(212)= 2552576 h(12)=h(371)= -163 h(44)=h(339)= -9283 h(76)=h(307)= -46389 h(108)=h(275)= 116461 h(140)=h(243)= 1103850 h(172)=h(211)= 2588870 h(13)=h(370)= -199 h(45)=h(338)= -10060 h(77)=h(306)= -46987 h(109)=h(274)= 131900 h(141)=h(242)= 1149907 h(173)=h(210)= 2623763 h(14)=h(369)= -240 h(46)=h(337)= -10881 h(78)=h(305)= -47431 h(110)=h(273)= 148246 h(142)=h(241)= 1196589 h(174)=h(209)= 2657194 h(15)=h(368)= -287 h(47)=h(336)= -11745 h(79)=h(304)= -47706 h(111)=h(272)= 165518 h(143)=h(240)= 1243847 h(175)=h(208)= 2689106 h(16)=h(367)= -342 h(48)=h(335)= -12654 h(80)=h(303)= -47793 h(112)=h(271)= 183736 h(144)=h(239)= 1291632 h(176)=h(207)= 2719443 h(17)=h(366)= -404 h(49)=h(334)= -13608 h(81)=h(302)= -47674 h(113)=h(270)= 202918 h(145)=h(238)= 1339892 h(177)=h(206)= 2748154 h(18)=h(365)= -475 h(50)=h(333)= -14605 h(82)=h(301)= -47330 h(114)=h(269)= 223081 h(146)=h(237)= 1388572 h(178)=h(205)= 2775188 h(19)=h(364)= -556 h(51)=h(332)= -15646 h(83)=h(300)= -46742 h(115)=h(268)= 244240 h(147)=h(236)= 1437615 h(179)=h(204)= 2800497 h(20)=h(363)= -647 h(52)=h(331)= -16730 h(84)=h(299)= -45888 h(116)=h(267)= 266410 h(148)=h(235)= 1486965 h(180)=h(203)= 2824037 h(21)=h(362)= -750 h(53)=h(330)= -17856 h(85)=h(298)= -44749 h(117)=h(266)= 289602 h(149)=h(234)= 1536559 h(181)=h(202)= 2845767 h(22)=h(361)= -865 h(54)=h(329)= -19023 h(86)=h(297)= -43301 h(118)=h(265)= 313827 h(150)=h(233)= 1586337 h(182)=h(201)= 2865647 h(23)=h(360)= -995 h(55)=h(328)= -20228 h(87)=h(296)= -41523 h(119)=h(264)= 339094 h(151)=h(232)= 1636234 h(183)=h(200)= 2883642 h(24)=h(359)= -1139 h(56)=h(327)= -21471 h(88)=h(295)= -39391 h(120)=h(263)= 365410 h(152)=h(231)= 1686186 h(184)=h(199)= 2899720 h(25)=h(358)= -1299 h(57)=h(326)= -22747 h(89)=h(294)= -36881 h(121)=h(262)= 392781 h(153)=h(230)= 1736126 h(185)=h(198)= 2913852 h(26)=h(357)= -1477 h(58)=h(325)= -24055 h(90)=h(293)= -33970 h(122)=h(261)= 421209 h(154)=h(229)= 1785986 h(186)=h(197)= 2926013 h(27)=h(356)= -1674 h(59)=h(324)= -25391 h(91)=h(292)= -30633 h(123)=h(260)= 450696 h(155)=h(228)= 1835697 h(187)=h(196)= 2936181 h(28)=h(355)= -1891 h(60)=h(323)= -26751 h(92)=h(291)= -26845 h(124)=h(259)= 481241 h(156)=h(227)= 1885189 h(188)=h(195)= 2944337 h(29)=h(354)= -2129 h(61)=h(322)= -28131 h(93)=h(290)= -22580 h(125)=h(258)= 512840 h(157)=h(226)= 1934391 h(189)=h(194)= 2950467 h(30)=h(353)= -2391 h(62)=h(321)= -29526 h(94)=h(289)= -17812 h(126)=h(257)= 545489 h(158)=h(225)= 1983233 h(190)=h(193)= 2954560 h(31)=h(352)= -2676 h(63)=h(320)= -30930 h(95)=h(288)= -12515 h(127)=h(256)= 579178 h(159)=h(224)= 2031641 h(191)=h(192)= 2956609

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