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rev 1.1.7 2/6/03 characteristics subject to change without notice. 1 of 24 www.xicor.com x9279 single digitally-controlled (xdcp tm ) potentiometer features 256 resistor taps 2-wire serial interface for write, read, and transfer operations of the potentiometer wiper resistance, 100 ? typical @ 5v 16 nonvolatile data registers for each potentiometer nonvolatile storage of multiple wiper positions power on recall. loads saved wiper position on power up. standby current < 5? max ? cc : 2.7v to 5.5v operation 50k ? , 100k ? versions of end to end resistance endurance: 100,000 data changes per bit per register 100 yr. data retention 14-lead tssop, 16-lead csp (chip scale package) low power cmos description the x9279 integrates a single digitally controlled potentiometer (xdcp) on a monolithic cmos integrated circuit. the digital controlled potentiometer is implemented using 255 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the 2-wire bus interface. the potentiometer has associated with it a volatile wiper counter register (wcr) and a four nonvolatile data registers that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. powerup recalls the contents of the default data register (dr0) to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. single supply / low power / 256-tap / 2-wire bus a pplication n otes and d evelopment s ystem a v a i l a b l e an99 ?an115 ?an124 ?n133 ?an134 ?an135 functional diagram 256-taps 50k ? and 100k ? r h r l r w pot v cc v ss 2-wire bus wiper interface power on recall wiper counter register (wcr) data registers 16 bytes bus interface and control address data status write read transfer inc/dec control
x9279 characteristics subject to change without notice. 2 of 24 rev 1.1.7 2/6/03 www.xicor.com detailed functional diagram dr0 dr1 dr2 dr3 wiper counter register (wcr) r h r l data r w interface and control circuitry v cc v ss 256-taps 50k ? and 100k ? bank 0 bank 1 bank 2 bank 3 12 additional nonvolatile registers 3 banks of 4 registers x 8-bits a0 scl sda a1 a2 wp control power on recall dr0 dr1 dr2 dr3 dr0 dr1 dr2 dr3 dr0 dr1 dr2 dr3 circuit level applications vary the gain of a voltage ampli?r provide programmable dc reference voltages for comparators and detectors control the volume in audio circuits trim out the offset voltage error in a voltage ampli?r circuit set the output voltage of a voltage regulator trim the resistance in wheatstone bridge circuits control the gain, characteristic frequency and q-factor in ?ter circuits set the scale factor and zero point in sensor signal conditioning circuits vary the frequency and duty cycle of timer ics vary the dc biasing of a pin diode attenuator in rf circuits provide a control variable (i, v, or r) in feedback circuits system level applications adjust the contrast in lcd displays control the power level of led transmitters in communication systems set and regulate the dc biasing point in an rf power ampli?r in wireless systems control the gain in audio and home entertainment systems provide the variable dc bias for tuners in rf wireless systems set the operating points in temperature control systems control the operating point for sensors in industrial systems trim offset and gain errors in arti?ial intelligent systems
x9279 characteristics subject to change without notice. 3 of 24 rev 1.1.7 2/6/03 www.xicor.com pin configuration pin assignments pin tssop pin csp symbol function 1 b2, b3 nc no connect 2 a4 a0 device address for 2-wire bus. 3 c2, c3 nc no connect 4 b4 a2 device address for 2-wire bus. 5 c4 scl serial clock for 2-wire bus. 6 d4 sda serial data input/output for 2-wire bus. 7d3 v ss system ground. 8d2 wp hardware write protect 9 d1 a1 device address for 2-wire bus. 10 c1 a3 device address for 2 wire-bus. 11 b1 r w wiper terminal of the potentiometer. 12 a1 r h high terminal of the potentiometer. 13 a2 r l low terminal of the potentiometer. 14 a3 v cc system supply voltage. v cc r l v ss 1 2 3 4 5 6 7 8 14 13 12 11 10 9 a0 r w scl a2 tssop r h x9279 nc nc sda a3 wp a1 a0 v cc r l r h a2 nc nc r w scl nc nc a3 sda vss wp a1 a b c d 4321 csp
x9279 characteristics subject to change without notice. 4 of 24 rev 1.1.7 2/6/03 www.xicor.com pin descriptions bus interface pins s erial d ata i nput /o utput (sda) the sda is a bidirectional serial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. it receives device address, opcode, wiper register address and data sent from an 2-wire master at the rising edge of the serial clock scl, and it shifts out data after each falling edge of the serial clock scl. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. s erial c lock (scl) this input is used by 2-wire master to supply 2-wire serial clock to the x9279. d evice a ddress (a2 - a0) the address inputs are used to set the least signi?ant 3 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9279. a maximum of 8 devices may occupy the 2- wire serial bus. potentiometer pins r h , r l the r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. r w the wiper pin is equivalent to the wiper terminal of a mechanical potentiometer. bias supply pins s ystem s upply v oltage (v cc ) and s upply g round (v ss ) the v cc pin is the system supply voltage. the v ss pin is the system ground. other pins n o c onnect no connect pins should be left open. this pins are used for xicor manufacturing and testing purposes. h ardware w rite p rotect i nput (wp ) the wp pin when low prevents nonvolatile writes to the data registers.
x9279 characteristics subject to change without notice. 5 of 24 rev 1.1.7 2/6/03 www.xicor.com principles of operation the x9279 is a integrated microcircuit incorporating a resistor array and associated registers and counter and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. this section provides detail description of the following: resistor array description. serial interface description. instruction and register description. array description the x9279 is comprised of a resistor array (see figure 1). the array contains, in effect, 255 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the ?ed terminals of a mechanical potentiometer (r h and r l inputs). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (r w ) output. within each individual array only one switch may be turned on at a time. these switches are controlled by a wiper counter register (wcr). the 8-bits of the wcr (wcr[7:0]) are decoded to select, and enable, one of 256 switches (see table 1). the wcr may be written directly. these data registers can the wcr can be read and written by the host system. power up and down recommendations. there are no restrictions on the power-up or power- down conditions of v cc and the voltages applied to the potentiometer pins provided that v cc is always more positive than or equal to v h , v l , and v w , i.e., v cc v h , v l , v w . the v cc ramp rate speci?ation is always in effect. figure 1. detailed potentiometer block diagram serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input counter register inc/dec logic up/dn clk modified sck up/dn r h r l r w 8 8 c o u n t e r d e c o d e if wcr = 00[h] then r w = r l if wcr = ff[h] then r w = r h wiper (wcr) bank_0 only (dr0) (dr1) (dr2) (dr3)
x9279 characteristics subject to change without notice. 6 of 24 rev 1.1.7 2/6/03 www.xicor.com serial interface description serial interface the x9279 supports a bidirectional bus oriented protocol. the protocol de?es any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the x9279 will be considered a slave device in all applications. clock and data conventions data states on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions. see figure 2. start condition all commands to the x9279 are preceded by the start condition, which is a high to low transition of sda while scl is high. the x9279 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition is met. see figure 2. stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high. see figure 2. acknowledge acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. the transmitting device, either the master or the slave, will release the sda bus after transmitting eight bits. the master generates a ninth clock cycle and during this period the receiver pulls the sda line low to acknowledge that it successfully received the eight bits of data. the x9279 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. if the command is followed by a data byte the x9279 will respond with a ?al acknowledge. see figure 2. figure 2. acknowledge response from receiver scl from master data output from transmitter 1 89 data output from receiver start acknowledge
x9279 characteristics subject to change without notice. 7 of 24 rev 1.1.7 2/6/03 www.xicor.com acknowledge polling the disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms eeprom write cycle time. once the stop condition is issued to indicate the end of the nonvolatile write command the x9279 initiates the internal write cycle. ack polling, flow 1, can be initiated immediately. this involves issuing the start condition followed by the device slave address. if the x9279 is still busy with the write operation no ack will be returned. if the x9279 has completed the write operation an ack will be returned and the master can then proceed with the next operation. flow 1: ack polling sequence instruction and register description device addressing: identification byte ( id and a) the ?st byte sent to the x9279 from the host, following a cs going high to low, is called the identi?ation byte. the most signi?ant four bits of the slave address are a device type identi?r. the id[3:0] bits is the device id for the x9279; this is ?ed as 0101[b] (refer to table 1). the a[2:0] bits in the id byte is the internal slave address. the physical device address is de?ed by the state of the a2-a0 input pins. the slave address is externally speci?d by the user. the x9279 compares the serial data stream with the address input state; a successful compare of both address bits is required for the x9279 to successfully continue the command sequence. only the device which slave address matches the incoming device address sent by the master executes the instruction. the a2-a0 inputs can be actively driven by cmos input signals or tied to v cc or v ss . instruction byte (i) the next byte sent to the x9279 contains the instruction and register pointer information. the three most signi?ant bits are used provide the instruction opcode i [2:0]. the rb and ra bits point to one of the four data registers. p0 is the pot selection; since the x9279 is single pot, the p0=0. the format is shown in table 2. register bank selection (rb, ra, p1, p0) there are 16 registers organized into four banks. bank 0 is the default bank of registers. only bank 0 registers can be used for data register to wiper counter register operations. banks 1, 2, and 3 are additional banks of registers (12 total) that can be used for 2-wire write and read operations. the data registers in banks 1, 2, and 3 cannot be used for direct read/write operations between the wiper counter register. nonvolatile write command completed enterack polling issue start issue slave address ack returned? further operation? issue instruction issue stop no yes yes proceed issue stop no proceed
x9279 characteristics subject to change without notice. 8 of 24 rev 1.1.7 2/6/03 www.xicor.com register selection (r0 to r3) table register bank selection (bank 0 to bank 3) table rb ra register selection operations 0 0 0 data register read and write; wiper counter register operations 0 1 1 data register read and write; wiper counter register operations 1 0 2 data register read and write; wiper counter register operations 1 1 3 data register read and write; wiper counter register operations p1 p0 bank selection operations 0 0 0 data register read and write; wiper counter register operations 0 1 1 data register read and write only 1 0 2 data register read and write only 1 1 3 data register read and write only table 1. identification byte format table 2. instruction byte format id3 id2 id1 id0 0 a2 a1 a0 0101 (msb) (lsb) device type identifier set to 0 for proper operation internal slave address i3 i2 i1 i0 rb ra p1 p0 (msb) (lsb) instruction opcode register pot selection (bank selection) set to p0=0 for potentiometer operations selection p1 and p0 are used also for register bank selection for 2-wire register write and read operations register selection register selected rb ra dr0 0 0 dr1 0 1 dr2 1 0 dr3 1 1
x9279 characteristics subject to change without notice. 9 of 24 rev 1.1.7 2/6/03 www.xicor.com table 3. instruction set note: 1/0 = data is one or zero instruction instruction set operation i3 i2 i1 i0 rb ra p 1 p 0 read wiper counter register 10010 0 0 0 read the contents of the wiper counter register write wiper counter register 10100 0 0 0 write new value to the wiper counter register read data register 10111/01/01/01/0 read the contents of the data register pointed to by p1-p0 and rb-ra write data register 11001/01/01/01/0 write new value to the data register pointed to by p1-p0 and rb-ra xfr data register to wiper counter register 11011/01/00 0 transfer the contents of the data register pointed to by rb-ra (bank 0 only) to the wiper counter register xfr wiper counter register to data register 11101/01/00 0 transfer the contents of the wiper counter register to the register pointed to by rb-ra (bank 0 only) increment/decrement wiper counter register 00100 0 0 0 enable increment/decrement of the wiper counter register device description wiper counter register (wcr) the x9279 contains contains a wiper counter register, for the dcp potentiometer. the wiper counter register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via the write wiper counter register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the xfr data register instruction (parallel load); it can be modi?d one step at a time by the increment/decrement instruction (see instruction section for more details). finally, it is loaded with the contents of its data register zero (dr0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x9279 is powered- down. although the register is automatically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. power- up guidelines are recommended to ensure proper loadings of the dr0 value into the wcr. the dr0 value of bank 0 is the default value. data registers (dr) the potentiometer has four 8-bit nonvolatile data registers (dr3-dr0). these can be read or written directly by the host. data can also be transferred between any of the four data registers and the associated wiper counter register. all operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiometer, the data registers can be used as regular memory locations for system parameters or user preference data. bit [7:0] are used to store one of the 256 wiper positions (0~255).
x9279 characteristics subject to change without notice. 10 of 24 rev 1.1.7 2/6/03 www.xicor.com table 4. wiper counter register, wcr (8-bit), wcr[7:0]: used to store the current wiper position (volatile, v). table 5. data register, dr (8-bit), bit [7:0]: used to store wiper positions or data (nonvolatile, nv). wcr7 wcr6 wcr5 wcr4 wcr3 wcr2 wcr1 wcr0 vvvvvvvv (msb) (lsb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nv nv nv nv nv nv nv nv msb lsb instructions four of the seven instructions are three bytes in length. these instructions are: read wiper counter register ?read the current wiper position of the potentiometer, write wiper counter register ?change current wiper position of the potentiometer, read data register ?read the contents of the selected data register; write data register ?write a new value to the selected data register. the basic sequence of the three byte instructions is illustrated in figure 4. these three-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram controlling the wiper position. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between the potentiometer and one of its four associated registers (bank 0). two instructions require a two-byte sequence to complete. these instructions transfer data between the host and the x9279; either between the host and one of the data registers or directly between the host and the wiper counter register. these instructions are: xfr data register to wiper counter register ? this transfers the contents of one speci?d data register to the wiper counter register. xfr wiper counter register to data register ? this transfers the contents of the wiper counter register to the speci?d data register. the ?al command is increment/decrement (figure 5 and 6). the increment/decrement command is different from the other commands. once the command is issued and the x9279 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a ?e tuning capability to the host. for each scl clock pulse (t high ) while sda is high, the selected wiper will move one resistor segment towards the r h terminal. similarly, for each scl clock pulse while sda is low, the selected wiper will move one resistor segment towards the r l terminal. see instruction format for more details. figure 3. two-byte instruction sequence these commands only valid when p1=p0=0 s t a r t 0 101 0 a2 a0 a c k i3 i2 i1 i0 rb ra p1 a c k scl sda s t o p 00 id3 id2 id1 id0 p0 device id internal instruction opcode address register address pot/bank address a1
x9279 characteristics subject to change without notice. 11 of 24 rev 1.1.7 2/6/03 www.xicor.com figure 4. three-byte instruction sequence figure 5. increment/decrement instruction squence figure 6. increment/decrement timing limits i3 i2 i1 i0 rb ra 0 id3 id2 id1 id0 device id external instruction opcode address register address pot/bank address 0 wcr[7:0] valid only when p1=p0=0; or data register d[7:0] for all values of p1 and p0 s t a r t 0 101 a2 a1 a0 a c k p1 p0 a c k scl sda s t o p a c k d7 d6 d5 d4 d3 d2 d1 d0 i3 i2 i1 i0 0 id3 id2 id1 id0 device id external instruction opcode address register address pot/bank address 0 s t a r t 0101 a2 a1 a0 a c k ra p1 p0 a c k scl sda s t o p i n c 1 i n c 2 i n c n d e c 1 d e c n rb scl sda v w /r w inc/dec cmd issued voltage out t wrid
x9279 characteristics subject to change without notice. 12 of 24 rev 1.1.7 2/6/03 www.xicor.com instruction format read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) write data register (dr) transfer wiper counter register (wcr) to data register (dr) s t a r t device type identifier device addresses s a c k instruction opcode dr/bank addresses s a c k wiper position (sent by x9279 on sda) m a c k s t o p 0 1 0 1 0a 2a 1a 0 10010000 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode dr/bank addresses s a c k wiper position (sent by master on sda) s a c k s t o p 01010a 2a 1a 0 1 0100000 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode dr/bank addresses s a c k wiper position (sent by x9279 on sda) m a c k s t o p 01010a 2a 1a 0 1011rbrap1 p0 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode dr/bank addresses s a c k wiper position (sent by master on sda) s a c k s t o p high-voltage write cycle 0 1 0 1 0a 2a 1a 0 1100rbrap1 p0 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode dr/bank addresses s a c k s t o p high-voltage write cycle 0 1 0 1 0a 2a 1a 0 1110rbra00
x9279 characteristics subject to change without notice. 13 of 24 rev 1.1.7 2/6/03 www.xicor.com transfer data register (dr) to wiper counter register (wcr) increment/decrement wiper counter register (wcr) notes: (1) ?ack??ack? stands for the acknowledge sent by the master/slave. (2) ?3 ~ a0? stands for the device addresses sent by the master. (3) ?? indicates that it is a ? for testing purpose but physically it is a ?on? care condition. (4) ?? stands for the increment operation, sda held high during active scl phase (high). (5) ?? stands for the decrement operation, sda held low during active scl phase (high). s t a r t device type identifier device addresses s a c k instruction opcode dr/bank addresses s a c k s t o p 01010a 2a 1a 0 1101rbra00 s t a r t device type identifier device addresses s a c k instruction opcode dr/bank addresses s a c k increment/decrement (sent by master on sda) s t o p 0 1 0 10a 2a 1a 0 00100000 i/di/d ....i/di/d
x9279 characteristics subject to change without notice. 14 of 24 rev 1.1.7 2/6/03 www.xicor.com absolute maximum ratings temperature under bias ....................?5 c to +135 c storage temperature .........................?5 c to +150 c voltage on scl, sda any address input with respect to v ss ..................................?v to +7v ? v = | (v h ? l ) |.................................................... 5.5v lead temperature (soldering, 10 seconds)........ 300 c i w (10 seconds).................................................. ?ma comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions temp min. max. commercial 0 c +70 c industrial ?0 c +85 c device supply voltage (v cc ) (4) limits x9279 5v 10% x9279-2.7 2.7v to 5.5v analog characteristics (over recommended industrial (2.7v) operating conditions unless otherwise stated.) notes: (1) absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position whe n used as a potentiometer. (2) relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. (3) mi = rtot / 255 or (r h ?r l ) / 255, single pot (4) during power up v cc > v h , v l , and v w . (5) n = 0, 1, 2, ....,255; m =0, 1, 2, ...., 254. symbol parameter limits test conditions min. typ. max. units r total end to end resistance 100 k ? t version r total end to end resistance 50 k ? u version end to end resistance tolerance ?0 % power rating 50 mw 25 c, each pot i w wiper current ? ma r w wiper resistance 300 ? i w = 3ma @ v cc = 3v r w wiper resistance 150 ? i w = 3ma @ v cc = 5v v term voltage on any r h or r l pin v ss v cc vv ss = 0v noise -120 dbv / hz ref: 1v resolution 0.4 % absolute linearity (1) ? mi (3) r w(n)(actual) ?r w(n)(expected) (5) relative linearity (2) ?.2 mi (3) r w(n + 1) ?[r w(n) + mi ] (5) temperature coefficient of r total 300 ppm/ c ratiometric temp. coefficient 20 ppm/? c h /c l /c w potentiometer capacitances 10/10/25 pf see macro model
x9279 characteristics subject to change without notice. 15 of 24 rev 1.1.7 2/6/03 www.xicor.com d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) endurance and data retention capacitance power-up timing a.c. test conditions notes: (6) this parameter is not 100% tested (7) t pur and t puw are the delays required from the time the (last) power supply (v cc -) is stable until the speci? instruction can be issued. these parameters are periodically sampled and not 100% tested. symbol parameter limits test conditions min. typ. max. units i cc1 v cc supply current (active) 3maf scl = 400khz; v cc = +6v; sda = open; (for 2-wire, active, read and i cc2 v cc supply current (nonvolatile write) 5maf scl = 400khz; v cc = +6v; sda = open; (for 2-wire, active, nonvolatile write state only) i sb v cc current (standby) 5 av cc = +6v; v in = v ss or v cc ; sda = v cc ; (for 2-wire, standby state only) i li input leakage current 10 av in = v ss to v cc i lo output leakage current 10 av out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 1 v v il input low voltage ? v cc x 0.3 v v ol output low voltage 0.4 v i ol = 3ma v oh output high voltage parameter min. units minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test max. units test conditions c in/out (6) input / output capacitance (sda) 8 pf v out = 0v c in (6) input capacitance ( scl, wp , a2, a1 and a0 ) 6 pf v in = 0v symbol parameter min. max. units t r v cc (6) v cc power-up rate 0.2 50 v/ms t pur (7) power-up to initiation of read operation 1 ms t puw (7) power-up to initiation of write operation 50 ms i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5
x9279 characteristics subject to change without notice. 16 of 24 rev 1.1.7 2/6/03 www.xicor.com equivalent a.c. load circuit ac timing high-voltage write cycle timing symbol parameter min. max. units f scl clock frequency 400 khz t cyc clock cycle time 2500 ns t high clock high time 600 ns t low clock low time 1300 ns t su:sta start setup time 600 ns t hd:sta start hold time 600 ns t su:sto stop setup time 600 ns t su:dat sda data input setup time 100 ns t hd:dat sda data input hold time 30 ns t r scl and sda rise time 300 ns t f scl and sda fall time 300 ns t aa scl low to sda data output valid time 0.9 s t dh sda data output hold time 0 ns t i noise suppression time constant at scl and sda inputs 50 ns t buf bus free time (prior to any transmission) 1200 ns t su:wpa a0, a1 setup time 0 ns t hd:wpa a0, a1 hold time 0 ns symbol parameter typ. max. units t wr high-voltage write cycle time (store instructions) 5 10 ms 5v 1533 ? 100pf sda pin r h 10pf c l c l r w r total c w 25pf 10pf r l spice macromodel 3v 867 ? 100pf sda pin
x9279 characteristics subject to change without notice. 17 of 24 rev 1.1.7 2/6/03 www.xicor.com xdcp timing symbol table . symbol parameter min. max. units t wrpo wiper response time after the third (last) power supply is stable 5 10 s t wrl wiper response time after instruction issued (all load instructions) 5 10 s waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
x9279 characteristics subject to change without notice. 18 of 24 rev 1.1.7 2/6/03 www.xicor.com timing diagrams start and stop timing input timing output timing t su:sta t hd:sta t su:sto scl sda t r (start) (stop) t f t r t f scl sda t high t low t cyc t hd:dat t su:dat t buf scl sda t dh t aa
x9279 characteristics subject to change without notice. 19 of 24 rev 1.1.7 2/6/03 www.xicor.com xdcp timing (for all load instructions) write protect and device address pins timing scl sda vwx (stop) lsb t wrl sda scl ... ... ... wp a0, a1 t su:wpa t hd:wpa (start) (stop) (any instruction)
x9279 characteristics subject to change without notice. 20 of 24 rev 1.1.7 2/6/03 www.xicor.com applications information basic configurations of electronic potentiometers application circuits v r rw +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current noninverting amplifier voltage regulator offset voltage adjustment comparator with hysterisis + v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) rl l = {r 1 /(r 1 +r 2 )} v o (min) 100k ? 10k ? 10k ? 10k ? -12v +12v tl072 + v s v o r 2 r 1 } }
x9279 characteristics subject to change without notice. 21 of 24 rev 1.1.7 2/6/03 www.xicor.com application circuits (continued) attenuator filter inverting amplifier equivalent l-r circuit + v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 rc) + v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + v s function generator r 2 r 4 r 1 = r 2 = r 3 = r 4 = 10k ? + v s r 2 r 1 r c } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + r 2 + r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c v o
x9279 characteristics subject to change without notice. 22 of 24 rev 1.1.7 2/6/03 www.xicor.com packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tssop, package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .01 18 (.30) 0 ?8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detaila (20x)
x9279 characteristics subject to change without notice. 23 of 24 rev 1.1.7 2/6/03 www.xicor.com ball matrix: 4321 a a0 vcc r l r h b a2 nc nc r w c scl nc nc a3 d sda vss wp a1 package dimensions symbol millimeters min nominal max package width a 2.593 2.623 2.653 package length b 2.771 2.801 2.831 package height c 0.644 0.677 0.710 body thickness d 0.444 0.457 0.470 ball height e 0.200 0.220 0.240 ball diameter f 0.300 0.320 0.340 ball pitch ?width j 0.5 ball pitch ?length k 0.5 ball to edge spacing ?width l 0.537 0.562 0.587 ball to edge spacing ?length m 0.626 0.651 0.676 16-bump chip scale package (csp b16) package outline drawing f m j l k b a d e e c top view (marking side) bottom view (bumped side) side view side view a4 a3 a2 a1 b4 b3 b2 b1 c4 c3 c2 c1 d4 d3 d2 d1 9279trb yww i lot #
x9279 characteristics subject to change without notice. 24 of 24 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2003 patents pending rev 1.1.7 2/6/03 www.xicor.com ordering information device v cc limits blank = 5v 10% ?.7 = 2.7 to 5.5v temperature range blank = commercial = 0 c to +70 c i = industrial = ?0 c to +85 c package v14 = 14-lead tssop b = 16-lead csp potentiometer organization pot t = 100k ? u = 50k ? x9279 p t v y

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