july 1999 4-1 stk10c68 8k x 8 nvsram quantumtrap ? cmos nonvolatile static ram features 20ns, 25ns, 35ns and 45ns access times store to eeprom initiated by hardware recall to sram initiated by hardware or power restore automatic store timing 10ma typical i cc at 200ns cycle time unlimited read, write and recall cycles 1,000,000 store cycles to eeprom 100-year data retention over full industrial temperature range commercial and industrial temperatures 28-pin dip and soic packages description the simtek stk10c68 is a fast static ram with a nonvol- atile electrically erasable prom ( eeprom ) element incorporated in each static memory cell. the sram can be read and written an unlimited number of times, while independent nonvolatile data resides in eeprom . data may easily be transferred from the sram to the eeprom (the store operation ), or from the eeprom to the sram (the recall operation), using the ne pin. transfers from the eeprom to the sram (the recall operation) also take place automatically on restoration of power. the stk10c68 combines the high performance and ease of use of a fast sram with nonvolatile data integrity. the stk10c68 features industry-standard pinout for non- volatile ram s. mil-std-883 and standard military draw- ing ( smd #5962-93056) devices are also available. block diagram column i/o column dec static ram array 128 x 512 row decoder input buffers eeprom array 128 x 512 store/ recall control store recall a 11 a 7 a 8 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 g e w a 6 a 5 a 3 a 2 a 0 a 1 a 10 a 12 a 9 ne a 4 pin names a 0 - a 12 address inputs w write enable dq 0 - dq 7 data in/out e chip enable g output enable ne nonvolatile enable v cc power (+ 5v) v ss ground pin configurations ne a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 v ss v cc nc a 8 a 9 a 11 g w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a 10 e dq 7 dq 6 dq 5 dq 4 dq 3 28 - 300 pdip 28 - 300 cdip 28 - 350 soic
stk10c68 july 1999 4-2 absolute maximum ratings a voltage on input relative to v ss . . . . . . . . . . ?0.6v to (v cc + 0.5v) voltage on dq 0-7 . . . . . . . . . . . . . . . . . . . . . . ?0.5v to (v cc + 0.5v) temperature under bias . . . . . . . . . . . . . . . . . . . . . ?55 c to 125 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . ?65 c to 150 c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1w dc output current (1 output at a time, 1s duration) . . . . . . . . 15ma dc characteristics (v cc = 5.0v 10%) b note b: the stk10c68-20 requires v cc = 5.0v 5% supply to operate at specified speed. note c: i cc 1 and i cc 3 are dependent on output loading and cycle rate. the specified values are obtained with outputs unloaded. note d: i cc 2 is the average current required for the duration of the store cycle (t store ). note e: e v ih will not produce standby current levels until any nonvolatile cycle in progress has timed out. ac test conditions capacitance f (t a = 25 c, f = 1.0mhz) note f: these parameters are guaranteed but not tested. symbol parameter commercial industrial units notes min max min max i cc 1 c average v cc current 100 90 75 65 n/a 90 75 65 ma ma ma ma t avav = 20ns t avav = 25ns t avav = 35ns t avav = 45ns i cc 2 d average v cc current during store 33ma all inputs don ? t care, v cc = max i cc 3 c average v cc current at t avav = 200ns 5v, 25 c, typical 10 10 ma w (v cc ? 0.2v) all others cycling, cmos levels i sb 1 e average v cc current (standby, cycling ttl input levels) 32 27 23 20 n/a 28 24 21 ma ma ma ma t avav = 20ns, e v ih t avav = 25ns, e v ih t avav = 35ns, e v ih t avav = 45ns, e v ih i sb 2 e v cc standby current (standby, stable cmos input levels) 750 750 a e (v cc ? 0.2v) all others v in 0.2v or (v cc ? 0.2v) i ilk input leakage current 1 1 a v cc = max v in = v ss to v cc i olk off-state output leakage current 5 5 a v cc = max v in = v ss to v cc , e or g v ih v ih input logic ? 1 ? voltage 2.2 v cc + .5 2.2 v cc + .5 v all inputs v il input logic ? 0 ? voltage v ss ? .5 0.8 v ss ? .5 0.8 v all inputs v oh output logic ? 1 ? voltage 2.4 2.4 v i out = ? 4ma v ol output logic ? 0 ? voltage 0.4 0.4 v i out = 8ma t a operating temperature 0 70 ? 40 85 c input pulse levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 3v input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns input and output timing reference levels . . . . . . . . . . . . . . . 1.5v output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see figure 1 symbol parameter max units conditions c in input capacitance 8pf ? v = 0 to 3v c out output capacitance 7pf ? v = 0 to 3v figure 1: ac output loading 480 ohms 30 pf 255 ohms 5.0v including output scope and fixture note a: stresses greater than those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at condi- tions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect reliability.
stk10c68 july 1999 4-3 sram read cycles #1 & #2 (v cc = 5.0v 10%) b note g: w must be high during sram read cycles and low during sram write cycles. ne must be high during entire cycle. note h: i/o state assumes e , g < v il , w > v ih , and ne v ih ; device is continuously selected. note i: measured + 200mv from steady state output voltage. sram read cycle #1: address controlled g, h sram read cycle #2: e controlled g no. symbols parameter stk10c68-20 stk10c68-25 stk10c68-35 stk10c68-45 units #1, #2 alt. min max min max min max min max 1t elqv t acs chip enable access time 20 25 35 45 ns 2t avav g t rc read cycle time 20 25 35 45 ns 3t avqv h t aa address access time 22 25 35 45 ns 4t glqv t oe output enable to data valid 8 10 15 20 ns 5t axqx h t oh output hold after address change 5 5 5 5 ns 6t elqx t lz chip enable to output active 5 5 5 5 ns 7t ehqz i t hz chip disable to output inactive 7 10 13 15 ns 8t glqx t olz output enable to output active 0 0 0 0 ns 9t ghqz i t ohz output disable to output inactive 7 10 13 15 ns 10 t elicch f t pa chip enable to power active 0 0 0 0 ns 11 t ehiccl e, f t ps chip disable to power standby 25 25 35 45 ns data valid 5 t axqx 3 t avqv dq (data out) address 2 t avav 6 t elqx standby data valid 8 t glqx 4 t glqv dq (data out) e address 2 t avav g i cc active 1 t elqv 10 t elicch 1 1 t ehiccl 7 t ehqz 9 t ghqz
stk10c68 july 1999 4-4 sram write cycles #1 & #2 (v cc = 5.0v 10%) b note j: if w is low when e goes low, the outputs remain in the high-impedance state. note k: e or w must be v ih during address transitions. ne v ih . sram write cycle #1 : w controlled k sram write cycle #2 : e controlled k no. symbols parameter stk10c68-20 stk10c68-25 stk10c68-35 stk10c68-45 units #1 #2 alt. min max min max min max min max 12 t avav t avav t wc write cycle time 20 25 35 45 ns 13 t wlwh t wleh t wp write pulse width 15 20 25 30 ns 14 t elwh t eleh t cw chip enable to end of write 15 20 25 30 ns 15 t dvwh t dveh t dw data set-up to end of write 8 10 12 15 ns 16 t whdx t ehdx t dh data hold after end of write 0 0 0 0 ns 17 t avwh t aveh t aw address set-up to end of write 15 20 25 30 ns 18 t avwl t avel t as address set-up to start of write 0 0 0 0 ns 19 t whax t ehax t wr address hold after end of write 0 0 0 0 ns 20 t wlqz i, j t wz write enable to output disable 7 10 13 15 ns 21 t whqx t ow output active after end of write 5 5 5 5 ns previous data data out e address 12 t avav w 16 t whdx data in 19 t whax 13 t wlwh 18 t avwl 17 t avwh data valid 20 t wlqz 15 t dvwh high impedance 21 t whqx 14 t elwh data out e address 12 t avav w data in 13 t wleh 17 t aveh data valid high impedance 14 t eleh 18 t avel 19 t ehax 15 t dveh 16 t ehdx
stk10c68 july 1999 4-5 mode selection note l: an automatic recall takes place at power up, starting when v cc exceeds 4.25v and taking t restore . store cycles #1 & #2 (v cc = 5.0v 10%) b note m: measured with w and ne both returned high, and g returned low. store cycles are inhibited below 4.0v. note n: once t wc has been satisfied by ne , g , w and e , the store cycle is completed automatically. any of ne , g , w or e may be used to terminate the store initiation cycle. note o: if e is low for any period of time in which w is high while g and ne are low, then a recall cycle may be initiated. store cycle #1: w controlled o store cycle #2: e controlled o e w g ne mode power h x x x not selected standby l h l h read sram active l l x h write sram active l h l l nonvolatile recall l active l l h l nonvolatile store i cc 2 l l l h l h l x no operation active no. symbols parameter min max units #1 #2 alt. 22 t wlqx m t elqx t store store cycle time 10 ms 23 t wlnh n t elnh t wc store initiation cycle time 20 ns 24 t ghnl output disable set-up to ne fall 5 ns 25 t ghel output disable set-up to e fall 5 ns 26 t nlwl t nlel ne set-up 5 ns 27 t elwl chip enable set-up 5 ns 28 t wlel write enable set-up 5 ns high impedance ne g w e dq (data out) 24 t ghnl 26 t nlwl 23 t wlnh 27 t elwl 22 t wlqx ne g w e dq (data out) high impedance 26 t nlel 25 t ghel 28 t wlel 23 t elnh 22 t elqx
stk10c68 july 1999 4-6 recall cycles #1, #2 & #3 (v cc = 5.0v 10%) b note p: measured with w and ne both high, and g and e low. note q: once t nlnh has been satisfied by ne , g , w and e , the recall cycle is completed automatically. any of ne , g or e may be used to terminate the recall initiation cycle. note r: if w is low at any point in which both e and ne are low and g is high, then a store cycle will be initiated instead of a recall . recall cycle #1: ne controlled o recall cycle #2: e controlled o recall cycle #3: g controlled o , r no. symbols parameter min max units #1 #2 #3 29 t nlqx p t elqxr t glqxr recall cycle time 20 s 30 t nlnh q t elnhr t glnh recall initiation cycle time 20 ns 31 t nlel t nlgl ne set-up 5 ns 32 t glnl t glel output enable set-up 5 ns 33 t whnl t whel t whgl write enable set-up 5 ns 34 t elnl t glel t elgl chip enable set-up 5 ns 35 t nlqz ne fall to outputs inactive 20 ns 36 t restore power-up recall duration 550 s ne g w e dq (data out) high impedance 30 t nlnh 32 t glnl 33 t whnl 34 t elnl 35 t nlqz 29 t nlqx ne g w e dq (data out) high impedance 31 t nlel 32 t glel 33 t whel 30 t elnhr 29 t elqxr ne g w e dq (data out) high impedance 31 t nlgl 29 t glqxr 30 t glnh 33 t whgl 34 t elgl
stk10c68 july 1999 4-7 the stk10c68 has two modes of operation: sram mode and nonvolatile mode, determined by the state of the ne pin. when in sram mode, the mem- ory operates as a standard fast static ram . while in nonvolatile mode, data is transferred in parallel from sram to eeprom or from eeprom to sram . noise considerations note that the stk10c68 is a high-speed memory and so must have a high-frequency bypass capaci- tor of approximately 0.1 f connected between v cc and v ss , using leads and traces that are as short as possible. as with all high-speed cmos ics, normal careful routing of power, ground and signals will help prevent noise problems. sram read the stk10c68 performs a read cycle whenever e and g are low and ne and w are high. the address specified on pins a 0-12 determines which of the 8,192 data bytes will be accessed. when the read is initi- ated by an address transition, the outputs will be valid after a delay of t avqv ( read cycle #1). if the read is initiated by e or g , the outputs will be valid at t elqv or at t glqv , whichever is later ( read cycle #2). the data outputs will repeatedly respond to address changes within the t avqv access time without the need for transitions on any control input pins, and will remain valid until another address change or until e or g is brought high or w or ne is brought low. sram write a write cycle is performed whenever e and w are low and ne is high. the address inputs must be sta- ble prior to entering the write cycle and must remain stable until either e or w goes high at the end of the cycle. the data on pins dq 0-7 will be writ- ten into the memory if it is valid t dvwh before the end of a w controlled write or t dveh before the end of an e controlled write . it is recommended that g be kept high during the entire write cycle to avoid data bus contention on the common i/o lines. if g is left low, internal circuitry will turn off the output buffers t wlqz after w goes low. nonvolatile store a store cycle is performed when ne , e and w and low and g is high. while any sequence that achieves this state will initiate a store , only w initi- ation ( store cycle #1) and e initiation ( store cycle #2) are practical without risking an unintentional sram write that would disturb sram data. during a store cycle, previous nonvolatile data is erased and the sram contents are then programmed into nonvolatile elements. once a store cycle is initi- ated, further input and output are disabled and the dq 0-7 pins are tri-stated until the cycle is complete. if e and g are low and w and ne are high at the end of the cycle, a read will be performed and the out- puts will go active, signaling the end of the store . nonvolatile recall a recall cycle is performed when e , g and ne are low and w is high. like the store cycle, recall is initiated when the last of the four clock signals goes to the recall state. once initiated, the recall cycle will take t nlqx to complete, during which all inputs are ignored. when the recall completes, any read or write state on the input pins will take effect. internally, recall is a two-step procedure. first, the sram data is cleared, and second, the nonvolatile information is transferred into the sram cells. the recall operation in no way alters the data in the nonvolatile cells. the nonvolatile data can be recalled an unlimited number of times. as with the store cycle, a transition must occur on any one control pin to cause a recall , preventing inadvertent multi-triggering. on power up, once v cc exceeds the v cc sense voltage of 4.25v, a recall cycle is automatically initiated. due to this automatic recall , sram operation cannot commence until t restore after v cc exceeds approximately 4.25v. power-up recall during power up, or after any low-power condition (v cc < 3.0v), an internal recall request will be latched. when v cc once again exceeds the sense voltage of 4.25v, a recall cycle will automatically be initiated and will take t restore to complete. device operation
stk10c68 july 1999 4-8 if the stk10c68 is in a write state at the end of power-up recall , the sram data will be corrupted. to help avoid this situation, a 10k ohm resistor should be connected either between w and system v cc or between e and system v cc . hardware protect the stk10c68 offers two levels of protection to suppress inadvertent store cycles. if the control signals (e , g , w and ne ) remain in the store con- dition at the end of a store cycle, a second store cycle will not be started. the store (or recall ) will be initiated only after a transition on any one of these signals to the required state. in addition to multi-trigger protection, store s are inhibited when v cc is below 4.0v, protecting against inadvertent store s. low average active power the stk10c68 draws significantly less current when it is cycled at times longer than 55ns. figure 2 shows the relationship between i cc and read cycle time. worst-case current consumption is shown for both cmos and ttl input levels (commercial tem- perature range, v cc = 5.5v, 100% duty cycle on chip enable). figure 3 shows the same relationship for write cycles. if the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. the overall average cur- rent drawn by the stk10c68 depends on the fol- lowing items: 1) cmos vs. ttl input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of read s to write s; 5) the operating temperature; 6) the v cc level; and 7) i/ o loading. figure 2: i cc (max) reads 0 20 40 60 80 100 50 100 150 200 cycle time (ns) ttl cmos average active current (ma) figure 3: i cc (max) writes 0 20 40 60 80 100 50 100 150 200 cycle time (ns) ttl cmos average active current (ma)
stk10c68 july 1999 4-9 ordering information temperature range blank = commercial (0 to 70 c) i = industrial ( ? 40 to 85 c ) access time 20 = 20ns (commercial only) 25 = 25ns 35 = 35ns 45 = 45ns package p = plastic 28-pin 300 mil dip c = ceramic 28-pin 300 mil dip s = plastic 28-pin 350 mil soic - p 25 i stk10c68
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