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integrated silicon solution, inc. ? 1-800-379-4774 1 rev. h 1/6/2010 i 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams features ? 1m x 36 or 2m x 18. on-chip delay-locked loop (dll) for wide data valid window. separate read and write ports with concurrent read and write operations. synchronous pipeline read with early write oper- ation. double data rate (ddr) interface for read and write input ports. fixed 2-bit burst for read and write operations. clock stop support. two input clocks (k and k ) for address and con- trol registering at rising edges only. tw o in p ut clocks ( c an d c ) for data output con- trol. tw o echo clocks (cq and cq) that are d e livered simultaneously with data. +1.8v core power supply and 1.5, 1.8v v ddq , used with 0.75, 0.9v v ref . hstl input and output levels. registered addresses, write and read controls, byte writes, data in, and data outputs. full data coherency. boundary scan using limited set of jtag 1149.1 functions. byte write capability. fine ball grid array (fbga) package - 15mm x 17mm body size - 1mm pitch - 165-ball (11 x 15) array programmable impedance output drivers via 5x user-supplied precision resistor. description the 36mb is61qdb21mx36 and is61qdb22mx18 are s yn chro nous, hi gh-perfo rmance cmos static random ac cess memory (sram) devices. these these srams have separate i/os, eliminating the need for high-speed bus turnaround. the rising edge of k clock initiates the read/write operation, and all internal operations are self-timed. refer to the timing reference diagram for truth table o n page 8 for a de scription of the basic op era- tions of the se sr a ms. the input address bus operates at double data r ate. the following are registered internally on the rising edge of the k clock: read address read enable write enable byte writes data-in for early writes the following are registered on the rising edge of the k clock: write address byte writes data-in for second burst addresses byte writes can change with the corresponding data- in to enable or disable writes on a per-byte basis. an internal write buffer enables the data-ins to be regis- tered half a cycle earlier than the write address. the first data-in burst is clocked at the same time as the write command signal, and the second burst is timed to the following rising edge of the k clock. during the burst read operation, the data-outs from the first burst are updated from output registers off the second rising edge of the c clock (1.5 cycles later). the data-outs from the second burst are updated with the third rising edge of the c clock. the k and k clocks are used to time the data-outs when- ever the c and c clocks are tied high. the device is operated with a single +1.8v power supply and is compatible with hstl i/o interfaces. .
2 integrated silicon solution, inc. ? 1-800-379-4774 rev. h 1/6/2010 i ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams x36 fbga pinout (top view) 1234567891011 acq v ss /sa nc/sa* w bw 2 k bw 1 r sa v ss /sa cq b q27 q18 d18 sa bw 3 kbw 0 sa d17 q17 q8 c d27 q28 d19 v ss sa sa sa v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 hdoff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss sa sa sa v ss q10 d9 d1 p q35 d35 q26 sa sa c sa sa q9 d0 q0 rtdotcksasasa c sa sa sa tms tdi note: the following pins are reserved for higher densities: a3 for 64mb, 10a for 144mb, and 2a for 288mb. x18 fbga pinout (top view) 1234567891011 acq v ss /sa* sa w bw 1 k nc r sa v ss /sa* cq bnc q9 d9 sa nc k bw 0 sa nc nc q8 cnc nc d10 v ss sa sa sa v ss nc q7 d8 dnc d11 q10 v ss v ss v ss v ss v ss nc nc d7 enc nc q11v ddq v ss v ss v ss v ddq nc d6 q6 fnc q12 d12v ddq v dd v ss v dd v ddq nc nc q5 gnc d13 q13v ddq v dd v ss v dd v ddq nc nc d5 hdoff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq jnc nc d14v ddq v dd v ss v dd v ddq nc q4 d4 knc nc q14v ddq v dd v ss v dd v ddq nc d3 q3 lnc q15 d15v ddq v ss v ss v ss v ddq nc nc q2 mnc nc d16 v ss v ss v ss v ss v ss nc q1 d2 nnc d17 q16 v ss sa sa sa v ss nc nc d1 pnc nc q17 sa sa c sa sa nc d0 q0 rtdotcksasasa c sa sa sa tms tdi note: the following pins are reserved for higher densities: 10a for 72mb and 2a for 144mb.
integrated silicon solution, inc. ? 1-800-379-4774 3 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams pin description symbol pin number description k, k 6b, 6a input clock. c, c 6p, 6r input clock for output data control. cq, cq 11a, 1a output echo clock. doff 1h dll disable when low. sa 9a, 4b, 8b, 5c, 6c, 7c, 5n, 6n, 7n, 4p, 5p, 7p, 8p, 3r, 4r, 5r, 7r, 8r, 9r 1m x 36 address inputs. sa 3a, 9a, 4b, 8b, 5c, 6c, 7c, 5n, 6n, 7n, 4p, 5p, 7p, 8p, 3r, 4r, 5r, 7r, 8r, 9r 2m x 18 address inputs. d0 ? d8 d9 ? d17 d18 ? d26 d27 ? d35 10p, 11n, 11m, 10k, 11j, 11g, 10e, 11d, 11c 10n, 9m, 9l, 9j, 10g, 9f, 10d, 9c, 9b 3b, 3c, 2d, 3f, 2g, 3j, 3l, 3m, 2n 1c, 1d, 2e, 1g, 1j, 2k, 1m, 1n, 2p 1m x 36 data inputs. q0 ? q8 q9 ? q17 q18 ? q26 q27 ? q35 11p, 10m, 11l, 11k, 10j, 11f, 11e, 10c, 11b 9p, 9n, 10l, 9k, 9g, 10f, 9e, 9d, 10b 2b, 3d, 3e, 2f, 3g, 3k, 2l, 3n, 3p 1b, 2c, 1e, 1f, 2j, 1k, 1l, 2m, 1p 1m x 36 data outputs. d0 ? d8 d9 ? d17 10p, 11n, 11m, 10k, 11j, 11g, 10e, 11d, 11c 3b, 3c, 2d, 3f, 2g, 3j, 3l, 3m, 2n 2m x 18 data inputs. q0 ? q8 q9 ? q17 11p, 10m, 11l, 11k, 10j, 11f, 11e, 10c, 11b 2b, 3d, 3e, 2f, 3g, 3k, 2l, 3n, 3p 2m x 18 data outputs. w 4a write control, active low. r 8a read control, active low. bw 0, bw 1, bw 2, bw 3 7b, 7a, 5a,5b 1m x 36 byte write control, active low. bw 0, bw 1 7b, 5a 2m x 18 byte write control, active low. v ref 2h, 10h input reference level. v dd 5f, 7f, 5g, 7g, 5h, 7h, 5j, 7j, 5k, 7k power supply. v ddq 4e,8e,4f,8f,4g,8g,3h,4h,8h,9h,4j,8j,4k,8k,4l,8l output power supply. v ss 2a, 10a, 4c, 8c, 4d, 5d, 6d, 7d, 8d, 5e, 6e, 7e, 6f, 6g, 6h, 6j, 6k, 5l, 6l, 7l, 4m, 5m, 6m, 7m, 8m 4n, 8n power supply. zq 11h output driver impedance control. tms, tdi, tck 10r, 11r, 2r ieee 1149.1 test inputs (1.8v lvttl lev- els). td nc nc 3a 7a,1b,5b,9b,10b,1c,2c,9c,1d,9d,10d,1e,2e,9e,1f,9f,10f,1g, 9g,10g,1j,2j,9j,1k,2k,9k,1l,9l,10l,1m,2m,9m,1n,9n,10n,1p, 2p,9p 1mx36 2mx18 o 1r ieee 1149.1 test output (1.8v lvttl level).
4 integrated silicon solution, inc. ? 1-800-379-4774 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams sram features read operations the sram operates continuously in a burst-of-two mode. read cycles are started by registering r in active low state at the rising edge of the k clock. a second set of clocks, c and c , are used to control the timing to the outputs. a set of free-running echo clocks, cq and cq , are produced internally with timings identical to the data-outs. the echo clocks can be used as data capture clocks by the receiver device. when the c and c clocks are connected high, the k and k clocks assume the function of those clocks. in this case, the data corresponding to the first address is clocked 1.5 cycles later by the rising edge of the k clock. the data corresponding to the second burst is clocked 2 cycles later by the following rising edge of the k clock. a nop operation (r is high) does not terminate the previous read. write operations write operations can also be initiated at every rising edge of the k clock whenever w is low. the write address is provided 0.5 cycles later, registered by the rising edge of k . again, the write always occurs in bursts of two. the write data is provided in an ? early write ? mode; that is, the data-in corresponding to the first address of the burst, is presented 0.5 cycles earlier or at the rising edge of the preceding k clock. the data-in corresponding to the second write burst address follows next, registered by the rising edge of k . the data-in provided for writing is initially kept in write buffers. the information on these buffers is written into the array on the following write cycle. a read cycle to the last write address produces data from the write buffers. similarly, a read address followed by the same write address produces the latest write data. the sram maintains data coherency. block diagram 1m x 36 (2m x 18) memory array write/read decode sense amps write driver select output control data reg add reg control logic clock gen output reg output select output driver 72 (or 36) 72 (or 36) 36 (or 18) q (data-out) cq, cq (echo clock out) d (data-in) 36 (or 18) address r w bw x k k c c 4 (or 2) 19 (or 20) 19 (or 20) 36 (or 18) 36 (or 18)
integrated silicon solution, inc. ? 1-800-379-4774 5 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams during a write, the byte writes independently control which byte of any of the two burst addresses is written (see x18/x36 write truth tables on page 9 and timing reference diagram for truth table on page 8). whenever a write is disabled (w is high at the rising edge of k), data is not written into the memory. rq programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to enable the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. for example, an rq of 250 ? results in a driver impedance of 50 ? . the allowable range of rq to guarantee impedance matching is between 175 ? and 350 ? , with the tolerance described in programmable impedance output driver dc electrical characteristics on page 13 . the rq resistor should be placed less than two inches away from the zq ball on the sra m module. the capacitance of the loaded zq trace must be less than 3 pf. the zq pin can also be directly connected to v ddq to obtain a minimum impedance setting. zq must never be connected to v ss . programmable impedance and power-up requirements periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. at power-up, the driver impedance is in the middle of allowable impedances values. the final impedance value is achieved within 1024 clock cycles. clock consideration this device uses an internal dll for maximum output data valid window. it can be placed in a stopped-clock mode to minimize power and requires only 1024 cycles to restart. no clocks can be issued until v dd reaches its allowable operating range. single clock mode this device can be also operated in single-clock mode. in this case, c and c are both connected high at power-up and must never change. under this condition, k and k will control the output timings. either clock pair must have both polarities switching and must never connect to v ref , as they are not differ- ential clocks depth expansion separate input and output ports enable easy depth expansion, as each port can be selected and deselected independently. read and write operations can occur simultaneously without affecting each other. also, all pending read and write transactions are always completed prior to deselecting the corresponding port. in the following application example, the second pair of c and c clocks is delayed such that the return data meets the data setup and hold times at the bus master.
6 integrated silicon solution, inc. ? 1-800-379-4774 rev. h 1/6/2010 36 mb (1m x 36 & 2m x 18) qu ad (bur st of 2) syn chr onous srams appli cat ion e xa mple 2m x 18 sa r w bw 0 bw 1 c c k k d 0?17 q 0?17 zq sram #4 r=250 ? vt data -in 0?71 data -out 0?71 ad dress 0?79 r w bw 0?7 mem ory controller return clk sour ce clk return clk sour ce clk sa r w bw 0 bw 1 c c k k d 0?17 q 0?17 zq sram #1 r=250 ? vt vt r vt vt r=50 ? vt=v ref r power-up and power-down sequences the following sequence is used for power-up: 1. the power supply inputs must be applied in the following order while keeping doff in low logic state: 1) vdd 2) vddq 3) vref 2. start applying stable clock inputs (k, k, c, and c). 3. after clock signals have stabilized, change doff to high logic state. 4. once the doff is switched to high logic state, wait an additional 1024 clock cycles to lock the dll. notes: 1. the power-down sequence must be done in reverse of the power-up sequence. 2. vddq can be allowed to exceed vdd by no more than 0.6v. 3. vref can be applied concurrently with vddq.
integrated silicon solution, inc. ? 1-800-379-4774 7 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams the timing reference diagram for truth table on page 8 is helpful i n understan ding the clock and write truth tables, as it shows the cycle relationship between clocks, address, data in, data out, and controls. all read and write commands are issued at the beginning of cycle ? t? . state diagram power up write nop load new write address ddr write read nop load new read address ddr read read write read write read write read write always (fixed) always (fixed) notes: 1. internal burst counter is fixed as two-bit linear; that is, when first address is a0+0, next internal burst address is a0+1 . 2. read refers to read active status with r = low. read refers to read inactive status with r = high. 5. state machine control timing sequence is controlled by k. 4. the read and write state machines can be active simultaneously. 3. write refers to write active status with w = low. write refers to write inactive status with w = high.
8 integrated silicon solution, inc. ? 1-800-379-4774 rev . h 1/6/2010 36 mb (1m x 36 & 2m x 18) qu ad (bur st of 2) syn chr onous srams ti mi ng re fere nc e di agram for t ruth table clo ck t ruth table (use the following table with th e timing reference diagram for tr uth table .) m ode tuo-atad ni-atad slortnoc kcolc k r w d b d b+1 q a q a+1 st op clock stop x x p re vi ou s st at e p re vi ous st at e pre vious sta te pre vious st ate no opera ti on (nop) l h h h x x h igh-z h igh-z re ad a l h l x x x d ou t at c (t + 1.5) d out at c (t + 2) write b l h x l d in at k (t) d in at k (t + 0.5) x x notes : 1. t he int ernal burst c oun ter is always fix ed as two-bi t. 2. x = do n?t care; h = l ogi c ?1?; l = l ogi c ?0?. 3. a r ead operati on is star ted w hen c ont rol signa l r is active low 4. a write oper ation is sta rt ed when con tr ol signal w is act ive lo w. be fo re enter ing in to t he stop clock, al l pending r ead and wr ite comm ands must be co mple ted. 5. f or tim ing defin it ion s, ref er to t he ac cha racter ist ics on page 15-16 . signals must have ac s pecif ications at timings indicated in pa rent hes is wi th r espect to switchi ng clo cks k , k , c, a nd c . t t +1 t+2 t+3 read a wri te b r ead c w ri te d a b c d q a q a+1 q c q c+1 k cl ock k clo ck w r bw 0,1,2,3 ad dress data -in data -out c clo ck c clo ck cq clock cq clo ck cycle d b d b+1 d d d d+1
integrated silicon solution, inc. ? 1-800-379-4774 9 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams x36 write truth table use the following table with the timing reference diagram for truth table on page 8. operation k(t) k (t + 0.5) bw 0 bw 1 bw 2 bw 3 d b d b+1 write byte 0 l h l h h h d0-8 (t) write byte 1 l h h l h h d9-17 (t) write byte 2 l h h h l h d18-26 (t) write byte 3 l h h h h l d27-35 (t) write all bytes l h l l l l d0-35 (t) abort write l h hhhh don ? t care write byte 0 l h l h h h d0-8 (t + 0.5) write byte 1 l h h l h h d9-17 (t + 0.5) write byte 2 l h h h l h d18-26 (t + 0.5) write byte 3 l h h h h l d27-35 (t + 0.5) write all bytes l h l l l l d0-35 (t + 0.5) abort write l hhhhh don ? t care notes ; 1. for all cases. w must be active low during the rising edge of k occurring at time t. 2. for timing definitions, refer to the ac characteristics on page 15- 16. signals must have ac specifications with respect to switching clocks k and k . x18 write truth table (use this table with the timing reference diagram for truth table on page 8.) operation k(t) k (t + 0.5) bw 0 bw 1 d b d b+1 write byte 0 on b l hlhd 0 ? 8 (t) write byte 1 on b l hhld 9 ? 17 (t) write all bytes on b l hlld 0 ? 17 (t) abort write on b l hhhd o n ? t care write byte 1 on b+1 l hl h d0 ? 8(t + 0.5) write byte 2 on b+1 l hh l d9 ? 17(t + 0.5) write all bytes on b+1 l hl l d0 ? 17(t + 0.5) abort write on b+1 l hh h don ? t care notes ; 1. refer to timing re f erence diagram f or truth table on page 8. cycle time starts at n and is referenced to the k clock. 2. for all cases, w must be active low during the rising edge of k occurring at t. 3. for timing definitions, refer to the ac characteristics on page 15- 16. signals must have ac specs with respect to switching clocks k and k .
10 integrated silicon solution, inc. ? 1-800-379-4774 rev. h 1/6/2010 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams absolute maximum ratings item symbol rating units power supply voltage vdd -0.5 to 2.6 v output power supply voltage vddq -0.5 to 2.6 v input voltage vin -0.5 to 2.6 v data out voltage vdout -0.5 to 2.6 v junction temperature tj 110 c storage temperature tstg -55 to +125 c note: stresses greater than those listed in this table can cause permanent damage to the device. this is a stress rating only and functional operation of the devic e at these or any other conditions above those indicated in the operational sections of this datasheet is not imp lied. exposure to absolute maximum rating co nditions for extended periods may affect reliability. operating temperature range range symbol rating unit commercial ta 0 to 70 c industrial ta -40 to +85 c
integrated silicon solution, inc. ? 1-800-379-4774 11 re v. h 1/6/2010 36 mb (1 m x 36 & 2m x 18) quad (b urst of 2) synchr onou s s ra ms recommended dc operating co nditions ( over the operat ing tempera ture ) para met er symbol minim um ty pi cal maximum u ni ts notes supply voltage v dd 1.8 - 5% 1.8 + 5% v 1 o ut put dr iver supply voltage v ddq 1.4 1.9 v 1 in pu t high voltage v ih v ref +0.1 v ddq + 0. 3 v 1, 2 1, 3 in pu t low voltage v il -0. 3 v ref - 0.1 v in pu t reference v olt age v ref 0.68 0.95 v 1, 5 clocks s igna l voltage v in - clk -0. 3 v ddq + 0. 3 v 1, 4 1. all vo ltages are refere nce d to v ss . all v dd , v ddq , and v ss pi ns must be connected. 2. v ih (max) ac = see 0vers ho ot an d u ndersh oot timings . 3. v il (min) ac = see 0v ersh oot an d unde rshoo t timings . 4. v in-clk specifies the maximum allowable dc ex cu rsions of each clock (k, k , c, and c ). 5. p eak-t o-pe ak ac com pone nt superi mpo sed on v ref may not exceed 5% of v ref. 0vershoot and undershoot timings pbga t her mal characteristics item symbol ra ti ng un its t he rmal re si stance junction to amb ient (ai rf low = 1m/ s) r ja 20 .4 c/ w thermal resistance junction to case r jc 4.0 c/w thermal re si stance ju nction to pi ns r jb 3.23 c/w v ddq 20% min cycle time v ddq +0.6v gnd-0.6v gnd 20% min cycle time overshoot timing undershoot timing v ih (max) ac v il (min) ac
12 integrated silicon solution, inc. ? 1-800-379-4774 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams capacitance (v dd = 1.8v -5%, +5%, f = 1mhz . over the operating temperature range.) parameter symbol test condition maximum units input capacitance c in v in = 0v 4 pf data-in capacitance (d0 ? d35) c din v din = 0v 4 pf data-out capacitance (q0 ? q35) c out v out = 0v 4 pf clocks capacitance (k, k , c, c d c el ec tri cal c h ara c t e ri st ics ( v dd = 1 . 8v -5%, +5 %. over the operating temperature range.) p arameter s ym bol m ini mum m a x im u m units n otes x 36 av erage power supply operati ng cur r ent (i o u t = 0, v in = v ih or v i l ) i d d 30 i d d 40 1 i d d 50 ? ? ma 1, 3 x 18 av erage power supply operati ng cur r ent (i ou t = 0, v in = v ih or v il ) i dd 30 i dd 40 1 i dd 50 ? ? 1 , 3 p o wer supply standby curr ent (r = v ih , w = v ih . a l l ot her inputs = v ih or v ih , i ih = 0) i sb ss ? 20 0 m a 1 input leakage cur r ent , an y input ( except j t a g ) (v in = v ss or v dd ) i li -2 + 2 ua o utput leakage curr ent (v ou t = v ss or v dd q , q i n hi g h - z) i lo -5 + 5 ua o u tput ? high ? level v o lt age (i oh = - 6 m a ) v oh v dd q -0. 4 v dd q o u tput ? low ? level v o lt age (i ol = +6m a ) v ol v ss v ss +0. 4 v 2, 4 j t a g leaka ge cu rrent (v in = v ss or v dd ) i li j t a g -100 ua5 1. i ou t = c hip output curr ent . 2. m inim um i m pedance output dr iv er . 3. t he n um er ic suf f ix i nd i c at es the par t operat ing at speed, as indicated i n a c character isti c s o n page 15- 16 ( t hat is , i dd 2 5 i n d i ca t e s 2.5ns cy cle time). 4. j e de c s t and ard j e s d 8-6 c l as s 1 com pati b le . 5. f o r jt a g input s only . 800 700 600 800 700 600 ma +100 v 2, 4
integrated silicon solution, inc. ? 1-800-379-4774 13 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams typical ac input characteristics item symbol minimum maximum notes ac input logic high v ih (ac) v ref + 0. 2 1, 2, 3, 4 ac input logic low v il (ac) v ref - 0. 2 1, 2, 3, 4 clock input logic high (k, k , c, c) v ih-clk (ac) v ref + 0. 2 1, 2, 3 clock input logic low (k, k , c, c) v il-clk (ac) v ref - 0. 2 1, 2, 3 1. the peak-to-peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2. performance is a function of v ih and v il levels to clock inputs. 3. see the ac input definition diagram. 4. see the ac input definition diagram. the signals should swing monotonically with no steps rail-to-rail with input signals never ring- ing back past vih (ac) and vil (ac) during the input setup and input hold window. vih (ac) and vil (ac) are used for timing pur - poses only. ac input definition programmable impedance output driver dc electrical characteristics (v dd = 1.8v -5%, +5%, v ddq = 1.5, 1.8v . over the operating temperature range. ) parameter symbol minimum maximum units notes output ? high ? level voltage v oh v ddq / 2 v ddq v1, 3 output ? low ? level voltage v ol v ss v ddq / 2 v 2, 3 1. i oh = 15% @ v oh = v ddq / 2 for: 175 ? rq 350 ? . 2. i ol = 15% @ v ol = v ddq / 2 for: 175 ? rq 350 ? . 3. parameter tested with rq = 250 ? and v ddq = 1.5v. v ih (ac) v ref v il (ac) setup time hold time v ref k k v rail v -rail vddq 2 ------------------ ?? ?? rq 5 -------- ? ? ? ? ? vddq 2 ------------------ ?? ?? rq 5 -------- ? ? ? ? ?
14 integrated silicon solution, inc. ? 1-800-379-4774 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams ac test loading q 50 ? 50 ? 5pf 0.75, 0.9v 0.75, 0.9v test comparator a c t e st c o n d it io n s ( v dd = 1 . 8 v -5 %, + 5 %, v ddq = 1.5, 1.8v . over the operating temperature range.) p a rameter s ym bol conditi on s u nits notes o u tput driver sup p l y v o l t age v dd q 1.5, 1.8 v input high l e v e l v ih 1.25 0.25 v input low level v il v input referenc e vo l t age v re f 0.75 v input rise ti m e t r 0. 35 ns input fall t i m e t f 0. 35 ns o u tput ti m i ng referenc e level v ddq/2 v o u tput load c ondit i ons 1, 2 1. s ee ac t e s t loading . 2. p a rameter t e s t ed wit h rq = 250 and v dd q = 1. 5v .
integrated silicon solution, inc. ? 1-800-379-4774 15 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams a c c h ara c t e r i st ic s ( v dd = 1 . 8 v -5 %, + 5 %. over the operating temperature range.) p a r a m e ter s ym bol 30 (300m hz) units notes min m ax cl o c k c y c l e ti m e ( k , k , c, c )t kh kh 3.3 7.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns c l oc k phase j i tt er (k , k , c, c )t kc - v ar c l oc k hi gh pulse (k, k , c , c )t kh kl c l oc k l o w pulse (k, k , c , c )t kl kh c l oc k t o clock (k h >k h , c h >c h )t kh k h c l oc k t o dat a clock (k h >c h , k h >c h )t kh ch d ll lock (k , c) t kc - lo c k k s t atic to dll re set t kc - re se t out put time s c, c high t o out put vali d t ch qv 0.40 1, 3 1, 3 c, c high t o out put hol d t ch qx -0.40 c, c high t o echo clock valid t chc qv 0.35 3 c, c high t o echo clock hold t chc qx - 0.35 3 cq , cq high to o u t put v a l i d t cq h q v 0.25 1, 3 1, 3 1, 3 1, 3 cq , cq high to o u t put hold t cq h q x - 0.25 c high t o out put high- z t ch qz 0.33 c high t o out put low- z t ch qx 1 - 0.33 se t up ti m e s a ddres s v a li d t o k, k r i s i ng edge t av k h 0.33 ? ns 2 c ont rol input s valid t o k rising edge t iv k h 0.33 ? ns 2 d a ta - i n v a l i d t o k , k rising edge t dv k h 0.33 ? ns 2 h o ld ti me s k r i s i n g edge t o addres s h o l d t kh ax 0.33 ? ns 2 k r i s i n g edge t o control inputs hold t kh i x 0.33 ? ns 2 k, k rising edge to da t a -in hold t kh dx 0.33 ? ns 2 1. s ee a c t e s t loading on page 14. 2. d u r i ng nor m a l operat ion, v ih , v il , t ri se , and t fa l l of inputs mus t be within 20% of v ih , v il , t ri s e , and t fa l l of cloc k. 3. if c , c are t i ed hi gh, t hen k, k becom e the re f e renc es f o r c , c t i ming par am eters . 0.12 1.32 1.32 1.35 0.0 1.35 1024 30 cycle ns
16 integrated silicon solution, inc. ? 1-800-379-4774 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams a c c h ara c t e r i st ic s ( v dd = 1 . 8 v -5 %, + 5 %. over the operating temperature range.) p a r a m e ter s ym bol 40 (250m hz) 50 4 (200mh z ) units n ot es min m a x min m ax cl o c k c y c l e ti m e ( k , k , c, c )t kh kh 4.0 7.5 5. 0 7 .5 ns c l oc k phase j i tt er (k , k , c, c )t kc - v ar 0. 2 0 .2 ns c l oc k hi gh pulse (k, k , c , c )t kh kl 1.6 2 . 0 ns c l oc k l o w pulse (k, k , c , c )t kl kh 1.6 2 . 0 ns c l oc k t o clock (k h >k h , c h >c h )t kh k h 1.8 2 . 2 c l oc k t o dat a clock (k h >c h , k h >c h )t kh ch 0.0 1.35 0. 0 1.35 d ll lock (k , c) t kc - lo c k 1024 1024 cycle ns k s t atic to dll re set t kc - re se t 30 30 out put time s c, c high t o out pu t vali d t ch qv 0.45 0. 45 ns 1, 3 c, c high t o out pu t hol d t ch qx -0. 4 5 - 0 . 45 ns ns 1, 3 c, c high t o echo clock valid t chc qv 0.40 0.4 3 c, c high t o echo clock hold t chc qx -0. 4 0 - 0 . 40 ns 3 cq , cq high to out put v a l i d t cq h q v 0.30 0. 40 ns 1, 3 cq , cq high to o u t put hold t cq h q x -0. 3 0 - 0 . 40 ns 1, 3 c high t o out put h i gh- z t ch qz 0.35 0. 38 ns 1, 3 c high t o out put low- z t ch qx 1 -0. 3 5 - 0 . 38 ns 1, 3 se t up ti m e s a ddres s v a li d t o k, k r i s i ng edge t av k h 0. 35 ? 0. 4 ? ns 2 ns 2 ns 2 c ont rol input s valid t o k rising edge t iv k h 0. 35 ? 0. 4 ? d a ta - i n v a l i d t o k , k rising edge t dv k h 0. 35 ? 0. 4 ? h o ld ti me s k r i s i n g edge t o addres s h o l d t kh ax 0. 35 ? 0. 4 ? ns 2 ns 2 ns 2 k r i s i n g edge t o control input s hold t kh i x 0. 35 ? 0. 4 ? k, k rising edge to da t a -in hold t kh dx 0. 35 ? 0. 4 ? 1. s ee a c t e s t loading on page 14. 2. d u r i ng nor m a l operat ion, v ih , v il , t ri se , and t fa l l of inputs mus t be within 20% of v ih , v il , t ri s e , and t fa l l of cloc k. 3. if c , c are t i ed hi gh, t hen k, k becom e the re f e renc es f o r c , c t i ming par am eters. ns ns
integrated silicon solution, inc. ? 1-800-379-4774 17 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams read and deselect cycles timing diagram t chcqx t chcqv t chcqx t chcqv t cqhqx t cqhqv t chqv t chqz t chqx t chqv t chqx t klkh t khkh t khkl t khix t ivkh t khax t avkh t khk h t klkh t khkh t khkl read read nop read nop a1 a2 a3 q1-1 q1-2 q2-1 q2-2 q3-1 k k sa r q (data out) c c cq cq t klk h notes: 1. q1-1 refers to output from address a1+0, q1-2 refers to output from address a1+1 (that is, the next internal burst address following a1+0). 2. outputs are disabled one cycle after an nop. don ? t care undefined
18 integrated silicon solution, inc. ? 1-800-379-4774 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams write and nop timing diagram t khdx t dvkh t khix t khix t ivkh t khax t avkh t khk h t khkh t klkh t khkl write write nop write nop a1 a2 a3 d1-1 d1-2 d2-1 d2-2 d3-1 d3-2 k k sa w d(data in) don ? t care undefined notes: 1. d1-1 refers to input to address a1+0, d1-2 refers to input to address a1+1 (that is, the next internal burst address following a1+0). 2. bw x assumed active. t khix t ivkh bw
integrated silicon solution, inc. ? 1-800-379-4774 19 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams read, write, and nop timing diagram read write read write read write nop write nop a1 a2 a3 a4 a5 a6 a7 d2-1 d2-2 d4-1 d6-1 d6-2 d7-1 d7-2 d4-2 q1-1 q1-2 q3-1 q3-2 q5-1 q5-2 notes: 1. if address a1=a2, data q1-1=d2-1, data q1-2=d2-2. write data is forwarded immediately as read results. k k sa w r d(data in) q(data out) c c cq cq don ? t care undefined bw x
20 integrated silicon solution, inc. ? 1-800-379-4774 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams ieee 1149.1 tap and boundary scan the sram provides a limited set of jtag functions to test the interconnection between sram i/os and printed circuit board traces or other components. there is no multiplexer in the path from i/o pins to the ram core. in conformance with ieee standard 1149.1, the sram contains a tap controller, instruction register, boundary scan register, bypass register, and id register. the tap controller has a standard 16-state machine that resets internally on power-up. therefore, a trst signal is not required. signal list tck: test clock tms: test mode select tdi: test data-in tdo: test data-out jtag dc operating characteristics (over the operating temperature range.) operates with jedec standard 8-5 (1.8v ) logic signal levels parameter symbol minimum typical maximum units notes jtag input high voltage v ih1 1.3 ? v dd +0.3 v 1 jtag input low voltage v il1 -0.3 ? 0.5 v 1 jtag output high level v oh1 v dd -0.4 ? v dd v1, 2 jtag output low level v ol1 v ss ? 0.4 v 1, 3 1. all jtag inputs and outputs are lvttl-compatible. 2. i oh1 -|2ma| 3. i ol1 +|2ma|. jtag ac test conditions (v dd = 1.8v -5%, +5% . over the operating temperature range) parameter symbol conditions units input pulse high level v ih1 1.3 v input pulse low level v il1 0.5 v input rise time t r1 1.0 ns input fall time t f1 1.0 ns input and output timing reference level 0.9 v
integrated silicon solution, inc. ? 1-800-379-4774 21 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams jtag ac characteristics (v dd = 1.8v -5%, +5% . over the operating temperature range.) parameter symbol minimum maximum units notes tck cycle time t thth 20 ? ns tck high pulse width t thtl 7 ? ns tck low pulse width t tlth 7 ? ns tms setup t mvth 4 ? ns tms hold t thmx 4 ? ns tdi setup t dvth 4 ? ns tdi hold t thdx 4 ? ns tck low to valid data t tlov ? 7ns1 1. see ac test loading on page 1 4. jtag timing diagram tck tms tdi tdo t thtl t tlth t thth t thmx t thdx t tlov t mvth t dvth
22 integrated silicon solution, inc. ? 1-800-379-4774 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams scan register definition register name bit size x18 or x36 instruction 3 bypass 1 id 32 boundary scan 109 id register definition part field bit number and description revision number (31:29) part configuration (28:12) jedec code (11:1) start bit (0) 2m x 18 000 00def0wx0t0q0b0s0 000 101 001 00 1 1m x 36 000 00def0wx0t0q0b0s0 000 101 001 00 1 part configuration definition : def = 010 for 36mb wx = 11 for x36, 10 for x18 t = 1 for dll, 0 for non-dll q = 1 for qdb2, 0 for ddr b = 1 for burst of 4, 0 for burst of 2 s = 1 for separate i/0, 0 for common i/o
integrated silicon solution, inc. ? 1-800-379-4774 23 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams list of ieee 1149.1 standard violations 7.2.1.b, e 7.7.1.a-f 10.1.1.b, e 10.7.1.a-d 6.1.1.d instruction set code instruction tdo output notes 000 extest boundary scan register 2,6 001 idcode 32-bit identification register 010 sample-z boundary scan register 1, 2 011 private do not use 5 100 sample boundary scan register 4 101 private do not use 5 110 private do not use 5 111 bypass bypass register 3 1. places qs in high-z in order to sample all input data, regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds the last serially loaded tdi when exiting the shift-dr state. 4. sample instruction does not place dqs in high-z. 5. this instruction is reserv ed. invoking this instruction will cause improper sram functionality. 6. this extest is not ieee 1149.1-compliant. by default, it places q in high-z. if the internal register on the scan chain is se t high, q will be updated with information loaded via a previous sample instruction. the actual transfer occurs during the update ir state after extest is loaded. the value of the internal register can be changed during sample and extest only. jtag block diagram bypass register (1 bit) identification register (32 bits) instruction register (3 bits) tap controller control signals tdi tms tck tdo
24 integrated silicon solution, inc. ? 1-800-379-4774 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams tap controller state machine test logic reset run test idle select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 0 0 0 0 1 0 1 1 0 1 1 1 0 01 1 1 0 1 0 0 0 1 1 0 0 0 0 1
integrated silicon solution, inc. ? 1-800-379-4774 25 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams order pin id order pin id order pin id 1 6r 37 10d 73 2c 26 p 3 79 e 7 43 e 3 6n 39 10c 75 2d 4 7p 40 11d 76 2e 57 n4 19 c7 71 e 67 r4 29 d7 82 f 7 8r 43 11b 79 3f 8 8p 44 11c 80 1g 99 r 4 59 b 8 11 f 10 11p 46 10b 82 3g 11 10p 47 11a 83 2g 12 10n 48 10a 84 1h 13 9p 49 9a 85 1j 14 10m 50 8b 86 2j 15 11n 51 7c 87 3k 16 9m 52 6c 88 3j 17 9n 53 8a 89 2k 18 11l 54 7a 90 1k 19 11m 55 7b 91 2l 20 9l 56 6b 92 3l 21 10l 57 6a 93 1m 22 11k 58 5b 94 1l 23 10k 59 5a 95 3n 24 9j 60 4a 96 3m 25 9k 61 5c 97 1n 26 10j 62 4b 98 2m 27 11j 63 3a 99 3p 28 11h 64 2a 100 2n 29 10g 65 1a 101 2p 30 9g 66 2b 102 1p 31 11f 67 3b 103 3r 32 11g 68 1c 104 4r 33 9f 69 1b 105 4p 34 10f 70 3d 106 5p 35 11e 71 3c 107 5n 36 10e 72 1d 108 5r 109 internal no te: 1) nc pins as defined on fbga pinouts on page 2 are read as ? don ? t cares ? . 2) state of internal pin (#109) is loaded via jtag
26 integrated silicon solution, inc. ? 1-800-379-4774 rev. h 1/6/2010 issi ? 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams note : 1. controlling dimension : mm package outline 12/10/2007
integrated silicon solution, inc. ? 1-800-379-4774 27 rev. h 1/6/2010 36 mb (1m x 36 & 2m x 18) quad (burst of 2) synchronous srams ordering information: commercial range: 0c to +70c speed order part no. organization package is61qdb21m36-300m3 1mx36 165 bga is61qdb21m36-300m3l 1mx36 165 bga, lead-free is61qdb22m18-300m3 2mx18 165 bga 300 mhz is61qdb22m18-300m3l 2mx18 165 bga, lead-free IS61QDB21M36-250M3 1mx36 165 bga IS61QDB21M36-250M3l 1mx36 165 bga, lead-free is61qdb22m18-250m3 2mx18 165 bga 250 mhz is61qdb22m18-250m3l 2mx18 165 bga, lead-free industrial range: -40c to +85c speed order part no. organization package is61qdb21m36-300m3i 1mx36 165 bga is61qdb21m36-300m3li 1mx36 165 bga, lead-free is61qdb22m18-300m3i 2mx18 165 bga 300 mhz is61qdb22m18-300m3li 2mx18 165 bga, lead-free IS61QDB21M36-250M3i 1mx36 165 bga IS61QDB21M36-250M3li 1mx36 165 bga, lead-free is61qdb22m18-250m3i 2mx18 165 bga 250 mhz is61qdb22m18-250m3li 2mx18 165 bga, lead-free speed top mark order part no. org. package is61qdb22m18-250m3 u757a-200m3i* 2mx18 165 bga is61qdb22m18-250m3l u757a-200m 3li* 2mx18 165 bga, lead-free IS61QDB21M36-250M3 u757d-200m3i* 1mx36 165 bga 200 mhz IS61QDB21M36-250M3l u757d-200m 3li* 1mx36 165 bga, lead-free note: * these parts are fully tested to industrial temperat ure, even though the top mark is commercial. by ordering these parts, the customer will receive parts that are tested to the indus trial temperature of -40 o c to +85 o c. the speed will be 200mhz at -40 o c to +85 o c.

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