W682388 layout guideline rev 1.3 - an-cs006a W682388 pro-x? codec layout guideline 1. W682388 layout considerations the winbond W682388 pro-x ? codec family is an excellent solution for short loop telephony applications. place the components carefully to insure best performance. this document outlines critical component layout issues. use it together with the W682388 data sheet and other supporting pro-x application notes. the W682388 will exhibit high-quality low-noise performa nce with the appropriate layout design. pins 52?61 are sensitive current input pins that are susceptible to induced noise. keep traces between these pins and their respective components (c7, c8, c10, c11, r13?16, and r18?27) to a minimum length. do not route any digital traces near these sensitive traces. place the line compensation capacitors, c5, c8, c9, and c12, near their respective tip and ring output pins. place a 0.1 f ceramic decoupling capacito r as close as possible to each vdd and vbat power supply input pin. these are pin 49 (vdd1), pin 64 (vdd2), pin 41 (vdd3), pin 8 (vdd4), pin 27 (vdd5) and pin 26 (vddl). replace the 0.1 f capacitors at vdd1 and vdd2 with 10 f ceramic capacitors for additional noise performance. refer to the figure 3 for an example of this layout. there are two external tip and ring capacitors for each channel. they are connected to ct1 (pin 39), cr1 (pin 38), ct2 (pin 10), and cr2 (pin 11). the capacitor is a 10 f ceramic (low leakage) capacitor. it is connected to 3.3v. route the capacitors directly to the appropriate vdd pin. for example, the ct1 and cr1 capacitors connect directly to their respective pi ns. their shared 3.3v connection is routed directly to vdd1 before connecting to the main 3.3v supply. th e situation is the same for ct2 and cr2, which must terminate at vdd2. the afe transistors qr3/qt3 (sot-223) and qr1/qt1 (sot-89) should have exposed copper pads to help reduce the thermal resistance of these components. the amount of copper used for the heat sink in combination with the surface area of the pcb will impr ove the heat dissipation of the transistor package. one way to increase the copper area when board space is limited is to connect the pad used for the heat sink by using multiple layers. a top and bottom si de can be used with multiple vias connecting them together. the optimal copper area to heat sink a sot-22 3 is 1 sq inch. this approach is similar to heat sinking used for the qfn package. (refer to section 4 on qfn grounding) place the resistors for iref (pin 13) and the transconductance amplifiers (pins 3,5,44 and 46) as close as possible to the part to minimize the trace l ength. these resistors are r29, r30 and r31. if more than two layers are used for the overall board circuit, separate analog and digital trace layers may enhance performance. digital signals are best applied to a dedicated layer. the ideal approach is to separate digital layers from analog layers by a power/ground plane. an-cs006a_W682388 pcb layout.doc page 1 of 8
W682388 layout guideline rev 1.3 idle channel noise (icn) performance can be further impr oved by splitting the 3.3v power plane. this way the front end power (vdd1 ? vdd4) and ground (gnd1 ? gnd4 & vssp) will be isolated from the main 3.3v and ground planes by using ferrite beads. 2. dc-to-dc converter layout the W682388 dc-to-dc converter circuit uses pulse width modulation to generate the desired voltages. lay out this circuit carefully to minimize the contri buted noise from the high switching currents. the dc-to-dc converter has spec ific areas to optimize to minimize this noise effect. the critical areas are described below: loop 1 in figure 1 is the secondary fl y-back current path that generates the negative vbat potential. place the components in this area in a tight loop. cove r the open areas in between with as much copper as possible. loop 2 in figure 1 is the primary input current loop fo r the dc-to-dc converter fr om the unregulated power supply. place the capacitors in this area near the sense resistor to maximize results. voltage sense resistors (rdh and rdl) 100v dcp1 c34 0.1uf 100v loop 2 r45 200 single point connection to ground current sense resistor (ris) bat1 d4 es1d r41 (rdh) 56.2k dch1 r42 (rdl) 56.2k dc_unreg loop 1 c36 0.1uf c31 10uf q16 zx5t955g 1 2 4 3 indp1 dc_in_ch1 r39 (re1) 200 bat1 100v r38(ris) 0.56 25v q18 2n2222 3 1 2 dcn1 l 150uh dcl1 c29 10uf figure 1. dc-to-dc converter circuit an-cs006a_W682388 pcb layout.doc page 2 of 8
W682388 layout guideline rev 1.3 dc-to-dc converter layout recommendations: 1) the perimeters of loops (1) & (2) must be as short as possible. 2) the high current paths mu st use large trace widths: typically wvdc>wvbat>5 mm [200 mils.] 3) the ground connection should be extended with multiple vias (3) in the case of inner layer or bottom layer ground plane (wvias<10 mm.) 4) even a small ground plane is better than no ground plane at all. 5) node n must have a very small area (low capacitance to ground.) 6) cvdc and cvbat should be low esr (or add a parallel ceramic capacitor to an electrolytic capacitor.) 7) lay out the diode, the transistor and the inductor as tightly as possible, preferably in a 15 mm by 15 mm square. it is most import ant that the layout of the diode, the capacitors and the inductor be as tight as possible. the inductor can be used as a heat sink for the switching transistor by merging and increasing the copper planes. vdc [9v ~ 12v] vbat [0v ~ -94.5v] gndvbat 3 wvbat wvdc r s pnp d l 1 2 n vdc [5v ~ 12v] cvdc cvbat wvias sense resistor figure 2. dc-to-dc switch cell layout an-cs006a_W682388 pcb layout.doc page 3 of 8
W682388 layout guideline rev 1.3 3. layout example the following layout example uses the W682388_rb1 daughter board. figure 3a. top view (component side) figure 3b. ground plane (inner layer) an-cs006a_W682388 pcb layout.doc page 4 of 8
W682388 layout guideline rev 1.3 figure 3c. power plane (inner layer)) figure 3d. bottom view (solder side) an-cs006a_W682388 pcb layout.doc page 5 of 8
W682388 layout guideline rev 1.3 4. qfn package grounding the W682388 qfn package uses an exposed pad to dissipate thermal energy. for best thermal performance of the package, solder the exposed pads to multiple ground planes. a top side, bottom side, and one inner ground plane must be used. there must be multiple vias connecting them together. twenty-five vias should be used in a 5x5 grid under the W682388. the size of the vias used for the W682388 epad should be at least 10 mils. (refer to figures 4, 5, and 6.) figure 4. epad top layer (component side) figure 5. epad gr ound (inner layer) figure 6. epad bottom layer (solder side) an-cs006a_W682388 pcb layout.doc page 6 of 8
W682388 layout guideline rev 1.3 5. layout check list perform the following steps to have hi gh quality, low-noise performance: 1. copy the W682388 evaluation board/examp le layout as closely as possible. 2. place the dc-to-dc converter near pins 17- 32 of the W682388 device as on the evaluation board. 3. put no power/ground planes under the protection circuitry in the front end. 4. isolate the analog front end power (vdd1, vdd2, vdd3, vdd4) and ground (gnd1, gnd2, gnd3, gnd4, vssp) by connecting them to the ma in 3.3v / gnd planes using ferrite beads. 5. route analog traces away from digital traces. stay away from pins 17 and 32 of W682388. 6. vdd capacitors should be placed close to the power and ground pins. connect all power and ground connections between the power pins and the bypass capacitors together with short traces. 7. use separate gnd and digital trace layers if the board has four or more layers, ideally separated by a power/gnd plane. 8. place the sense resistors (r18, r19, r20, r21, r22, r23, r 24, r25, r26, r27), the iref resistor (r31) and transconductance resistors (r 29 & 30) as close to the pins as possible. have no digital traces in path. 9. width of high current traces (i.e. dc-to-dc converter, etc.), should be at least 50 mils. 10. width of the tip and ring traces must be as wide as possible. 11. keep the components and traces related to the dc-to-dc converter isolated. avoid running a trace away from these components and traces. 12. each dc-to-dc converter must have a separate ground trace leading back to the supply as shown in figure 1. 13. minimize the surface area formed by the curre nt sense resistor, ris (r38), and the voltage sense resistors rdh and rdl (r41& r42). pl ace the voltage sense resistors close to the W682388. route the voltage sensing trace betw een ris to the pair rdh and rdl tightly in parallel or on top of each other on two separate layers. perform the following steps to optimize the analog front end: 1. place the discrete transistors near pins 49-65 of the W682388 similar to the evaluation board. 2. compensation capacitors should be placed as follows: 1. c9 as close as possible to the collector of transistors qr1_c1 and qr3_c1. 2. c12 as close as possible to the colle ctor of transistors qt1_c1 and qt3_c1. 3. c8 as close as possible to the collector of transistors qr1_c2 and qr3_c2. 4. c5 as close as possible to the collector of transistors qt1_c2 and qt3_c2. the afe transistors qr3/qt3 (sot-223) and qr1/qt1 (sot-89) should have exposed copper pads to help reduce the thermal resistance of these components. the amount of copper used for the heat sink in combination with the surface area of the pcb will impr ove the heat dissipation of the transistor package. one way to increase the copper area when board space is limited is to connect the pad used for the heat sink by using multiple layers. a top and bottom side can be used with multiple vias connecting them together. the optimal copper area to heat sink a sot- 223 is 1 sq inch. this approach is similar to heat sinking used for the qfn package. (refer to section 4 on qfn grounding) an-cs006a_W682388 pcb layout.doc page 7 of 8
W682388 layout guideline rev 1.3 6. version history version date page description 1.1 march 21, 2006 initial revision 1.2 april 17, 2006 1,4,5,7 modified per new layout and schematic annotation. 1.3 june 21, 2006 1,2,3,7,8 added paragraph on afe lay out and heat sinking. changed a few words for clarity. corrected typos. important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical impl antation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other app lications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. the information contained in this document may be subject to change without notice. it is the responsibility of the cu stomer to check the winbond usa website ( www.winbond-usa.com ) periodically for the latest version of this document, and any errata sheets that may be generated between document revisions. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.
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