ucc1580-1,-2,-3,-4 ucc2580-1,-2,-3,-4 ucc3580-1,-2,-3,-4 sl us 29 2 - f eb ru ary 1 999 features provides auxiliary switch activation complementary to main power switch drive programmable deadtime (turn-on delay) between activation of each switch voltage mode control with feedforward operation programmable limits for both transformer volt- second product and pwm duty cycle high current gate driver for both main and auxiliary outputs multiple protection features with latched shutdown and soft restart low supply current (100 m a startup, 1.5ma operation) block diagram description the ucc3580 family of pwm controllers is designed to implement a variety of active clamp/reset and synchronous rectifier switching converter topolo- gies. while containing all the necessary functions for fixed frequency, high performance pulse width modulation, the additional feature of this design is the inclusion of an auxiliary switch driver which complements the main power switch, and with a programmable deadtime or delay between each transition. the active clamp/reset technique allows operation of single ended converters beyond 50% duty cycle while reducing voltage stresses on the switches, and allows a greater flux swing for the power transformer. this approach also allows a reduction in switching losses by recovering en- ergy stored in parasitic elements such as leakage inductance and switch capacitance. the oscillator is programmed with two resistors and a capacitor to set switching frequency and maximum duty cycle. a separate synchronized ramp provides a voltage feedforward pulse width modulation and a pro- grammed maximum volt-second limit. the generated clock from the oscilla- tor contains both frequency and maximum duty cycle information. (continued) single ended active clamp/reset pwm udg-95069-2 pin numbers refer to dil-16 and soic-16 packages
2 ucc1580-1,-2,-3,-4 ucc2580-1,-2,-3,-4 ucc3580-1,-2,-3,-4 vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16v i vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ma line, ramp . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to vdd + 1v i line , i ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3v i delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 5ma i out1 (tpw < 1 m s and duty cycle < 10%) . . . . . . . - 0.6a to 1.2a i out2 (tpw < 1 m s and duty cycle < 10%) . . . . . . . - 0.4a to 0.4a i clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 100ma to 100ma osc1, osc2, ss, shtdwn, eain . . . . . - 0.3v to ref + 0.3v i eaout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 5ma to 5ma i ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30ma pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.2v to 0.2v storage temperature . . . . . . . . . . . . . . . . . . . - 65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . - 55c to +150c lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . +300c all voltages are with respect to ground unless otherwise stated. currents are positive into, negative out of the specified termi- nal. consult packaging section of databook for thermal limita- tions and considerations of packages. absolute maximum ratings plcc-20 (top view) q packages connection diagrams dil-16, soic-16 (top view) j, n, or d packages order information the main gate drive output (out1) is controlled by the pulse width modulator. the second output (out2) is in- tended to activate an auxiliary switch during the off time of the main switch, except that between each transition there is deadtime where both switches are off, pro- grammed by a single external resistor. this design offers two options for out2, normal and inverted. in the -1 and -2 versions, out2 is normal and can be used to drive pmos fets. in the -3 and -4 versions, out2 is inverted and can be used to drive nmos fets. in all versions, both the main and auxiliary switches are held off prior to startup and when the pwm command goes to zero duty cycle. during fault conditions, out1 is held off while out2 operates at maximum duty cycle with a guaran- teed off time equal to the sum of the two deadtimes. undervoltage lockout monitors supply voltage (vdd), the precision reference (ref), input line voltage (line), and the shutdown comparator (shtdwn). if after any of these four have sensed a fault condition, recovery to full operation is initiated with a soft start. vdd thresholds, on and off, are 15v and 8.5v for the -2 and -4 versions, 9v and 8.5v for the -1 and -3 versions. the ucc1580-x is specified for operation over the mili- tary temperature range of - 55c to 125c. the ucc2580-x is specified from - 40c to 85c. the ucc3580-x is specified from 0c to 70c. package op- tions include 16-pin surface mount or dual in-line, and 20-pin plastic leadless chip carrier. description (cont.)
3 ucc1580-1,-2,-3,-4 ucc2580-1,-2,-3,-4 ucc3580-1,-2,-3,-4 electrical characteristics unless otherwise stated, all specifications are over the full temperature range, vdd = 12v, r1 = 18.2k, r2 = 4.41k, c t = 100pf, r3 = 100k, c out1 = 0, c out2 = 0. t a = 0c to 70c for the ucc3580, - 40c to 85c for the ucc2580, - 55c to 125c for the ucc1580, t a = t j . parameter test conditions min typ max units oscillator section frequency 370 400 430 khz clk pulse width 650 750 850 ns clk v oh i clk = - 3ma 4.3 4.7 v clk v ol i clk = 3ma 0.3 0.5 v ramp generator section ramp v ol i ramp = 100 m a 50 100 mv flux comparator vth 3.16 3.33 3.50 v pulse width modulator section minimum duty cycle out1, eaout = vol 0 % maximum duty cycle out1, eain = 2.6v 63 66 69 % pwm comparator offset 0.1 0.4 0.9 v error amplifier section eain eaout = eain 2.44 2.5 2.56 v i eain eaout = eain 150 400 na eaout, vol eain = 2.6v, i eaout = 100 m a 0.3 0.5 v eaout, voh eain = 2.4v, i eaout = - 100 m a 4 5 5.5 v avol 70 80 db gain bandwidth product f = 100khz (note 1) 2 6 mhz softstart/shutdown section start duty cycle eain = 2.4v 0 % ss v ol i ss = 100 m a 100 350 mv ss restart threshold 400 550 mv i ss C20 C35 m a shtdwn v th 0.4 0.5 0.6 v i shtdwn 50 150 na undervoltage lockout section vdd on ucc3580-2,-4 14 15 16 v ucc3580-1,-3 8 9 10 v vdd off 7.5 8.5 9.5 v line on 4.7 5 5.3 v line off 4.2 4.5 4.8 v i line line = 6v 50 150 na supply section vdd clamp i vdd = 10ma 14 15 16 v i vdd start vdd < vdd on 160 250 m a i vdd operating no load 2.5 3.5 ma output drivers section out1 v sat high i out1 = - 50ma 0.4 1.0 v out1 v sat low i out1 =100ma 0.4 1.0 v out2 v sat high i out2 = - 30ma 0.4 1.0 v out2 v sat low i out2 = 30ma 0.4 1.0 v out1 fall time c out1 = 1nf, r s = 3 w 20 50 ns out1 rise time c out1 = 1nf, r s = 3 w 40 80 ns out2 fall time c out2 = 300pf, r s = 10 w 20 50 ns
4 ucc1580-1,-2,-3,-4 ucc2580-1,-2,-3,-4 ucc3580-1,-2,-3,-4 electrical characteristics unless otherwise stated, all specifications are over the full temperature range, vdd = 12v, r1 = 18.2k, r2 = 4.41k, c t = 100pf, r3 = 100k, c out1 = 0, c out2 = 0. t a = 0c to 70c for the ucc3580, - 40c to 85c for the ucc2580, - 55c to 125c for the ucc1580, t a = t j . parameter test conditions min typ max units output drivers section (cont.) out2 rise time c out2 = 300pf, r s = 10 w 20 40 ns delay 1 out2 to out1 r3 = 100k, c out1 = c out2 = 15pf 90 120 160 ns t a = t j = 25c 100 120 140 ns delay 2 out1 to out2 r3 = 100k, c out1 = c out2 = 15pf 110 170 250 ns t a = t j = 25c 140 170 200 ns reference section ref i ref = 0 4.875 5 5.125 v load regulation i ref = 0ma to 1ma 1 20 mv line regulation vdd = 10v to 14v 1 20 mv clk: oscillator clock output pin from a low impedance cmos driver. clk is high during guaranteed off time. clk can be used to synchronized up to five other ucc3580 pwms. delay: a resistor from delay to gnd programs the nonoverlap delay between out1 and out2. the delay times, delay1 and delay2, are shown in figure 1 and are as follows: delay pf r 111 3 = . delay2 is designed to be larger than delay1 by a ratio shown in figure 2. eain: inverting input to the error amplifier. the noninverting input of the error amplifier is internally set to 2.5v. eain is used for feedback and loop compensation. eaout: output of the error amplifier and input to the pwm comparator. loop compensation components connect from eaout to eain. gnd: signal ground. line: hysteretic comparator input. thresholds are 5.0v and 4.5v. used to sense input line voltage and turn off out1 when the line is low. osc1 & osc2: oscillator programming pins. a resistor connects each pin to a timing capacitor. the resistor connected to osc1 sets maximum on time. the resistor connected to osc2 controls guaranteed off time. the combined total sets frequency with the timing capacitor. frequency and maximum duty cycle are approximately given by: () frequency 1 r1 1.25 r2 ct = + maximum duty cycle r1 r1 1.25 r2 = + maximum duty cycle for out1 will be slightly less due to delay1 which is programmed by r3. out1: gate drive output for the main switch capable of sourcing up to 0.5a and sinking 1a. out2: gate drive output for the auxiliary switch with 0.3a drive current capability. pgnd: ground connection for the gate drivers. connect pgnd to gnd at a single point so that no high frequency components of the output switching currents are in the ground plane on the circuit board. ramp: a resistor (r4) from ramp to the input voltage and a capacitor (cr) from ramp to gnd programs the feedforward ramp signal. ramp is discharged to gnd when clk is high and allowed to charge when clk is low. ramp is the line feedforward sawtooth signal for the pwm comparator. assuming the input voltage is much greater than 3.3v, the ramp is very linear. a flux comparator compares the ramp signal to 3.3v to limit the maximum allowable volt-second product: volt-second product clamp = 3.3 ? r4 ? cr. ref: precision 5.0v reference pin. ref can supply up to 5ma to external circuits. ref is off until vdd exceeds 9v (C1 and C3 versions) or activates the 15v clamp (C2 and C4 versions) and turns off again when vdd droops below 8.5v. bypass ref to gnd with a 1 m f capacitor. shtdwn: comparator input to stop the chip. the threshold is 0.5v. when the chip is stopped, out1 is low and out2 continues to oscillate with guaranteed off time equal to two non-overlap delay times. pin descriptions
5 ucc1580-1,-2,-3,-4 ucc2580-1,-2,-3,-4 ucc3580-1,-2,-3,-4 uvlo and startup for self biased off-line applications, -2 and -4 versions (uvlo on and off thresholds of 15v and 8.5v typical) are recommended. for all other applications, -1 and -3 versions provide the lower on threshold of 9v. the ic re- quires a low startup current of only 160 m a when vdd is under the uvlo threshold, enabling use of a large trickle charge resistor (with corresponding low power dissipa- tion) from the input voltage. vdd has an internal clamp at 15v which can sink up to 10ma. measures should be taken not to exceed this current. for -2 and -4 versions, this clamp must be activated as an indication of reaching the uvlo on threshold. the internal reference (ref) is brought up when the uvlo on threshold is crossed. the startup logic ensures that line and ref are above and shtdwn is below their respective thresholds before outputs are asserted. line input is useful for monitoring actual input voltage and shutting off the ic if it falls be- low a programmed value. a resistive divider should be used to connect the input voltage to the line input. this feature can protect the power supply from excessive currents at low line voltages. figure 1. output time relationships. application information udg-95070-2 note: waveforms are not to scale. ss: a capacitor from ss to ground programs the soft start time. during soft start, eaout follows the amplitude of sss slowly increasing waveform until regulation is achieved. vdd: chip power supply pin. vdd should be bypassed to pgnd. the C1 and C3 versions require vdd to ex- ceed 9v to start and remain above 8.5v to continue run- ning. a shunt clamp from vdd to gnd limits the supply voltage to 15v. the C2 and C4 versions do not start until the shunt clamp threshold is reached and operation con- tinues as long as vdd is greater than 8.5v. pin descriptions (cont.)
6 ucc1580-1,-2,-3,-4 ucc2580-1,-2,-3,-4 ucc3580-1,-2,-3,-4 the soft start pin provides an effective means to start the ic in a controlled manner. an internal current of 20 m a begins charging a capacitor connected to ss once the startup conditions listed above have been met. the voltage on ss effectively controls maximum duty cycle on out1 during the charging period. out2 is also con- trolled during this period (see figure 1). negation of any of the startup conditions causes ss to be immediately discharged. internal circuitry ensures full discharge of ss (to 0.3v) before allowing charging to begin again, provided all the startup conditions are again met. oscillator simplified oscillator block diagram and waveforms are shown in figure 3. osc1 and osc2 pins are used to program the frequency and maximum duty cycle. ca- pacitor ct is alternately charged through r1 and dis- charged through r2 between levels of 1v and 3.5v. the charging and discharging equations for ct are given by vc(charge) = ref C 4.0 ? e - t 1 t vc(discharge) = 3.5 ? e - t 2 t where t 1 =r1?ct and t 2 = r2 ? ct. the charge time and discharge time are given by t ch = r1 ? c t and t dis = 1.25 ? r2 ? c t the clk output is high during the discharge period. it blanks the output to limit the maximum duty cycle of out1. the frequency and maximum duty cycle are given by frequency = 1 (r1 +1.25 ? r2) ? ct maximum duty cycle = r1 r1 +1.25 ? r2 maximum duty cycle for out1 will be slightly less due to delay1 which is programmed by r3. voltage feedforward and volt-second clamp ucc3580 has a provision for input voltage feedforward. as shown in figure 3, the ramp slope is made propor- tional to input line voltage by converting it into a charg- ing current for cr. this provides a first order cancellation of the effects of line voltage changes on converter performance. the maximum volt-second clamp is provided to protect against transient saturation of the transformer core. it terminates the out1 pulse when the ramp voltage exceeds 3.3v. if the feedforward feature is not used, the ramp can be gener- ated by tying r4 to ref. however, the linearity of ramp suffers and in this case the maximum volt-second clamp is no longer available. figure 3. oscillator and ramp circuits. udg-96016-1 delay times 0 200 400 600 800 1000 1200 1400 0 100 200 300 400 500 600 700 800 900 1000 r3 programmingresistor [k w ] delay [ns] 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 delay2/delay1 ratio delay ratio delay1 delay2 figure 2. delay times. application information (cont.)
7 ucc1580-1,-2,-3,-4 ucc2580-1,-2,-3,-4 ucc3580-1,-2,-3,-4 output configurations the ucc3580 family of ics is designed to provide con- trol functions for single ended active clamp circuits. for different implementations of the active clamp approach, different drive waveforms for the two switches (main and auxiliary) are required. the -3 and -4 versions of the ic supply complementary non-overlapping waveforms (out1 and out2) with programmable delay which can be used to drive the main and auxiliary switches. most active clamp configurations will require one of these out- puts to be transformer coupled to drive a floating switch (e.g. figure 5). the -1 and -2 versions have the phase of out2 inverted to give overlapping waveforms. this con- figuration is suitable for capacity coupled driving of a ground referenced p-channel auxiliary switch with the out2 drive while out1 is directly driving an n-channel main switch (e.g. figure 4). the programmable delay can be judiciously used to get zero voltage turn-on of both the main and auxiliary switches in the active clamp circuits. for the ucc3580, a single pin is used to program the delays between out1 and out2 on both sets of edges. figure 1 shows the relationships between the outputs. figure 2 gives the ratio between the two delays. during the transition from main to auxiliary switch, the delay is not very critical for zvs turn-on. for the first half of out1 off-time, the body diode of the auxiliary switch conducts and out2 can be turned on any time. the transition from auxiliary to main switch is more critical. energy stored in the parasitic in- ductance(s) at the end of the out2 pulse is used to dis- charge the parasitic capacitance across the main switch during the delay time. the delay (delay 1) should be op- timally programmed at 1/4 the resonant period deter- mined by parasitic capacitance and the resonant inductor (transformer leakage and/or magnetizing induc- tances, depending on the topology). however, depend- ing on other circuit parasitics, the resonant behavior can change, and in some cases, zvs turn-on may not be ob- tainable. it can be shown that the optimum delay time is independent of operating conditions for a specific circuit and should be determined specifically for each circuit. application information (cont.) figure 4. active clamp forward converter. udg-95071-2 note that vicor corporation has claimed that the use of active reset in a forward converter topology is covered by their u.s. patent no. 4,441,146. unitrode is not suggesting or encouraging persons to infringe or use vicors patented technology absent a license from vicor.
8 ucc1580-1,-2,-3,-4 ucc2580-1,-2,-3,-4 ucc3580-1,-2,-3,-4 figure 5. off-line active clamp flyback converter. application information (cont.) udg-96017-1 the use of active reset in a flyback power converter topology may be covered by u.s. patent no. 5,402,329 owned by technical witts, inc., and for which unitrode offers users a paid up license for application of the ucc1580 product family.
9 ucc1580-1,-2,-3,-4 ucc2580-1,-2,-3,-4 ucc3580-1,-2,-3,-4 unitrode corporation 7 continental blvd. ? merrimack, nh 03054 tel. (603) 424-2410 fax (603) 424-3460 figure 6. ucc3580 used in a synchronous rectifier application. application information (cont.) udg-96018-1
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