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d a t a sh eet product speci?cation supersedes data of 2004 sep 03 2005 jan 11 integrated circuits tda8260tw satellite zero-if qpsk/8psk downconverter with pll synthesizer
2005 jan 11 2 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw features direct conversion quadrature phase shift keying (qpsk) and 8-phase shift keying (8psk) demodulation (zero-if) frequency range: 950 to 2175 mhz high level asymmetrical rf input 0 to 50 db variable gain with agc control loop-controlled 0 to 90 phase shifter high agc linearity (<1 db per bit with an 8-bit dac), agc voltage variable between 0 and 3 v integrated 5th-order matched baseband filters for in-phase (i) and quadrature (q) signal paths controlled i-to-q gain balance i 2 c-bus controlled pll frequency synthesizer low phase noise operation from a 4 mhz crystal (allowing the use of an smd crystal) five frequency steps from 125 khz to 2 mhz crystal frequency output to drive the demodulator ic compatible with 5, 3.3 and 2.5 v i 2 c-bus fully compatible and easy to interface with philips semiconductors family of digital satellite demodulators +5 v dc supply voltage 38-pin high heat dissipation package. applications direct broadcasting satellite (dbs) qpsk demodulation digital video broadcasting (dvb) qpsk demodulation bs digital 8psk demodulation. general description the direct conversion qpsk demodulator is the front-end receiver dedicated to digital tv broadcasting, satisfying both dvb and dbs tv standards. the wide range oscillator (from 950 to 2175 mhz) covers the american, european and asian satellite bands, as well as the sma-tv us standard. the zero-if concept discards traditional if filtering and intermediate conversion techniques. it also simplifies the signal path. optimum signal level is guaranteed by gain-controlled amplifiers in the rf path. the 0 to 50 db variable gain is controlled by the signal returned from the satellite demodulator and decoder (sdd) and applied to pin agcin. the pll synthesizer is built on a dual-loop concept. the first loop controls a fully integrated l-band oscillator, using as a reference the lc vco which runs at a quarter of the synthesized frequency. the second loop controls the tuning voltage of the vco and improves the phase noise of the carrier within the loop bandwidth. the step size is equal to the comparison frequency. the input of the main divider of the pll synthesizer is connected internally to the vco output. the comparison frequency of the second loop is obtained from an oscillator driven by an external 4 mhz crystal. the 4 mhz output available at pin xtout may be used to drive the crystal inputs of the sdd, thereby saving an additional crystal in the application. both the divided and the comparison frequencies of the second loop are compared in a fast phase detector which drives the charge pump. the tda8260tw includes a loop amplifier with an internal high-voltage transistor to drive an external 33 v tuning voltage. control data is entered via the i 2 c-bus. the i 2 c-bus voltage can be 5.0, 3.3 or 2.5 v, thus allowing compatibility with most existing microcontrollers. a 5-byte frame is required to address the device and to program the main divider ratio, the reference divider ratio, the charge pump current and the operating mode. a flag is set when the loop is in-lock, this can be read during read operations, as well as the power-on reset flag. the device has four selectable i 2 c-bus addresses. the selection is done by applying a specific voltage to pin as. this feature gives the possibility to use up to four tda8260tw ics in the same system.
2005 jan 11 3 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw performance summary tda8260tw performance: noise figure at maximum gain = +18 db high linearity; ip2 = +19 dbm and ip3 = +14 dbm low phase noise on baseband outputs: - 78 dbc/hz (f offset = 1 and 10 khz; f comp = 1 mhz) 0 to 50 db variable gain with agc control agc linearity <1 db/bit with an 8-bit dac maximum i-to-q amplitude mismatch = 1 db maximum i-to-q phase mismatch = 3 signal rates from 1 to 45 msymbol/s. system performance, for example, in a tuner application with the ic placed after a low-cost discrete lna (see fig.11): noise figure at maximum gain = 8 db high linearity; ip2 = +15 dbm and ip3 = +5 dbm 0 to 50 db variable gain with agc control. speci?cation limitation the content of this specification is applies to the device tda8260tw with versions c2 and above. version c1 is not covered by this document. please contact your philips semiconductors representative for further information. quick reference data ordering information symbol parameter conditions min. typ. max. unit v cc supply voltage 4.75 5.0 5.25 v i cc supply current - 155 - ma f osc oscillator frequency 950 - 2175 mhz ? eq ? quadrature error (absolute value) v agc = 1.5 v; v o(p-p) = 750 mv; measured in baseband - 0 3 deg v o(p-p) recommended output voltage (peak-to-peak value) - 750 - mv lpf co lpf cut-off frequency - 36 - mhz j n phase noise on baseband outputs f offset = 1 and 10 khz; f comp = 1 mhz with appropriate loop ?lter and charge pump setting --- 78 dbc/hz d g v agc range v agc =0to3v 48 50 - db v xtout(p-p) ac output voltage on pin xtout (peak-to-peak value) t 2 = 1, t 1 = 0, t 0 =0; driving a load of c l =10pf, r l =1m w 500 650 - mv t amb ambient temperature - 20 - +85 c type number package name description version tda8260tw htssop38 plastic thermal enhanced thin shrink small outline package; 38 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad sot633-3
2005 jan 11 4 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw block diagram handbook, full pagewidth 25 13 12 17 26 6 27 15 24 11 10 7 8 31 28 3 4 9 agc control vco f div f xtal f comp fast phase/ frequency comparator digital phase comparator reference divider power-on reset control logic and latch oscillator charge pump divide-by-4 15-bit divider 33 v amp 14 16 23 21 22 20 19 18 38 33 34 5 i q integrated oscillator 29 30 2 1 i 2 c-bus 36 37 32 35 tda8260tw mgu790 xtout sda scl as cp vt bvs v cc(vco) tka tkb vcognd cap1 cap2 iout bbgnd2 ibbin n.c. ibbout iin xt1 xt2 v cc(pll) pllgnd agcin biasn rfgnd1 v cc(rf) rfa rfb rfgnd2 lp1 lp2 qout bbgnd1 qbbin v cc(bb) qbbout qin fig.1 block diagram.
2005 jan 11 5 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw pinning information symbol pin description xt1 1 4 mhz crystal oscillator input 1 xt2 2 4 mhz crystal oscillator input 2 v cc(pll) 3 supply voltage for pll circuit (+5 v) pllgnd 4 ground for pll circuit agcin 5 agc input from satellite demodulator and decoder biasn 6 rf isolation input (+5 v) rfgnd1 7 ground 1 for rf circuit v cc(rf) 8 supply voltage for rf stage (+5 v) rfa 9 rf signal input a rfb 10 rf signal input b rfgnd2 11 ground 2 for rf circuit lp1 12 low-pass ?lter loop ?ltering output lp2 13 low-pass ?lter loop ?ltering input qout 14 quadrature output for ac coupling to pin 16 bbgnd1 15 ground 1 for baseband stage qbbin 16 quadrature baseband ac-coupled input from pin 14 v cc(bb) 17 supply voltage for baseband stage (+5 v) qbbout 18 quadrature baseband output to satellite demodulator and decoder qin 19 quadrature input for auto-amplitude matching iin 20 in-phase input for auto-amplitude matching ibbout 21 in-phase baseband output to satellite demodulator and decoder n.c. 22 not connected ibbin 23 in-phase ac-coupled baseband input from pin 25 bbgnd2 24 ground 2 for baseband stage iout 25 in-phase output for ac-coupling to pin 23 cap2 26 amplitude matching loop ?ltering output 2 cap1 27 amplitude matching loop ?ltering output 1 vcognd 28 ground for vco circuit tkb 29 vco tank circuit input b tka 30 vco tank circuit input a v cc(vco) 31 supply voltage for vco circuit (+5 v) bvs 32 bus voltage select input vt 33 tuning voltage output for vco cp 34 charge pump output as 35 address selection input scl 36 i 2 c-bus clock input sda 37 i 2 c-bus data input/output xtout 38 4 mhz crystal oscillator output to satellite demodulator and decoder
2005 jan 11 6 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw functional description the tda8260tw contains the core of the rf analog part of a digital satellite receiver. the signal coming from the low noise block (lnb) is coupled through a low noise amplifier (lna) to the rf inputs. the internal circuitry performs the zero-if quadrature frequency conversion and the two in-phase (ibbout) and quadrature (qbbout) output signals can be used directly to feed a satellite demodulator and decoder circuit (sdd). the tda8260tw has a gain-controlled amplifier in the converter circuit. the gain is controlled by the agcin input from the sdd. an external vco tank circuit is connected between pins tka and tkb. the main elements of the external tank circuit are an smd coil and a varactor diode. the tuning voltage of 0 to 30 v covers the whole frequency range from 237.5 to 543.75 mhz. the internal loop controls a fully integrated vco to cover the range 950 to 2175 mhz. the vco provides both in-phase and quadrature signals to drive the two mixers. except for the 4 mhz crystal and the loop filter, all circuit components necessary to control the varactor-tuned oscillator are integrated in the tda8260tw. the tuning circuit includes a fast phase detector with a high comparison frequency in order to achieve the lowest possible level of phase noise in the local oscillator. the f div output of the15-bit programmable divider passes through the fast phase comparator where it is compared in both phase and frequency with the comparison frequency (f comp ). the frequency f comp is derived from the signal present at the xt1/xt2 pins (f xtal ) divided-down by the reference divider. the buffered xtout signal can drive the crystal frequency input of the sdd, thereby saving a crystal in the application. the output of the phase comparator drives the charge pump and loop amplifier section. the loop amplifier includes a high voltage transistor to handle the 30 v tuning voltage at pin vt, this drives a variable capacitance diode in the external circuit of the voltage controlled oscillator. pin cp is the output of the charge pump. the loop filter is connected between pins cp and vt and the post-filter section is connected between pin vt and the variable capacitance diode. for test and alignment purposes, it is possible to release the tuning voltage output and apply an external voltage to pin vt, also to select the charge pump function to sink current, source current or to be switched off. handbook, halfpage tda8260tw mgu791 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 xtout sda scl as cp vt bvs v cc(vco) tka tkb vcognd cap1 cap2 iout bbgnd2 ibbin n.c. ibbout iin xt1 xt2 v cc(pll) pllgnd agcin biasn rfgnd1 v cc(rf) rfa rfb rfgnd2 lp1 lp2 qout bbgnd1 qbbin v cc(bb) qbbout qin fig.2 pin configuration.
2005 jan 11 7 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw programming the programming of the tda8260tw is performed through the i 2 c-bus. the read/write selection is made through the r/ w bit (address lsb). the tda8260tw fulfils the i 2 c-bus fast mode, according to the philips i 2 c-bus specification, see document 9398 393 40011 . i 2 c-bus voltage the i 2 c-bus lines scl and sda can be connected to an i 2 c-bus system tied either to 2.5, 3.3 or 5.0 v, that will allow direct connection to most existing microcontrollers. the choice of the threshold voltage for the i 2 c-bus lines is made with pin bvs that needs to be left open-circuit, connected to supply voltage or connected to ground; see table 1. table 1 i 2 c-bus voltage selection i 2 c-bus write mode i 2 c-bus write mode: r/ w = logic 0; see table 2. after transmission of the address (first byte), four data bytes can be sent to fully program the tda8260tw. the transmission sequence is one address byte followed by four data bytes pd1, pd2, cd1 and cd2. the i 2 c-bus transceiver has an auto-increment facility that permits the tda8260tw to be programmed within a single transmission. the tda8260tw can be partly programmed provided that the first data byte following the address is pd1 or cd1. the first bit of the first data byte transmitted indicates whether pd1 (first bit = logic 0) or cd1 (first bit = logic 1) will follow. additional data bytes can be entered without the need to re-address the device until an i 2 c-bus stop condition is sent by the controller. each byte is loaded after the corresponding 8th clock pulse. programmable divider data (contents of pd1 and pd2) become valid only after the 8th clock pulse of pd2, or after a stop condition if only pd1 needs to be programmed. pin bvs i 2 c-bus voltage (v) gnd 2.5 open-circuit 3.3 v cc 5 table 2 i 2 c-bus write data format notes 1. msb is transmitted first. 2. x = undefined. 3. acknowledge bit (a). byte (msb) (1) bits (2) (lsb) ack (3) programmable address 1 1 0 0 0 ma1 ma0 0 a programmable divider (pd1) 0 n14 n13 n12 n11 n10 n9 n8 a programmable divider (pd2) n7 n6 n5 n4 n3 n2 n1 n0 a control data (cd1) 1 t2 t1 t0 r2 r1 r0 x a control data (cd2) c1 c0 x x x x x x a
2005 jan 11 8 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw p rogrammable addresses the programmable address bits ma1 and ma0 offer the possibility of having up to four tda8260tw devices in the same system. the relationship between the voltage applied to pin as and the value of bits ma1 and ma0 is given in table 3. table 3 i 2 c-bus address selection p rogrammable main divider ratio program bytes pd1 and pd2 contain the fifteen bits n14 to n0 that set the main divider ratio. the ratio n = n14 2 14 + n13 2 13 +...+ n1 2 + n0. o perating and test modes the mode of operation is set using bits t2, t1 and t0 in control byte cd1; see table 4. table 4 mode selection note 1. status at power-on: the tuning voltage output is released and pin vt is in the high-impedance state. r eference divider five reference divider ratios allow the adjustment of the comparison frequency to different values depending on the compromise that has to be found between step size and phase noise. the reference divider ratios and the corresponding comparison frequencies are programmed using bits r2, r1 and r0; see table 5. table 5 reference divider ratio c harge pump current four values of charge pump current can be chosen using bits c1 and c0; see table 6. table 6 charge pump current v as ma1 ma0 0 to 0.1v cc 00 open-circuit 0 1 0.4v cc to 0.6v cc 10 0.9v cc to v cc 11 t2 t1 t0 mode xtout 0 0 0 normal operation off 0 0 1 por state = cp sink (1) f xtal 010 1 / 2 f div 1 / 2 f div 0 1 1 cp sink f xtal 1 0 0 normal operation f xtal 1012 f ref 2 f ref 1 1 0 cp off f xtal 1 1 1 cp source f xtal r2 r1 r0 divider ratio comparison frequency 000 2 2mhz 001 4 1mhz 0 1 0 8 500 khz 0 1 1 not allowed 1 0 0 not allowed 1 0 1 16 250 khz 1 1 0 not allowed 1 1 1 32 125 khz c1 c0 typical charge pump current absolute values ( m a) 0 0 420 0 1 900 1 0 1360 1 1 2320
2005 jan 11 9 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw i 2 c-bus read mode i 2 c-bus read mode: r/ w = logic 1 (address lsb; see table 7). when a read sequence is started, all eight bits of the status byte must be read. data can be read from the tda8260tw by setting the r/ w bit to logic 1. after recognition of its slave address, the tda8260tw generates an acknowledge pulse and transfers the status byte onto the sda line (msb first). data is valid on the sda line when the scl clock signal is high. a second data byte can be read from the tda8260tw if the microcontroller generates an acknowledge on the sda line. end of transmission will occur if no acknowledge is received from the microcontroller. the tda8260tw will then release the data line to allow the microcontroller to generate a stop condition. the por flag (power-on reset) is set to logic 1 at power-on and when v cc goes below 2.7 v. it is reset to logic 0 when an end-of-data condition is detected by the tda8260tw (end of a read sequence). the in-lock flag fl indicates that the loop is phase-locked when set to logic 1. table 7 i 2 c-bus read data format notes 1. acknowledge bit (a). 2. fl is valid only in normal mode. 3. x can be 1 or 0 and needs to be masked in the microcontrollers software; msb is transmitted first. p ower - on reset power-on reset flag por = 1 at power-on. at power-on, or when the supply voltage drops below 2.7 v, internal registers are reset as shown in table 8. table 8 status at power-on reset note 1. x = not set. byte (msb) bits (lsb) ack (1) address 1 1 0 0 0 ma1 ma0 1 a status byte por fl (2) x (3) x (3) x (3) x (3) x (3) x (3) - byte (msb) bits (1) (lsb) programmable divider (pd1) 0 n14 = x n13 = x n12 = x n11 = x n10 = x n9 = x n8 = x programmable divider (pd2) n7 = x n6 = x n5 = x n4 = x n3 = x n12 = x n1 = x n0 = x control data (cd1) 1 t2 = 0 t1 = 0 t0 = 1 r2 = x r1 = x r0 = x x control data (cd2) c1 = x c0 = x xxxxxx
2005 jan 11 10 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw limiting values in accordance with the absolute maximum rating system (iec 60134); see note 1. note 1. maximum ratings cannot be exceeded, not even momentarily, without causing irreversible damage to the ic. maximum ratings cannot be accumulated. thermal characteristics handling inputs and outputs are protected against electrostatic discharge in normal handling. however it is good practice to take normal precautions appropriate to handling mos devices (see handling mos devices ). esd specification: every pin withstands 2000 v in the esd test in accordance with jedec specification eia/jesd-a114a , hbm model (category 2); except pin v cc(rf) (pin 8). identically every pin withstands 200 v in the esd test in accordance with jedec specification eia/jesd22-a115a , mm model (category b). symbol parameter min. max. unit v cc supply voltage - 0.3 +6.0 v v i(max) ; v o(max) maximum input or output voltage on all pins except sda, scl and vt - 0.3 v cc + 0.3 v v i(sda) ; v o(sda) data input or data output voltage - 0.3 +6.0 v v i(scl) clock input voltage - 0.3 +6.0 v v o(tune) tuning voltage output - 0.3 +35 v t amb ambient temperature - 20 +85 c t stg ic storage temperature - 40 +150 c t j(max) maximum junction temperature - 150 c t sc(max) maximum short-circuit time; each pin; short-circuit to v cc or gnd - 10 s symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 39 k/w
2005 jan 11 11 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw characteristics t amb =25 c; v cc =5v; r l =1k w and v o(p-p) = 750 mv on baseband output pins ibbout and qbbout; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v cc supply voltage 4.75 5.00 5.25 v i cc supply current - 155 - ma v cc(por) supply voltage threshold for por active - 2.7 - v performance from rf inputs to i, q outputs (from pins rfa, rfb to pins ibbout, qbbout) p l(lo) lo power leakage through pins rfa and rfb -- 75 - dbm g v(rf-bbout)(max) maximum voltage gain from pins rfa, rfb to ibbout, qbbout v agc = 3 v 55 57 - db d g v agc range v agc =0to3v 48 50 - db v o(p-p) output voltage (peak-to-peak value) recommended value - 750 - mv ip2i 2nd-order interception point at rf input; v agc =0v - 19 - dbm ip3i 3rd-order interception point at rf input; v agc =0v - 14 - dbm f noise ?gure at maximum gain; v agc =3v - 18 - db d g v(iq) voltage gain mismatch between i and q in 22.5 mhz band -- 1db ? eq ? quadrature error (absolute value) v agc = 1.5 v; v o(p-p) = 750 mv; measured in baseband - 0 3 deg g v(iq)ripple voltage gain ripple for i or q in 30 mhz band -- 2db t d(g)(iq)(r) group delay ripple for i or q in 22.5 mhz band - 5 - ns rr 60 ripple rejection for i and q f ripple = 60 mhz 30 -- db pulling sensitivity 3/4lo sensitivity to pulling on the third harmonic of the external vco see table 9 -- 40 - 35 dbc 5/4lo sensitivity to pulling on the ?fth harmonic of the external vco see table 9 -- 40 - 35 dbc vco and synthesizer f osc oscillator frequency range 950 - 2175 mhz j n(osc) oscillator phase noise in the satellite band; f offset = 100 khz; out of pll loop bandwidth -- 100 - 94 dbc/hz j n phase noise on baseband outputs f offset = 1 and 10 khz; f comp = 1 mhz with appropriate loop ?lter and charge pump setting --- 78 dbc/hz
2005 jan 11 12 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw mdr main divider ratio 64 - 32767 ? z osc ? crystal oscillator negative impedance (absolute value) 1.0 1.5 - k w f xtal crystal frequency - 4 - mhz v xtout(p-p) ac output voltage on pin xtout (peak-to-peak value) t 2 = 1, t 1 = 0, t 0 =0; driving a load of c l =10pf, r l =1m w 500 650 - mv z xtal crystal series impedance recommended value -- 200 w charge pump output; pin cp i l(cp) charge pump leakage current t 2 = 1; t 1 = 1; t 0 =0 - 10 0 +10 na tuning voltage output; pin vt i lo(off) leakage current when pin vt is in high-impedance off-state t 2 = 0; t 1 = 0; t 0 =1; v tune =33v -- 10 m a v o output voltage when the loop is locked normal mode; v tune =33v 0.2 - 32.7 v bus voltage select input; pin bvs i lih high-level input leakage current v bvs =v cc -- 100 m a i lil low-level input leakage current v bvs =0v - 100 --m a scl and sda inputs v il low-level input voltage pin bvs ?oating -- 0.2v cc v v bvs =0v -- 0.15v cc v v bvs =5v -- 0.3v cc v v ih high-level input voltage pin bvs ?oating 0.46v cc -- v v bvs = 0 v 0.35v cc -- v v bvs = 5 v 0.6v cc -- v i lih high-level leakage current v ih = 5.5 v; v cc = 5.5 v -- 10 m a v ih = 5.5 v; v cc =0v -- 10 m a i lil low-level leakage current v il =0v; v cc = 5.5 v - 10 --m a f scl(max) maximum input clock frequency 400 -- khz sda output v ack output voltage during acknowledge i sink =3ma -- 0.4 v as input i ih high-level input current v as =v cc -- 10 m a i il low-level input current v as =0v - 10 --m a symbol parameter conditions min. typ. max. unit
2005 jan 11 13 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw handbook, halfpage f (mhz) g (db) 950 1350 1750 2150 1150 1550 1950 68 64 56 52 60 mgu797 fig.3 overall maximum gain as a function of frequency. handbook, halfpage v agc (v) g (db) 0123 80 60 20 0 40 mgu799 fig.4 overall gain as a function of agc voltage. handbook, halfpage f (db) mgu798 f (mhz) 950 1350 1750 2150 1150 1550 1950 20 16 18 14 12 10 fig.5 noise figure at maximum gain as a function of frequency. handbook, halfpage j n (dbc/hz) - 70 - 80 - 100 - 90 mgu796 f (mhz) 950 1350 1750 2150 1150 (1) (2) 1550 1950 - 110 fig.6 phase noise on i and q baseband outputs as a function of frequency. (1) f offset = 10 khz; f comp = 1 mhz. (2) f offset = 100 khz; f comp = 1 mhz.
2005 jan 11 14 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw handbook, halfpage 02040 f offset (mhz) v ibbout v qbbout (dbc) 60 0 - 10 - 30 - 40 - 20 mbl732 fig.7 baseband output filters. measurement method for pulling sensitivity handbook, full pagewidth mgu793 rf signal generator wanted signal rf signal generator anzac tda8260tw spectrum analyser unwanted signal fig.8 test set-up.
2005 jan 11 15 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw table 9 test signal conditions for pulling measurements the level of the wanted and unwanted signals given in table 9 are measured at the outputs of the rf signal generators. the sensitivity to pulling is measured in baseband by the difference expressed in db ( d ) between the level of the wanted signal and the spurious signal that has been generated by pulling. the anzac reference is hh128. test signal frequency level content (see fig.9) 3/4lo test wanted f w = 2161 mhz - 10 dbm f w =f lo + 11 mhz unwanted f uw = 1613 mhz - 2 dbm f uw =f lo 3 / 4 + 500 khz local oscillator f lo = 2150 mhz -- 5/4lo test wanted f w = 1761 mhz - 10 dbm f w =f lo + 11 mhz unwanted f uw = 2188 mhz - 2 dbm f uw =f lo 5 / 4 + 500 khz local oscillator f lo = 1750 mhz -- handbook, halfpage mgu794 11 wanted signal 11.5 spurious signal f (mhz) d v signal fig.9 baseband spectrum.
2005 jan 11 16 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw application information handbook, full pagewidth rf in xt1 xt2 v cc(pll) pllgnd agcin biasn rfgnd1 v cc(rf) rfa rfb rfgnd2 lp1 lp2 qout bbgnd1 qbbin v cc(bb) qbbout qin mgu795 33 w r4 4.7 k w r2 1.5 k w r3 c13 100 nf c14 100 nf 4.7 k w r5 4.7 k w r1 22 k w r10 c12 220 nf c38 39 pf c2 39 pf 4 mhz c15 220 nf c3 330 pf l1 18 nh d1 bb178 c11 100 nf c10 2.2 pf c3 2.2 pf c1 12 nf c2 330 pf c21 82 pf c22 82 pf c31 220 nf c16 220 nf tda8260tw 1 4 mhz x1 2 3 + 5 v v agc + 5 v + 5 v + 5 v + 30 v + 5 v 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 heatsink xtout sda scl as cp vt bvs v cc(vco) tka tkb vcognd cap1 cap2 iout bbgnd2 ibbin n.c. ibbout iin fig.10 typical application circuit.
2005 jan 11 17 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw h andbook, full pagewidth mgu792 i 2 c-bus i 2 c-bus 5 ibbout 4 mhz 4 mhz clock mpeg2 ts 21 9 12 14 30 agcin pwm lna rfa 18 i tda8260tw tda10086 input matching qbbout q fig.11 tuner configuration of the tda8260tw. application design the performance of the application using the tda8260tw strongly depends on the application design itself. furthermore the printed-circuit board design and the soldering conditions should take into account the exposed die pad underneath the device, as this requires an optimum electrical ground path for electrical performance, together with the capability to dissipate into the application the heat created in the device. philips semiconductors can provide support through reference designs and application notes for tda8260tw together with associated channel decoders. please contact your local philips semiconductors sales office for more information. wave soldering is not suitable for the tda8260tw package. this is because the heatsink needs to be soldered to the printed-circuit board underneath the package but with wave soldering the solder cannot penetrate between the printed-circuit board and the heatsink.
2005 jan 11 18 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw package outline unit a 1 a 2 a 3 b p ce (2) d (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 8 0 o o 0.1 dimensions (mm are the original dimensions). notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. sot633-3 04-01-22 w m q a a 1 a 2 e h d h d l p detail x e z exposed die pad side e c l x (a 3 ) 0.25 1 19 38 20 y b p h e 1.05 0.80 0.30 0.19 d h 3.65 3.45 e h 2.85 2.65 0.20 0.09 12.6 12.4 6.2 6.0 8.3 7.9 0.65 1 0.2 0.6 0.2 0.1 0.75 0.45 v m a a htssop38: plastic thermal enhanced thin shrink small outline package; 38 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad sot633-3 a max. 1.2 0 2.5 5 mm scale - - - - - - - - - pin 1 index
2005 jan 11 19 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 c to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c.
2005 jan 11 20 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the reflow oven. the package body peak temperature must be kept as low as possible. 4. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 6. wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on flex foil. however, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. the appropriate soldering profile can be provided on request. 9. hot bar soldering or manual soldering is suitable for pmfp packages. package (1) soldering method wave reflow (2) bga, htsson..t (3) , lbga, lfbga, sqfp, ssop..t (3) , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable (4) suitable plcc (5) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (5)(6) suitable ssop, tssop, vso, vssop not recommended (7) suitable cwqccn..l (8) , pmfp (9) , wqccn..l (8) not suitable not suitable
2005 jan 11 21 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2005 jan 11 22 philips semiconductors product speci?cation satellite zero-if qpsk/8psk downconverter with pll synthesizer tda8260tw purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2005 sca77 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r25/03/pp 23 date of release: 2005 jan 11 document order number: 9397 750 14556

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