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opa2631 features high bandwidth: 75mhz (g = +2) low supply current: 6ma/chan +3v to +10v supply operation input range includes ground 4.8v output swing on +5v supply high slew rate: 100v/ s low input voltage noise: 6nv/ hz dual, low-power, single-supply operational amplifier applications differential receivers/drivers active filters matched i and q channel amplifiers ccd imaging channels low power ultrasound portable consumer electronics tm description the opa2631 is a dual, low-power, voltage-feedback amplifier designed to operate on a single +3v or +5v supply. operation on 5v or +10v supplies is also supported. the input range extends below ground and to within 1v of the positive supply. using comple- mentary common-emitter outputs provides an output swing to within 30mv of ground and 130mv of the positive supply. the high output drive current and low differential gain and phase errors also make it ideal for single-supply consumer video products. low-distortion operation is ensured by the high gain bandwidth product (68mhz) and slew rate (100v/ s), making the opa2631 an ideal input buffer stage to 3v and 5v cmos converters. unlike other low-power, single-supply amplifiers, distortion performance im- proves as the signal swing is decreased. a low 6nv/ hz input voltage noise supports wide dynamic- range operation. the opa2631 is available in an industry standard so-8 package. where a single-channel, single-supply operational amplifier is required, consider the opa631 and opa632. where higher full-power bandwidth and lower distortion are required, consider the opa2634. description singles duals medium speed, no disable opa631 opa2631 with disable opa632 high speed, no disable opa634 opa2634 with disable opa635 related products opa2631 spice model available at www.ti.com 1/2 opa2631 v in 750 ? 562 ? 2.26k ? 374 ? 22pf +3v 100 ? +3v ads901 10-bit 20msps copyright ?1999, texas instruments incorporated sbos067a printed in u.s.a. february, 2001 www.ti.com
opa2631 2 sbos067a opa2631u typ guaranteed 0 c to C40 c to min/ test parameter conditions +25 c +25 c70 c +85 c units max level (1) specifications: v s = +5v at t a = 25 c, g = +2, r f = 750 ? , and r l = 150 ? to v s /2, unless otherwise noted. ac performance (figure 1) small-signal bandwidth g = +2, v o 0.5vp-p 75 50 40 32 mhz min b g = +5, v o 0.5vp-p 16 12 10 8.5 mhz min b g = +10, v o 0.5vp-p 7.6 5.6 4.2 3.7 mhz min b gain bandwidth product g +10 68 51 40 36 mhz min b peaking at a gain of +1 v o 0.5vp-p 5 db typ c slew rate g = +2, 2v step 100 64 52 47 v/ s min b rise time 0.5v step 5.3 8.0 11 12.8 ns max b fall time 0.5v step 5.4 7.5 10 11.6 ns max b settling time to 0.1% g = +2, 1v step 17 28 38 42 ns max b spurious free dynamic range v o = 2vp-p, f = 5mhz 44 40 38 35 db min b v o = 2vp-p, f = 1mhz, r l = 1k ? 84 68 66 62 db min b input voltage noise f > 1mhz 6.0 6.8 7.6 7.9 nv/ hz max b input current noise f > 1mhz 1.9 2.6 2.9 3.6 pa/ hz max b ntsc differential gain 0.5 % typ c ntsc differential phase 1.2 degrees typ c channel-to-channel isolation input referred, f = 5mhz 93 db typ c dc performance open-loop voltage gain 62 56 50 46 db min a input offset voltage 2.5 6 8 11 mv max a average offset voltage drift 50 v/ c max b input bias current v cm = 2.0v 11 25 31 48 a max a input offset current v cm = 2.0v 0.3 1.5 1.8 2.8 a max a input offset current drift 7 na/ c max b input least positive input voltage C 0.5 C 0.1 C 0.1 C 0.1 v max b most positive input voltage 4.0 3.7 3.7 3.5 v min a common-mode rejection ratio (cmrr) input referred 74 70 68 60 db min a input impedance differential-mode 10 || 2.1 k ? || pf typ c common-mode 400 || 1.2 k ? || pf typ c output least positive output voltage r l = 1k ? to 2.5v 0.03 0.07 0.10 0.13 v max a r l = 150 ? to 2.5v 0.16 0.17 0.20 1.7 v max a most positive output voltage r l = 1k ? to 2.5v 4.87 4.8 4.7 4.6 v min a r l = 150 ? to 2.5v 4.60 4.4 4.4 3.1 v min a current output, sourcing 80 25 20 5 ma min a current output, sinking 90 31 19 8 ma min a short-circuit current (output shorted to either supply) 100 ma typ c closed-loop output impedance figure 1, f 50khz 0.6 ? typ c power supply minimum operating voltage 2.7 2.7 2.7 v min b maximum operating voltage 10.5 10.5 10.5 v max a maximum quiescent current v s = +5v 6 6.6 6.9 7.1 ma/chan max a minimum quiescent current v s = +5v 6 5.8 5.5 4.8 ma/chan min a power supply rejection ratio (psrr) input referred 59 52 49 48 db min a thermal characteristics specification: u C 40 to +85 c typ c thermal resistance u so-8 125 c/w typ c note: (1) test levels: (a) 100% tested at 25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information.
opa2631 3 sbos067a specifications: v s = +3v at t a = 25 c, g = +2, r f = 750 ? , and r l = 150 ? to v s /2, unless otherwise noted. opa2631u typ guaranteed 0 c to min/ test parameter conditions +25 c +25 c70 c units max level (1) ac performance (figure 2) small-signal bandwidth g = +2, v o 0.5vp-p 61 45 35 mhz min b g = +5, v o 0.5vp-p 15 11 9 mhz min b g = +10, v o 0.5vp-p 7.7 4.6 4.0 mhz min b gain bandwidth product g +10 63 47 34 mhz min b peaking at a gain of +1 v o 0.5vp-p 5 db typ c slew rate 1v step 95 52 46 v/ s min b rise time 0.5v step 5.6 9 11.3 ns max b fall time 0.5v step 5.6 9 11.3 ns max b settling time to 0.1% 1v step 40 63 85 ns max b spurious free dynamic range v o = 1vp-p, f = 5mhz 44 37 34 db min b v o = 1vp-p, f = 1mhz, r l = 1k ? 846765 db min b input voltage noise f > 1mhz 6.2 7.0 7.8 nv/ hz max b input current noise f > 1mhz 2.0 2.6 2.9 pa/ hz max b channel-to-channel isolation input reference, f = 5mhz 93 db typ c dc performance open-loop voltage gain 60 54 50 db min a input offset voltage 0.5 4.0 4.5 mv max a average offset voltage drift 45 v/ c max b input bias current v cm = 1.0v 12 25 30 a max a input offset current v cm = 1.0v 0.3 1 1.3 a max a input offset current drift 2 na/ c max b input least positive input voltage C 0.5 C 0.3 C 0.1 v max b most positive input voltage 2 1.75 1.3 v min a common-mode rejection ratio (cmrr) input referred 72 66 65 db min a input impedance differential-mode 10 || 2.1 k ? || pf typ c common-mode 400 || 1.2 k ? || pf typ c output least positive output voltage r l = 1k ? to 1.5v 0.03 0.05 0.05 v max a r l = 150 ? to 1.5v 0.05 0.15 0.16 v max a most positive output voltage r l = 1k ? to 1.5v 2.95 2.85 2.84 v min a r l = 150 ? to 1.5v 2.85 2.66 2.60 v min a current output, sourcing 55 21 14 ma min a current output, sinking 55 18 11 ma min a short circuit current (output shorted to either supply) 80 ma typ c closed-loop output impedance figure 2, f < 50khz 0.6 ? typ c power supply minimum operating voltage 2.7 2.7 v min b maximum operating voltage 10.5 10.5 v max a maximum quiescent current v s = +3v 5.3 5.9 6.4 ma/chan max a minimum quiescent current v s = +3v 5.3 5.0 4.8 ma/chan min a power supply rejection ratio (psrr) input referred 57 50 48 db min a thermal characteristics specification: u C 40 to +85 c typ c thermal resistance u so-8 125 c/w typ c note: (1) test levels: (a) 100% tested at 25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information.
opa2631 4 sbos067a pin configurations top view so 1 2 3 4 8 7 6 5 +v s out b C in b +in b out a C in a +in a gnd opa2631 absolute maximum ratings power supply ................................................................................ +11v dc internal power dissipation .................................... see thermal analysis differential input voltage .................................................................. 1.2v input voltage range .................................................... C 0.5 to +v s +0.3v storage temperature range ......................................... C 40 c to +125 c lead temperature (soldering, 10s) .............................................. +300 c junction temperature (t j ) ........................................................... +175 c electrostatic discharge sensitivity electrostatic discharge can cause damage ranging from perfor- mance degradation to complete device failure. burr-brown corpo- ration recommends that all integrated circuits be handled and stored using appropriate esd protection methods. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. package specified drawing temperature package ordering transport product package number range marking number (1) media opa2631u so-8 surface-mount 182 C 40 c to +85 c opa2631 opa2631u rails """"" opa2631u/2k5 tape and reel note: (1) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2k5 indicates 2500 de vices per reel). ordering 2500 pieces of opa2631u/2k5 will get a single 2500-piece tape and reel. package/ordering information
opa2631 5 sbos067a typical performance curves: v s = +5v at t a = 25 c, g = +2, r f = 750 ? , and r l = 150 ? to v s /2, unless otherwise noted (see figure 2). 6 3 0 C 3 C 6 C 9 C 12 C 15 C 18 C 21 C 24 small-signal frequency response frequency (mhz) normalized gain (db) 1 10 100 300 v o = 200mvp-p g = +10 g = +5 g = +2 12 9 6 3 0 C 3 C 6 C 9 C 12 C 15 C 18 large-signal frequency response frequency (mhz) gain (db) 1 10 100 300 v o = 0.2vp-p v o = 4vp-p v o = 2vp-p v o = 1vp-p small-signal pulse response time (10ns/div) input and output voltage (50mv/div) v o = 200mvp-p v o v in 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 output swing vs load resistance r l ( ? ) 50 100 1000 maximum output voltage (v) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 minimum output voltage (v) maximum v o minimum v o right scale left scale large-signal pulse response time (10ns/div) input and output voltage (500mv/div) v o = 4vp-p v o v in C 40 C 50 C 60 C 70 C 80 C 90 C 100 channel-to-channel crosstalk frequency (mhz) 1 10 100 input-refered isolation (db)
opa2631 6 sbos067a typical performance curves: v s = +5v (cont.) at t a = 25 c, g = +2, r f = 750 ? , and r l = 150 ? to v s /2, unless otherwise noted (see figure 1). C 30 C 40 C 50 C 60 C 70 C 80 harmonic distortion vs output voltage output voltage (vp-p) 0.1 1 f = 5mhz 4 harmonic distortion (dbc) 3rd harmonic 2nd harmonic C 30 C 40 C 50 C 60 C 70 C 80 harmonic distortion vs inverting gain gain magnitude (v/v) 110 harmonic distortion (dbc) v o = 2vp-p f = 5mhz 3rd harmonic 2nd harmonic C 30 C 40 C 50 C 60 C 70 C 80 harmonic distortion vs frequency frequency (mhz) 1 0.1 10 harmonic distortion (dbc) v o = 2vp-p 3rd harmonic 2nd harmonic C 30 C 40 C 50 C 60 C 70 C 80 harmonic distortion vs load resistance r l ( ? ) 100 1000 harmonic distortion (dbc) v o = 2vp-p f o = 5mhz 3rd harmonic 2nd harmonic C 30 C 40 C 50 C 60 C 70 C 80 harmonic distortion vs supply voltage single-supply voltage (v) 389 7 6 5 410 harmonic distortion (dbc) v o = 2vp-p f o = 5mhz 3rd harmonic 2nd harmonic C 30 C 40 C 50 C 60 C 70 C 80 harmonic distortion vs non-inverting gain gain magnitude (v/v) 110 harmonic distortion (dbc) v o = 2vp-p f = 5mhz 3rd harmonic 2nd harmonic
opa2631 7 sbos067a typical xperformance curves: v s =+5v (cont.) at t a = 25 c, g = +2, r f = 750 ? , and r l = 150 ? to v s /2, unless otherwise noted (see figure 1). 100 10 1 input noise density vs frequency frequency (hz) 100 1k 10k 100k 1m 10m voltage noise (nv/ hz) current noise (pa/ hz) voltage noise, e ni = 6.0nv/ hz current noise, i ni = 1.9pa/ hz 2 1 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 frequency response vs capacitive load frequency (mhz) 1 10 100 300 normalized gain (db) r s 1/2 opa2631 v o 1k ? c l +v s /2 c l = 100pf r s = 35.7 ? c l =1000pf r s = 10 ? c l = 10pf r s = 249 ? C 30 C 40 C 50 C 60 C 70 C 80 C 90 two-tone, 3rd-order intermodulation spurious single-tone load power (dbm) C 16 C 14 C 12 C 10 C 8 C 6 C 4 C 20 3rd-order spurious level (dbc) load power at matched 50 ? load f o = 1mhz f o = 5mhz f o = 10mhz 80 75 70 65 60 55 50 45 40 35 30 cmrr and psrr vs frequency frequency (hz) 100 1k 10k 100k 1m 10m rejection ratio, input referred (db) cmrr psrr 100 90 80 70 60 50 40 30 20 10 0 C 10 C 20 open-loop gain and phase frequency (hz) 1k 10k 100k 1m 10m 100m 1g open-loop gain (db) 0 C 30 C 60 C 90 C 120 C 150 C 180 C 210 C 240 C 270 C 300 C 330 C 360 open-loop phase ( ) open-loop phase open-loop gain 1000 100 10 1 recommended r s vs capacitive load capacitive load (pf) 1 10 100 1000 r s ( ? )
opa2631 8 sbos067a typical performance curves: v s = +5v (cont.) at t a = 25 c, g = +2, r f = 750 ? , and r l = 150 ? to v s /2, unless otherwise noted (see figure 1). 100 10 1 0.1 closed-loop output impedance vs frequency frequency (hz) 1k 10k 100k 1m 10m 100m output impedance ( ? ) g = +1 r f = 25 ? 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 input dc errors vs temperature temperature ( c) C 40 C 20 0 20 40 60 80 100 input offset voltage (mv) 20 18 16 14 12 10 8 6 4 2 0 input bias current ( a) 10x input offset current ( a) input offset voltage input bias current 10x input offset current 12 10 8 6 4 2 0 power supply and output current vs temperature temperature ( c) C 40 C 20 0 20 40 60 80 100 quiescent supply current (ma) 120 100 80 60 40 20 0 output current (ma) sourcing output current sinking output current quiescent supply current
opa2631 9 sbos067a 6 3 0 C 3 C 6 C 9 C 12 C 15 C 18 C 21 C 24 small-signal frequency response frequency (mhz) normalized gain (db) 1 10 100 300 v o = 200mvp-p g = +10 g = +2 g = +5 12 9 6 3 0 C 3 C 6 C 9 C 12 C 15 C 18 large-signal frequency response frequency (mhz) gain (db) 1 10 100 300 v o = 2vp-p v o = 200mvp-p v o = 1vp-p typical performance curves: v s = +3v at t a = 25 c, g = +2, r f = 750 ? , and r l = 150 ? to v s /2, unless otherwise noted (see figure 1). C 30 C 40 C 50 C 60 C 70 C 80 C 90 two-tone, 3rd-order intermodulation spurious single-tone load power (dbm) C 16 C 14 C 12 C 10 C 8 C 6 C 4 3rd-order spurious level (dbc) load power at matched 50 ? load f o = 10mhz f o = 1mhz f o = 5mhz 6 3 0 C 3 C 6 C 9 C 12 C 15 C 18 C 21 C 24 frequency response vs capacitive load frequency (mhz) 1 10 100 300 normalized gain (db) v o = 0.2vp-p r s 1/2 opa2631 v o 1k ? c l +v s /2 c l = 100pf r s = 35.7 ? c l = 1000pf r s = 10 ? c l = 10pf r s = 249 ? 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 output swing vs load resistance r l ( ? ) 50 100 1000 maximum output voltage (v) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 minimum output voltage (v) maximum v o minimum v o right scale left scale 1000 100 10 1 recommended r s vs capacitive load capacitive load (pf) 1 10 100 1000 r s ( ? )
opa2631 10 sbos067a typical performance curves: v s = +3v (cont.) at t a = 25 c, g = +2, r f = 750 ? , and r l = 150 ? to v s /2, unless otherwise noted (see figure 2). 120 100 80 60 40 20 0 slew rate and gain bandwidth product vs supply voltage supply voltage (v) 345678910 slew rate (v/ s) 120 100 80 60 40 20 0 gain bandwidth product (mhz) slew rate gain bandwidth product 10 9 8 7 6 5 4 3 2 1 0 supply and output currents vs supply voltage supply voltage (v) 345678910 quiescent supply current (ma/chan) 200 180 160 140 120 100 80 60 40 20 0 output current (ma) quiescent supply current output current, sourcing output current, sinking
opa2631 11 sbos067a applications information wideband voltage-feedback operation the opa2631 is a unity-gain stable, very high-speed, volt- age-feedback op amp designed for single-supply operation (+3v to +10v). the input stage supports input voltages below ground, and to within 1.0v of the positive supply. the complementary common-emitter output stage provides an output swing to within 30mv of ground and 130mv of the positive supply. it is compensated to provide stable opera- tion with a wide range of resistive loads. figure 1 shows the ac-coupled, gain of +2 configuration used for the +5v specifications and typical performance curves. for test purposes, the input impedance is set to 50 ? with a resistor to ground. voltage swings reported in the specifications are taken directly at the input and output pins. for the circuit of figure 1, the total effective load on the output at high frequencies is 150 ? || 1500 ? . the 1.50k ? resistors at the non-inverting input provide the common- mode bias voltage. their parallel combination equals the dc resistance at the inverting input, minimizing the output dc offset. 1/2 opa2631 +v s = 5v v out 53.6 ? v in r f 750 ? r g 750 ? 1.50k ? 1.50k ? r l 150 ? +v s 2 6.8 f + 0.1 f 0.1 f 0.1 f figure 1. ac-coupled signal?esistive load to supply midpoint. figure 2. dc-coupled signal?esistive load to supply midpoint. 1/2 opa2631 +v s = 3v v out 57.6 ? v in 374 ? 2.26k ? r l 150 ? +v s 2 6.8 f + 0.1 f r f 750 ? r g 562 ? figure 2 shows the dc-coupled, gain of +2 configuration used for the +3v specifications and typical performance curves. for test purposes, the input impedance is set to 50 ? with a resistor to ground. though not strictly a ?ail-to-rail design, this part comes very close, while maintaining excel- lent performance. it will deliver 2.9vp-p on a single +3v supply with 61mhz bandwidth. the 374 ? and 2.26k ? resistors at the input level-shift v in so that v out is within the allowed output voltage range when v in = 0. see the typical performance curves for information on driving ca- pacitive loads. single-supply adc converter interface the front page shows a dc-coupled, single-supply, dual adc (analog-to-digital converter) driver circuit. many systems are now requiring +3v supply capability of both the adc and its driver. the opa2631 provides excellent per- formance in this demanding application. its large input and output voltage ranges, and low distortion support converters such as the ads901 shown in this figure. the input level- shifting circuitry was designed so that v in can be between 0v and 0.5v, while delivering an output voltage of 1v to 2v for the ads901.
opa2631 12 sbos067a bandpass filter figure 3 shows a single opa2631 implementing a 6th-order bandpass filter. this filter cascades two 2nd-order sallen- key sections with transmission zeros, and a double real pole section. it has ?db frequencies of 630khz and 1.5mhz, and ?0db frequencies of 230khz and 4.2mhz. this filter was designed to work well on +5v or 5v supplies, while driving an a/d converter at 6msps to 10msps (e.g., the ads804). the filter transfer function is based on a 4th-order elliptic bandpass filter, with real highpass and lowpass poles added at the output to give a 6th-order response. the components were chosen to give this transfer function. the 20 ? resistor isolates the first opa2631 output from capacitive loading, but affects the response at very high frequencies only. figure 4 shows the nominal response simulated by spice . dc level shifting figure 5 shows a dc-coupled non-inverting amplifier that level-shifts the input up to accommodate the desired output voltage range. given the desired signal gain (g) and the amount v out needs to be shifted up ( ? v out ), when v in is at the center of its range, the following equations give the resistor values that produce the desired performance. start by setting r 4 between 200 ? and 1.5k ? . ng = g + ? v out /v s r 1 = r 4 /g r 2 = r 4 /(ng ?g) r 3 = r 4 /(ng ?) where: ng = 1 + r 4 /r 3 (noise gain) v out = (g)v in + (ng ?g)v s 10 0 C 10 C 20 C 30 C 40 C 50 C 60 frequency (hz) gain (db) 10k 1m 10m 100k 100m 1/2 opa2631 +v s v out v in r 3 r 2 r 1 r 4 figure 3. bandpass filter. figure 4. nominal filter response. figure 5. dc level shifting circuit. 1/2 opa2631 86.6 ? v in 60.4 ? 7.32k ? 200 ? 2.2nf 1% resistors 5% capacitors 27pf 3.9nf 3.9nf 1.2nf 130 ? 59 ? 1/2 opa2631 46.4 ? 20 ? 133 ? 73.2 ? v out 1.2nf 200 ? 1.8nf 1.2nf 681 ? 330pf
opa2631 13 sbos067a make sure that v in and v out stay within the specified input and output voltage ranges. the front page circuit is a good example of this type of application. it was designed to take v in between 0v and 0.5v, and produce v out between 1v and 2v, when using a +3v supply. this means g = 2.00, and ? v out = 1.50v ?g ?0.25v = 1.00v. plugging into the above equations (with r 4 = 750 ? ) gives: ng = 2.33, r 1 = 375 ? , r 2 = 2.25k ? , and r 3 = 563 ? . the resistors were adjusted to the nearest standard values. non-inverting amplifier with reduced peaking figure 6 shows a non-inverting amplifier that reduces peak- ing at low gains. the resistor r c compensates the opa2631 to have higher noise gain (ng), which reduces the ac response peaking (typically 5db at g = +1 without r c ) without changing the dc gain. v in needs to be a low impedance source, such as an op amp. the resistor values are low to reduce noise. using both r t and r f helps minimize the impact of parasitic impedances. design-in tools demonstration boards a single pc board is available to assist in the initial evalu- ation of circuit performance using the opa2631u. it is available free as an unpopulated pc board delivered with descriptive documentation. the summary information for this board is shown in table i. figure 6. compensated non-inverting amplifier. board literature part request product package number number opa2631u so-8 dem-opa268xu mkt-352 table i. demo board summary information. the noise gain can be calculated as follows: g r r g rrg r ng g g f g tf c 1 2 1 12 1 1 =+ =+ + = / a unity gain buffer can be designed by selecting r t = r f = 20.0 ? and r c = 40.2 ? (do not use r g ). this gives a noise gain of 2, so its response will be similar to the typical performance curves with g = +2 which typically gives a flat frequency response, but with less bandwidth. 1/2 opa2631 v out v in r g r t r f r c contact the texas instruments technical applications sup- port line at 1-972-644-5580 to request this board. operating suggestions optimizing resistor values since the opa2631 is a voltage-feedback op amp, a wide range of resistor values may be used for the feedback and gain setting resistors. the primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. for a non-inverting unity gain follower application, the feedback connection should be made with a 20 ? resistor, not a direct short (see figure 6). this will isolate the inverting input capacitance from the output pin and improve the frequency response flatness. usually, for g > 1 application, the feedback resistor value should be between 200 ? and 1.5k ? . below 200 ? , the feedback network will present additional output loading which can degrade the harmonic-distortion performance. above 1.5k ? , the typical parasitic capacitance (approxi- mately 0.2pf) across the feedback resistor may cause unin- tentional band-limiting in the amplifier response. a good rule of thumb is to target the parallel combination of r f and r g (figure 1) to be less than approximately 400 ? . the combined impedance (r f || r g ) interacts with the invert- ing input capacitance, placing an additional pole in the feedback network and thus, a zero in the forward response. assuming a 3pf total parasitic on the inverting node, hold- ing r f || r g < 400 ? will keep this pole above 130mhz. by itself, this constraint implies that the feedback resistor r f can increase to several k ? at high gains. this is acceptable as long as the pole formed by r f , and any parasitic capaci- tance appearing in parallel, is kept out of the frequency range of interest.
opa2631 14 sbos067a bandwidth versus gain: non-inverting operation voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. in theory, this relationship is described by the gain bandwidth product (gbp) shown in the specifications table. ideally, dividing gbp by the non-inverting signal gain (also called the noise gain, or ng) will predict the closed-loop bandwidth. in practice, this only holds true when the phase margin ap- proaches 90 , as it does in high-gain configurations. at low gains (increased feedback factors), most amplifiers will exhibit a more complex response with lower phase margin. the opa2631 is compensated to give a slightly peaked response in a non-inverting gain of 2 (figure 1). this results in a typical gain of +2 bandwidth of 75mhz, far exceeding that predicted by dividing the 68mhz gbp by 2. increasing the gain will cause the phase margin to approach 90 and the bandwidth to more closely approach the predicted value of (gbp/ng). at a gain of +10, the 7.6mhz bandwidth shown in the specifications table is close to that predicted using the simple formula and the typical gbp. the opa2631 exhibits minimal bandwidth reduction going to +3v single-supply operation as compared with +5v supply. this is because the internal bias control circuitry retains nearly constant quiescent current as the total supply voltage between the supply pins is changed. inverting amplifier operation since the opa2631 is a general-purpose, wideband voltage- feedback op amp, all of the familiar op amp application circuits are available to the designer. figure 7 shows a typical inverting configuration where the i/o impedances and signal gain from figure 1 are retained in an inverting circuit configu- ration. inverting operation is one of the more common requirements and offers several performance benefits. the inverting configuration shows improved slew rate and distor- tion. it also biases the input at v s /2 for the best headroom. the output voltage can be independently moved with bias adjust- ment resistors connected to the inverting input. in the inverting configuration, three key design consider- ation must be noted. the first is that the gain resistor (r g ) becomes part of the signal channel input impedance. if input impedance matching is desired (which is beneficial when- ever the signal is coupled through a cable, twisted pair, long pc board trace, or other transmission line conductor), r g may be set equal to the required termination value, and r f adjusted to give the desired gain. this is the simplest approach and results in optimum bandwidth and noise per- formance. however, at low inverting gains, the resultant feedback resistor value can present a significant load to the amplifier output. for an inverting gain of 2, setting r g to 50 ? for input matching eliminates the need for r m but requires a 100 ? feedback resistor. this has the interesting advantage of the noise gain becoming equal to 2 for a 50 ? source impedance?he same as the non-inverting circuits considered above. however, the amplifier output will now see the 100 ? feedback resistor in parallel with the external load. in general, the feedback resistor should be limited to the 200 ? to 1.5k ? range. in this case, it is preferable to increase both the r f and r g values, as shown in figure 7, and then achieve the input matching impedance with a third resistor (r m ) to ground. the total input impedance becomes the parallel combination of r g and r m . the second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and hence influences the bandwidth. for the example in figure 7, the r m value combines in parallel with the external 50 ? source imped- ance, yielding an effective driving impedance of 50 ? || 576 ? = 26.8 ? . this impedance is added in series with r g for calculating the noise gain. the resultant is 2.87 for figure 7, as opposed to only 2 if r m could be eliminated as discussed above. the bandwidth will therefore be lower for the gain of ? circuit of figure 7 (ng = +2.87) than for the gain of +2 circuit of figure 1. the third important consideration in inverting amplifier design is setting the bias current cancellation resistors on the non-inverting input (a parallel combination of r t = 750 ? ). if this resistor is set equal to the total dc resistance looking out of the inverting node, the output dc error, due to the input bias currents, will be reduced to (input offset current) ?r f . the inverting input's bias current flows through r f because of the 0.1 f capacitor. thus, we need r t = 750 ? = 1.50k ? || 1.50k ?. to reduce the additional high-frequency noise introduced by this r t resistor, and power-supply feedthrough, it is bypassed with a capacitor. if we had r t < 400 ? , its noise contribu- tion would be minimal. as a minimum, the opa2631 requires an r t value of 50 ? to damp out parasitic-induced peaking? direct short to ground on the non-inverting input runs the risk of a very high-frequency instability in the input stage. figure 7. gain of ? example circuit. 0.1 f 1/2 opa2631 50 ? r f 750 ? r g 374 ? 2r t 1.50k ? r m 57.6 ? source +5v 2r t 1.50k ? r o 50 ? 0.1 f 6.8 f + 0.1 f 50 ? load
opa2631 15 sbos067a (1) e o = e ni 2 + i bn r s () 2 +4 ktr s () ng 2 + i bi r f () 2 +4 ktr f ng dividing this expression by the noise gain (ng = (1 + r f /r g )) will give the equivalent input-referred spot noise voltage at the non-inverting input, as shown in equation 2. (2) e n = e ni 2 + i bn r s () 2 +4 ktr s + i bi r f ng ? ? ? ? 2 + 4 ktr f ng output current and voltage the opa2631 provides outstanding output voltage capabil- ity. under no-load conditions at +25 c, the output voltage typically swings closer than 130mv to either supply rail; the guaranteed over temperature swing is within 400mv of either rail (v s = +5v). the minimum specified output voltage and current specifi- cations over temperature are set by worst-case simulations at the cold temperature extreme. only at cold start-up will the output current and voltage decrease to the numbers shown in the guaranteed tables. as the output transistors deliver power, their junction temperatures will increase, decreasing their v be ? (increasing the available output voltage swing) and increasing their current gains (increasing the available out- put current). in steady-state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications, since the output stage junction temperatures will be higher than the minimum specified operating ambient. to maintain maximum output stage linearity, no output short-circuit protection is provided. this will not normally be a problem, since most applications include a series matching resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground. driving capacitive loads one of the most demanding and yet very common load conditions for an op amp is capacitive loading. often, the capacitive load is the input of an adc?ncluding additional external capacitance which may be recommended to im- prove adc linearity. a high-speed, high open-loop gain amplifier like the opa2631 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. when the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. the typical performance curves show the recommended r s versus capacitive load and the resulting frequency re- sponse at the load. parasitic capacitive loads greater than 2pf can begin to degrade the performance of the opa2631. long pc board traces, unmatched cables, and connections to multiple devices can easily exceed this value. always con- sider this effect carefully, and add the recommended series resistor as close as possible to the output pin (see board layout guidelines section). the criterion for setting this r s resistor is a maximum bandwidth, flat frequency response at the load. for a gain of +2, the frequency response at the output pin is already slightly peaked without the capacitive load, requiring rela- tively high values of r s to flatten the response at the load. increasing the noise gain will also reduce the peaking (see figure 6). distortion performance the opa2631 provides good distortion performance into a 150 ? load. relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +3v supply. generally, the 3rd harmonic will dominate the distortion. focusing then on the 3rd harmonic, increasing the load impedance improves distortion directly. remember that the total load includes the feedback network; in the non-inverting configuration (figure 1) this is sum of r f + r g , while in the inverting configuration, only r f needs to be included in parallel with the actual load. noise performance high slew rate, unity gain stable, voltage-feedback op amps usually achieve their slew rate at the expense of a higher input noise voltage. the 6.0nv/ hz input voltage noise for the opa2631 is, however, much lower than comparable amplifiers. the input-referred voltage noise, and the two input-referred current noise terms (1.9pa/ hz), combine to give low output noise under a wide variety of operating conditions. figure 8 shows the op amp noise analysis model with all the noise terms included. in this model, all noise terms are taken to be noise voltage or current density terms in either nv/ hz or pa/ hz. the total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. equation 1 shows the general form for the output noise voltage using the terms shown in figure 8. figure 8. noise analysis model. 4kt r g r g r f r s 1/2 opa2631 i bi e o i bn 4kt = 1.6 ? 10 C 20 j at 290 k e rs e ni 4ktr s 4ktr f
opa2631 16 sbos067a evaluating these two equations for the circuit and compo- nent values shown in figure 1 will give a total output spot noise voltage of 13.1nv/ hz and a total equivalent input spot noise voltage of 6.6nv/ hz. this is including the noise added by the resistors. this total input-referred spot noise voltage is not much higher than the 6.0nv/ hz specification for the op amp voltage noise alone. this will be the case as long as the impedances appearing at each op amp input are limited to the previously recommend maximum value of 400 ? , and the input attenuation is low. dc accuracy and offset control the balanced input stage of a wideband voltage-feedback op amp allows good output dc accuracy in a wide variety of applications. the power-supply current trim for the opa2631 gives even tighter control than comparable products. al- though the high-speed input stage does require relatively high input bias current (typically 11 a out of each input terminal), the close matching between them may be used to reduce the output dc error caused by this current. this is done by matching the dc source resistances appearing at the two inputs. evaluating the configuration of figure 1 (which has matched dc input resistances), using worst-case +25 c input offset voltage and current specifications, gives a worst- case output offset voltage equal to: (ng = non-inverting signal gain at dc) (ng ?v os(max) ) (r f ?i os(max) ) = (1 ?6.0mv) (750 ? ?1.5 a) = 7.1mv [output offset range for figure 1] a fine scale output offset null, or dc operating point adjustment, is often required. numerous techniques are available for introducing dc offset control into an op amp circuit. most of these techniques are based on adding a dc current through the feedback resistor. in selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. if the signal path is intended to be non-inverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. if the signal path is intended to be inverting, applying the offset control to the non-inverting input may be considered. bring the dc offsetting current into the inverting input node through resistor values that are much larger than the signal path resistors. this will insure that the adjustment circuit has minimal effect on the loop gain and hence the frequency response. thermal analysis maximum desired junction temperature will set the maxi- mum allowed internal power dissipation as described below. in no case should the maximum junction temperature be allowed to exceed 175 c. operating junction temperature (t j ) is given by t a + p d ja . the total internal power dissipation (p d ) is the sum of quiescent power (p dq ) and additional power dissipated in the output stage (p dl ) to deliver load power. quiescent power is simply the specified no-load supply current times the total supply voltage across the part. p dl will depend on the required output signal and load but would, for resistive load connected to mid-supply (v s /2), be at a maximum when the output is fixed at a voltage equal to v s /4 or 3v s /4. under this condition, p dl = v s 2 /(16 ?r l ), where r l includes feedback network loading. note that it is the power in the output stage, and not into the load, that determines internal power dissipation. as a worst-case example, compute the maximum t j using the circuit of figure 1 operating at the maximum specified ambient temperature of +85 c and driving a 150 ? load at mid-supply, for both channels: p d = 2 (10v ?7.1ma + 5 2 /(16 ?(150 ? || 1500 ? ))) = 161mw maximum t j = +85 c + (0.16w ?150 c/w) = 109 c. although this is still well below the specified maximum junction temperature, system reliability considerations may require lower guaranteed junction temperatures. the highest possible internal dissipation will occur if the load requires current to be forced into the output at high output voltages or sourced from the output at low output voltages. this puts a high current through a large internal voltage drop in the output transistors. board layout guidelines achieving optimum performance with a high frequency amplifier like the opa2631 requires careful attention to board layout parasitics and external component types. rec- ommendations that will optimize performance include: a) minimize parasitic capacitance to any ac ground for all of the signal i/o pins. parasitic capacitance on the output and inverting input pins can cause instability: on the non- inverting input, it can react with the source impedance to cause unintentional bandlimiting. to reduce unwanted ca- pacitance, a window around the signal i/o pins should be opened in all of the ground and power planes around those pins. otherwise, ground and power planes should be unbro- ken elsewhere on the board. b) minimize the distance (<0.25") from the power-supply pins to high frequency 0.1 f decoupling capacitors. at the device pins, the ground and power plane layout should not be in close proximity to the signal i/o pins. avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. each power-supply connection should always be decoupled with one of these capacitors. an optional supply decoupling capacitor (0.1 f) across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. larger (2.2 f to 6.8 f) decoupling capacitors, effective at lower fre- quency, should also be used on the main supply pins. these may be placed somewhat farther from the device and may be shared among several devices in the same area of the pc board.
opa2631 17 sbos067a c) careful selection and placement of external compo- nents will preserve high frequency performance. resis- tors should be a very low reactance type. surface-mount resistors work best and allow a tighter overall layout. metal film or carbon composition axially-leaded resistors can also provide good high frequency-performance. again, keep their leads and pc board traces as short as possible. never use wirewound type resistors in a high-frequency application. since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feed- back and series output resistor, if any, as close as possible to the output pin. other network components, such as non- inverting input termination resistors, should also be placed close to the package. where double-side component mount- ing is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. even with a low parasitic capaci- tance shunting the external resistors, excessively high resis- tor values can create significant time constants that can degrade performance. good axial metal film or surface- mount resistors have approximately 0.2pf in shunt with the resistor. for resistor values > 1.5k ? , this parasitic capaci- tance can add a pole and/or zero below 500mhz that can effect circuit operation. keep resistor values as low as possible consistent with load driving considerations. the 750 ? feedback used in the typical performance specifica- tions is a good starting point for design. d) connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. for short connections, consider the trace and the input to the next device as a lumped capacitive load. relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. estimate the total capacitive load and set r s from the typical performance curve ?ecommended r s vs capacitive load? low parasitic capacitive loads (< 5pf) may not need an r s since the opa2631 is nominally compensated to operate with a 2pf parasitic load. higher parasitic capacitive loads without an r s are allowed as the signal gain increases (increasing the unloaded phase margin) if a long trace is required, and the 6db signal loss intrinsic to a doubly- terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ecl design handbook for microstrip and stripline layout techniques). a 50 ? environ- ment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. with a character- istic board trace impedance defined (based on board material and trace dimensions), a matching series resistor into the trace from the output of the opa2631 is used as well as a terminating shunt resistor at the input of the destination device. remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effec- tive impedance should be set to match the trace impedance. if the 6db attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. treat the trace as a capacitive load in this case and set the series resistor value as shown in the typical performance curve ?ecommended r s vs capacitive load? this will not preserve signal integrity as well as a doubly-terminated line. if the input impedance of the desti- nation device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) socketing a high-speed part is not recommended. the additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. best results are obtained by soldering the opa2631 onto the board. input and esd protection the opa2631 is built using a very high-speed complemen- tary bipolar process. the internal junction breakdown volt- ages are relatively low for this very small geometry device. this breakdown is reflected in the absolute maximum ratings table. all device pins are protected with internal esd protection diodes to the power supplies, as shown in figure 9. these diodes provide moderate protection to input overdrive external pin +v cc C v cc internal circuitry figure 9. internal esd protection. voltages above the supplies as well. the protection diodes can typically support 30ma continuous current. where higher currents are possible (e.g., in systems with 15v supply parts driving into the opa2631), current-limiting series resistors should be added into the two inputs. keep these resistor values as low as possible, since high values degrade both noise performance and frequency response.
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