View ADS7841EB2K5_1192888.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

12-bit, 4-channel serial output sampling analog-to-digital converter features single supply: 2.7v to 5v 4-channel single-ended or 2-channel differential input up to 200khz conversion rate 1lsb max inl and dnl no missing codes 72db sinad serial interface dip-16 or ssop-16 package alternate source for max1247 ads7841es: +125 c version description the ads7841 is a 4-channel, 12-bit sampling analog-to- digital converter (adc) with a synchronous serial inter- face. the resolution is programmable to either 8 bits or 12 bits. typical power dissipation is 2mw at a 200khz through- put rate and a +5v supply. the reference voltage (v ref ) can be varied between 100mv and v cc , providing a correspond- ing input voltage range of 0v to v ref . the device includes a shutdown mode which reduces power dissipation to under 15 w. the ads7841 is tested down to 2.7v operation. low power, high speed, and on-board multiplexer make the ads7841 ideal for battery-operated systems such as per- sonal digital assistants, portable multi-channel data loggers, and measurement equipment. the serial interface also pro- vides low-cost isolation for remote data acquisition. the ads7841 is available in a dip-16 or a ssop-16 package and is specified over the ?0 c to +125 c (1) temperature range. note: (1) es grade only. cdac sar comparator four channel multiplexer serial interface and control ch0 ch1 ch2 ch3 com v ref cs shdn din dout mode busy dclk ads7841 ads7841 applications data acquisition test and measurement industrial process control personal digital assistants battery-powered systems ads7841 sbas084b ?july 2001 www.ti.com copyright ?2000, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
ads7841 2 sbas084b pin configurations top view minimum maximum relative gain specification package accuracy error temperature package drawing ordering transport product (lsb) (lsb) range package designator number number (1) media ads7841e 2 4 ?0 c to +85 c ssop-16 dbq 322 ads7841e rails " " " " " " " ads7841e/2k5 tape and reel ads7841p 2 " ?0 c to +85 c dip-16 n 180 ads7841p rails ads7841eb 1 3 ?0 c to +85 c ssop-16 dbq 322 ads7841eb rails " " " " " " " ads7841eb/2k5 tape and reel ads7841pb 1 " ?0 c to +85 c dip-16 n 180 ads7841pb rails ads7841es 2 4 ?0 c to +125 c ssop-16 dbq 322 ads7841es/2k5 tape and reel notes: (1) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2k5 indicates 2500 d evices per reel). ordering 2500 pieces of ?ds7841e/2k5?will get a single 2500-piece tape and reel. package/ordering information 1 2 3 4 5 6 7 8 +v cc ch0 ch1 ch2 ch3 com shdn v ref dclk cs din busy dout mode gnd +v cc 16 15 14 13 12 11 10 9 ads7841 1 2 3 4 5 6 7 8 +v cc ch0 ch1 ch2 ch3 com shdn v ref dclk cs din busy dout mode gnd +v cc 16 15 14 13 12 11 10 9 ads7841 dip ssop pin descriptions pin name description 1+v cc power supply, 2.7v to 5v 2 ch0 analog input channel 0 3 ch1 analog input channel 1 4 ch2 analog input channel 2 5 ch3 analog input channel 3 6 com ground reference for analog inputs. sets zero code voltage in single-ended mode. connect this pin to ground or ground refer ence point. 7 shdn shutdown. when low, the device enters a very low power shutdown mode. 8v ref voltage reference input 9+v cc power supply, 2.7v to 5v 10 gnd ground 11 mode conversion mode. when low, the device always performs a 12-bit conversion. when high, the resolution is set by the mode b it in the control byte. 12 dout serial data output. data is shifted on the falling edge of dclk. this output is high impedance when cs is high. 13 busy busy output. this output is high impedance when cs is high. 14 din serial data input. if cs is low, data is latched on rising edge of dclk. 15 cs chip select input. controls conversion timing and enables the serial input/output register. 16 dclk external clock input. this clock runs the sar conversion process and synchronizes serial data i/o. absolute maximum ratings (1) +v cc to gnd ........................................................................ 0.3v to +6v analog inputs to gnd ............................................ 0.3v to +v cc + 0.3v digital inputs to gnd ........................................................... 0.3v to +6v power dissipation .......................................................................... 250mw maximum junction temperature ................................................... +150 c operating temperature range .................................. 40 c to +125 c (2) storage temperature range ......................................... 65 c to +150 c lead temperature (soldering, 10s) ............................................... +300 c notes: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. (2) ads7841es 0nly. all other grades are: 40 c to +85 c. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ads7841 3 sbas084b ? same specifications as ads7841e, p. note: (1) lsb means least significant bit. with v ref equal to +5.0v, one lsb is 1.22mv. (2) first five harmonics of the test frequency. (3) auto power-down mode (pd1 = pd0 = 0) active or shdn = gnd. electrical characteristics: +5v at t a = t min to t max , +v cc = +5v, v ref = +5v, f sample = 200khz, and f clk = 16 f sample = 3.2mhz, unless otherwise noted. parameter conditions min typ max min typ max min typ max units analog input full-scale input span positive input - negative input 0v ref ??? ? v absolute input range positive input 0.2 +v cc +0.2 ??? ? v negative input 0.2 +1.25 ??? ? v capacitance 25 ?? pf leakage current 200 200 200 na system performance resolution 12 ?? bits no missing codes 12 12 11 bits integral linearity error 2 1 2 lsb (1) differential linearity error 0.8 0.5 1 0.8 lsb offset error 3 ?? lsb offset error match 0.15 1.0 ?? ?? lsb gain error 4 3 4 lsb gain error match 0.1 1.0 ?? ?? lsb noise 30 ?? vrms power-supply rejection 70 ?? db sampling dynamics conversion time 12 ?? clk cycles acquisition time 3 ?? clk cycles throughput rate 200 ?? khz multiplexer settling time 500 ?? ns aperture delay 30 ?? ns aperture jitter 100 ?? ps dynamic characteristics total harmonic distortion (2) v in = 5vp-p at 10khz 78 72 80 76 78 72 db signal-to-(noise + distortion) v in = 5vp-p at 10khz 68 71 70 72 68 71 db spurious-free dynamic range v in = 5vp-p at 10khz 72 79 76 81 72 79 db channel-to-channel isolation v in = 5vp-p at 50khz 120 ? 120 db reference input range 0.1 +v cc ??? ? v resistance dclk static 5 ?? g ? input current 40 100 ?? ?? a f sample = 12.5khz 2.5 ?? a dclk static 0.001 3 ?? ?? a digital input/output logic family cmos ?? logic levels v ih | i ih | +5 a 3.0 5.5 ??? ? v v il | i il | +5 a 0.3 +0.8 ??? ? v v oh i oh = 250 a 3.5 ?? v v ol i ol = 250 a 0.4 ?? v data format straight binary ?? pwr supply requirements +v cc specified performance 4.75 5.25 ??? ? v quiescent current 550 900 ?? a f sample = 12.5khz 300 ?? a power-down mode (3) , cs = +v cc 3 ?? a power dissipation 4.5 ?? mw temperature range specified performance 40 +85 ??? +125 c ads7841e, p ads7841eb, pb ads7841es
ads7841 4 sbas084b electrical characteristics: +2.7v at t a = 40 c to +85 c, +v cc = +2.7v, v ref = +2.5v, f sample = 125khz, and f clk = 16 f sample = 2mhz, unless otherwise noted. ads7841e, p ads7841eb, pb parameter conditions min typ max min typ max units analog input full-scale input span positive input - negative input 0 v ref ?? v absolute input range positive input 0.2 +v cc +0.2 ?? v negative input 0.2 +0.2 ?? v capacitance 25 ? pf leakage current 1 ? a system performance resolution 12 ? bits no missing codes 12 12 bits integral linearity error 2 1 lsb (1) differential linearity error 0.8 0.5 1 lsb offset error 3 ? lsb offset error match 0.15 1.0 ?? lsb gain error 4 3 lsb gain error match 0.1 1.0 ?? lsb noise 30 ? vrms power-supply rejection 70 ? db sampling dynamics conversion time 12 ? clk cycles acquisition time 3 ? clk cycles throughput rate 125 ? khz multiplexer settling time 500 ? ns aperture delay 30 ? ns aperture jitter 100 ? ps dynamic characteristics total harmonic distortion (2) v in = 2.5vp-p at 10khz 77 72 79 76 db signal-to-(noise + distortion) v in = 2.5vp-p at 10khz 68 71 70 72 db spurious-free dynamic range v in = 2.5vp-p at 10khz 72 78 76 80 db channel-to-channel isolation v in = 2.5vp-p at 50khz 100 ? db reference input range 0.1 +v cc ?? v resistance dclk static 5 ? g ? input current 13 40 ?? a f sample = 12.5khz 2.5 ? a dclk static 0.001 3 ?? a digital input/output logic family cmos ? logic levels v ih | i ih | +5 a+v cc 0.7 5.5 ?? v v il | i il | +5 a 0.3 +0.8 ?? v v oh i oh = 250 a+v cc 0.8 ? v v ol i ol = 250 a 0.4 ? v data format straight binary ? power supply requirements +v cc specified performance 2.7 3.6 ?? v quiescent current 280 650 ?? a f sample = 12.5khz 220 ? a power-down mode (3) , cs = +v cc 3 ? a power dissipation 1.8 ? mw temperature range specified performance 40 +85 ?? c ? same specifications as ads7841e, p. note: (1) lsb means least significant bit. with v ref equal to +2.5v, one lsb is 610mv. (2) first five harmonics of the test frequency. (3) auto power-down mode (pd1 = pd0 = 0) active or shdn = gnd.
ads7841 5 sbas084b typical characteristics: +5v at t a = +25 c, +v cc = +5v, v ref = +5v, f sample = 200khz, and f clk = 16 f sample = 3.2mhz, unless otherwise noted. 0 20 40 60 80 100 120 frequency spectrum (4096 point fft; f in = 1,123hz, 0.2db) 0 100 25 75 50 frequency (khz) amplitude (db) 0 20 40 60 80 100 120 frequency spectrum (4096 point fft; f in = 10.3khz, 0.2db) 0 100 25 75 50 frequency (khz) amplitude (db) 12.0 11.8 11.6 11.4 11.2 11.0 effective number of bits vs input frequency 10 1 100 input frequency (khz) effective number of bits change in signal-to-(noise+distortion) vs temperature 20 40 100 temperature ( c) delta from +25 c (db) 0.4 0.2 0.0 0.2 0.4 0.6 0.6 0 20 40 60 80 f in = 10khz, 0.2db signal-to-noise ratio and signal-to- (noise+distortion) vs input frequency 10 1 100 input frequency (khz) snr and sinad (db) 74 73 72 71 70 69 68 sinad snr spurious-free dynamic range and total harmonic distortion vs input frequency 10 1 100 input frequency (khz) sfdr (db) thd (db) 85 80 75 70 65 85 80 75 70 65 thd sfdr
ads7841 6 sbas084b 0 20 40 60 80 100 120 frequency spectrum (4096 point fft; f in = 1,129hz, 0.2db) 0 62.5 15.6 46.9 31.3 frequency (khz) amplitude (db) 0 20 40 60 80 100 120 frequency spectrum (4096 point fft; f in = 10.6khz, 0.2db) 0 62.5 15.6 46.9 31.3 frequency (khz) amplitude (db) effective number of bits vs input frequency 10 1 100 input frequency (khz) effective number of bits 12.0 11.5 11.0 10.5 10.0 9.5 9.0 typical characteristics: +2.7v at t a = +25 c, +v cc = +2.7v, v ref = +2.5v, f sample = 125khz, and f clk = 16 f sample = 2mhz, unless otherwise noted. change in signal-to-(noise+distortion) vs temperature 20 40 100 temperature ( ? c) delta from +25 c (db) 0.2 0.0 0.2 0.4 0.6 0.8 0.4 0 20 40 60 80 f in = 10khz, 0.2db signal-to-noise ratio and signal-to- (noise+distortion) vs input frequency 10 1 100 input frequency (khz) snr and sinad (db) 78 74 70 66 62 58 54 sinad snr thd sfdr spurious-free dynamic range and total harmonic distortion vs input frequency 10 1 100 input frequency (khz) sfdr (db) thd (db) 90 85 80 75 70 65 60 55 50 90 85 80 75 70 65 60 55 50
ads7841 7 sbas084b supply current vs temperature 20 40 100 20 0 40 temperature ( ? c) supply current ( a) 400 350 300 250 200 150 100 60 80 power down supply current vs temperature 20 40 100 20 0 40 temperature ( ? c) supply current (na) 140 120 100 80 60 40 20 60 80 output code 1.00 0.75 0.50 0.25 0.00 0.25 0.50 0.75 1.00 integral linearity error vs code 800 h fff h 000 h ile (lsb) output code 1.00 0.75 0.50 0.25 0.00 0.25 0.50 0.75 1.00 differential linearity error vs code 800 h fff h 000 h dle (lsb) change in gain vs temperature 20 40 100 20 0 40 temperature ( ? c) delta from +25 ? c (lsb) 0.15 0.10 0.05 0.00 0.05 0.10 0.15 60 80 change in offset vs temperature 20 40 100 20 0 40 temperature ( ? c) delta from +25 ? c (lsb) 0.6 0.4 0.2 0.0 0.2 0.4 0.6 60 80 typical characteristics: +2.7v (cont.) at t a = +25 c, +v cc = +2.7v, v ref = +2.5v, f sample = 125khz, and f clk = 16 f sample = 2mhz, unless otherwise noted.
ads7841 8 sbas084b reference current vs sample rate 75 0 125 25 50 100 sample rate (khz) reference current ( a) 14 12 10 8 6 4 2 0 reference current vs temperature 20 40 100 20 0 40 temperature ( ? c) reference current ( a) 18 16 14 12 10 8 6 60 80 supply current vs +v cc 3.5 25 2.5 4 +v cc (v) supply current ( a) 320 300 280 260 240 220 200 180 4.5 3 f sample = 12.5khz v ref = +v cc maximum sample rate vs +v cc 3.5 25 2.5 4 +v cc (v) sample rate (hz) 1m 100k 10k 1k 4.5 3 v ref = +v cc typical characteristics: +2.7v (cont.) at t a = +25 c, +v cc = +2.7v, v ref = +2.5v, f sample = 125khz, and f clk = 16 f sample = 2mhz, unless otherwise noted.
ads7841 9 sbas084b converter +in in ch0 ch1 ch2 ch3 com a2-a0 (shown 001 b ) sgl/dif (shown high) theory of operation the ads7841 is a classic successive approximation reg- ister (sar) adc. the architecture is based on capacitive redistribution that inherently includes a sample-and-hold function. the converter is fabricated on a 0.6 s cmos process. the basic operation of the ads7841 is shown in figure 1. the device requires an external reference and an external clock. it operates from a single supply of 2.7v to 5.25v. the external reference can be any voltage between 100mv and +v cc . the value of the reference voltage directly sets the input range of the converter. the average reference input current depends on the conversion rate of the ads7841. the analog input to the converter is differential and is provided via a four-channel multiplexer. the input can be provided in reference to a voltage on the com pin (which is generally ground) or differentially by using two of the four input channels (ch0 - ch3). the particular configuration is selectable via the digital interface. analog input figure 2 shows a block diagram of the input multiplexer on the ads7841. the differential input of the converter is derived from one of the four inputs in reference to the com pin or two of the four inputs. table i and table ii show the relationship between the a2, a1, a0, and sgl/dif control bits and the configuration of the analog multiplexer. the control bits are provided serially via the din pin, see the digital interface section of this data sheet for more details. when the converter enters the hold mode, the voltage difference between the +in and ?n inputs (as shown in figure 2) is captured on the internal capacitor array. the voltage on the ?n input is limited between ?.2v and 1.25v, allowing the input to reject small signals that are common to both the +in and ?n input. the +in input has a range of ?.2v to +v cc + 0.2v. figure 2. simplified diagram of the analog input. a2 a1 a0 ch0 ch1 ch2 ch3 com 001+in in 101 in +in 010 +in in 110 in +in table ii. differential channel control (sgl/dif low). a2 a1 a0 ch0 ch1 ch2 ch3 com 001+in in 101 +in in 010 +in in 110 +in in table i. single-ended channel selection (sgl/dif high). the input current on the analog inputs depends on the conversion rate of the device. during the sample period, the source must charge the internal sampling capacitor (typi- cally 25pf). after the capacitor has been fully charged, there is no further input current. the rate of charge transfer from the analog source to the converter is a function of conver- sion rate. figure 1. basic operation of the ads7841. +v cc ch0 ch1 ch2 ch3 com shdn v ref 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dclk cs din busy dout mode gnd +v cc serial/conversion clock chip select serial data in serial data out 0.1f 0.1f +2.7v to +5v ads7841 single-ended or differential analog inputs + 1f to 10f
ads7841 10 sbas084b figure 3. conversion timing, 24-clocks per conversion, 8-bit bus interface. no dclk delay required with dedicated serial port. t acq acquire idle conversion idle 1 dclk cs 81 11 dout busy (msb) (start) (lsb) a2 s din a1 a0 mode sgl/ dif pd1 pd0 1098765 4 3210 zero filled... 81 8 reference input the external reference sets the analog input range. the ads7841 will operate with a reference in the range of 100mv to +v cc . keep in mind that the analog input is the difference between the +in input and the ?n input, see figure 2. for example, in the single-ended mode, a 1.25v reference, and with the com pin grounded, the selected input channel (ch0 - ch3) will properly digitize a signal in the range of 0v to 1.25v. if the com pin is connected to 0.5v, the input range on the selected channel is 0.5v to 1.75v. there are several critical items concerning the reference input and its wide voltage range. as the reference voltage is re- duced, the analog voltage weight of each digital output code is also reduced. this is often referred to as the lsb (least significant bit) size and is equal to the reference voltage divided by 4096. any offset or gain error inherent in the adc will appear to increase, in terms of lsb size, as the reference voltage is reduced. for example, if the offset of a given converter is 2lsbs with a 2.5v reference, then it will typically be 10lsbs with a 0.5v reference. in each case, the actual offset of the device is the same, 1.22mv. likewise, the noise or uncertainty of the digitized output will increase with lower lsb size. with a reference voltage of 100mv, the lsb size is 24 v. this level is below the internal noise of the device. as a result, the digital output code will not be stable and vary around a mean value by a number of lsbs. the distribution of output codes will be gaussian and the noise can be reduced by simply averaging consecutive conversion results or applying a digital filter. with a lower reference voltage, care should be taken to provide a clean layout including adequate bypassing, a clean (low-noise, low-ripple) power supply, a low-noise reference, and a low-noise input signal. because the lsb size is lower, the converter will also be more sensitive to nearby digital signals and electromagnetic interference. the voltage into the v ref input is not buffered and directly drives the capacitor digital-to-analog converter (cdac) portion of the ads7841. typically, the input current is 13 a with a 2.5v reference. this value will vary by microamps depending on the result of the conversion. the reference current diminishes directly with both conversion rate and reference voltage. as the current from the reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will not reduce overall current drain from the reference. digital interface figure 3 shows the typical operation of the ads7841? digital interface. this diagram assumes that the source of the digital signals is a microcontroller or digital signal processor with a basic serial interface (note that the digital inputs are over-voltage tolerant up to 5.5v, regardless of +v cc ). each communication between the processor and the converter consists of eight clock cycles. one complete conversion can be accomplished with three serial communications, for a total of 24 clock cycles on the dclk input. the first eight clock cycles are used to provide the control byte via the din pin. when the converter has enough information about the following conversion to set the input multiplexer appropriately, it enters the acquisition (sample) mode. after three more clock cycles, the control byte is complete and the converter enters the conversion mode. at this point, the input sample-and-hold goes into the hold mode. the next twelve clock cycles accomplish the actual analog-to-digital conversion. a thirteenth clock cycle is needed for the last bit of the conversion result. three more clock cycles are needed to complete the last byte (dout will be low). these will be ignored by the converter.
ads7841 11 sbas084b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (msb) (lsb) s a2 a1 a0 mode sgl/dif pd1 pd0 table iii. order of the control bits in the control byte. table iv. descriptions of the control bits within the control byte. bit name description 7 s start bit. control byte starts with first high bit on din. a new control byte can start every 15th clock cycle in 12-bit conversion mode or every 11th clock cycle in 8-bit conversion mode. 6 - 4 a2 - a0 channel select bits. along with the sgl/dif bit, these bits control the setting of the multiplexer input, see tables i and ii. 3 mode 12-bit/8-bit conversion select bit. if the mode pin is high, this bit controls the number of bits for the next conversion: 12-bits (low) or 8-bits (high). if the mode pin is low, this bit has no function and the conversion is always 12 bits. 2 sgl/dif single-ended/differential select bit. along with bits a2 - a0, this bit controls the setting of the multiplexer input, see tables i and ii. 1 - 0 pd1 - pd0 power-down mode select bits. see table v for details. control byte also shown in figure 3 is the placement and order of the control bits within the control byte. tables iii and iv give detailed information about these bits. the first bit, the ??bit, must always be high and indicates the start of the control byte. the ads7841 will ignore inputs on the din pin until the start bit is detected. the next three bits (a2 - a0) select the active input channel or channels of the input multiplexer (see tables i and ii and figure 2). mode pin is high, then the mode bit determines the number of bits for each conversion, either 12 bits (low) or 8 bits (high). the sgl/dif bit controls the multiplexer input mode: either single-ended (high) or differential (low). in single-ended mode, the selected input channel is referenced to the com pin. in differential mode, the two selected inputs provide a differential input. see tables i and ii and figure 2 for more information. the last two bits (pd1 - pd0) select the power- down mode, as shown in table v. if both inputs are high, the device is always powered up. if both inputs are low, the device enters a power-down mode between conversions. when a new conversion is initiated, the device will resume normal operation instantly?o delay is needed to allow the device to power up and the very first conversion will be valid. 16-clocks per conversion the control bits for conversion n+1 can be overlapped with conversion ??to allow for a conversion every 16 clock cycles, as shown in figure 4. this figure also shows possible serial communication occurring with other serial peripherals between each byte transfer between the processor and the converter. this is possible provided that each conversion completes within 1.6ms of starting. otherwise, the signal that has been captured on the input sample-and-hold may droop enough to affect the conversion result. in addition, the ads7841 is fully powered while other serial communica- tions are taking place. 1 dclk cs 81 11 dout busy s din control bits s control bits 1098765 43210 11 10 9 81 1 8 figure 4. conversion timing, 16-clocks per conversion, 8-bit bus interface. no dclk delay required with dedicated serial port. pd1 pd0 description 0 0 power-down between conversions. when each conversion is finished, the converter enters a low power mode. at the start of the next conversion, the device instantly powers up to full power. there is no need for additional delays to assure full operation and the very first conversion is valid. 0 1 reserved for future use 1 0 reserved for future use 1 1 no power-down between conversions, device al- ways powered. table v. power-down selection. the mode bit and the mode pin work together to deter- mine the number of bits for a given conversion. if the mode pin is low, the converter always performs a 12-bit conversion regardless of the state of the mode bit. if the
ads7841 12 sbas084b digital timing figure 5 and tables vi and vii provide detailed timing for the digital interface of the ads7841. 15-clocks per conversion figure 6 provides the fastest way to clock the ads7841. this method will not work with the serial interface of most symbol description min typ max units t acq acquisition time 1.5 s t ds din valid prior to dclk rising 100 ns t dh din hold after dclk high 10 ns t do dclk falling to dout valid 200 ns t dv cs falling to dout enabled 200 ns t tr cs rising to dout disabled 200 ns t css cs falling to first dclk rising 100 ns t csh cs rising to dclk ignored 0 ns t ch dclk high 200 ns t cl dclk low 200 ns t bd dclk falling to busy rising 200 ns t bdv cs falling to busy enabled 200 ns t btr cs rising to busy disabled 200 ns table vi. timing specifications (+v cc = +2.7v to 3.6v, t a = ?0 c to +85 c, c load = 50pf). symbol description min typ max units t acq acquisition time 900 ns t ds din valid prior to dclk rising 50 ns t dh din hold after dclk high 10 ns t do dclk falling to dout valid 100 ns t dv cs falling to dout enabled 70 ns t tr cs rising to dout disabled 70 ns t css cs falling to first dclk rising 50 ns t csh cs rising to dclk ignored 0 ns t ch dclk high 150 ns t cl dclk low 150 ns t bd dclk falling to busy rising 100 ns t bdv cs falling to busy enabled 70 ns t btr cs rising to busy disabled 70 ns table vii. timing specifications (+v cc = +4.75v to +5.25v, t a = ?0 c to +85 c, c load = 50pf). figure 6. maximum conversion rate, 15-clocks per conversion. 1 dclk cs 11 dout busy a2 s din a1 a0 mode sgl/ dif pd1 pd0 109876543210 111098765432 a1 a0 15 1 15 1 a2 sa1a0 mode sgl/ dif pd1 pd0 a2 s figure 5. detailed timing diagram. pd0 t bdv t dh t ch t cl t ds t css t dv t bd t bd t tr t btr t d0 t csh dclk cs 11 dout busy din 10 microcontrollers and digital signal processors as they are generally not capable of providing 15 clock cycles per serial transfer. however, this method could be used with field programmable gate arrays (fpgas) or application spe- cific integrated circuits (asics). note that this effectively increases the maximum conversion rate of the converter beyond the values given in the specification tables, which assume 16 clock cycles per conversion.
ads7841 13 sbas084b data format the ads7841 output data is in straight binary format, as shown in figure 7. this figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. output code 0v fs = full-scale voltage = v ref 1lsb = v ref /4096 fs 1lsb 11...111 11...110 11...101 00...010 00...001 00...000 1lsb note 1: voltage at converter input, after multiplexer: +in ( in). see figure 2. input voltage (1) (v) figure 7. ideal input voltages and output codes. 8-bit conversion the ads7841 provides an 8-bit conversion mode that can be used when faster throughput is needed and the digital result is not as critical. by switching to the 8-bit mode, a conversion is complete four clock cycles earlier. this could be used in conjunction with serial interfaces that provide a 12-bit transfer or two conversions could be accomplished with three 8-bit transfers. not only does this shorten each conversion by four bits (25% faster throughput), but each conversion can actually occur at a faster clock rate. this is because the internal settling time of the ads7841 is not as critical, settling to better than 8 bits is all that is needed. the clock rate can be as much as 50% faster. the faster clock rate and fewer clock cycles combine to provide a 2x increase in conversion rate. power dissipation there are three power modes for the ads7841: full power (pd1 - pd0 = 11b), auto power-down (pd1 - pd0 = 00b), and shutdown (shdn low). the affects of these modes varies depending on how the ads7841 is being operated. for example, at full conversion rate and 16 clocks per conver- sion, there is very little difference between full power mode and auto power-down. likewise, if the device has entered auto power-down, a shutdown (shdn low) will not lower power dissipation. when operating at full-speed and 16-clocks per conversion (see figure 4), the ads7841 spends most of its time acquir- ing or converting. there is little time for auto power-down, assuming that this mode is active. thus, the difference between full power mode and auto power-down is negli- gible. if the conversion rate is decreased by simply slowing the frequency of the dclk input, the two modes remain approximately equal. however, if the dclk frequency is kept at the maximum rate during a conversion, but conver- sion are simply done less often, then the difference between the two modes is dramatic. figure 8 shows the difference between reducing the dclk frequency (?caling?dclk to match the conversion rate) or maintaining dclk at the highest frequency and reducing the number of conversion per second. in the later case, the converter spends an increas- ing percentage of its time in power-down mode (assuming the auto power-down mode is active). if dclk is active and cs is low while the ads7841 is in auto power-down mode, the device will continue to dissipate some power in the digital logic. the power can be reduced to a minimum by keeping cs high. the differences in supply current for these two cases are shown in figure 9. operating the ads7841 in auto power-down mode will result in the lowest power dissipation, and there is no conversion time ?enalty?on power-up. the very first conversion will be valid. shdn can be used to force an immediate power-down. figure 8. supply current vs directly scaling the fre- quency of dclk with sample rate or keeping dclk at the maximum possible frequency. 10k 100k 1k 1m f sample (hz) supply current (a) 100 10 1 1000 f clk = 2mhz f clk = 16 f sample t a = 25 c +v cc = +2.7v v ref = +2.5v pd1 = pd0 = 0 figure 9. supply current vs state of cs. 10k 100k 1k 1m f sample (hz) supply current (a) 0.00 0.09 14 0 2 4 6 8 10 12 cs low (gnd) cs high (+v cc ) t a = 25 c +v cc = +2.7v v ref = +2.5v f clk = 16 f sample pd1 = pd0 = 0
ads7841 14 sbas084b layout for optimum performance, care should be taken with the physical layout of the ads7841 circuitry. this is particu- larly true if the reference voltage is low and/or the conver- sion rate is high. the basic sar architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connec- tions, and digital inputs that occur just prior to latching the output of the analog comparator. thus, during any single conversion for an n-bit sar converter, there are n ?in- dows?in which large external transient voltages can easily affect the conversion result. such glitches might originate from switching power supplies, nearby digital logic, and high power devices. the degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. the error can change if the external event changes in time with respect to the dclk input. with this in mind, power to the ads7841 should be clean and well bypassed. a 0.1 f ceramic bypass capacitor should be placed as close to the device as possible. in addition, a 1 f to 10 f capacitor and a 5 ? or 10 ? series resistor may be used to low-pass filter a noisy supply. the reference should be similarly bypassed with a 0.1 f capacitor. again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. if the reference voltage originates from an op amp, make sure that it can drive the bypass capacitor without oscillation (the series resistor can help in this case). the ads7841 draws very little current from the reference on average, but it does place larger demands on the reference circuitry over short periods of time (on each rising edge of dclk during a conversion). the ads7841 architecture offers no inherent rejection of noise or voltage variation in regards to the reference input. this is of particular concern when the reference input is tied to the power supply. any noise and ripple from the supply will appear directly in the digital results. while high fre- quency noise can be filtered out as discussed in the previous paragraph, voltage variation due to line frequency (50hz or 60hz) can be difficult to remove. the gnd pin should be connected to a clean ground point. in many cases, this will be the ?nalog?ground. avoid connections which are too near the grounding point of a microcontroller or digital signal processor. if needed, run a ground trace directly from the converter to the power supply entry point. the ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry.
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, license, warranty or endorsement thereof. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information with alteration voids all warranties provided for an associated ti product or service, is an unfair and deceptive business practice, and ti is not responsible nor liable for any such use. resale of ti's products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service, is an unfair and deceptive business practice, and ti is not responsible nor liable for any such use. also see: standard terms and conditions of sale for semiconductor products. www.ti.com/sc/docs/stdterms.htm mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2001, texas instruments incorporated

▲Up To Search▲

Price & Availability of ADS7841EB2K5

	To Download ADS7841EB2K5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .