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ww w .fai r childsemi.com features rotation, warping, panning, zooming, and compression of images in real time 20 mhz clock rate 4096 x 4096 image ?ld addressing capability use r -selectable nearest-neighbo r , bilinear interpolation, and cubic co n v olution resampling algorithms static co n v olutional ?tering of up to 16 x 16 pi x el wind o ws single-pass or two-pass co n v olution operations l o w p o wer consumption cmos process single 5v p o wer supply a v ailable in a 68-pin grid array and l o w-cost plastic leaded chip carrier (j-bend) applications v ideo special-e f fects generators image recognition systems, robotics arti?ial intelligence high-precision image r e gistration (lands a t processing) high-speed data encoding/decoding general purpose image processing image data compression description th e TMC2301 is a vlsi circuit which supports image resampling, rotation, rescaling and ?tering by generating input bit plane, interpolation coe f ?ient lookup table, and output bit plane memory addresses along with e xternal multiplie r -accumulator control signals . th e TMC2301 can process data ?lds of up to 4096 x 4096 multibit words at a clock rate of up to 20 mhz . an image resampling sequencer (irs) based system can nearest-neighbor resam- ple a 512 x 512 image in 15 milliseconds, translating, zoom- ing, rotating, or warping it, depending on the transform parameter set loaded . a complete bilinear interpolation of the same image can be completed in 60 milliseconds. image resampling speed is independent of the angle of rotation, d e gree of warp, or amount of zoom speci?d. a high performance , TMC2301-based system can e x ecute bilinear and cubic co n v olution algorithms that rotate images accurately and in real time. k e ystone or other perspect i v e correction, image plane distortion, and numerous other second order polynomial transformations can be program- med and ex ecuted under direct user control. direct access to the interpolation coe f ?ient lookup table all o ws dynamic modi?ation of the algorithm. f oll o wing an initialization with the transform parameters and control bits de?ing the operation to be ex ecuted, the irs assumes control of the input and output data ?lds and ex ecutes unattended . all inputs e xcept inter and all out- puts are r e gistered on the rising edge of clock . all outputs are three-state controlled e xcept acc , czero , end, and done. f abricated in a 1 micron cmos process, th e TMC2301 operates at clock rates of up to 20 mhz ov er the full commercial (0 to 70 c) temperature and supply v oltage ranges . all signals ar e ttl compatible. logic symbol ldr wen b 3-0 4 p 11-0 x 11-0 u 11-0 ca 7-0 clk czero end uwri acc done oeta init inter noop 8 12 12 12 65-2301-01 TMC2301 image resampling sequencer 15, 18, 20 mhz r e v . 1. 1 .0
TMC2301 product specification 2 functional description general inf ormation the irs is a v ersatile self-sequencing address generator designed primarily to lter a tw o-dimensional image or to remap and resample it from one set of cartesian coordinates (x, y) into a ne w transformed set (u, v). most applications use tw o identical de vices in tandem, one generating the ro w coordinates (x and u), the other generating the column coor - dinates (y and v). the algorithm performed by the TMC2301 consists of tw o steps: a coordinate system trans- formation, follo wed by pix el interpolation. interpolation is necessary when the transformed pix el positions (u, v) do not coincide with the original pix el positions (x, y). the ne w pix el intensity v alues are obtained by interpolating the original pix els in the neighborhood of the transformed pix el positions. see figure 1. the irs e x ecutes a general second order coordinate transfor - mation of the form: x(u, v) = au 2 + bu + cuv + dv 2 + ev + f y(u, v) = gu 2 + hu + k uv + lv 2 + mv + n where a through n are user -de ned parameters. it steps sequentially through the pix els of a user -de ned rectangle in the ne w set of coordinates, computing the "old" address (x, y) corresponding to each "ne w" location (u, v). the TMC2301 uses the e xternal multiplier -accumulator , connected to the system clock, to calculate the interpolated pix el v alue by summing the products of the original pix el v alues stored in the source b uf fer ram and the appropriate weights from the polynomial transform lookup table. the ne w interpolated image v alue is then stored in the corre- sponding (u, v) memory location. finally , the ne w image address is incremented by one pix el in the "u" direction or reset to the start of the ne xt line (with "v" incremented) pro- ceeding line-by-line through the entire destination image. the TMC2301 can support an y nearest neighbor , bilinear , or cubic resampling, according to the user's requirements. the bilinear and cubic k ernels require a coef cient lookup table and multiplier -accumulator . both one-pass and tw o-pass algorithms are supported. sophisticated "w alkaround" algo- rithms implementing static lters are also easily realized uti- lizing con v olutional k ernels of up to 16 x 16 pix els. f or each output point in a typical static single-pass lter , the irs will generate a series of addresses, "w alking" around that point in tw o dimensions. at the end of each w alk, it will adv ance one pix el along the output scan line, then be gin the w alk for the ne xt pix el. bloc k dia gram register load integer x fraction write enable register address clk instructions control word and transform parameter storage register source address generator input image boundary comparator out of range interpolation coefficient address source address target address counter xo, d 's xmin xmax walk count limits limits reset count at limit target out enable umin umax control 4 parameter data in clk initialize interconnect: next row/column noop 8 12 12 target address end of row/ column target write enable 12 65-2301-02 accumulate transform done
product specification TMC2301 3 a basic TMC2301-based system is sho wn in figure 2. in this typical system, tw o image resampling sequencers process the image. the only other e xternal parts needed are a multiplier -accumulator , e xternal interpolation coef cient lookup table ram, and the user -speci ed source and destination image memory . figure 1. image resampling geometry showing image rotation and expansion notes: 1. 2. coordinate transformation u, v pixel mapped into x, y coordinates. pixel interpolation walk new u, v pixel intensity calculated from surrounding x, y pixel neighborhood. note 1 note 2 (0, 0) original (source) image new (target) image (u 0 , v 0 ) y (0, 0) new pixel v x u 65-2301-05 figure 2. basic 2-d image convolver using TMC2301 image resampling sequencer utilizing typical 8-bit data path 65-2301-06 8 8 24 inter address x 11-0 acc initialization data control clock uwri clk x, y, p acc uwri y k d out u 11-0 ca 7-0 ca 7-0 y 11-0 v 11-0 irs row (x) irs column (y) interpolation coefficient buffer ram end inter end 8 8 8 8 8 address destination address 24 source address image data in source image buffer ram tmc2208 8 x 8 mac destination image buffer ram image data out 4k x 4k words maximum image size 4k x 4k words maximum image size 12 12 12
TMC2301 product specification 4 pin assignments 68 pin grid arra y 68 pin plcc b2 65-2301-03 b1 c2 c1 d2 d1 e2 e1 f2 f1 g2 g1 h2 h1 j2 j1 k1 pin init oeta inter end done u 0 u 1 u 2 gnd u 3 u 4 u 5 u 6 u 7 u 8 u 9 gnd name k2 l2 k3 l3 k4 l4 k5 l5 k6 l6 k7 l7 k8 l8 k9 l9 l10 pin u 10 u 11 uwri acc czero ca 0 ca 1 v dd gnd ca 2 ca 3 ca 4 ca 5 ca 6 ca 7 x 0 gnd name k10 k11 j10 j11 h10 h11 g10 g11 f10 f11 e10 e11 d10 d11 c10 c11 b11 pin x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 gnd x 9 x 10 x 11 p 11 p 10 p 9 p 8 p 7 name b10 a10 b9 a9 b8 a8 b7 a7 b6 a6 b5 a5 b4 a4 b3 a3 a2 pin p 6 p 5 p 4 p 3 p 2 p 1 p 0 clk gnd v dd noop ldr b 0 b 1 b 2 b 3 wen name a 2 3 1 4 5 6 7 8 9 10 11 b c d e f g h j k l 1 65-2301-04 2 3 4 5 6 7 1 68 8 9 10 11 12 13 14 15 16 17 pin gnd ca 2 ca 3 ca 4 ca 5 ca 6 ca 7 x 0 gnd x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 name 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 pin gnd x 9 x 10 x 11 p 11 p 10 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 clk name 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 pin gnd v dd noop ldr b 0 b 1 b 2 b 3 wen init oeta inter end done u 0 u 1 u 2 name 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 pin gnd u 3 u 4 u 5 u 6 u 7 u 8 u 9 gnd u 10 u 11 uwri acc czero ca 0 ca 1 v dd name
product specification TMC2301 5 pin descriptions pin name pin number pin function description pga plcc p o wer gnd f2, f10, k1, k6, l10, b6 1, 9, 18, 35, 52, 60 supply voltage. the TMC2301 operates from a single +5v supply. all pins must be connected. v dd l5, a6 36, 68 ground. the TMC2301 operates from a single +5v supply. all pins must be connected. cloc k clk a7 34 system clock. the TMC2301 has a angle clock input. the rising edge of clk strobes all enabled registers. all timing specifications are referenced to the rising edge of clk. inputs b 3-0 a3, b3, a4, b4 42-39 parameter register address. the write addresses for the individual coordinate transform parameters are presented at the registered 4-bit b input port. b 3 is the most significant bit. p 11-0 d10, d11, c10, c11, b11, b10, a10, b9, a9, b8, a8, b7 22-33 parameter register data. the coordinate transformation parameters are loaded through the registered 12-bit p input port. p11 is the most significant bit. outputs ca 7-0 k9, l8, k8, l7, k7, l6, k5, l4 7-2, 67, 66 coefficient address. the current interpolation kernel coefficient lookup table address is indicated by the registered 8-bit ca 7-0 output bus. this output is forced to the high impedance state when noop is low. ca 7 is the most significant bit. u 11-0 l2, k2, j1, j2, h1, h2, g1, g2, f1, e1, e2, d1 62, 61, 59-53, 51-49 target address. the u (or v) target address of the image being generated is indicated by the registered 12-bit u 11-0 output bus. this output is forced to the high impedance state when oeta is high. u 11 is the most significant bit. x 11-0 e11, e10, f11, g11, g10, h11, h10, j11, j10, k11, k10, l9 21-19, 17-10, 8 source address. the current x (or y) source pixel address of the image being resampled is indicated by the registered 12-bit x 11-0 output bus. this output is forced to the high impedance state when noop is low. x 11 is the most significant bit. contr ols acc l3 64 accumulate. the accumulation register of the external multiplier- accumulator is initialized by the registered acc output. acc goes low for one cycle at the start of each interpolation "walk," effectively clearing the storage register by loading in only the new first product. see figure 9. init b2 44 initialize. the control logic is cleared and initialized for the start of a new image transformation when the registered init input is high for a minimum of two clock cycles. normal operation begins after init goes low. inter c2 46 interconnect. in the common two-device system configuration, the interconnect inputs are connected to the end flag outputs. the end flag from the row (x) sequencer thus indicates an "end of line" to the column (y) device, while the column sequencer in turn sends a "bottom of frame" signal to the row device, forcing a reset of the address counter.
TMC2301 product specification 6 ldr a5 38 load parameter data registers. the data held in all transformation parameter preload registers are latched into the working registers when the registered input ldr is high. when ldr is low, the working parameters remain unchanged. see figure 4. noop b5 37 no operation. the clock is overidden when the registered input noop is low, holding each address generator in their current state. also, the output buffers for the address busses x 11-0 and ca 7-0 are forced to the high impedance state. this allows the user access to all external memory. when noop goes high, normal operation resumes on the next clock cycle. oeta b1 45 target memory output enable. the target memory outputs uwri and address bus u 11-0 are in the high-impedance state when the registered output enable input is high. when oeta is low, they are enabled on the next clock cycle. uwri k3 63 target memory write enable. after the end of each interpolation "walk," the target memory (u or v) write enable goes low for one clock cycle. see figure 9. this registered output is forced to the high impedance state when oeta is high. wen a2 43 parameter write enable. the registered write enable input allows the transformation parameters to be written into the preload register indicated by the address at the b input port when low. see figure 4. fla gs czero k4 65 coefficient zero. the registered czero flag of a horizontal dimension TMC2301 goes high if x < 0, xmin x xmax, or x 3 4096 (1000 hex). it goes low if 0 x xmin or xmax < x < 4096. the logical and of the czero flags of a two-dimensional pair of TMC2301s will go low when the source address falls outside a rectangle with vertices (xmin, ymin), (xmax, ymin), (xmin, ymax), and (xmax, ymax), denoting an invalid address. the external data path can be wired to substitute a selected background value whenever this and = 0. done d2 48 end of transform. in the standard two-device system, a row sequencer done flag high after the last walk at the end of the last row of an image (during uwri low) indicates the end of the transform. this registered output is usually ignored on the column device. see the transformation control parameters, autoinit. end c1 47 end of row/page. the registered end flag goes high during the last pixel of the last walk in a row in the case of the row chip, and the last pixel of the last walk in a column in the column chip, in the two-device architecture. this output is used as the end-of- line and end-of-frame indicator in conjunction with the inter inputs of both TMC2301s. pin descriptions (contin ued) pin name pin number pin function description pga plcc
product specification TMC2301 7 t ransf ormation contr ol p arameter s the TMC2301 is a self-sequencing de vice which requires no c ycle-to-c ycle interv ention from the host system. t o program the de vice, the user loads the 16 operating parameters, which de ne the transformation to be performed, which sections of the original and resampled image spaces are to be utilized, and v arious control w ords. filtering operations are further de ned by the v alues the user loads into the e xternal coef - cient memory . the transform parameters are described belo w . see also t ables 1 through 3. note: 1. for each incremental move along the u axis, the starting point of the new "walk around spiral" is indexed to the ending point of the previous walk around spiral, rather than to its center. therefore, the terms dx/du 0 and dy/du 0 must be adjusted accordingly. since each new line is referenced back to the previous line's initial spiral starting point, no similar dx/dv 0 or dy/dv 0 correction is needed. xmin, xmax, ymin, ymax these four parameters outline the "source" rectangular region of the original image. whenever the irs pair generates an (x, y) address within this boundary the czero flags will denote a valid memory read. in the most common case, xmin < xmax, ymin < ymax, 000h < x < fffh, and 000h < y< fffh. in this case, addresses out of bounds cause one or both czero s to go low. refer to application note tp-38 for further information on other boundary violation cases. each parameter is expressed in 12-bit unsigned binary integer notation. see figure 12. umin, umax, vmin, vmax these four parameters outline the "target" region of the (u, v) plane, into which the resampled image will be written. the irs will generate, line by line, a scan that fills only this portion of the plane, permitting the user to assemble a mosaic of multiple rectangular subimages. care must be taken to ensure that umax > umin and vmax > vmin. each parameter is expressed in 12-bit unsigned binary integer notation. see figure 12. (x 0 , y 0 ) these are the coordinates of the first pixel to be read from the original image. in many applications, this point will be one of the four corners of the original image to be resampled. the pixels near (x 0 , y 0 ) in the original image will be used to compute the upper left pixel of the transformed image. in non-inverting, non-reversing applications (x 0 , y 0 ) will be the upper left corner of the original subimage. each coordinate is expressed in 13-bit integer plus 5-bit fraction, two's complement notation. dx/du 0 is the initial horizontal partial first derivative indicating the displacement along the x axis which corresponds to each one pixel movement along the u axis. usually, 0 < dx/du 0 < 1 corresponds to magnification, whereas dx/du 0 > 1 represents reduction and dx/du 0 < 0 denotes reflection about a vertical axis. the first derivatives are expressed in 8-bit integer, 12-bit fraction two's complement notation. dx/dv 0 is the initial horizontal-vertical partial first derivative. it indicates the displacement along the x axis corresponding to each one pixel movement along the v axis. the coefficients dx/dv 0 and dx/du 0 define image rotation and shear. dy/du 0 is the initial vertical-horizontal partial first derivative. it indicates the displacement along the y axis corresponding to each one pixel movement along the u axis. dy/dv 0 is the initial vertical partial first derivative. it indicates the displacement along the y axis corresponding to each one-pixel step along the v axis. since dx/dv 0 and dy/dv 0 are separate parameters, vertical magnification and reflection need not match their horizontal counterparts. d 2 x/du 2 is the second order horizontal derivative. it indicates the rate of change of the horizontal-horizontal first derivative with each step along a line in the output image space. all six second-order derivatives are 4-bit integer, 20-bit fractional two's complement parameters. d 2 x/dv 2 is the second order horizontal- vertical-vertical derivative. it indicates the rate of change of the horizontal-vertical first derivative with each step down a column in the output image space.
TMC2301 product specification 8 in single-pass operation, the de vice w alks through the entire (k + 1) x (k + 1) k ernel for each output pix el, where k is the v alue written into the k ernel section (see belo w) of the parameter re gister . t w o-pass operation, which requires a dimensionally separable k ernel, is e x ecuted rst for a (k + 1) element k ernel in one direction, then for a (k + 1) element k ernel in the other direction. f or k ernel sizes e xceeding 2 x 2, the tw o-pass algorithm is ob viously bene cial, requir - ing 2n samples per output point instead of n x n. in this case, the intermediate image data stored in the destination image memory follo wing the rst pass is used as the source image data on the second pass. the user may design a system to d 2 y/du 2 is the second order vertical- horizontal-horizontal derivative. it indicates the rate of change of the the vertical-horizontal first derivative with each step along a line of the output image space. d 2 y/dv 2 is the second order vertical derivative. it indicates the rate of change of the vertical- vertical first derivative with each step down a column of the output image space. d 2 x/dudv is the mixed second order derivative indicating the rate of change of the first order horizontal derivative as one proceeds downwards through the output image space. this is also the rate of change of the first order horizontal-vertical derivative during horizontal sweeps in the output image space. d 2 y/dudv is the mixed second order derivative indicating the rate of change of the first order vertical derivative as one moves horizontally across the output space, or, equivalently, the rate of change of the first order vertical- horizontal derivative as one moves vertically in the output image space row/column select sets the mode to either row (0) or column (1) operation. mode this 2-bit control word defines three unique instructions: code instruction 00, 01 single-pass operation 10 pass 1 of two-pass operation 11 pass 2 of two pass operation switch source and destination memory bank addresses in place, or could utilize a second TMC2301 pair in a pipelined architecture. this w ould require a third image b uf fer for the nal destination image. both de vices of a system pair are usually set to the same mode. kernel the effective kernel width (height) exceeds this 4-bit unsigned number by 1, thereby providing kernels of 1 x 1 to 16 x 16 source pixels per output, for either resampling or filtering. simple static filters can be implemented with kernels of up to 16 x 16 pixels (kernel = 15), while resampling interpolation kernels are limited to 4 x 4 pixels (kernel = 3), due to the four bits of fractional x (or y) address generated by the TMC2301. see the applications discussion. again, both devices in a pair are generally initialized with equal kernel values. field of view (fov) as the device walks through its kernel coefficients, each corresponding step in (x, y) space is normally one pixel length or height; this is a field of view of 1. however, the user can subsample the original space before filtering or resampling, by applying the coefficient kernel over a view field of up to 7 units. at a field of view of f, the pixels selected for each kernel operation are f pixels apart. this is useful in oversampled pictures, whose intensity changes only slowly from pixel to pixel. autoload (alr) when set to 1 (high), the ldr control is automatically asserted when init is strobed, loading the coefficient set currently stored in the preload registers. autoinit (ain) at the end of an image, if the ain bit is 1 (high) the done flag goes high for one clock cycle and a new transform begins. if 0 (low), uwri and the done flag remain high during the sequence until the user strobes the init control to begin a new image transformation. pipe (pipe) adjusts the timing of the target memory write controls, to compensate for buffered source image ram. if the pipe bit is 1 (high), outputs acc and uwri will be delayed one clock cycle relative to the generation of the target address (u or v). see figure 9.
product specification TMC2301 9 test mode (tm) this mode is available for user inspection of the coefficient data. the source image and coefficient addresses are calculated by an internal 28-bit accumulator. when tm is 1 (high), the sign bit, normally discarded, and the lower 11 bits of internal data are substituted for the upper 12 bits appearing at the source address port (x) during a standard transform cycle. this allows user verification of algorithm mathematics during debug. since the tm bit is registered and cannot be changed during a single clock cycle, two distinct clock cycles are required to access both the msw and lsw of the internal accumulator. see figure 3. figure 3. test mode data routing x 11-0 /t 11-0 ca 7-4 ca 3-0 test mode t 11 65-2301-07 internal accumulator walk counter 12 11 1 4 4 8 4 sign 12 4 11 t ab le 1. p arameter register s ?ro w sequencer ad dr name description 0000 xmin left side of source window 0001 xmax right side of source window 0010 x 0 (lsw) source starting point ? x coordinate 0011 x 0 (msw) source starting point ? x coordinate 0011 controls mode select bits 0100 dx/du 0 (lsw) row/row first differential 0101 dx/du 0 (msw) row/row first differential 0101 tm, fov test mode, field of view 0110 dx/dv 0 (lsw) row/column first differential 0111 dx/dv 0 (msw) row/column first differential 0111 kernel resampling/filtering kernel 1000 d 2 x/dudv (lsw) mixed second differential 1001 d 2 x/dudv (msw) mixed second differential 1010 d 2 x/du 2 (lsw) row second differential 1011 d 2 x/du 2 (msw) row second differential 1100 d 2 x/dv 2 (lsw) row/column second differential 1101 d 2 x/dv 2 (msw) row/column second differential 1110 umin left edge of final image 1111 umax right edge of final image t ab le 2. p arameter register s ?column sequencer ad dr name description 0000 ymin top of source window 0001 ymax bottom of source window 0010 y 0 (lsw) source starting point ? y coordinate 0011 y 0 (msw) source starting point ? y coordinate 0011 controls mode select bits 0100 dy/du 0 (lsw) column/row first differential 0101 dy/du 0 (msw) column/row first differential 0101 tm, fov test mode, field of view 0110 dy/dv 0 (lsw) column/column first differential 0111 dy/dv 0 (msw) column/column first differential 0111 kernel resampling/filtering kernel sure 1000 d 2 y/dudv (lsw) mixed second differential 1001 d 2 y/dudv (msw) mixed second differential 1010 d 2 y/du 2 (lsw) column/row second differential 1011 d 2 y/du 2 (msw) column/row second differential 1100 d 2 y/dv2 (lsw) column second differential 1101 d 2 y/dv 2 (msw) column second differential 1110 vmin top edge of final image 1111 vmax bottom edge of final image
TMC2301 product specification 10 t ab le 3. p arameter register s binar y format (ro w or column sequencer) notes: 1. * unsigned binary notation 2. a ?indicates msb is sign bit ad dress format limits msb lsb dec he x 0000* 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 fff 000 0001* 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 fff 000 0010 0011 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ? 12 2 -1 2 11 2 -2 2 10 2 -3 2 9 2 -4 2 8 2 -5 2 7 4096-2 -5 -4096 0fff .f8 f000.00 0011 (control) alr ain pipe r/c m 1 m 0 0100 0101 2 -1 2 -2 2 -3 2 -4 2 -5 -2 7 2 -6 2 6 2 -7 2 5 2 -8 2 4 2 -9 2 3 2 -10 2 2 2 -11 2 1 2 -12 2 0 128-2 -12 -128 007f .fff ff80.000 0101* (tm, fov) tm 2 2 2 1 2 0 0110 0111 2 -1 2 -2 2 -3 2 -4 2 -5 -2 7 2 -6 2 6 2 -7 2 5 2 -8 2 4 2 -9 2 3 2 -10 2 2 2 -11 2 1 2 -12 2 0 128-2 -12 -128 007f .fff ff80.000 0111* (kernel) 2 3 2 2 2 1 2 0 15 0 f 0 1000 1001 2 -9 -2 3 2 -10 2 2 2 -11 2 1 2 -12 2 0 2 -13 2 -1 2 -14 2 -2 2 -15 2 -3 2 -16 2 -4 2 -17 2 -5 2 -18 2 -6 2 -19 2 -7 2 -10 2 -8 8-2 -20 -8 0007.fffff 1010 1011 2 -9 -2 3 2 -10 2 2 2 -11 2 1 2 -12 2 0 2 -13 2 -1 2 -14 2 -2 2 -15 2 -3 2 -16 2 -4 2 -17 2 -5 2 -18 2 -6 2 -19 2 -7 2 -10 2 -8 8-2 -20 -8 0007.fffff 1100 1101 2 -9 -2 3 2 -10 2 2 2 -11 2 1 2 -12 2 0 2 -13 2 -1 2 -14 2 -2 2 -15 2 -3 2 -16 2 -4 2 -17 2 -5 2 -18 2 -6 2 -19 2 -7 2 -10 2 -8 8-2 -20 -8 0007.fffff 1110* 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 ff 000 1111* 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 4095 0 ff 000
product specification TMC2301 11 internal bit mapping (f or par ametr ic inputs , integers in tab le are bits of p , the input point) 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 x out [11:0] 11 10 9 8 7 6 5 4 3 2 1 0 c adn [7:4] 7 6 5 4 xmax, xmin 11 10 9 8 7 6 5 4 3 2 1 0 x o 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2 1 dx/du, dx/dv 7 6 5 4 3 2 1 0 11 10 9 8 d 2 x/dudv, d 2 x/du 2 , d 2 x/dv 2 11 10 9 8 7 6 5 4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 2 -17 2 -18 2 -19 2 -20 x out [11:0] c adn [7:4] xmax, xmin x o 0 dx/du, dx/dv 7 6 5 4 3 2 1 0 d 2 x/dudv, d 2 x/du 2 , d 2 x/dv 2 3 2 1 0 11 10 9 8 7 6 5 4 3 2 1 0 operation of the t ransf ormation p arameter register s numerous applications require the ability to update the coor - dinate transformation parameters "on the y ." because the parameters are double-b uf fered, the user can load an y or all of them into the preload re gisters without upsetting the oper - ation in progress. then ldr (load data re gisters) will update all transform parameters to the ne w v alues simultaneously . this feature is particularly v aluable for "pin cushion" and " sh e ye" transformations, or polar -to-rectangular con v er - sions which cannot be performed with constant second deri v ati v es. the autoload function updates the preread re gis- ters at the be ginning of a ne w image automatically . see the t ransformation control p arameters section. note also that data can be loaded in to the re gisters while noop is acti v e (lo w). figure 4. operation of ldr control for parameter update p 11-0 b 3-0 wen 65-2301-08 clk decode c16 c15 c14 c2 c1 ldr
TMC2301 product specification 12 timing dia gram equiv alent cir cuits and t ransition le vels figure 5. equivalent input circuit figure 6. equivalent output circuit figure 7. transition level for three-state output clk inputs inter 1 outputs 2 valid valid end 1 notes: 1. t s and t d(e) are guaranteed to allow full speed operation in the standard two-device archite cture. see text. 2. all outputs except end. see text. t pwh t d(e) t s t h t s t d 65-2301-09 t ho t ho(e) t h(i) t cy t pwl n substrate control input d1 p+ p n p well n+ 1k gnd v dd 65-2301-10 d2 p well d3 n substrate output d1 p+ p n p well n+ gnd v dd 65-2301-11 d2 oeta 65-2301-12 noop clk high impedance three-state outputs 1 t dis t s t h t ena note: 1. all outputs except czero, acc, end and done.
product specification TMC2301 13 absolute maxim um ratings (be y ond which the de vice ma y be damaged) 1 notes: 1. absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. functional operation under any of these conditions is not implied. 2. applied voltage must be current limited to specified range, and measured with respect to gnd. 3. forcing voltage must be limited to specified range. 4. current is specified as conventional current flowing into the device. operating conditions p arameter min t yp max unit supply voltage -0.5 7.0 v input voltage -0.5 v dd + 0.5 v output applied voltage 2 -0.5 v dd + 0.5 v forced current 3,4 -1.0 6.0 ma short circuit duration (single output in high state to ground) 1 sec t emperature operating, case -60 130 c operating, junction 175 c lead soldering (10 seconds) 300 c storage -65 150 c p arameter min t yp max units v dd supply voltage 4.75 5.0 5.25 v v il input voltage, logic low 0.8 v v ih input voltage, logic high 2.0 v i ol output current, logic low 8.0 ma i oh output current, logic high -4.0 ma t a ambient temperature, still air 0 70 c t c case temperature c
TMC2301 product specification 14 dc characteristics within speci ed oper ating conditions 1 notes: 1. actual test conditions may vary from those shown, but guarantee operation as specified. 2. guaranteed but not tested. a c characteristics within speci ed oper ating conditions notes: 1. t s + t d(e) = t cy max. 2. excluding output pin end. p arameter conditions min max units i ddq supply current, quiescent v dd = max, v in = 0v 5 ma i ddu supply current, unloaded v dd = max, f = 15mhz 75 ma i il input current, logic low v dd = max, v in = 0v -10 10 m a i ih input current, logic high v dd = min, v in = v dd -10 10 m a v ol output voltage, logic low v dd = min, i ol = max 0.4 v v oh output voltage, logic high v dd = min, i oh = max 2.4 v i ozl hi-z output leakage current, output low v dd = min, v in = 0v -40 40 m a i ozh hi-z output leakage current, output high v dd = min, v in = v dd -40 40 m a i os short- circuit output current 2 v dd = max, output high, one pin to ground, one second duration max. -100 ma c i input capacitance t a = 25 c, f = 1mhz 10 pf c o output capacitance t a = 25 c, f = 1mhz 10 pf p arameter conditions -2 -1 min max unit min max min max t cy cycle time v dd = min 50 55 66 ns t pwl clock pulse width low v dd = min 20 22 25 ns t pwh clock pulse width high v dd = min 25 28 33 ns t s input setup time 1 15 18 20 ns t h input hold time 1 2 2 ns t h(i) input hold time, inter 8 10 10 ns t d output delay 2 v dd = min, c load = 40pf 25 27 35 ns t d(e) output delay, end 1 v dd = min, c load = 10pf 35 37 45 ns t ho output hold time 2 v dd = max, c load = 40pf 5 5 5 ns t ho(e) output hold time, end v dd = max, c load = 10pf 10 10 10 ns t dis three-state disable delay v dd = min, c load = 40pf 25 27 35 ns t ena three-state enable delay v dd = min, c load = 40pf 25 27 35 ns
product specification TMC2301 15 applications discussion basic operation each TMC2301 pair contains address controllers which e x e- cute patterns much lik e the follo wing for tran 3-le v el nested do loop: 1. the inner loop is a clockwise outgoing spiral "w alk" through the n-element coef cient k ernel. 2. the middle loop is a left-to-right "scan" along each ro w of the output image space. 3. finally , the outer loop is a top-to-bottom "scan" do wn each column of the output image space. a typical one pass image transformation proceeds as follo ws: 1. the de vice pair outputs the addresses (x 0 , y 0 ), which is the rst point in the source image, and (cax, ca y), the interpolation lookup table address for the rst pix el in the k ernel. the output acc goes lo w , causing the e xternal accumulator to load the rst product without summation, clearing the accumulator . 2. f or the ne xt n c ycles, the irs w alks through an outw ard clockwise spiral in (x, y) space, accumulating pix el- interpolation coef cient products. the spiral sequence is depicted in figure 8. 3. after the completion of the rst spiral w alk, the irs out- puts the tar get address of the rst pix el, (umin, vmin) and the control uwri , along with the initial (x, y) v al- ues of the ne xt spiral w alk. acc and uwri can be delayed by one clock c ycle by setting the control bit pipe to 1 (high) simplifying the task of interf acing the TMC2301 to b uf fered source image memory . 4. after the last c ycle of the ne xt spiral, uwri ag ain goes lo w for one clock, and the tar get address outputs are updated, pointing to the location of the pix el calculation just completed, (umin + 1, vmin). 5. the third spiral w alk be gins with acc going lo w , and ends with (umin + 2, vmin) output and uwri going lo w . figure 8. timing diagram and pixel map showing outward clockwise spiral walk generated by TMC2301 (2x2 kernel shown) clk 65-2301-13 x, y 11-0 ca 7-0 u, v 11-0 acc pipe = 0 uwri acc uwri next walk new u, v pipe = 1 notes: 1. assumes that oeta is low and noop is high. 2. timing parameters are not shown on this diagram.
TMC2301 product specification 16 6. the procedure continues until (umax + 1, vmin) is reached, at which point the de vice resets to u (position within ro w) and increments v (number of ro w). thus, the ne xt (u, v) set after (umax + 1, vmin) will be (umin, vmin + 1), follo wed by (umin + 1, vmin + 1), etc. 7. upon completion of the w alk corresponding to (umax + 1, vmax + 1), the TMC2301 will generate a done ag with the nal uwri , and be gin a ne w sequence. on an y gi v en clock c ycle, the actual (x, y) and (u, v) out- puts of the irs are gi v en by the follo wing equations: x = x 0 + dx/du 0 * m + dx/dv 0 * n + d 2 x/dudv * m * n + d 2 x/du 2 * (m2 ?m)/2 + d 2 x/dv 2 * (n 2 ?n)/2 + fo v * cax(w) + fo v * m * cax(k er) y = y 0 + dy/du 0 * m + dx/dv 0 * n + d 2 y/dudv * m * n + d 2 y/du 2 * (m2 ?m)/2 + d 2 y/dv 2 * (n 2 ?n)/2 + fo v * ca y(w) + fo v * m * ca y(k er) u = umin + m v = vmin + n where fo v is the 4-bit eld of vie w parameter , normally set to 1 so that the spiral w alk proceeds in single-pix el steps. setting fo v to 4 w ould e xpand the spiral w alk, allo wing the user to trade tw o bits of image size for tw o bits of additional interpix el positioning resolution. cax(w) and ca y(w) are the current v alue of the coef cient address outputs and cax(ker) and ca y(ker) are the terminal v alues of each pix el w alk. the ca(ker) terms arise because the irs com- putes each ne w w alk's starting paint from the pre vious spiral w alk's end point rather than its starting point. interpolation coef cient lookup t ab le ad dressing the e xternal coef cient lookup table ram stores the inter - polation v alues used to calculate the v alue of the ne w pix el. these v alues are selected by the user allo wing maximum l- tering e xibility . in simple ltering applications, all 8 bits of coef cient address are a v ailable to access up to 256 interpo- lation coef cients, for k ernels of 16 x 16 pix els. this address is generated by the internal w alk counter of the TMC2301. in most applications, the same k ernel parameter v alue is selected in both irs de vices; thus, the coef cient address outputs ca 7-0 for the x and y de vices are identical, and the user needs only one of the 8-bit b uses for memory access. applications e x ecuting a coordinate transformation, ho we v er will almost al w ays generate non-inte ger source pix el addresses; that is the u (or v) locations will not map to the x (or y) addresses e xactly and fractional address components are generated. the user then must account for this spatial of f- set in both dimensions by storing the appropriate corrected interpolation k ernel v alues in the lookup table. the 8-bit address b us is brok en up into tw o parts: the fractional portion (upper 4 bits), and the w alk counter (lo wer 4 bits). thus, in resampling applications, the maximum k ernel size is 4 x 4 pix els, or 16 locations. as in the ltering e xample, assuming that the user has selected the same k ernel size for both irs de vices, the 4 bits of least-signi cant address generated by both de vices will be identical and redundant. the four most signi cant address bits, ho we v er , will re ect the current frac- tional of fsets of the resampled pix el from the nearest x (y) location, to a spatial resolution of 4 bits in the x (or y) direc- tions. utilization of the 12 bits (total) of lookup table address is left to the user to be arranged as desired for memory access. see figure 3. application examples one of the more common applications for the TMC2301 is simple static ltering in this case the source and tar get mem- ories locations are identical and no coordinate transforma- tion is performed. the (x, y) and (u, v) outputs listed in t able 4 sho w the address sequencing generated by the TMC2301 to e x ecute the w alk of a 5 x 5 pix el interpolation k ernel. the normalized coef cients sho wn implement a rst- order butterw orth lo w p ass filter with cutof f radius of 1/ . note that the (u, v) output address is updated follo w- ing the completion of the w alk for that location. figure 9. pixel map showing walk sequence for 5x5 static filter 2 (0, 0) 65-2301-14 20 21 22 23 24 7 8 0 1 9 15 14 13 4 3 2 12 19 18 17 10 11 6 5 16
product specification TMC2301 17 t ab le 4. irs outputs f or static filter illustrated in figure 10 figure 10 illustrates the sequence for a bilinear resampling of a 63 rotation. the starting point is translated +1 in the y -direction. a common rotation matrix might be: dx/du 0 = cos (a) = .6 dy/du 0 = sin (a) = .8 dx/dv 0 = -sin (a) = -.8 dy/dv 0 = cos (a) = .6 cyc le x y inde x (ca) coef cient u v 1 2 3 4 5 6 7 3 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 3 4 4 3 2 2 2 3 4 5 5 5 5 4 3 2 1 1 1 1 2 3 4 5 4 4 4 5 5 5 4 3 3 3 3 4 5 6 6 6 6 6 5 4 3 2 2 2 2 2 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0 0.2176 0.0725 0.0435 0.0725 0.0435 0.0725 0.0435 0.0725 0.0435 0.0198 0.0272 0.0198 0.0128 0.0198 0.0272 0.0198 0.0128 0.0198 0.0272 0.0198 0.0128 0.0198 0.0272 0.0198 0.0128 0.2175 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ho we v er , we ha v e included a linear compression f actor of 5:1, and must accommodate the f act that each time u is incre- mented, the start of the ne w w alk is referenced to the end of the pre vious w alk. gi v en these corrections, the rotation matrix becomes: dx/du 0 = 5cos(a) = 3 dy/du 0 = 5sin(a) ?fo v = 3 dx/dv 0 = 5sin(a) = -4 dy/dv 0 = 5cos(a) = 3 k ernel = 1 figure 10. pixel map showing parameters for 63 rotation and 5:1 compression listed in table 5 65-2301-15 (0, 0) = -4 d x d v (0, 10) (0, 20) (10, 0) (20, 0) = 3 d x d u = 3 d y d v = 4 d y d u
TMC2301 product specification 18 t ab le 5. irs outputs f or operation illustrated in figure 11 figure 11 may help clarify the relationships among (x 0 , y 0 ), (xmin, ymin), (xmax, ymax), (umin, vmin), and (umax, vmax). w ith positi v e rst deri v ati v es, (x 0 , y 0 ) and (umin, vmin) represent the upper left corners of the original image and the ne w destination eld, respecti v ely . the lo wer right corner of the transformed image is located at cyc le x y inde x u v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 5 6 6 5 8 9 9 8 11 12 12 11 14 15 15 14 1 2 2 1 4 5 5 4 7 8 8 7 10 11 11 10 0 5 5 6 6 9 9 10 10 13 13 14 14 17 17 18 18 8 8 9 9 12 12 13 13 16 16 17 17 20 20 21 21 5 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 5 5 5 5 6 6 6 6 7 7 7 7 8 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 (umax + 1, vmax + 1); the location of the corresponding corner of the original image depends on the v alues of the deri v ati v es. not to be confused with (x 0 , y 0 ), the points (xmin, ymin) and (xmax, ymax) de ne the "usable" rectangular portion of the original image; points (x, y) lying outside this re gion are ignored in most resampling and lter - ing applications. this feature permits one to construct a mosaic of se v eral ab utting subimages in the (x, y) plane, without danger of edge ef fect interference between adjacent subimages. note in the gure that the upper right and lo wer right corners of the resampled image lie outside the admis- sible re gion; in practice, the v alues fetched at these locations will not be included in the con v olutional sums. figure 11. pixel maps demonstrating source and destination image boundaries and image clipping (note shaded area) 65-2301-15 (x 0 , y 0 ) y x (xmin, ymin) (umin, vmin) (umax, vmax) (xmax, ymin) note: assume 000h < x < fffh, 000h < y < fffh (xmax, ymax) czero = low (xmin, ymax) t t czero = low (u 0 , v 0 ) v u
product specification TMC2301 19 application note nearest neighbor operation?d ditional timing details example a, pipe = 0 inspecting figure 13: pipe = 0, ker = 0 (near neighbor), a ut oin = 1 (on), umn = 0, umx = 5, vmn = 0, vmx = 5, dx/du = 1, d y/d v = 1, xo = 0 first rising edge of clk after init f alling edge is #0. t able entries are e v ents after listed clock rising edge. end, done ags = 0, e xcept where sho wn as 1. uwri goes lo w and remains lo w with clk #2. example b, pipe = 1 no w , referring to figure 14: pipe = 1, ker = 0 (near neighbor), a ut oin = 1 (on), umn = 0, umx = 5,vmn = 0,vmx=5, dx/du = 1, d y/d v = 1, xo = 0 first rising edge of clk after init f alling edge is #0. t able entries are e v ents after listed clock rising edges. end, done, ags = 0, e xcept where sho wn as 1. uwri goes lo w with clk #3, stays lo w . otherwise, the tim- ing is the same as figure 13, i.e., pipeline delays uwri and a cc by one clock c ycle. bilinear interpolation example c, pipe = 0 from figure 15, we can see the follo wing: pipe = 0, ker = 1 (bilinear), a ut oin = 1 (on), umn = 0,umx = 5,vmn = 0,vmx=5, dx/du = 1, d y/d v = 1, y o = 0, xo = 0 first rising edge of clk after init f alling edge is #0. t able entries are e v ents after listed clock rising edges. end, done ags = 0, e xcept where sho wn as 1. clk x u v end don comments r c 0 0 0 first clock after init falling edge 1 0 0 2 0 0 0 first v alid x addresses = xo 3 1 0 0 0 0 second x; first valid u, v = umn, vmn 4 2 1 0 0 0 5 3 2 0 1 0 end r o w ag 3 cycles bef ore last x 6 4 3 0 0 0 7 5 4 0 0 0 8 6 5 0 0 0 last x of rst ro w 9 0 6 0 0 0 last u , v or rst ro w; rst x of 2nd ro w 10 1 0 1 0 0 first u , v of second ro w 11 2 1 1 0 0 12 3 2 1 1 0 end r o w ag 4 cycles bef ore last u , v 13 4 3 1 0 0 14 5 4 1 0 0 15 6 5 1 0 0 last x of second row 16 0 6 1 0 0 last u, v of second row u = umx + 1 35 5 4 4 0 1 end col goes high before last x 36 6 5 4 0 1 last x of v = vmx ? ro w 37 0 6 4 0 1 first x of last (v = vmx) row 38 1 0 5 0 1 first u , v = umn, vmx of last no w 39 2 1 5 0 1 40 3 2 5 1 1 last end r o w ag of fr ame 41 4 3 5 0 1 end col goes lo w when done goes high 42 5 4 5 0 0 1 done immediately before last x 43 6 5 5 0 0 last x of frame 44 0 6 5 0 0 last u, v = umx + 1, vmx 45 1 0 0 0 0 first u , v = umn, vmn of ne w fr ame 46 2 1 0 0 0 47 3 2 0 1 0 first end row flag of new frame clk x u v end r o w uwr a cc don comments 0 1 0 1st clk after init f alling edge 1 0 0 2 0 1 0 1st valid x address = xo: start 1st accum 3 1 0 1 4 1 1 1 5 0 1 1 end 1st 2x2 k er nel; end 1st a ccum 6 1 0 0 1 0 1st v alid u, v = umn, vmn; 2nd a ccum star t 7 2 0 0 0 1 8 2 0 0 1 1 9 1 0 0 1 1 10 2 1 0 1 0 2nd v alid u, v = umn + 1, vmn 11 3 1 0 0 1 12 3 1 0 1 1 13 2 1 0 1 1 14 3 2 0 1 0 3rd v alid u, v = umn + 2, vmn 15 4 2 0 0 1 16 4 2 0 1 1 17 3 2 0 1 1 end 4th 2x2 k er nel 160 5 3 5 1 1 1 161 4 3 5 1 1 1 162 5 4 5 1 1 0 begin ne xt-to-last x-w alk 163 6 5 4 1 0 1 164 6 5 4 1 1
TMC2301 product specification 20 p erf orming lar g er interpolation k ernels w ith pipe = 0, a ut oinit = 1, and the follo wing de nitions: t xdone = clock c ycle of nal x address of a transform. t x end = clock c ycle of nal x address along a ro w . ker = (k + 1)(k + 1), where k is the v alue in the ? ernel size" parameter re gister . the follo wing relationships hold true: first x address v alid 3 rising clock edges after inlts f ailing edge. end fla g goes high for ker c ycles at clock c ycle t x end ?1 ?2*ker. otherwise stated, end is acti v e for one w alkaround starting tw o w alkarounds and one c ycle prior to the nal source address of a ro w . done fla g goes high for one c ycle at clock c ycle t xdone ?1. otherwise stated, done is acti v e for one clock c ycle one c ycle prior to the last source address of the nal w alkaround. 165 5 4 5 1 1 166 6 5 5 1 0 begin last x-w alk 167 7 5 5 0 1 168 7 5 5 1 1 1 169 6 5 5 1 1 last x of frame 170 0 6 5 1 0 171 1 6 5 0 1 172 1 6 5 1 1 173 0 6 5 1 1 last u, v = umx + 1, vmx 174 1 0 0 1 0 first u, v of ne w fr ame 175 2 0 0 0 1 176 2 0 0 1 1 177 1 0 0 1 1 clk x u v end r o w uwr a cc don comments example d , ker = 0 (nearest neighbor), umin = 0, umax = 3, umin = 0, vmax = 2 if rst clock edge after init goes lo w is 0, then: first x, y out (= xo, y o) appears after clock edge 2. first u, v out (= 0, 0) appears after clock edge 3. end is high after clock edge 13 only . done is high after clock edge 16. last x out appears after clock edge 16. last u, v out (= 4, 2) appears after clock edge 17. example e, ker = 1, (1 pass bilinear), umin = 0, umax = 4, vmin = 1,vmax = 3 if rst clock edge after init goes lo w is 0, then: first x, y out (= xo, y o) appears after clock edge 2. first u, v out (= 0, 1) appears after clock edge 6 and remains through edges 7, 8 and 9. end is high after clock edge 92, goes lo w after 96. done is high after clock edge 100 only . last x out appears clock edge 101. last u, v out (= 5, 3) appears after clock edge 102 and remains through edges 103, 104 and 105.
product specification TMC2301 21 figure 12. v003 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 0 ker = 0 pipe = 0 umin = 0 umax = 5 vmin = 0 vmax = 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 1 2 3 4 6 0 5 1 2 3 4 6 0 2 4 6 0 2 4 5 0 0 2 4 0 0 1 1 3 5 2 3 4 6 0 5 1 2 3 4 5 1 2 3 4 6 0 5 1 2 3 4 5 5 5 1 3 5 1 3 5 1 2 3 5 4 0 v002 v001 v000 u003 u002 u001 u000 done endr init noop accr uwri clok ldrc y003 y002 y001 y000 x003 x002 x001 x000 done endr init noop accr uwri clok ldrc 65-2301-17
TMC2301 product specification 22 figure 13. v003 v002 v001 v000 u003 u002 u001 u000 done endr init noop accr uwri clok ldrc y003 y002 y001 y000 x003 x002 x001 x000 done endr init noop accr 65-2301-18 uwri clok ldrc ker = 0 pipe = 0 umin = 0 umax = 5 vmin = 0 vmax = 5 0 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 3 5 1 3 5 1 3 5 1 3 5 1 3 5 1 1 3 3 5 5 2 3 4 6 5 0 1 0 2 0 2 4 6 8 1 0 0 1
product specification TMC2301 23 figure 14 v003 v002 v001 v000 u003 u002 u001 u000 done endr init noop accr uwri clok ldrc y003 y002 y001 y000 x003 x002 x001 x000 done endr init noop accr uwri clok ldrc ker = 1 pipe = 0 1 0 0 0 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 2 2 1 1 1 1 4 6 6 6 6 0 0 5 5 5 7 7 1 1 1 1 1 3 3 3 3 2 2 2 2 4 10 10 10 10 12 12 0 0 11 11 11 11 4 1 1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 7 1 7 1 7 1 7 1 7 1 7 1 7 1 7 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 8 1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 7 1 7 1 7 1 7 1 7 1 7 1 7 1 7 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 8 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 5 2 4 6 7 umin = 0 umax = 5 vmin = 0 vmax = 5 65-2301-19
TMC2301 product specification 24 mec hanical dimensions 68 lead pin grid arra y l a2 a ? ?2 a1 p e d1 pin 1 identifier d see note 5 see note 1 beveled corner vendor option a .080 .125 2.03 3.18 symbol inches min. max. min. max. millimeters notes a1 .040 .060 1.02 1.52 .190 4.83 a2 .115 2.92 ? .017 .020 0.43 0.51 d 1.140 1.180 28.96 29.97 d1 .120 .140 3.05 3.56 e .050 nom. 1.27 nom. 1.000 bsc 25.40 bsc .100 bsc 2.54 bsc l .003 .076 m 11 11 68 68 2 3 n p ?2 notes: 1. 2. 3. 4. 5. pin #1 identifier shall be within shaded area shown. dimension "m" defines matrix size. dimension "n" defines the maximum possible number of pins. controlling dimension: inch. optional index pin.
product specification TMC2301 25 mec hanical dimensions (contin ued) 68 lead plastic leaded chip carrier -c- b lead coplanarity ccc c d d1 e1 e j a d3/e3 e j b1 a1 a2 a .165 .200 4.19 5.08 symbol inches min. max. min. max. millimeters notes a1 .090 .130 2.29 3.30 a2 .020 .51 b .013 .021 .33 .53 d/e .985 .995 25.02 25.27 d1/e1 .950 .958 24.13 24.33 d3/e3 .800 bsc 20.32 bsc .050 bsc 1.27 bsc e j .042 .056 1.07 1.42 2 3 nd/ne 17 17 68 68 n ccc .004 0.10 b1 .026 .032 .66 .81 notes: 1. 2. 3. all dimensions and tolerances conform to ansi y14.5m-1982 corner and edge chamfer (j) = 45 dimension d1 and e1 do not include mold protrusion. allowable protrusion is .101" (.25mm)
TMC2301 product specification 2/23/99 0.0m 002 stock# ds70002301 1999 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com or dering inf ormation pr oduct number t emperature rang e screening p ac ka g e p ac ka g e marking TMC2301g8c std? a = 0 c to 70 c commercial 68 pin gr id arr a y 2301g8c TMC2301g8c1 std? a = 0 c to 70 c commercial 68 pin gr id arr a y 2301g8c1 TMC2301g8c2 std? a = 0 c to 70 c commercial 68 pin gr id arr a y 2301g8c2 TMC2301h8c std? a =0 c to 70 c commercial 68 pin gr id arr a y 2301h8c TMC2301h8c1 std? a = 0 c to 70 c commercial 68 pin gr id arr a y 2301h8c1 TMC2301h8c2 std? a = 0 c to 70 c commercial 68 pin gr id arr a y 2301h8c2 TMC2301r1c std-t a = 0 c to 70 c commercial 68 lead plastic j-leaded chip carr ier 2301r1c TMC2301r1c1 std t a = 0 c to 70 c commercial 68 lead plastic j-leaded chip carr ier 2301r1c1 TMC2301r1c2 std-t a = 0 c to 70 c commercial 68 lead plastic j-leaded chip carr ier 2301r1c2

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