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? 2001 microchip technology inc. ds40151c-page 1 hcs512 features security ? secure storage of manufacturer?s code secure storage of transmitter?s keys up to four transmitters can be learned k ee l oq ? code hopping technology normal and secure learning mechanisms operating 3.0v ? 6.0v operation 4 mhz rc oscillator learning indication on lrnout auto baud rate detection power saving sleep mode other stand alone decoder on-chip eeprom for transmitter storage four binary function outputs?15 functions 18-pin dip/soic package typical applications automotive remote entry systems automotive alarm systems automotive immobilizers gate and garage openers electronic door locks identity tokens burglar alarm systems compatible encoders hcs200, hcs300, hcs301, hcs360, hcs361 ntq106 description the microchip technology inc. hcs512 is a code hop- ping decoder designed for secure remote keyless entry (rke) systems. the hcs512 utilizes the pat- ented k ee l oq code hopping system and high security learning mechanisms to make this a canned solution when used with the hcs encoders to implement a uni- directional remote keyless entry system. package type block diagram the manufacturer?s code, transmitter keys, and syn- chronization information are stored in protected on- chip eeprom. the hcs512 uses the data and clk inputs to load the manufacturer?s code which cannot be read out of the device. the hcs512 operates over a wide voltage range of 3.0 volts to 6.0 volts. the decoder employs automatic baud rate detection which allows it to compensate for wide variations in transmitter data rate. the decoder contains sophisticated error checking algorithms to ensure only valid codes are accepted. hcs512 pdip, soic 1 2 3 4 5 6 7 8 9 lrnin lrnout nc mclr gnd s0 s1 s2 s3 18 17 16 15 14 13 12 11 10 rfin nc oscin osc out v dd data clk sleep v low s0 s1 s3 s2 v low 67-bit reception register eeprom control decryptor output sel rfin oscillator oscin control lrnout data clk lrnin mclr sleep k ee l oq ? code hopping decoder k eeloq is a registered trademark of microchip technology, inc. microchip ? s secure data products are covered by some or all of the following patents: code hopping encoder patents issued in europe, u.s.a., and r.s.a. ? u.s.a.: 5,517,187; europe: 0459781; r.s.a.: za93/4726 secure learning patents issued in the u.s.a. and r.s.a. ? u.s.a.: 5,686,904; r.s.a.: 95/5429
hcs512 ds40151c-page 2 ? 2001 microchip technology inc. 1.0 k ee l oq system overview 1.1 key terms manufacturer ? s code ? a 64-bit word, unique to each manufacturer, used to produce a unique encoder key in each transmitter (encoder). encoder key ? a 64-bit key, unique for each trans- mitter. the encoder key controls the decryption algorithm and is stored in eeprom on the decoder device. learn ? the receiver uses information that is transmitted to derive the transmitter ? s secret key, decrypt the discrimination value and the synchro- nization counter in learning mode. the encoder key is a function of the manufacturer ? s code and the device serial number and/or seed value. the hcs encoders and decoders employ the k ee l oq code hopping technology and an encryption algorithm to achieve a high level of security. code hopping is a method by which the code transmitted from the trans- mitter to the receiver is different every time a button is pushed. this method, coupled with a transmission length of 66 bits, virtually eliminates the use of code ? grabbing ? or code ? scanning ? . 1.2 hcs encoder overview the hcs encoders have a small eeprom array which must be loaded with several parameters before use. the most important of these values are: a 28-bit serial number which is meant to be unique for every encoder an encoder key that is generated at the time of production a 16-bit synchronization value the serial number for each encoder is programmed by the manufacturer at the time of production. the generation of the encoder key is done using a key gen- eration algorithm (figure 1-1). typically, inputs to the key generation algorithm are the serial number of the encoder and a 64-bit manufacturer ? s code. the manu- facturer ? s code is chosen by the system manufacturer and must be carefully controlled. the manufacturer ? s code is a pivotal part of the overall system security. figure 1-1: creation and storage of encoder key during production transmitter manufacturer ? s serial number or code encoder key key generation algorithm serial number encoder key sync counter . . . hcsxxx eeprom array seed
? 2001 microchip technology inc. ds40151c-page 3 hcs512 the 16-bit synchronization value is the basis for the transmitted code changing for each transmission and is updated each time a button is pressed. because of the complexity of the code hopping encryption algorithm, a change in one bit of the synchronization value will result in a large change in the actual transmitted code. there is a relationship (figure 1-3) between the key values in eeprom and how they are used in the encoder. once the encoder detects that a button has been pressed, the encoder reads the button and updates the synchronization counter. the synchroniza- tion value is then combined with the encoder key in the encryption algorithm, and the output is 32 bits of encrypted information. this data will change with every button press, hence, it is referred to as the hopping portion of the code word. the 32-bit hopping code is combined with the button information and the serial number to form the code word transmitted to the receiver. 1.3 hcs decoder overview before a transmitter can be used with a particular receiver, the transmitter must be ? learned ? by the receiver. upon learning a transmitter, information is stored by the receiver so that it may track the transmitter, including the serial number of the transmitter, the current synchronization value for that transmitter, and the same encoder key that is used on the transmitter. if a receiver receives a message of valid format, the serial number is checked and, if it is from a learned transmitter, the message is decrypted and the decrypted synchronization counter is checked against what is stored. if the synchronization value is verified, then the button status is checked to see what operation is needed. figure 1-3 shows the relationship between some of the values stored by the receiver and the values received from the transmitter. figure 1-2: basic operation of transmitter (encoder) figure 1-3: basic operation of receiver (decoder) k ee l oq algorithm button press information encryption eeprom array 32 bits of encrypted data serial number transmitted information encoder key sync counter serial number button press information eeprom array encoder key 32-bits of encrypted data serial number received information decrypted synchronization counter check for match check for match k ee l oq algorithm decryption sync counter serial number manufacturer ? s code
hcs512 ds40151c-page 4 ? 2001 microchip technology inc. 2.0 pin assignment pin decoder function i/o (1) buffer type (1) description 1 lrnin i ttl learn input - initiates learning, 10k pull-up required on input 2 lrnout o ttl learn output - indicates learning 3nc ? ttl do not connect 4mclr i st master clear input 5ground p ? ground connection 6s0 ottl switch 0 7s1 ottl switch 1 8s2 ottl switch 2 9s3 ottl switch 3 10 vlow o ttl battery low indication output 11 sleep i ttl connect to rfin to allow wake-up from sleep 12 clk i/o ttl/st (2) clock in programming mode and synchronous mode 13 data i/o ttl/st (2) data in programming mode and synchronous mode 14 v dd p ? power connection 15 osc out ?? oscillator out ? no connection 16 osc in (4 mhz) i st oscillator in ? recommended values 10 k ? and 10pf 17 nc ?? 18 rfin i ttl rf input from receiver note 1: p = power, i = in, o = out, and st = schmitt trigger input. 2: pin 12 and pin 13 have a dual purpose. after reset, these pins are used to determine if programming mode is selected in which case they are the clock and data lines. in normal operation, they are the clock and data lines of the synchronous data output stream.
? 2001 microchip technology inc. ds40151c-page 5 hcs512 3.0 description of functions 3.1 parallel interface the hcs512 activates the s3, s2, s1 & s0 outputs according to table 3-1 when a new valid code is received. the outputs will be activated for approxi- mately 500 ms. if a repeated code is received during this time, the output extends for approximately 500 ms. table 3-1: function output table 3.2 serial interface the decoder has a pwm/synchronous interface con- nection to microcontrollers with limited i/o. an output data stream is generated when a valid transmission is received. the data stream consists of one start bit, four function bits, one bit for battery status, one bit to indi- cate a repeated transmission, two status bits, and one stop bit. (table 3-1). the data and clk lines are used to send a synchronous event message. a special status message is transmitted on the second pass of learn. this allows the controlling microcontrol- ler to determine if the learn was successful (result = 1) and if a previous transmitter was overwritten (overwrite = 1). the status message is shown in figure 3-2. table 3-2 show the values for tx1:0 and the number of transmitters learned. table 3-2: status bits figure 3-1: data output format figure 3-2: status message format a 1-wire pwm or 2-wire synchronous interface can be used. in 1-wire mode, the data is transmitted as a pwm signal with a basic pulse width of 400 s. in 2-wire mode, synchronous mode pwm bits start on the rising edge of the clock, and the bits must be sampled on the falling edge. the start and stop bits are ? 1 ? . figure 3-3: pwm transmission format function code s3 s2 s1 s0 0001 0 0 0 1 0010 0 0 1 0 0011 0 0 1 1 0100 0 1 0 0 0101 0 1 0 1 0110 0 1 1 0 01110111 1000 1 0 0 0 1001 1 0 0 1 1010 1 0 1 0 10111011 11001100 11011101 1110 1 1 1 0 1111 1 1 1 1 tx1 tx0 number of transmitters 00 one 01 two 10 three 11 four start s3 s2 s1 s0 v low tx1 tx0 stop repeat start0000 result tx1 tx0 stop ovrwr s3 start s2s1s0v low rpt reserved reserved stop 1200s clk data ? 1 ?? 0 ? 600s
hcs512 ds40151c-page 6 ? 2001 microchip technology inc. 4.0 decoder operation 4.1 learning a transmitter to a receiver either the serial number-based learning method or the seed-based learning method can be selected. the learning method is selected in the configuration byte. in order for a transmitter to be used with a decoder, the transmitter must first be ? learned ? . when a transmitter is learned to a decoder, the decoder stores the encoder key, a check value of the serial number and current synchronization value in eeprom. the decoder must keep track of these values for every transmitter that is learned. the maximum number of transmitters that can be learned is four. the decoder must also contain the manufacturer ? s code in order to learn a transmitter. the manufacturer ? s code will typically be the same for all decoders in a system. the hcs512 has four memory slots. after an ? erase all ? procedure, all the memory slots will be cleared. erase all is activated by taking lrnin low for approxi- mately 10 seconds. when a new transmitter is learned, the decoder searches for an empty memory slot and stores the transmitter ? s information in that memory slot. when all memory slots are full, the decoder randomly overwrites existing transmitters. 4.1.1 learning procedure learning is activated by taking the lrnin input low for longer than 64 ms. this input requires an external pull- up resistor. to learn a new transmitter to the hcs512 decoder, the following sequence is required: 1. enter learning mode by pulling lrnin low for longer than 64 ms. the lrnout output will go high. 2. activate the transmitter until the lrnout out- put goes low indicating reception of a valid code (hopping message). 3. activate the transmitter a second time until the lrnout toggles for 4 seconds (in secure learn- ing mode, the seed transmission must be trans- mitted during the second stage of learn by activating the appropriate buttons on the trans- mitter). if lrnin is taken low momentarily during the learn status indication, the indication will be ter- minated. once a successful learning sequence is detected, the indication can be terminated allowing quick learning in a manufacturing setup. 4. the transmitter is now learned into the decoder. 5. repeat steps 1-4 to learn up to four transmitters. 6. learning will be terminated if two non-sequential codes were received or if two acceptable codes were not decoded within 30 seconds. the following checks are performed on the decoder to determine if the transmission is valid during learn: the first code word is checked for bit integrity. the second code word is checked for bit integrity. the hopping code is decrypted. if all the checks pass, the serial number and syn- chronization counters are stored in eeprom memory. figure 4-1 shows a flow chart of the learn sequence. figure 4-1: learn sequence 4.2 validation of codes the decoder waits for a transmission and checks the serial number to determine if the transmitter has been learned. if learned, the decoder decrypts the encrypted portion of the transmission using the encoder key. it uses the discrimination bits to determine if the decryp- tion was valid. if everything up to this point is valid, the synchronization value is evaluated. enter learn mode wait for reception of second compare discrimination value with serial number use generated key to decrypt equal serial number check value synchronization counter ? exit learn successful. store: learn unsuccessful no yes wait for reception of a valid code non-repeated valid code generate key from serial number or seed value encoder key
? 2001 microchip technology inc. ds40151c-page 7 hcs512 4.3 validation steps validation consists of the following steps: search eeprom to find the serial number check value match decrypt the hopping code compare the 10 bits of discrimination value with the lower 10 bits of serial number check if the synchronization counter falls within the first synchronization window. check if the synchronization counter falls within the second synchronization window. if a valid transmission is found, update the syn- chronization counter, else use the next transmitter block and repeat the tests. figure 4-2: decoder operation 4.4 synchronization with decoder the k ee l oq technology features a sophisticated synchronization technique (figure 4-3) which does not require the calculation and storage of future codes. if the stored counter value for that particular transmitter and the counter value that was just decrypted are within a formatted window of 16, the counter is stored and the command is executed. if the counter value was not within the single operation window, but is within the double operation window of 16k, the transmitted syn- chronization value is stored in a temporary location, and it goes back to waiting for another transmission. when the next valid transmission is received, it will check the new value with the one in temporary storage. if the two values are sequential, it is assumed that the counter was outside of the single operation ? window ? , but is now back in sync, so the new synchronization value is stored and the command executed. if a trans- mitter has somehow gotten out of the double operation window, the transmitter will not work and must be relearned. since the entire window rotates after each valid transmission, codes that have been used become part of the ? blocked ? (48k) codes and are no longer valid. this eliminates the possibility of grabbing a previ- ous code and retransmitting it to gain entry. figure 4-3: synchronization window 4.5 sleep mode the sleep mode of the hcs512 is used to reduce cur- rent consumption when no rf input signal is present. sleep mode will only be effective in systems where the rf receiver is relatively quiet when no signal is present. during sleep, the clock stops, thereby significantly reducing the operating current. sleep mode is enabled by the sleep bit in the configuration byte. the hcs512 will enter sleep mode when: the rf line is low after a function output is switched off learn mode is terminated (time-out reached) the device will not enter sleep mode when: a function output is active learn sequence active device is in programming mode the device will wake up from sleep when: the sleep input pin changes state the clock line changes state ? transmission received does ser # check val match ? decrypt transmission is decryption valid ? is counter within 16 ? is counter within 32k ? update counter execute command save counter in temp location start no no no no yes yes yes yes yes no and note: during sleep mode the clk line will change from an output line to an input line that can be used to wake up the device. connect clk to lrnin via a 100k resistor to reliably enter the learn mode whenever sleep mode is active. blocked entire window rotates to eliminate previously used codes current position (48k codes) double operation (16k single operation window (16 codes) codes)
hcs512 ds40151c-page 8 ? 2001 microchip technology inc. 5.0 integrating the hcs512 into a system the hcs512 can act as a stand alone decoder or be interfaced to a microcontroller. typical stand alone applications include garage door openers and elec- tronic door locks. in stand alone applications, the hcs512 will handle learning, reception, decryption, and validation of the received code; and generate the appropriate output. for a garage door opener, the hcs512 input will be connected to an rf receiver, and the output, to a relay driver to connect a motor control- ler. typical systems where the hcs512 will be connected to a microcontroller include vehicle and home security systems. the hcs512 input will be connected to an rf receiver and the function outputs to the microcontroller. the hcs512 will handle all the decoding functions and the microcontroller, all the system functions. the serial output mode with a 1- or 2-wire interface can be used if the microcontroller is i/o limited. 6.0 decoder programming the pg306001 production programmer will allow easy setup and programming of the configuration byte and the manufacturer ? s code. 6.1 configuration byte the configuration byte is used to set system configura- tion for the decoder. the lrn bits determine which algorithm (decrypt or xor) is used for the key genera- tion. sc_lrn determines whether normal learn (key derived from serial number) or secure learn (key derived from seed value) is used. table 6-1: configuration byte table 6-2: learn method lrn0, lrn1 definitions bit name description 0 lrn0 learn algorithm select 1 lrn1 not used 2 sc_lrn secure learn enable (1 = enabled) 3 sleep sleep enable (1 = enabled) 4 res1 not used 5 res2 not used 6 res3 not used 7 res4 not used lrn0 description 0 decrypt algorithm 1 xor algorithm
? 2001 microchip technology inc. ds40151c-page 9 hcs512 6.2 programming the manufacturer?s code the manufacturer ? s code must be programmed into eeprom memory through the synchronous program- ming interface using the data and clk lines. provision must be made for connections to these pins if the decoder is going to be programmed in circuit. programming mode is activated if the clk is low for at least 1ms and then goes high within 64 ms after power- up, stays high for longer than 8ms but not longer than 128 ms. after entering programming mode the 64-bit manufacturer ? s code, 8-bit configuration byte, and 8-bit checksum is sent to the device using the synchronous interface. after receiving the 80-bit message the check- sum is verified and the information is written to eeprom. if the programming operation was success- ful, the hcs512 will respond with an acknowledge pulse. after programming the manufacturer ? s code, the hcs512 decoder will automatically activate an erase all function, removing all transmitters from the system. 6.3 download format the manufacturer ? s code and configuration byte must be downloaded least significant byte, least significant bit first as shown in table 6-3. 6.4 checksum the checksum is used by the hcs512 to check that the data downloaded was correctly received before pro- gramming the data. the checksum is calculated so that the 10 bytes added together (discarding the overflow bits) is zero. the checksum can be calculated by add- ing the first 9 bytes of data together and subtracting the result from zero. throughout the calculation the over- flow is discarded. given a manufacturer ? s code of 01234567- 89abcdef 16 and a configuration word of 1 16 , the checksum is calculated as shown in figure 6-1. the checksum is 3f 16 . 6.5 test transmitter the hcs512 decoder will automatically add a test transmitter each time an erase all function is done. a test transmitter is defined as a transmitter with a serial number of zero. after an erase all, the test transmitter will always work without learning and will not check the synchronization counter of the transmitter. learning of any new transmitters will erase the test transmitter. table 6-3: download data figure 6-1: checksum calculation note 1: a transmitter with a serial number of zero cannot be learned. learn will fail after the first transmission. 2: always learn at least one transmitter after an erase all sequence. this ensures that the test transmitter is erased. byte 9 byte 8 byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 check- sum config man key_7 man key_6 man key_5 man key_4 man key_3 man key_2 man key_1 man key_0 byte 0, right-most bit downloaded first. 01 16 + 23 16 = 24 6 24 16 + 45 16 = 69 16 69 16 + 67 16 = d0 16 d0 16 + 89 16 = 159 16 59 16 + ab 16 = 104 16 (carry is discarded) 04 16 + cd 16 = d1 16 (carry is discarded) d1 16 + ef 16 = 1c0 16 c0 16 + 1 16 = c1 16 (carry is discarded) (ff 16 - c1 16 ) + 1 16 = 3f 16
hcs512 ds40151c-page 10 ? 2001 microchip technology inc. figure 6-2: programming waveforms table 6-4: programming timing requirements bit1 bit0 bit78 bit79 ack mclr clk (clock) dat (data) enter program mode acknowledge pulse t ps t ph1 t ckl t ckh t ack t ph2 80-bit data package parameter symbol min. max. units program mode setup time tps 1 64 ms hold time 1 tph1 8 128 ms hold time 2 tph2 0.05 320 ms clock high time tckh 0.05 320 ms clock low time tckl 0.050 320 ms acknowledge time tack ? 80 ms note: f osc equals 4 mhz.
? 2001 microchip technology inc. ds40151c-page 11 hcs512 7.0 key generation schemes the hcs512 decoder has two key generation schemes. normal learning uses the transmitter ? s serial number to derive two input seeds which are used as inputs to the key generation algorithm. secure learning uses the seed transmission to derive the two input seeds. two key generation algorithms are available to convert the inputs seeds to secret keys. the appropriate scheme is selected in the configuration word. figure 7-1: 7.1 normal learning (serial number derived) the two input seeds are composed from the serial number in two ways, depending on the encoder type. the encoder type is determined from the number of bits in the incoming transmission. sourceh is used to calculate the upper 32 bits of the encoder key, and sourcel, for the lower 32 bits. for 24-bit serial number encoders (56-bit transmissions): sourceh = 65h + 24 bit serial number sourcel = 2bh + 24 bit serial number for 28-bit serial number encoders (66 / 67-bit transmissions): sourceh = 6h + 28 bit serial number sourcel = 2h + 28 bit serial number 7.2 secure learning (seed derived) the two input seeds are composed from the seed value that is transmitted during secure learning. the lower 32 bits of the seed transmission is used to compose the lower seed, and the upper 32 bits, for the upper seed. the upper 4 bits (function code) are set to zero. for 32-bit seed encoders: sourceh = serial number lower 28 bits with upper 4 bits always zero sourcel = seed 32 bits for 48-bit seed encoders: sourceh = seed upper 16 bits + serial number upper 16 bits with upper 4 bits always zero sourcel = seed lower 32 bits for 64-bit seed encoders: note: 64-bit seeds are handled as 48-bit seeds sourceh = seed upper 16 bits + serial number upper 16 bits with upper 4 bits always zero sourcel = seed lower 32 bits seed patched serial number key generation algorithms ------------------- decrypt xor encoder key manufacturer ? s key
hcs512 ds40151c-page 12 ? 2001 microchip technology inc. 7.3 key generation algorithms there are two key generation algorithms implemented in the hcs512 decoder. the k ee l oq decryption algorithm pro- vides a higher level of security than the xor algorithm. section 6.1 describes the selection of the algorithms in the con- figuration byte. 7.3.1 k ee l oq decrypt algorithm this algorithm uses the k ee l oq decryption algorithm and the manufacturer ? s code to derive the encoder key as follows: key upper 32 bits = f k ee l oq decrypt (sourceh) | 64 bit manufacturers code key lower 32 bits = f k ee l oq decrypt (sourcel) | 64 bit manufacturers code 7.3.2 xor with the manufacturer ? s code the two 32-bits seeds are xor with the manufacturer ? s code to form the 64 bit encoder key. key upper 32 bits = sourceh ? manufacturers code | upper 32 bits key lower 32 bits = sourcel ? manufacturers code | lower 32 bits after programming the manufacturer ? s code, the hcs512 decoder will automatically activate an erase all function, removing all transmitters from the system. if lrnin is taken low momentarily during the learn status indication, the indication will be terminated. once a successful learning sequence is detected, the indication can be terminated, allowing quick learning in a manufacturing set up. figure 7-2: hcs512 key generation k ee l oq decryption algorithm padding 6/65 28/24-bit serial number padding 2/2b 28/24-bit serial number ms 32 bits of encoder key ls 32 bits of encoder key sc_lrn = 0 lrn0 = 0 k ee l oq decryption algorithm padding 0000b ms 28 bits of seed transmission ls 32 bits of seed transmission ms 32 bits of encoder key ls 32 bits of encoder key sc_lrn = 1 xor padding 0000b ms 28 bits of seed transmission ls 32 bits of seed transmission ms 32 bits of encoder key ls 32 bits of encoder key lrn0 = 1
? 2001 microchip technology inc. ds40151c-page 13 hcs512 8.0 k ee l oq encoders 8.1 transmission format (pwm) the k ee l oq encoder transmission is made up of sev- eral parts (figure 8-1). each transmission begins with a preamble and a header, followed by the encrypted and then the fixed data. the actual data is 56/66/67 bits which consists of 32 bits of encrypted data and 24/34/ 35 bits of non-encrypted data. each transmission is followed by a guard period before another transmission can begin. the encrypted portion provides up to four billion changing code combinations and includes the button status bits (based on which buttons were acti- vated) along with the synchronization counter value and some discrimination bits. the non-encrypted por- tion is comprised of the status bits, the function bits, and the 24/28-bit serial number. the encrypted and non-encrypted combined sections increase the number of combinations to 7.38 x 10 19 . 8.2 code word organization the hcsxxx encoder transmits a 66/67-bit code word when a button is pressed. the 66/67-bit word is con- structed from an encryption portion and a non- encrypted code portion (figure 8-2). the encrypted data is generated from four button bits, two overflow counter bits, ten discrimination bits, and the 16-bit synchronization value. the non-encrypted data is made up from 2 status bits, 4 function bits, and the 28/32-bit serial number. figure 8-1: code word transmission format figure 8-2: code word organization logic ? 0 ? logic ? 1 ? bit period preamble header encrypted portion of transmission fixed portion of transmission guard time t p t h t hop t fix t g repeat vlow (1 bit) button sta- tus (4 bits) 28-bit serial number button status (4 bits) discrimina- tion bits (12 bits) 16-bit sync value crc1* crc0* 3/2 bits + serial number and but- ton status (32 bits) + 32 bits of encrypted data encrypted data non-encrypted data *hcs360/361 66/67 bits of data transmitted
hcs512 ds40151c-page 14 ? 2001 microchip technology inc. 9.0 electrical characteristics for hcs512 absolute maximum ratings ? ambient temperature under bias ................................................................................................. ........... -55 c to +125 c storage temperature ............................................................................................................ .................. -65 c to +150 c voltage on any pin with respect to v ss (except v dd )........................................................................ -0.6v to v dd +0.6v voltage on v dd with respect to vss........................................................................................................... ........0 to +7.5v total power dissipation (note 1) ............................................................................................... ............................800 mw maximum current out of v ss pin ........................................................................................................................... 150 ma maximum current into v dd pin ........................................................................................................................... ...100 ma input clamp current, iik (v i < 0 or v i > v dd ) ......................................................................................................... 20 ma output clamp current, iok (v o < 0 or v o >v dd ) .................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin.................................................................................. ...................20 ma note: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd ? v oh ) x i oh } + (v o l x i ol ) ? notice: stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
? 2001 microchip technology inc. ds40151c-page 15 hcs512 table 9-1: dc characteristics table 9-2: ac characteristics figure 9-1: reset watchdog timer, oscillator start-up timer and power-up timer timing standard operating conditions (unless otherwise stated) operating temperature commercial (c): 0 c t a +70 c for commercial industrial (i): -40 c t a +85 c for industrial symbol characteristic min typ ( ? ) max units conditions v dd supply voltage 3.0 ? 6.0 v v por v dd start voltage to ensure reset ? v ss ? v s vdd v dd rise rate to ensure reset 0.05* ?? v/ms i dd supply current ? ? 1.8 7.3 15 4.5 10 32 ma ma a f osc = 4 mhz, v dd = 5.5v (during eeprom programming) in sleep mode v il input low voltage v ss ? 0.16 v dd vexcept mclr = 0.2 v dd v ih input high voltage 0.48 v dd ? v dd v except mclr = 0.85 v dd v ol output low voltage ?? 0.6 v i ol = 8.5 ma, v dd = 4.5v v oh output high voltage v dd -0.7 ?? vi oh = -3.0 ma, v dd = 4.5v ? data in ? typ ? column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. *these parameters are characterized but not tested. note: negative current is defined as coming out of the pin. symbol characteristic min typ max units conditions f osc oscillator frequency 2.7 4 6.21 mhz rext = 10k, cext = 10pf t e pwm elemental pulse width 65 ? 1080 s 4.5v < v dd < 5.5v oscillator components tolerance < 6%. 130 ? 1080 s 3v < vdd < 6v oscillator components tolerance <10% t od output delay 70 90 115 ms t a output activation time 322 500 740 ms t rpt repeat activation time 32 50 74 ms t lrn lrnin activation time 21 32 ? ms t mclr mclr low time 150 ?? ns t ov time output valid ? 150 222 ms v dd mclr i/o pins t ov tmclr
hcs512 ds40151c-page 16 ? 2001 microchip technology inc. figure 9-2: output activation rfin s[3,2,1,0] lrnout 0s 1s 2s 3s 4s 5s 1 code word 50ms tod t a t a v low note 1: output is activated as long as code is received. 2: output is activated if battery low (v low ) is detected. note 2 note 1
? 2001 microchip technology inc. ds40151c-page 17 hcs512 figure 9-3: typical decoder application circuit s1 s2 s3 lrnout s0 v d d g n d g n d v dd low voltage detector ? do not omit vi vo 10k v dd 10k 10 pf 14 p2 5 v dd 10k 1 receive data input 1 2 3 12v gnd 1n4004/7 100 f power supply g n d lm7805 vi vo v dd nc rfin lrnin lrnout s0 s1 s2 s3 v low sleep clk dat mclr nc osc in osc out 4 3 16 15 learn button vlow p3 1k 1k 1k 1k 1k 1k 100f p4 p3 p2 in circuit 17 18 1 2 6 7 8 9 10 11 12 13 hcs512 p4 100k programming pads data clock reset gnd p1
hcs512 ds40151c-page 18 ? 2001 microchip technology inc. hcs512 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. sales and support package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (300 mil body), 18-lead temperature range: blank = 0 c to +70 c i =-40 c to +85 c device: hcs512 code hopping decoder hcs512t code hopping decoder (tape and reel) hcs512 ? /p data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide web site (www.microchip.com)
? 2001 microchip technology inc. ds40151c-page 19 hcs512 ? all rights reserved. copyright ? 2001, microchip technology incorporated, usa. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip ? s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. ? trademarks the microchip name, logo, pic, picmicro, picmaster, picstart, pro mate, k ee l oq , seeval, mplab and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. total endurance, icsp, in-circuit serial programming, filterlab, mxdev, microid, flexrom, fuzzylab, mpasm, mplink, mplib, picdem, icepic, migratable memory, fansense, economonitor, selectmode and microport are trademarks of microchip technology incorporated in the u.s.a. serialized quick term programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2001, microchip technology incorporated, printed in the u.s.a., all rights reserved. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.
information contained in this publication regarding device applications and the like is intended through suggestion only and ma y be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warrant y is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patent s or other intellectual property rights arising from such use or otherwise. use of microchip ? s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec- tual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and othe r countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds40151c-page 20 ? 2001 microchip technology inc. all rights reserved. ? 2001 microchip technology incorporated. printed in the usa. 2/01 printed on recycled paper. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 austin analog product sales 8303 mopac expressway north suite a-201 austin, tx 78759 tel: 512-345-2030 fax: 512-345-6085 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 boston analog product sales unit a-8-1 millbrook tarry condominium 97 lowell road concord, ma 01742 tel: 978-371-6400 fax: 978-371-0050 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 dayton two prestige place, suite 130 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 mountain view analog product sales 1300 terra bella avenue mountain view, ca 94043-1836 tel: 650-968-9241 fax: 650-967-1590 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing microchip technology beijing office unit 915 new china hong kong manhattan bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - shanghai microchip technology shanghai office room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 hong kong microchip asia pacific rm 2101, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o ? 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