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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 p0 6 /int2/a-d4 x out h sync v sync p0 0 /pwm0 p0 1 /pwm1 p0 2 /pwm2 p0 3 /pwm3 p0 4 /pwm4 p0 5 /pwm5 p0 7 /int1 p2 3 /tim3 p2 4 /tim2 p2 5 p2 6 p2 7 d-a p3 2 cnv ss x in v ss p5 2 /r p5 3 /g p5 4 /b p5 5 /out1 p2 0 /s clk p2 1 /s out p2 2 /s in p1 0 /out2 p1 1 /scl1 p1 2 /scl2 p1 3 /sda1 p1 4 /sda2 p1 5 /a-d1/int3 p1 6 /a-d2 p3 0 /a-d5/da1 p3 1 /a-d6/da2 reset osc1/p3 3 osc2/p3 4 v cc p1 7 /a-d3 M37221ef-xxxsp M37221efsp pin configuration (top view) ? crt display function number of display characters ................ 24 characters 5 2 lines (16 lines maximum) kinds of characters ..................................................... 256 kinds dot structure .......................................................... 12 5 16 dots kinds of character sizes .................................................. 3 kinds kinds of character colors (it can be specified by the character) maximum 7 kinds (r, g, b) kinds of character background colors (it can be specified by the character) maximum 7 kinds (r, g, b) kinds of raster colors (maximum 7 kinds) display position horizontal .................................................................. 64 levels vertical .................................................................... 128 levels bordering (horizontal and vertical) application tv outline 42p4b description the M37221ef-xxxsp and M37221efsp are single-chip microcom- puters designed with cmos silicon gate technology. they are housed in a 42-pin shrink plastic molded dip. in addition to their simple instruction sets, the rom, ram and i/o addresses are placed on the same memory map to enable easy pro- gramming. the M37221ef-xxxsp and M37221efsp have a pwm output func- tion and a osd display function, so it is useful for a channel selection system for tv. features ? number of basic instructions ..................................................... 71 ? memory size rom ........................................................ 62 k bytes ram ....................................................... 1216 bytes rom for display ......................................... 8 k bytes ram for display .......................................... 96 bytes ? the minimum instruction execution time ......................................... 0.5 m s (at 8 mhz oscillation frequency) ? power source voltage .................................................. 5 v 10 % ? power dissipation............................................................. 165 mw (at 8 mhz oscillation frequency, v cc =5.5v, at crt display) ? subroutine nesting ....................................... 96 levels (maximum) ? interrupts ....................................................... 14 types, 14 vectors ? 8-bit timers .................................................................................. 4 ? programmable i/o ports (ports p0, p1, p2, p3 0 Cp3 2 ) .............. 27 ? input ports (ports p3 3 , p3 4 ) ......................................................... 2 ? output ports (ports p5 2 Cp5 5 ) ...................................................... 4 ? 12 v withstand ports .................................................................... 6 ? led drive ports ........................................................................... 4 ? serial i/o ............................................................ 8-bit 5 1 channel ? multi-master i 2 c-bus interface ............................... 1 (2 systems) ? a-d comparator (6-bit resolution) ................................ 6 channels ? d-a converter (6-bit resolution) ................................................... 2 ? pwm output circuit ......................................... 14-bit 5 1, 8-bit 5 6 ? rom correction function ........................................... 32 bytes 5 2 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller M37221ef-xxxsp,M37221efsp mitsubishi microcomputers
M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 2 functional block diagram of M37221ef-xxxsp out1 clock input clock output x in x out reset input v cc v ss cnv ss clock output for display input ports p3 3, p3 4 osc1 osc2 clock input for display int2 int1 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 p5 (4) b g r h sync v sync a-d comparator 14-bit pwm circuit 8-bit pwm circuit accumulator a (8) timer 4 t4 (8) timer 3 t3 (8) timer 2 t2 (8) timer 1 t1 (8) timer count source selection circuit tim2 tim3 instruction register (8) instruction decoder control signal crt circuit stack pointer s (8) index register y (8) index register x (8) processor status register ps (8) 8-bit arithmetic and logical unit rom 62 k bytes program counter pc l (8) program counter pc h (8) ram 1216 bytes data clock generating circuit reset output ports p5 2 Cp5 5 address bus si/o(8) s in s clk s out int3 109876543 i/o port p0 2829303132333435 p1 (8) i/o port p1 15141312 11363738 p2 (8) i/o port p2 i/o ports p3 0 Cp3 2 172627 16 p3 (3) p0 (8) 39 40 41 42 2 1 20 19 25 22 21 18 24 23 ( ) timing output d-a d-a converter out2 multi-master i c-bus interface 2 M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 3 71 0.5 m s (the minimum instruction execution time, at 8 mhz oscillation fre- quency) 8 mhz (maximum) 62 k bytes 1216 bytes 8 k bytes 96 bytes 8-bit 5 1 (n-channel open-drain output structure, can be used as pwm output pins, int input pins, a-d input pin) 4-bit 5 1 (cmos input/output structure, can be used as crt output pin, a-d input pins, int input pin) 4-bit 5 1 (cmos input/output structure, can be used as multi-master i 2 c- bus interface) 2-bit 5 1 (cmos input/output or n-channel open-drain output structure, can be used as serial i/o pins) 6-bit 5 1 (cmos input/output structure, can be used as serial input pin, external clock input pins) 2-bit 5 1 (cmos input/output or n-channel open-drain output structure, can be used as a-d input pins, d-a conversion output pins) 1-bit 5 1 (n-channel open-drain output structure) 2-bit 5 1 (can be used as crt display clock i/o pins) 4-bit 5 1 (cmos output structure, can be used as crt output pins) 8-bit 5 1 1 (2 systems) 6 channels (6-bit resolution) 2 (6-bit resolution) 14-bit 5 1, 8-bit 5 6 8-bit timer 5 4 32 bytes 5 2 96 levels (maximum) external interrupt 5 3, internal timer interrupt 5 4, serial i/o interrupt 5 1, crt interrupt 5 1, multi-master i 2 c-bus interface interrupt 5 1, f(x in )/4096 interrupt 5 1, v sync interrupt 5 1, brk interrupt 5 1 2 built-in circuits (externally connected a ceramic resonator or a quartz- crystal oscillator) 5 v 10 % 165 mw typ. (at oscillation frequency f cpu = 8 mhz, f crt = 8 mhz) 110 mw typ. (at oscillation frequency f cpu = 8 mhz) 1.65 mw (maximum) C10 c to 70 c cmos silicon gate process 42-pin shrink plastic molded dip 24 characters 5 2 lines (maximum 16 lines by software) 12 5 16 dots 256 kinds 3 kinds maximum 7 kinds (r, g, b); can be specified by the character 64 levels (horizontal) 5 128 levels (vertical) parameter functions functions number of basic instructions instruction execution time clock frequency memory size input/output ports serial i/o multi-master i 2 c-bus interface a-d comparator d-a converter pwm output circuit timers rom correction function subroutine nesting interrupt clock generating circuit power source voltage power dissipation operating temperature range device structure package crt display function rom ram crt rom crt ram p0 p1 0 , p1 5 Cp1 7 p1 1 Cp1 4 p2 0 , p2 1 p2 2 Cp2 7 p3 0 , p3 1 p3 2 p3 3 , p3 4 p5 2 Cp5 5 i/o i/o i/o i/o i/o i/o i/o input output crt on crt off in stop mode number of display characters dot structure kinds of characters kinds of character sizes kinds of character colors display position (horizontal, vertical) M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 4 power source cnv ss reset input clock input clock output i/o port p0 pwm output external interrupt input analog input i/o port p1 crt output multi-master i 2 c-bus interface analog input external interrupt input i/o port p2 external clock input serial i/o synchro- nizing clock input/ output serial i/o data input/output i/o port p3 analog input d-a conversion output input port p3 clock input for crt display clock output for crt display v cc , v ss. cnv ss ______ reset x in x out p0 0 /pwm0C p0 5 /pwm5, p0 6 /int2/ a-d4 , p0 7 /int1 p1 0 /out2, p1 1 /scl1, p1 2 /scl2, p1 3 /sda1, p1 4 /sda2, p1 5 /a-d1/ int3, p1 6 /a-d2, p1 7 /a-d3 p2 0 /s clk , p2 1 /s out , p2 2 /s in , p2 3 /tim3, p2 4 /tim2, p2 5 Cp2 7 p3 0 /a-d5/ da1, p3 1 /a-d6/ da2, p3 2 p3 3 /osc1, p3 4 /osc2 input input output i/o output input input i/o output i/o input input i/o input i/o i/o i/o input output input input output apply voltage of 5 v 10 % (typical) to v cc , and 0 v to v ss . this is connected to v ss . to enter the reset state, the reset input pin must be kept at a l for 2 m s or more (under normal v cc conditions). if more time is needed for the quartz-crystal oscillator to stabilize, this l condition should be maintained for the required time. this chip has an internal clock generating circuit. to control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins x in and x out . if an external clock is used, the clock source should be connected to the x in pin and the x out pin should be left open. port p0 is an 8-bit i/o port with direction register allowing each i/o bit to be individually programmed as input or output. at reset, this port is set to input mode. the output structure is n-channel open-drain output. the note out of this table gives a full of port p0 function. pins p0 0 Cp0 5 are also used as pwm output pins pwm0Cpwm5 respectively. the output structure is n-channel open-drain output. pins p0 6 , p0 7 are also used as external interrupt input pins int2, int1 respectively. p0 6 pin is also used as analog input pin a-d4. port p1 is an 8-bit i/o port and has basically the same functions as port p0. the output structure is cmos output. pins p1 0 is also used as crt output pin out2. the output structure is cmos output. pins p1 1 Cp1 4 are used as scl1, scl2, sda1 and sda2 respectively, when multi-master i 2 c-bus interface is used. the output structure is n-channel open-drain output. pins p1 5 Cp1 7 are also used as analog input pins a-d1 to a-d3 respectively. p1 5 pin is also used as external interrupt input pin int3. port p2 is an 8-bit i/o port and has basically the same functions as port p0. the output structure is cmos output. pins p2 3 , p2 4 are also used as external clock input pins tim3, tim2 respectively. p2 0 pin is also used as serial i/o synchronizing clock input/output pin s clk . the output structure is n-channel open-drain output. pins p2 1 , p2 2 are also used as serial i/o data input/output pins s out , s in respectively. the output structure is n-channel open-drain output. ports p3 0 Cp3 2 are a 3-bit i/o port and has basically the same functions as port p0. either cmos output or n-channel open-drain output structure can be selected as the port p3 0 and p3 1 . the output structure of port p3 2 is n-channel open-drain output. pins p3 0 , p3 1 are also used as analog input pins a-d5, a-d6 respectively. pins p3 0 , p3 1 are also used as d-a conversion output pins da1, da2 respectively. ports p3 3 , p3 4 are a 2-bit input port. p3 3 pin is also used as crt display clock input pin osc1. p3 4 pin is also used as crt display clock output pin osc2. the output structure is cmos output. pin description pin name functions input/ output M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 5 output port p5 crt output h sync input v sync input da output pin description (continued) p5 2 /r, p5 3 /g, p5 4 /b, p5 5 /out1 h sync v sync d-a ports p5 2 Cp5 5 are a 4-bit output port. the output structure is cmos output. pins p5 2 Cp5 5 are also used as crt output pins r, g, b, out1 respectively. the output structure is cmos output. this is a horizontal synchronizing signal input for crt. this is a vertical synchronizing signal input for crt. this is a 14-bit pwm output pin. output output input input output note : as shown in the memory map (figure 3), port p0 is accessed as a memory at address 00c0 16 of zero page. port p0 has the port p0 direction register (address 00c1 16 of zero page) which can be used to program each bit as an input (0) or an output (1). the pins programmed as 1 in the direction register are output pins. when pins are programmed as 0, they are input pins. when pins are programmed as output pins, the output data are written into the port latch and then output. when data is read from the output pins, the output pin level is not read but the data of the port latch is read. this allows a previously-output value to be read correctly even if the output l voltage has risen, for example, because a light emitting diode was directly driven. the input pins are in the floating state, so the values of the pins can be read. when data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state. M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 6 cpu mode register the cpu mode register contains the stack page selection bit. the cpu mode register is allocated at address 00fb 16 . functional description central processing unit (cpu) the M37221ef-xxxsp uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine in- structions or the series 740 M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 7 memory special function register (sfr) area the special function register (sfr) area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom rom is used for storing user programs as well as the interrupt vector area. ram for display ram for display is used for specifying the character codes and col- ors to display. rom for display rom for display is used for storing character data. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function registers (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the spe- cial page area. the special page addressing mode can be used to specify memory addresses in the special page area. access to this area with only 2 bytes is possible in the special page addressing mode. 0000 16 00c0 16 00ff 16 01ff 16 06b7 16 0800 16 sfr area rom correction memory (ram) not used ffff 16 ffde 16 ff00 16 0600 16 interrupt vector area not used 10000 16 11fff 16 1ffff 16 rom for display (8 k bytes) special page rom (62 k bytes) ram for display (note) (96 bytes) zero page ram (448 bytes) 05ff 16 0300 16 ram (768 bytes) 02ff 16 02c0 16 0217 16 not used 2 page register not used 021b 16 note: refer to table 12. contents of crt display ram. fig. 2. memory map M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 8 fig. 3. memory map of sfr (special function register) (1) p30s p31s pw0 pw1 pw2 pw3 pw4 pw5 pw6 pw7 pn2 pn3 pn4 sm0 sm1 sm2 sm3 sm5 sm6 b7 b0 ? 00 16 b7 b0 ? 00 16 ? 00 16 ? ? ? ? ? 0 0 0 0 0 00 0 00 0 ? ? 0 0 0 0 00 0 00 0 ? ? ? ? ? 0 0 00 0 00 0 ? 0 0 ? ? ? ? ? ? ? ? ? ? ? 00 16 0 0 00 0 00 0 ? 0 0 00 0 00 0 ? ? 0 0 ? ? ?? ? ? 0 0 ? ? ?? ? ? ? da1s da2s da10 da11 da12 da13 da14 da15 da20 da21 da22 da23 da24 da25 sad0 sad1 sad2 sad3 sad4 sad5 sad6 rbw lrb ad0 aas al pin bb trx mst bc0 bc1 bc2 es0 als 10 bit sad bsel0 bsel1 ccr0 ccr1 ccr2 ccr3 ccr4 fast mode ack bit ack 00 16 00 16 00 16 0 0 00 0 1? 0 0 : 0 immediately after reset : fix this bit to 0 (do not write 1) : nothing is allocated n sfr area (addresses c0 16 to df 16 ) : 1 immediately after reset : undefined immediately after reset 1 ? d0 16 d1 16 d2 16 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 c0 16 c1 16 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c9 16 cb 16 cc 16 cd 16 ce 16 cf 16 ca 16 address port p5 (p5) port p5 direction register (d5) port p3 output mode control register (p3s) da-h register (da-h) da-l register (da-l) pwm0 register (pwm0) port p1 (p1) port p1 direction register (d1) port p3 (p3) port p3 direction register (d3) port p2 (p2) port p2 direction register (d2) register port p0 (p0) port p0 direction register (d0) pwm1 register (pwm1) pwm2 register (pwm2) pwm3 register (pwm3) pwm4 register (pwm4) pwm output control register 1 (pw) pwm output control register 2 (pn) serial i/o mode register (sm) serial i/o regsiter (sio) da1 conversion register (da1) da2 conversion register (da2) bit allocation state immediately after reset i c data shift register (s0) 2 i c address register (s0d) 2 i c status register (s1) 2 i c control register (s1d) 2 i c clock control register (s2) 2 M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 9 fig. 4. memory map of sfr (special function register) (2) b7 b0 hr0 hr1 hr2 hr3 hr4 hr5 cv10 cv11 cv12 cv13 cv14 cv15 cv16 cv20 cv21 cv22 cv23 cv24 cv25 cv26 cs10 cs11 cs20 cs21 md10 md20 co01 co02 co03 co05 aaa aaa co11 co12 co13 co15 co21 co22 co23 co25 co31 co32 co33 co35 cc0 cc1 cc2 vsyc r/g/b out1 op5 op6 op7 hsyc ck0 ck1 adm0 adm1 adm2 adm4 a a a aaa adc0 adc1 a a a aaa adc2 adc4 adc3 adc5 aaa aaa t34m0 aaa aaa t34m1 t34m2 t34m3 t34m4 aaa aaa t12m0 aaa aaa t12m1 t12m2 t12m3 t12m4 ck0 re5 re4 re3 cm2 aaa aaa tm1r aaa aaa tm2r tm3r tm4r crtr vscr it3r ck0 aa aa msr 1t1r 1t2r s1r aaa a a a aaa tm1e aaa a a a aaa tm2e tm3e tm4e crte vsce it3e 1t1e 1t2e s1e mse t34m5 ? aaa aaa aaa aaa b7 b0 a a aa a a aa aa aa aa aa aa aa aa aa aa aa ck0 aa aa aa aa aa aa ck0 a a a aaa aa a a aa aa a a aa aa a a aa aa a a aa aa a a aa aa a a aa aaa a a a aaa 00000000 0 ?????? ? 0 ?????? ? ???? 0000 ?? 00000 0 00000000 ? 00 16 aa aa aaa aaa aaa aaa aaa aaa aa aa 00 00 00 0 aa aa 0 ? 00 0 00 0 0 00 00 00 0 0 ff 16 07 16 ff 16 07 16 00 00 00 0 0 00 00 00 0 0 ? ? ? aaaaaaaaaaaaa aaaaaaaaaaaaa 00 00 aaa aaa 0? aa aa 0 1 aa aa 1 aaa aaa 0 00 00 0 0 00 00 00 0 0 a a aa 00 00 00 0 0 00 00 00 0 0 00 00 16 aaa aaa 1 aa aa aaa aaa 11 aa aa 1 aaa aaa aaa aaa 00 0 00 00 0 0 0 0 00 00 0 0 0 0 00 00 0 0 0 0 00 00 0 0 0 co04 co14 co24 co34 co06 co16 co26 co36 co07 co17 co27 co37 cc7 out2 iicr iice f0 16 f1 16 f2 16 f3 16 f4 16 f5 16 f6 16 f7 16 f8 16 f9 16 fa 16 fb 16 fc 16 fd 16 fe 16 ff 16 e0 16 e1 16 e2 16 e3 16 e4 16 e5 16 e6 16 e7 16 e8 16 e9 16 eb 16 ec 16 ed 16 ee 16 ef 16 ea 16 address crt control register (cc) crt port control register (crtp) a-d control register 1 (ad1) a-d control register 2 (ad2) timer 1 (tm1) vertical register 2 (cv2) color register 0 (co0) color register 1 (co1) character size register (cs) border selection register (md) register horizontal register (hr) vertical register 1 (cv1) timer 2 (tm2) timer 3 (tm3) timer 4 (tm4) timer 12 mode register (t12m) timer 34 mode register (t34m) pwm5 register (pwm5) interrupt input polarity register (re) test register (test) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) color register 2 (co2) color register 3 (co3) crt clock selection register (ck) cpu mode register (cpum) bit allocation state immediately after reset aa aa 0 : ??immediately after reset aa aa : fix this bit to ??(do not write ?? : nothing is allocated n sfr area (addresses e0 16 to ff 16 ) : ??immediately after reset : undefined immediately after reset 1 ? : fix this bit to ??(do not write ?? M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 10 fig. 5. memory map of 2 page register 210 16 211 16 212 16 213 16 214 16 215 16 216 16 217 16 218 16 219 16 21a 16 21b 16 21c 16 21d 16 21e 16 21f 16 200 16 201 16 202 16 203 16 204 16 205 16 206 16 207 16 208 16 209 16 20b 16 20c 16 20d 16 20e 16 20f 16 20a 16 b7 b0 rcr1 aa aa aaa aaa aa aa b7 b0 ? ? ? ? 0 0 0 00 aaa aaa 0 00 rcr0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? address register rom correction address 1 (high-order) bit allocation state immediately after reset 0 : ??immediately after reset aa aa : fix this bit to ??(do not write ?? : nothing is allocated n sfr area (addresses 200 16 to 21f 16 ) rom correction address 1 (low-order) rom correction address 2 (high-order) rom correction address 2 (low-order) rom correction enable register (rcr) M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 11 interrupts interrupts can be caused by 14 different sources consisting of 4 ex- ternal, 8 internal, 1 software, and reset. interrupts are vectored inter- rupts with priorities shown in table 1. reset is also included in the table because its operation is similar to an interrupt. when an interrupt is accepted, (1) the contents of the program counter and processor status register are automatically stored into the stack. (2) the interrupt disable flag i is set to 1 and the corresponding interrupt request bit is set to 0. (3) the jump destination address stored in the vector address enters the program counter. other interrupts are disabled when the interrupt disable flag is set to 1. all interrupts except the brk instruction interrupt have an interrupt request bit and an interrupt enable bit. the interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. figure 7 shows the structure of the interrupt-related registers. interrupts other than the brk instruction interrupt and reset are ac- cepted when the interrupt enable bit is 1, interrupt request bit is 1, and the interrupt disable flag is 0. the interrupt request bit can be set to 0 by a program, but not set to 1. the interrupt enable bit can be set to 0 and 1 by a program. reset is treated as a non-maskable interrupt with the highest priority. figure 6 shows interrupt control. interrupt causes (1) v sync and crt interrupts the v sync interrupt is an interrupt request synchronized with the vertical sync signal. the crt interrupt occurs after character block display to the crt is completed. (2) int1, int2, int3 interrupts with an external interrupt input, the system detects that the level of a pin changes from l to h or from h to l, and generates an interrupt request. the input active edge can be selected by bits 3, 4 and 5 of the interrupt input polarity register (address 00f9 16 ) : when this bit is 0, a change from l to h is de- tected; when it is 1, a change from h to l is detected. note that all bits are cleared to 0 at reset. (3) timer 1, 2, 3 and 4 interrupts an interrupt is generated by an overflow of timer 1, 2, 3 or 4. (4) serial i/o interrupt this is an interrupt request from the clock synchronous serial i/o function. priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vector addresses ffff 16 , fffe 16 fffd 16 , fffc 16 fffb 16 , fffa 16 fff9 16 , fff8 16 fff5 16 , fff4 16 fff3 16 , fff2 16 fff1 16 , fff0 16 ffef 16 , ffee 16 ffed 16 , ffec 16 ffeb 16 , ffea 16 ffe9 16 , ffe8 16 ffe7 16 , ffe6 16 ffe5 16 , ffe4 16 ffdf 16 , ffde 16 interrupt source reset crt interrupt int2 interrupt int1 interrupt timer 4 interrupt f(x in )/4096 interrupt v sync interrupt timer 3 interrupt timer 2 interrupt timer 1 interrupt serial i/o interrupt multi-master i 2 c-bus interface interrupt int3 interrupt brk instruction interrupt remarks non-maskable active edge selectable active edge selectable active edge selectable active edge selectable non-maskable (software interrupt) table 1. interrupt vector addresses and priority M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 12 (5) f(x in )/4096 interrupt this interrupt occurs regularly with a f(x in )/4096 period. set bit 0 of the pwm output control register 1 to 0. (6) multi-master i 2 c-bus interface interrupt this is an interrupt related to the multi-maseter i 2 c-bus inter- face. (7) brk instruction interrupt this software interrupt has the least significant priority. it does not have a corresponding interrupt enable bit, and it is not af- fected by the interrupt disable flag i (non-maskable). fig. 6. interrupt control interrupt request bit interrupt enable bit interrupt disable flag i brk instruction reset interrupt request M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 13 fix this bit to 0. int3 polarity switch bit 0 : positive polarity 1 : negative polarity interrupt input polarity register (re : address 00f9 16 ) fix these bits to 0. int1 polarity switch bit 0 : positive polarity 1 : negative polarity int2 polarity switch bit 0 : positive polarity 1 : negative polarity 7 0 00 interrupt request register 1 (ireq1 : address 00fc 16 ) 0 : no interrupt request issued 1 : interrupt request issued interrupt request register 2 (ireq2 : address 00fd 16 ) serial i/o interrupt request bit fix this bit to 0. 7 int1 interrupt request bit 0 int2 interrupt request bit f(x in )/4096 interrupt request bit 0 0 : interrupt disabled 1 : interrupt enabled serial i/o interrupt enable bit 7 interrupt control register 2 (icon2 : address 00ff 16 ) int1 interrupt enable bit 0 int2 interrupt enable bit fix this bit to 0. f(x in )/4096 interrupt enable bit 0 fix these bits to 0. 00 0 7 interrupt control register 1 (icon1 : address 00fe 16 ) timer 1 interrupt enable bit 0 timer 2 interrupt enable bit timer 3 interrupt enable bit timer 4 interrupt enable bit crt interrupt enable bit v sync interrupt enable bit int3 interrupt enable bit 7 timer 1 interrupt request bit 0 timer 2 interrupt request bit timer 3 interrupt request bit timer 4 interrupt request bit crt interrupt request bit v sync interrupt request bit int3 interrupt request bit 0 multi-master i c-bus interface interrupt request bit 2 multi-master i c-bus interface interrupt enable bit 2 fig. 7. structure of interrupt-related registers M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 14 timers the M37221ef-xxxsp has 4 timers: timer 1, timer 2, timer 3, and timer 4. all timers are 8-bit timer with the 8-bit timer latch. the timer block diagram is shown in figure 9. all of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. the value is set to a timer at the same time by writing a count value to the corresponding timer latch (addresses 00f0 16 to 00f3 16 ). the count value is decremented by 1. the timer interrupt request bit is set to 1 by a timer overflow at the next count pulse after the count value reaches 00 16 . (1) timer 1 timer 1 can select one of the following count sources: ? f(x in )/16 ? f(x in )/4096 the count source of timer 1 is selected by setting bit 0 of the timer 12 mode register (address 00f4 16 ). timer 1 interrupt request occurs at timer 1 overflow. (2) timer 2 timer 2 can select one of the following count sources: ? f(x in )/16 ? timer 1 overflow signal ? external clock from the p2 4 /tim2 pin the count source of timer 2 is selected by setting bits 4 and 1 of the timer 12 mode register (address 00f4 16 ). when timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8- bit prescaler. timer 2 interrupt request occurs at timer 2 overflow. (3) timer 3 timer 3 can select one of the following count sources: ? f(x in )/16 ? external clock from the h sync pin ? external clock from the p2 3 /tim3 pin the count source of timer 3 is selected by setting bits 5 and 0 of the timer 34 mode register (address 00f5 16 ) timer 3 interrupt request occurs at timer 3 overflow. (4) timer 4 timer 4 can select one of the following count sources: ? f(x in )/16 ? f(x in )/2 ? timer 3 overflow signal the count source of timer 3 is selected by setting bits 4 and 1 of the timer 34 mode register (address 00f5 16 ). when timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8- bit prescaler. timer 4 interrupt request occurs at timer 4 overflow. at reset, timers 3 and 4 are connected by hardware and ff 16 is automatically set in timer 3; 07 16 in timer 4. the f(x in )/16 is se- lected as the timer 3 count source. the internal reset is released by timer 4 overflow at these state, the internal clock is connected. at execution of the stp instruction, timers 3 and 4 are connected by hardware and ff 16 is automatically set in timer 3; 07 16 in timer 4. however, the f(x in )/16 is not selected as the timer 3 count source. so set bit 0 of the timer 34 mode register (address 00f5 16 ) to 0 before the execution of the stp instruction (f(x in )/16 is selected as the timer 3 count source). the internal stp state is released by timer 4 overflow at these state, the internal clock is connected. because of this, the program starts with the stable clock. the structure of timer-related registers is shown in figure 8. M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 15 fig. 8. structure of timer-related registers timer 2 count stop bit 0 : count start 1 : count stop 70 timer 12 mode register (t12m : address 00f4 16 ) timer 1 count source selection bit 0 : f(x in )/16 1 : f(x in )/4096 timer 2 count source selection bit 0 : internal clock 1 : external clock from p2 4 /tim2 pin timer 1 count stop bit 0 : count start 1 : count stop timer 2 internal count source selection bit 0 : f(x in )/16 1 : timer 1 overflow 70 timer 34 mode register (t34m : address 00f5 16 ) timer 3 count source selection bit 0 : f(x in )/16 1 : external clock timer 4 internal count source selection bit 0 : timer 3 overflow 1 : f(x in )/16 timer 3 count stop bit 0 : count start 1 : count stop timer 4 count stop bit 0 : count start 1 : count stop timer 4 count source selection bit 0 : internal clock 1 : f(x in )/2 timer 3 external count source selection bit 0 : external clock from p2 3 /tim3 pin 1 : external clock from h sync pin 0 fix this bit to ?. M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 16 fig. 9. timer block diagram timer 1 (8) 1/4096 1/2 1/8 timer 1 latch (8) 8 8 8 t12m0 t12m2 t12m4 t12m1 t12m3 timer 2 (8) timer 2 latch (8) 8 8 8 timer 3 (8) timer 3 latch (8) 8 8 8 timer 4 (8) timer 4 latch (8) 8 8 8 data bus timer 1 interrupt request timer 2 interrupt request t34m0 t34m2 t34m5 t34m4 t34m3 t34m1 x in p2 4 /tim2 p2 3 /tim3 selection gate : connected to black colored side at reset t12m : timer 12 mode register t34m : timer 34 mode register notes 1 : h pulse width of external clock inputs tim2 and tim3 needs 4 machine cycles or more. 2 : when the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal. 3 : in the stop mode or the wait mode, external clock inputs tim2 and tim3 cannot be used. ff 16 07 16 h sync reset stp instruction timer 3 interrupt request timer 4 interrupt request M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 17 serial i/o the M37221ef-xxxsp has a built-in serial i/o which can either trans- mit or receive 8-bit data in serial in the clock synchronous mode. the serial i/o block diagram is shown in figure 10. the synchroniz- ing clock i/o pin (s clk ), and data i/o pins (s out , s in ) also function as port p2. bit 2 of the serial i/o mode register (address 00dc 16 ) selects whether the synchronizing clock is supplied internally or externally (from the p2 0 /s clk pin). when an internal clock is selected, bits 1 and 0 select whether f(x in ) is divided by 4, 16, 32, or 64. bit 3 selects whether port p2 is used for serial i/o or not. to use the p2 2 /s in pin as the s in pin, set the bit 2 of the port p2 direction register (address 00c5 16 ) to 0. the operation of the serial i/o function is described below. the func- tion of the serial i/o differs depending on the clock source; external clock or internal clock. fig. 10. serial i/o block diagram 8 serial i/o shift register (8) data bus serial i/o interrupt request selection gate : connected to black colored side at reset. synchronization circuit frequency divider 1/8 1/4 1/16 sm1 sm0 serial i/o counter (8) sm5: lsb msb s sm2 1/2 sm6 x in p2 2 /s in p2 1 /s out p2 0 /s clk 1/2 sm3 p2 1 latch p2 0 latch sm3 (address 00dd 16 ) sm : serial i/o mode register note: when the data is set in the serial i/o register (address 00dd 16 ), the register functions as the serial i/o shift register. (note) M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 18 7 serial i/o mode register (sm : address 00dc 16 ) internal synchronizing clock selection bits b1 b0 0 0 : f(x in )/4 0 1 : f(x in )/16 1 0 : f(x in )/32 1 1 : f(x in )/64 0 0 synchronizing clock selection bit 0 : external clock 1 : internal clock serial i/o port selection bit 0 : p2 0 , p2 1 functions as port 1 : s clk , s out fix this bit to 0. transfer direction selection bit 0 : lsb first 1 : msb first serial input pin selection bit 0 : input signal from s in pin 1 : input signal from s out pin internal clockthe serial i/o counter is set to 7 during write cycle into the serial i/o register (address 00dd 16 ), and transfer clock goes h forcibly. at each falling edge of the transfer clock after the write cycle, serial data is output from the s out pin. transfer direction can be selected by bit 5 of the serial i/o mode register. at each rising edge of the transfer clock, data is input from the s in pin and data in the serial i/o register is shifted 1 bit. after the transfer clock has counted 8 times, the serial i/o counter becomes 0 and the transfer clock stops at h. at this time the inter- rupt request bit is set to 1. external clockwhen an external clock is selected as the clock source, the interrupt request is set to 1 after the transfer clock has counted 8 times. however, transfer operation does not stop, so con- trol the clock externally. use the external clock of 1mhz or less with a duty cycle of 50%. the serial i/o timing is shown in figure 12. when using an external clock for transfer, the external clock must be held at h for initializing the serial i/o counter. when switching between an internal clock and an external clock, do not switch during transfer. also, be sure to ini- tialize the serial i/o counter after switching. notes 1: on programming, note that the serial i/o counter is set by writing to the serial i/o register with the bit managing in- structions as seb and clb instructions. 2: when an external clock is used as the synchronizing clock, write transmit data to the serial i/o register at h of the transfer clock input level. fig. 11. structure of serial i/o mode register fig. 12. serial i/o timing (for lsb first) synchroninzing clock transfer clock serial i/o register write signal serial i/o output s out d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 (note) serial i/o input s in note : when an internal clock is selected, the s out pin is at high-impedance after transfer is completed. interrupt request bit is set to 1 M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 19 fig. 13. signals on serial i/o common transmission/reception mode serial i/o common transmission/reception mode by writing 1 to bit 6 of the serial i/o mode register, signals s in and s out are switched internally to be able to transmit or receive the serial data. figure 13 shows signals on serial i/o common transmission/recep- tion mode. note: when receiving the serial data after writing ff 16 to the serial i/o register. serial i/o shift register (8) ? ? clock p2 0 /s clk p2 1 /s out p2 2 /s in sm6 sm: serial i/o mode register M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 20 function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at f = 4 mhz) table 2. multi-master i 2 c-bus interface functions multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a circuit for serial communica- tions conformed with the philips i 2 c-bus data transfer format. this interface, having an arbitration lost detection function and a synchro- nous function, is useful for serial communications of the multi-mas- ter. figure 14 shows a block diagram of the multi-master i 2 c-bus inter- face and table 2 shows multi-master i 2 c-bus interface functions. this multi-master i 2 c-bus interface consists of the i 2 c address reg- ister, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register and other control circuits. item format communication mode scl clock frequency f : system clock = f(x in )/2 note: we are not responsible for any third partys infringement of patent rights or other rights attributable to the use of the con- trol function (bits 6 and 7 of the i 2 c control register at address 00da 16 ) for connections between the i 2 c-bus interface and ports (scl1, scl2, sda1, sda2). fig. 14. block diagram of multimaster i 2 c-bus interface i 2 c address register b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw noise elimination circuit serial data (sda) address comparator i 2 c data shift register b7 b0 data control circuit al circuit i 2 c clock control register system clock ( f ) interrupt generating circuit interrupt request signal (iicirq) b7 mst trx bb pin al aas ad0 lrb b0 i 2 c status register s1 internal data bus b7 b0 bsel1 bsel0 10bit sad als eso bc2 bc1 bc0 s1d i 2 c control register bit counter bb circuit clock control circuit noise elimination circuit serial clock (scl) b7 b0 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 clock division s0 s2 s0d M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 21 (1) i 2 c data shift register the i 2 c data shift register (s0 : address 00d7 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. the i 2 c data shift register is in a write enable status only when the es0 bit of the i 2 c control register (address 00da 16 ) is 1. the bit counter is reset by a write instruction to the i 2 c data shift register. when both the es0 bit and the mst bit of the i 2 c status register (address 00d9 16 ) are 1, the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift regis- ter is always enabled regardless of the es0 bit value. note: to write data into the i 2 c data shift register after setting the mst bit to 0 (slave mode), keep an interval of 8 machine cycles or more. (2) i 2 c address register the i 2 c address register (address 00d8 16 ) consists of a 7-bit slave address and a read/write bit. in the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the start condition are detected. n bit 0: read/write bit (rbw) not used in the 7-bit addressing mode. in the 10-bit addressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rbw) of the i 2 c address register. the rbw bit is cleared to 0 automatically when the stop condition is detected. n bits 1 to 7: slave address (sad0Csad6) these bits store slave addresses. regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. (3) i 2 c clock control register the i 2 c clock control register (address 00db 16 ) is used to set ack control, scl mode and scl frequency. n bits 0 to 4: scl frequency control bits (ccr0Cccr4) these bits control the scl frequency. refer to table 3. n bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to 0, the stan- dard clock mode is set. when the bit is set to 1, the high-speed clock mode is set. n bit 6: ack bit (ack bit) this bit sets the sda status when an ack clock ] is generated. when this bit is set to 0, the ack return mode is set and make sda l at the occurrence of an ack clock. when the bit is set to 1, the ack non-return mode is set. the sda is held in the h status at the oc- currence of an ack clock. however, when the slave address matches the address data in the reception of address data at ack bit = 0, the sda is automatically made l (ack is returned). if there is a mismatch between the slave address and the address data, the sda is automatically made h(ack is not returned). ] ack clock: clock for acknowledgement n bit 7: ack clock bit (ack) this bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. when this bit is set to 0, the no ack clock mode is set. in this case, no ack clock occurs after data transmission. when the bit is set to 1, the ack clock mode is set and the master generates an ack clock upon comple- tion of each 1-byte data transmission.the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (make sda h) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 c clock control register during transmitting. if data is written during transmitting, the i 2 c clock generator is reset, so that data cannot be transmitted nor- mally. fig. 15. structure of i 2 c address register sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw slave address i 2 c address register (s0d: address 00d8 16 ) read/write bit 70 M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 22 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 i 2 c clock control register (s2 : address 00db 16 ) 70 scl frequency control bits refer to table 3. scl mode specification bit 0 : standard clock mode 1 : high-speed clock mode ack bit 0 : ack is returned. 1 : ack is not returned. ack clock bit 0 : no ack clock 1 : ack clock table 3. set values of i 2 c clock control register and scl frequency (4) i 2 c control register the i 2 c control register (address 00da 16 ) controls data communica- tion format. n bits 0 to 2: bit counter (bc0Cbc2) these bits decide the number of bits for the next 1-byte data to be transmitted. an interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. when a start condition is received, these bits become 000 2 and the address data is always transmitted and received in 8 bits. n bit 3: i 2 c interface use enable bit (es0) this bit enables to use the multimaster i 2 c bus interface. when this bit is set to 0, the use disable status is provided, so the sda and the scl become high-impedance. when the bit is set to 1, use of the interface is enabled. when es0 = 0, the following is performed. ? pin = 1, bb = 0 and al = 0 are set (they are bits of the i 2 c status register at address 00d9 16 ). ? writing data to the i 2 c data shift register (address 00d7 16 ) is dis- abled. n bit 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0, the addressing format is selected, so that ad- dress data is recognized. when a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to (5) i 2 c status register, bit 1) is received, trans- mission processing can be performed. when this bit is set to 1, the free data format is selected, so that slave addresses are not recog- nized. n bit 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0, the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address register (ad- dress 00d8 16 ) are compared with address data. when this bit is set to 1, the 10-bit addressing format is selected, all the bits of the i 2 c address register are compared with address data. n bits 6 and 7: connection control bits between i 2 c-bus interface and ports (bsel0, bsel1) these bits controls the connection between scl and ports or sda and ports (refer to figure 17). scl frequency (at f = 4mhz, unit : khz) setting value of ccr4Cccr0 standard clock mode setting disabled setting disabled setting disabled setting disabled setting disabled 100 83.3 500/ccr value 17.2 16.6 16.1 high-speed clock mode setting disabled setting disabled setting disabled 333 250 400(note) 166 1000/ccr value 34.5 33.3 32.3 ccr4 0 0 0 0 0 0 0 1 1 1 ccr3 0 0 0 0 0 0 0 1 1 1 ccr2 0 0 0 0 1 1 1 1 1 1 ccr1 0 0 1 1 0 0 1 0 1 1 ccr0 0 1 0 1 0 1 0 1 0 1 note: at 400 khz in the high-speed clock mode, the duty is 40%. in the other cases, the duty is 50%. fig. 16. structure of i 2 c clock control register M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 23 (5) i 2 c status register the i 2 c status register (address 00d9 16 ) controls the i 2 c-bus inter- face status. the low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. n bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0. if ack is not returned, this bit is set to 1. except in the ack mode, the last bit value of received data is input. the state of this bit is changed from 1 to 0 by execut- ing a write instruction to the i 2 c data shift register (address 00d7 16 ). n bit 1: general call detecting flag (ad0) this bit is set to 1 when a general call ] whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave device receives control data after the general call. the ad0 bit is set to 0 by detecting the stop condition or start con- dition. ] general call: the master transmits the general call address 00 16 to all slaves. n bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data. in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to 1 in one of the following conditions. ? the address data immediately after occurrence of a start condition agrees with the slave address stored in the high-order 7 bits of the i 2 c address register (address 00d8 16 ). ? a general call is received. in the slave reception mode, when the 10-bit addressing format is selected, this bit is set to 1 with the following condition. ? when the address data is compared with the i 2 c address register (8 bits consisted of slave address and rbw), the first bytes agree. a the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 00d7 16 ). fig. 17. connection port control by bsel0 and bsel1 fig. 18. structure of i 2 c control register ? ??bsel0 scl1/p1 1 scl2/p1 2 ? ??bsel1 ? ??bsel0 sda1/p1 3 sda2/p1 4 ? ??bsel1 multi-master i 2 c-bus interface scl sda 7 bsel1 bsel0 10 bit sad als es0 bc2 bc1 bc0 0 connection control bits between i 2 c-bus interface and ports b7 b6 connection port 0 0 : none 0 1 : scl1, sda1 1 0 : scl2, sda2 1 1 : scl1, sda1, scl2, sda2 i 2 c control register (s1d : address 00da 16 ) bit counter (number of transmit/receive bits) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 i 2 c-bus interface use enable bit 0 : disabled 1 : enabled data format selection bit 0 : addressing format 1 : free data format addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 24 n bit 3: arbitration lost ] detecting flag (al) in the master transmission mode, when the sda is made l by any other device, arbitration is judged to have been lost, so that this bit is set to 1. at the same time, the trx bit is set to 0, so that immedi- ately after transmission of the byte whose arbitration was lost is com- pleted, the mst bit is set to 0. in the case arbitration is lost during slave address transmission, the trx bit is set to 0 and the recep- tion mode is set. consequently, it becomes possible to receive and recognize its own slave address transmitted by another master de- vice. ] arbitration lost: the status in which communication as a master is disabled. n bit 4: i 2 c-bus interface interrupt request bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the state of the pin bit changes from 1 to 0. at the same time, an interrupt request signal occurs to the cpu. the pin bit is set to 0 in synchronization with a falling of the last clock (in- cluding the ack clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the pin bit. when the pin bit is 0, the scl is kept in the 0 state and clock generation is disabled. figure 20 shows an interrupt request signal generating timing chart. the pin bit is set to 1 in one of the following conditions. ? executing a write instruction to the i 2 c data shift register (address 00d7 16 ). ? when the es0 bit is 0 ? at reset the conditions in which the pin bit is set to 0 are shown below: ? immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) ? immediately after completion of 1-byte data reception ? in the slave reception mode, with als = 0 and immediately after completion of slave address or general call address reception ? in the slave reception mode, with als = 1 and immediately after completion of address data reception n bit 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0, this bus system is not busy and a start condition can be generated. when this bit is set to 1, this bus system is busy and the occurrence of a start condition is disabled by the start condi- tion duplication prevention function (note). this flag can be written by software only in the master transmission mode. in the other modes, this bit is set to 1 by detecting a start condition and set to 0 by detecting a stop condition. when the es0 bit of the i 2 c control register (address 00da 16 ) is 0 and at reset, the bb flag is kept in the 0 state. n bit 6: communication mode specification bit (transfer direction specification bit: trx) this bit decides a direction of transfer for data communication. when this bit is 0, the reception mode is selected and the data of a trans- mitting device is received. when the bit is 1, the transmission mode is selected and address data and control data are output onto the sda in synchronization with the clock generated on the scl. when the als bit of the i 2 c control register (address 00da 16 ) is 0 in the slave reception mode is selected, the trx bit is set to 1 (transmit) if the least significant bit (r/w bit) of the address data trans- mitted by the master is 1. when the als bit is 0 and the r/w bit is 0, the trx bit is cleared to 0 (receive). the trx bit is cleared to 0 in one of the following conditions. ? when arbitration lost is detected. ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication preventing function (note). ? with mst = 0 and when a start condition is detected. ? with mst = 0 and when ack non-return is detected. ? at reset n bit 7: communication mode specification bit (master/slave speci- fication bit: mst) this bit is used for master/slave specification for data communica- tion. when this bit is 0, the slave is specified, so that a start condition and a stop condition generated by the master are re- ceived, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1, the master is specified and a start condition and a stop condition are gener- ated, and also the clocks required for data communication are gen- erated on the scl. the mst bit is cleared to 0 in one of the following conditions. ? immediately after completion of 1-byte data transmission when ar- bitration lost is detected ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication preventing function (note). ? at reset note: the start condition duplication prevention function disables the occurence of a start condition, reset of bit counter and scl output when the following condition is satisfied: ? a start condition is set by another master device. M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 25 (7) stop condition generating method when the es0 bit of the i 2 c control register (address 00da 16 ) is 1, execute a write instruction to the i 2 c status register (address 00d9 16 ) for setting the mst bit and the trx bit to 1 and the bb bit to 0. then a stop condition occurs. the stop condition generating tim- ing and the bb flag reset timing are different in the standard clock mode and the high-speed clock mode. refer to figure 22, the stop condition generating timing diagram, and table 4, the start condi- tion/stop condition generating timing table. table 4. start condition/stop condition generating timing table item setup time hold time set/reset time for bb flag standard clock mode 5.0 m s (20 cycles) 5.0 m s (20 cycles) 3.0 m s (12 cycles) high-speed clock mode 2.5 m s (10 cycles) 2.5 m s (10 cycles) 1.5 m s (6 cycles) note: absolute time at f = 4 mhz. the value in parentheses de- notes the number of f cycles. fig. 21. start condition generating timing diagram fig. 22. stop condition generating timing diagram fig. 20. interrupt request signal generating timing fig. 19. structure of i 2 c status register 7 mst 0 i 2 c status register (s1 : address 00d9 16 ) last receive bit (note) 0 : last bit = ?? 1 : last bit = ?? general call detecting flag (note) 0 : no general call detected 1 : general call detected slave address comparison flag (note) 0 : address disagreement 1 : address agreement arbitration lost detecting flag (note) 0 : not detected 1 : detected i 2 c-bus interface interrupt request bit 0 : interrupt request issued 1 : no interrupt request issued bus busy flag 0 : bus free 1 : bus busy communication mode specification bits 00 : slave receive mode 01 : slave transmit mode 10 : master receive mode 11 : master transmit mode trx bb pin al aas ad 0 lrb note: these bit and flags can be read out but cannot be written. scl pin iicirq i 2 c status register write signal reset time for bb flag aaa hold time setup time scl sda bb flag i 2 c status register write signal set time for bb flag aaa aaa hold time setup time scl sda bb flag setup time (6) start condition generating method when the es0 bit of the i 2 c control register (address 00da 16 ) is 1, execute a write instruction to the i 2 c status register (address 00d9 16 ) for setting the mst, trx and bb bits to 1. then a start condition occurs. after that, the bit counter becomes 000 2 and an scl for 1 byte is output. the start condition generating timing and bb bit set timing are different in the standard clock mode and the high-speed clock mode. refer to figure 21, the start condition generating tim- ing diagram, and table 4, the start condition/stop condition gen- erating timing table. M37221ef-xxxsp,M37221efsp mitsubishi microcomputers single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller 26 fig. 23. start condition/stop condition detecting timing diagram table 5. start condition/stop condition detecting conditions (8) start/stop condition detecting condi- tions the start/stop condition detecting conditions are shown in fig- ure 23 and table 5. only when the 3 conditions of table 5 are satis- fied, a start/stop condition can be detected. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal iicirq occurs to the cpu. note: absolute time at f = 4 mhz. the value in parentheses de- notes the number of f cycles. (9) address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective ad- dress communication formats is described below. 7-bit addressing format to meet the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00da 16 ) to 0. the first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the i 2 c address register (address 00d8 16 ). at the time of this comparison, address comparison of the rbw bit of the i 2 c address register (address 00d8 16 ) is not made. for the data transmission format when the 7-bit addressing format is selected, refer to figure 24, (1) and (2). 10-bit addressing format to meet the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00da 16 ) to 1. an address compari- son is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the i 2 c address register (address 00d8 16 ). at the time of this comparison, an ad- dress comparison between the rbw bit of the i 2 c address regis- ter (address 00d8 16 ) and the r/w bit which is the last bit of the address data transmitted from the master is made. in the 10-bit addressing mode, the r/w bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. fig. 24. address data communication format aa aa hold time setup time scl sda (start condition) sda (stop condition) scl release time aa aa hold time setup time standard clock mode 6.5 m s (26 cycles) |