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may 1994 order number: 290166-007 82077AA chmos single-chip floppy disk controller y single-chip floppy disk solution e 100% pc at * compatible e 100% ps/2 * compatible e 100% ps/2 model 30 compatible e integrated drive and data bus buffers y integrated analog data separator e 250 kbits/sec e 300 kbits/sec e 500 kbits/sec e 1 mbits/sec y high speed processor interface y perpendicular recording support y integrated tape drive support y 12 ma host interface drivers, 40 ma disk drivers y four fully decoded drive select and motor signals y programmable write precompensation delays y addresses 256 tracks directly, supports unlimited tracks y 16 byte fifo y 68-pin plcc (see packaging spec., order y 240800, package type n) the 82077AA floppy disk controller has completely integrated all of the logic required for floppy disk control. the 82077AA, a 24 mhz crystal, a resistor package and a device chip select implements a pc at or ps/2 solution. all programmable options default to compatible values. the dual pll data separator has better performance than most board level/discrete pll implementations. the fifo allows better system perform- ance in multi-master systems (e.g. ps/2, eisa). the 82077AA is available in three versionse82077AA-5, 82077AA and 82077AA-1. 82077AA-1 has all features listed in this data sheet. it supports both tape drives and 4 mb floppy drives. the 82077AA supports 4 mb floppy drives and is capable of operation at all data rates through 1 mbps. the 82077AA-5 supports 500/300/250 kbps data rates for high and low density floppy drives. the 82077AA is fabricated with intel's chmos iii technology and is available in a 68-lead plcc (plastic) package. 290166 1 figure 1. 82077AA pinout * ps/2 and pc at are trademarks of ibm.
82077AA chmos single-chip floppy disk controller contents page 1.0 introduction 7 1.1 oscillator 8 1.2 perpendicular recording mode 8 2.0 microprocessor interface 8 2.1 status, data, and control registers 8 2.1.1a status register a (sra, ps/2 mode) 8 2.1.1b status register a (sra, model 30 mode) 8 2.1.2a status register b (srb, ps/2 mode) 9 2.1.2b status register b (srb, model 30 mode) 9 2.1.3 digital output register (dor) 9 2.1.4 tape drive register (tdr) 9 2.1.5 datarate select register (drs) 10 2.1.6 main status register (msr) 10 2.1.7 fifo (data) 11 2.1.8a digital input register (dir, pc-at mode) 11 2.1.8b digital input register (dir, ps/2 mode) 11 2.1.8c digital input register (dir, model 30 mode) 12 2.1.9a configuration control register (ccr, pc at and ps/2 modes) 12 2.1.9b configuration control register (ccr, model 30 mode) 12 2.2 reset 12 2.2.1 reset pin (``hardware'') reset 12 2.2.2 dor reset vs dsr reset (``software'' reset) 12 contents page 2.3 dma transfers 12 3.0 drive interface 12 3.1 cable interface 13 3.2 data separator 13 3.2.1 jitter tolerance 14 3.2.2 locktime (t lock ) 14 3.2.3 capture range 14 3.2.4 reference filter 15 3.3 write precompensation 15 4.0 controller phases 15 4.1 command phase 15 4.2 execution phase 16 4.2.1 non-dma mode, transfers from the fifo to the host 16 4.2.2 non-dma mode, transfers from the host to the fifo 16 4.2.3 dma mode, transfers from the fifo to the host 16 4.2.4 dma mode, transfers from the host to the fifo 17 4.2.5 data transfer termination 17 4.3 result phase 17 5.0 command set/descriptions 17 5.1 data transfer commands 24 5.1.1 read data 24 5.1.2 read deleted data 25 5.1.3 read track 26 5.1.4 write data 26 5.1.5 write deleted data 26 5.1.6 verify 26 5.1.7 format track 27 5.1.7.1 format fields 28 5.1.8 scan commands 29 2
contents page 5.0 command set/descriptions (continued) 5.2 control commands 30 5.2.1 read id 30 5.2.2 recalibrate 30 5.2.3 seek 30 5.2.4 sense interrupt status 31 5.2.5 sense drive status 31 5.2.6 specify 31 5.2.7 configure 32 5.2.8 version 32 5.2.9 relative seek 32 5.2.10 dumpreg 33 5.2.11 perpendicular mode command 33 5.3 command set enhancements 34 5.3.1 perpendicular mode 34 5.3.2 lock 35 5.3.3 enhanced dumpreg command 35 6.0 status register encoding 36 6.1 status register 0 36 6.2 status register 1 36 6.3 status register 2 37 6.4 status register 3 37 7.0 compatibility 37 7.1 register set compatibility 37 7.2 ps/2 vs. at vs. model 30 mode 38 7.2.1 ps/2 mode 38 7.2.2 pc/at mode 38 7.2.3 model 30 mode 38 7.3 compatibility with the fifo 38 7.4 drive polling 39 contents page 8.0 programming guidelines 39 8.1 command and result phase handshaking 39 8.2 initialization 40 8.3 recalibrates and seeks 42 8.4 read/write operations 43 8.5 formatting 43 8.6 verifies 46 9.0 design applications 46 9.1 pc/at floppy disk controller 46 9.1.1 pc/at floppy disk controller architecture 46 9.1.2 82077AA pc/at solution 48 9.2 3.5 drive interfacing 50 9.2.1 3.5 drives under the at mode 50 9.2.2 3.5 drives under the ps/2 modes 51 9.2.3 combining 5.25 and 3.5 drives 51 10.0 d.c. specifications 52 10.1 absolute maximum ratings 52 10.2 d.c. characteristics 52 11.0 a.c. specifications 53 12.0 data separator characteristics for floppy disk mode 60 13.0 data separator characteristics for tape drive mode 61 14.0 82077AA 68-lead plcc package thermal characteristics 61 15.0 revision summary 62 3
82077AA table 1. 82077AA pin description symbol pin y i/o description host interface reset 32 i reset: a high level places the 82077AA in a known idle state. all registers are cleared except those set by the specify command. cs 6i chip select: decodes base address range and qualifies rd and wr inputs. a0 7 i address: selects one of the host interface registers: a1 8 a2 a1 a0 register a2 10 0 0 0 r status register a 0 0 1 r status register b 0 1 0 r/w digital output register 0 1 1 r/w tape drive register 1 0 0 r main status register 1 0 0 w data rate select register 1 0 1 r/w data (fifo) 1 1 0 reserved 1 1 1 r digital input register 1 1 1 w configuration control register db0 11 i/o data bus: data bus with 12 ma drive db1 13 db2 14 db3 15 db4 17 db5 19 db6 20 db7 22 rd 4i read: control signal wr 5i write: control signal drq 24 o dma request: requests service from a dma controller. normally active high, but goes to high impedance in at and model 30 modes when the appropriate bit is set in the dor. dack 3i dma acknowledge: control input that qualifies the rd ,wr inputs in dma cycles. normally active low, but is disabled in at and model 30 modes when the appropriate bit is set in the dor. tc 25 i terminal count: control line from a dma controller that terminates the current disk transfer. tc is accepted only while dack is active. this input is active high in the at, and model 30 modes and active low in the ps/2 mode. int 23 o interrupt: signals a data transfer in non-dma mode and when status is valid. normally active high, but goes to high impedance in at, and model 30 modes when the appropriate bit is set in the dor. x1 33 crystal 1,2: connection for a 24 mhz fundamental mode parallel resonant crystal. x1 may be driven with a mos level clock and x2 would be left unconnected. x2 34 4
82077AA table 1. 82077AA pin description (continued) symbol pin y i/o description host interface (continued) ident 27 i identity: upon hardware reset, this input (along with mfm pin) selects between the three interface modes. after reset, this input selects the type of drive being accessed and alters the level on densel. the mfm pin is also sampled at hardware reset, and then becomes an output again. internal pull- ups on mfm permit a no connect. ident mfm interface 1 1 or nc at mode 1 0 illegal 0 1 or nc ps/2 mode 0 0 model 30 mode at mode: major options are: enables dma gate logic, tc is active high, status register sa&bnot available. ps/2 mode: major options are: no dma gate logic, tc is active low, status register sa&bare available. model 30 mode: major options are: enable dma gate logic, tc is active high, status register sa&b available. after hardware reset this pin determines the polarity of the densel pin. ident at a logic level of ``1'', densel will be active high for high (500 kbps/1 mbps) data rates (typically used for 5.25 drives). ident at a logic level of ``0'', densel will be active low for high data rates (typically used for 3.5 drives). invert is tied to ground. disk control (all outputs have 40 ma drive capability) invert 35 i invert: strapping option. determines the polartity of all signals in this section. should be strapped to ground when using the internal buffers and these signals become active low. when strapped to vcc, these signals become active high and external inverting drivers and receivers are required. me0 57 o me03: decoded motor enables for drives 0 3. the motor enable pins are directly controlled via the digital output register. me1 61 me2 63 me3 66 ds0 58 o drive select 0 3: decoded drive selects for drives 0 3. these outputs are decoded from the select bits in the digital output register and gated by ds1 62 me03. ds2 64 ds3 67 hdsel 51 o head select: selects which side of a disk is to be used. an active level selects side 1. step 55 o step: supplies step pulses to the drive. dir 56 o direction: controls the direction the head moves when a step signal is present. the head moves toward the center if active. wrdata 53 o write data: fm or mfm serial data to the drive. precompensation value is selectable through software. we 52 o write enable: drive control signal that enables the head to write onto the disk. 5
82077AA table 1. 82077AA pin description (continued) symbol pin y i/o description disk control (all outputs have 40 ma drive capability) (continued) densel 49 o density select: indicates whether a low (250/300 kbps) or high (500 kbps/1 mbps) data rate has been selected. dskchg 31 i disk change: this input is reflected in the digital input register. drv2 30 i drive2: this indicates whether a second drive is installed and is reflected in status register a. trk0 2 i track0: control line that indicates that the head is on track 0. wp 1 i write protect: indicates whether the disk drive is write protected. indx 26 i index: indicates the beginning of the track. pll section rddata 41 i read data: serial data from the disk. invert also affects the polarity of this signal. hifil 38 i/o high filter: analog reference signal for internal data separator compensation. this should be filtered by an external capacitor to lofil. lofil 37 i/o low filter: low noise ground return for the reference filter capacitor. mfm 48 i/o mfm: at hardware reset, aids in configuring the 82077AA. internal pull-up allows a no connect if a ``1'' is required. after reset this pin becomes an output and indicates the current data encoding/decoding mode (note: if the pin is held at logic level ``0'' during hardware reset it must be pulled to ``1'' after reset to enable the output. the pin can be released on the falling edge of hardware reset to enable the output). mfm is active high (mfm). drate0 28 o datarate0 1: reflects the contents of bits 0,1 of the data rate register. drate1 29 (drive capability of a 6.0 ma @ 0.4v and b 4.0 ma @ 2.4v) pll0 39 i pll0: this input optimizes the data separator, for either floppy disks or tape drives. a ``1'' (or v cc ) selects the floppy mode, a ``0'' (or gnd) selects tape mode. miscellaneous vcc 18 voltage: a 5v 40 60 68 gnd 9 ground 12 16 21 36 50 54 59 65 avcc 46 analog supply avss 45 analog ground nc 42 no connection: these pins must be left unconnected. 43 44 47 6
82077AA 1.0 introduction the 82077AA is a true single-chip floppy disk, and tape drive controller for the pc-at and ps/2. the 82077AA, a 24 mhz crystal, a resistor package and a chip select implement a complete design. all drive control signals are fully decoded and have 40 ma drive buffers with selectable polarity. signals re- turned from the drive are sent through on-chip input buffers with hysteresis for noise immunity. the inte- grated analog data separator needs no external compensation yet allows for a wide motor speed variation with exceptionally low soft error rates. the microprocessor interface has a 12 ma drive buffer on the data bus plus 100% hardware register com- patibility for pc-at's and ps/2's. the 16-byte fifo with programmable thresholds is extremely useful in multi-master systems (ps/2, eisa) or systems with a large amount of bus latency. upon reset, (pin 32) the 82077AA defaults to 8272a functionality. new features are either selected via hardware straps or new commands. figure 1-1 is a block diagram of the 82077AA. 290166 2 figure 1-1. 82077AA block diagram 7
82077AA 1.1 oscillator 290166 3 figure 1-2. crystal oscillator circuit the 24 mhz clock can be supplied either by a crystal or a mos level square wave. all internal timings are referenced to this clock or a scaled count which is data rate dependent. the crystal oscillator must be allowed to run for 10 ms after vcc has reached 4.5v or exiting the powerdown mode to guarantee that it is stable. crystal specifications frequency: 24 mhz g 0.1% mode: parallel resonant fundamental mode series resistance: less than 40 x shunt capacitance: less than 5 pf 1.2 perpendicular recording mode an added capability of the 82077AA is the ability to interface directly to perpendicular recording floppy drives. perpendicular recording differs from the tradi- tional longitudinal method by orienting the magnetic bits vertically. this scheme packs in more data bits for the same area. the 82077AA with perpendicular recording drives can read standard 3.5 floppies as well as read and write perpendicular media. some manufacturers of- fer drives that can read and write standard and per- pendicular media in a perpendicular media drive. a single command puts the 82077AA into perpen- dicular mode. all other commands operate as they normally do. the perpendicular mode requires the 1 mbps data rate of the 82077AA. at this data rate, the fifo eases the host interface bottleneck due to the speed of data transfer to or from the disk. 2.0 microprocessor interface the interface consists of the standard asynchronous signals: rd ,wr ,cs , a0 a2, int, dma control and a data bus. the address lines select between config- uration registers, the fifo and control/status regis- ters. this interface can be switched between pc at, model 30, or ps/2 normal modes. the ps/2 register sets are a superset of the registers found in a pc- at. 2.1 status, data and control registers the base address range is supplied via the cs pin. for pc-at or ps/2 designs this would be 3f0 hex to 3f7 hex. a2 a1 a0 register 0 0 0 r status register a sra 0 0 1 r status register b srb 0 1 0 r/w digital output register dor 0 1 1 r/w tape drive register tdr 1 0 0 r main status register msr 1 0 0 w data rate select register dsr 1 0 1 r/w data (fifo) fifo 1 1 0 reserved 1 1 1 r digital input register dir 1 1 1 w configuration control register ccr 2.1.1a status register a (sra, ps/2 mode) this register is read-only and monitors the state of the interrupt pin and several disk interface pins. this register is part of the register set, and is not accessi- ble in pc-at mode. 76 * 54 * 32 * 1 * 0 int drv2 step trk0 hdsel indx wp dir pending the int pending bit is used by software to monitor the state of the 82077AA interrupt pin. the bits marked with a `` * '' reflect the state of drive signals on the cable and are independent of the state of the invert pin. as a read-only register, there is no default value as- sociated with a reset other than some drive bits will change with a reset. the int pending, step, hdsel, and dir bits will be low after reset. 2.1.1b status register a (sra, model 30 mode) 76543210 int drq step trko hdsel index wp dir pending f/f this register has the following changes in ps/2 model 30 mode. disk interface pins (bits 0, 1, 2, 3, & 4) are inverted from ps/2 mode. the drq bit 8
82077AA monitors the status of the dma request pin. the step bit is latched with the step output going active and is cleared with a read to the dir register, hard- ware or software reset. 2.1.2a status register b (srb, ps/2 mode) this register is read-only and monitors the state of several disk interface pins. this register is part of the ps/2 register set, and is not accessible in pc-at mode. 76 5 4 3 * 21 0 11 drive wrdata rddata we mot mot sel 0 toggle toggle en1 en0 as the only drive input, rddata toggle's activity is independent of the invert pin level and reflects the level as seen on the cable. the two toggle bits do not read back the state of their respective pins directly. instead, the pins drive a flip/flop which produces a wider and more reli- ably read pulse. bits 6 and 7 are undefined and al- ways return a 1. after any reset, the activity on the toggle pins are cleared. drive select and motor bits cleared by the reset pin and not software resets. 2.1.2b status register b (srb, model 30 mode) 765 4 3 210 drv2 ds1 ds0 wrdata rddata we ds3 ds2 f/f f/f f/f this register has the following changes in model 30 mode. bits 0, 1, 5, and 6 return the decoded value of the drive select bits in the dor register. bits 2, 3, and 4 are set by their respective active going edges and are cleared by reading the dir register. the wrdata bit is triggered by raw wrdata signals and is not gated by we. bits 2, 3, and 4 are cleared to a low level by either hardware or software re- set. 2.1.3 digital output register (dor) the digital output register contains the drive select and motor enable bits, a reset bit and a dma gate bit. 76543210 mot mot mot mot dma reset drive drive en3 en2 en1 en0 gate sel 1 sel 0 the mot enx bits directly control their respective motor enable pins (me0 3). a one means the pin is active, the invert pin determines the active level. the drive selx bits are decoded to provide four drive select lines and only one may be active at a time. a one is active and the invert pin determines the level on the cable. standard programming prac- tice is to set both mot enx and drive selx bits at the same time. table 2-1 lists a set of dor values to activate the drive select and motor enable for each drive. table 2-1. drive activation values drive dor value 0 1ch 1 2dh 2 4eh 3 8fh the dmagate bit is enabled only in pc-at and model 30 modes. if dmagate is set low, the int and drq outputs are tristated and the dack and tc inputs are disabled. dmagate set high will en- able int, drq, tc, and dack to the system. in ps/ 2 mode dmagate has no effect upon int, drq, tc or dack pins and they are always active. this reset bit clears the basic core of the 82077AA and the fifo circuits when the lock bit is set to ``0'' (see section 5.3.2 for lock bit definition). once set, it remains set until the user clears this bit. this bit is set by a chip reset and the 82077AA is held in a reset state until the user clears this bit. the reset bit has no effect upon this register. 2.1.4 tape drive register (tdr) this register allows the user to assign tape support to a particular drive during initialization. any future references to that drive number automatically in- vokes tape support. this register is cleared by hard- ware reset, software resets have no effect. 765432 1 0 eeeeee tape tape sel1 sel0 bits 2 thru 7 are not writable and remain tristated if read. the tape select bits are hardware reset to 0's, making drive 0 not available for tape support. drive 0 is ``reserved'' for the floppy boot drive. tape sel1 tape sel0 drive selected 0 0 none 01 1 10 2 11 3 9
82077AA the tuning of the pll for tape characteristics can also be done in hardware. i f a 0 (gnd) is applied to pin 39 (pll0) the pll is optimized for tape drives, a 1(v cc ) optimizes the pll for floppies. this hard- ware selection mechanism overrides the software selection scheme. a typical hardware application would route the drive select pin used for tape drive support to pin 39 (pll0). 2.1.5 datarate select register (dsr) this register is included for compatibility with the 82072 floppy controller and is write-only. changing the data rate changes the timings of the drive con- trol signals. to ensure that drive timings are not vio- lated when changing data rates, choose a drive tim- ing such that the fastest data rate will not violate the timing. 76543210 s/w power pre- pre- pre- drate drate reset down 0 comp comp comp sel 1 sel 0 210 this register is the same as used in the 82072 ex- cept that the internal/external pll select bit is re- moved. it is recommended that bit 5 be written with a 0 for compatibility. s/w reset behaves the same as dor reset ex- cept that this reset is self clearing. power down deactivates the internal clocks and shuts off the oscillator. disk control pins are put in an inactive state. all input signals must be held in a valid state (d.c. level 1 or 0). power down is exit- ed by activating one of the reset functions. precomp 0 2 adjusts the wrdata output to the disk to compensate for magnetic media phenomena known as bit shifting. the data patterns that are sus- ceptible to bit shifting are well understood and the 82077AA compensates the data pattern as it is writ- ten to the disk. the amount of precompensation is dependent upon the drive and media but in most cases the default value is acceptable. the 82077AA starts precompensating the data pat- tern starting on track 0. the configure com- mand can change the track that precompensating starts on. table 2-2 lists the precompensation val- ues that can be selected and table 2-3 lists the de- fault precompensation values. the default value is selected if the three bits are zeros. drate 0 1 select one of the four data rates as listed in table 2-4. the default value is 250 kbps upon a chip (``hardware'') reset. other (``software'') resets do not affect the drate or precomp bits. table 2-2. precompensation delays precomp precompensation delay 432 111 0.00 nsedisabled 001 41.67 ns 010 83.34 ns 011 125.00 ns 100 166.67 ns 101 208.33 ns 110 250.00 ns 000 default table 2-3. default precompensation delays data rate precompensation delays 1 mbps 41.67 ns 500 kbps 125 ns 300 kbps 125 ns 250 kbps 125 ns table 2-4. data rates dratesel data rate 1 0 mfm 1 1 1 mbps 0 0 500 kbps 0 1 300 kbps 1 0 250 kbps 2.1.6 main status register (msr) the main status register is a read-only register and is used for controlling command input and result out- put for all commands. 76543210 rqm dio non cmd drv 3 drv 2 drv 1 drv 0 dma bsy busy busy busy busy rqmeindicates that the host can transfer data if set to a 1. no access is permitted if set to a 0. dioeindicates the direction of a data transfer once rqm is set. a 1 indicates a read an d a 0 indicates a write is required. non-dmaethis mode is selected in the specify command and will be set to a 1 during the execution phase of a command. this is for polled data trans- fers and helps differentiate between the data trans- fer phase and the reading of result bytes. 10
82077AA command busyethis bit is set to a one when a command is in progress. this bit will go active after the command byte has been accepted and goes in- active at the end of the results phase. if there is no result phase (seek, recalibrate commands), this bit is returned t o a 0 after the last command byte. drv x busyethese bits are set to ones when a drive is in the seek portion of a command, including seeks, and recalibrates. 2.1.7 fifo (data) all command parameter information and disk data transfers go through the fifo. the fifo is 16 bytes in size and has programmable threshold values. data transfers are governed by the rqm and dio bits in the main status register. the fifo defaults to an 8272a compatible mode after a ``hardware'' reset (reset via pin 32). ``soft- ware'' resets (reset via dor or dsr register) can also place the 82077AA into 8272a compatible mode if the lock bit is set to ``0'' (see section 5.3.2 for the definition of the lock bit). this maintains pc-at hardware compatibility. the default values can be changed through the configure com- mand (enable full fifo operation with threshold control). the advantage of the fifo is that it allows the system a larger dma latency without causing a disk error. table 2.5 gives several examples of the delays with a fifo. the data is based upon the fol- lowing formula: threshold y c 1 data rate c 8 b 1.5 m s e delay table 2-5. fifo service delay fifo threshold maximum delay to servicing examples at 1 mbps data rate 1 byte 1 c 8 m s b 1.5 m s e 6.5 m s 2 bytes 2 c 8 m s b 1.5 m s e 14.5 m s 8 bytes 8 c 8 m s b 1.5 m s e 62.5 m s 15 bytes 15 c 8 m s b 1.5 m s e 118.5 m s fifo threshold maximum delay to servicing examples at 500 kbps data rate 1 byte 1 c 16 m s b 1.5 m s e 14.5 m s 2 bytes 2 c 16 m s b 1.5 m s e 30.5 m s 8 bytes 8 c 16 m s b 1.5 m s e 126.5 m s 15 bytes 15 c 16 m s b 1.5 m s e 238.5 m s at the start of a command, the fifo action is always disabled and command parameters must be sent based upon the rqm and dio bit settings. as the 82077AA enters the command execution phase, it clears the fifo of any data to ensure that invalid data is not transferred. an overrun or underrun will terminate the current command and the transfer of data. disk writes will complete the current sector by generating a 00 pat- tern and valid crc. 2.1.8a digital input register (dir, pc-at mode) this register is read only in all modes. in pc-at mode only bit 7 is driven, all other bits remain tristat- ed. 76543210 dsk eeeeeee chg dskchg monitors the pin of the same name and reflects the opposite value seen on the disk cable, regardless of the value of invert . 2.1.8b digital input register (dir, ps/2 mode) 76543 2 1 0 dsk 1111 drate drate high chg sel1 sel0 dens the following is changed in ps/2 mode: bits 6, 5, 4, and 3 return a value of ``1'', and the drate sel1-0 return the value of the current data rate selected (see table 2-4 for values). high dens is low whenever the 500 kbps or 1 mbps data rates are selected. this bit is indepen- dent of the effects of the ident and invert pins. table 2-6 shows the state of the densel pin when invert is low. table 2-6. densel encoding data rate ident * densel 1 mbps 0 0 11 500 kbps 0 0 11 300 kbps 0 1 10 250 kbps 0 1 10 * after (``hardware'') chip reset 11
82077AA this pin is set high after a pin reset and is unaf- fected by dor and dsr resets. 2.1.8c digital input register (dir, model 30 mode) 76543 2 10 dsk 000 dma noprec drate drate chg gate sel1 sel0 the following is changed in model 30 mode: bits 6, 5, and 4 return a value of ``0'', and bit 7 (dskchg ) is inverted in model 30 mode. bit 3 reflects the value of dmagate bit set in the dor register. bit 2 reflects the value of noprec bit set in the ccr register. 2.1.9a configuration control register (ccr, pc at and ps/2 modes) this register sets the datarate and is write only. in the pc-at it is named the dsr. 76543210 eeeeee drate drate sel1 sel0 refer to the table in the data rate select register for values. unused bits should be set to 0. 2.1.9b configuration control register (ccr, model 30 mode) 76543 2 10 e e e e e noprec drate drate sel1 sel0 noprec has no function, and is reset to ``0'' with a hardware reset only. 2.2 reset there are three sources of reset on the 82077AA; the reset pin, a reset generated via a bit in the dor and a reset generated via a bit in the dsr. all resets take the 82077AA out of the power down state. on entering the reset state, all operations are termi- nated and the 82077AA enters an idle state. activat- ing reset while a disk write activity is in progress will corrupt the data and crc. on exiting the reset state, various internal registers are cleared, and the 82077AA waits for a new com- mand. drive polling will start unless disabled by a new configure command. 2.2.1 reset pin (``hardware'') reset the reset pin is a global reset and clears all regis- ters except those programmed by the specify command. the dor reset bit is enabled and must be cleared by the host to exit the reset state. 2.2.2 dor reset vs dsr reset (``software'' reset) these two resets are functionally the same. the dsr reset is included to maintain 82072 compatibil- ity. both will reset the 8272 core which affects drive status information. the fifo circuits will also be re- set if the lock bit is a ``0'' (see section 5.3.2 for the definition of the lock bit). the dsr reset clears itself automatically while the dor reset requires the host to manually clear it. dor reset has prece- dence over the dsr reset. the dor reset is set automatically upon a pin reset. the user must manually clear this reset bit in the dor to exit the reset state. 2.3 dma transfers dma transfers are enabled with the specify com- mand and are initiated by the 82077AA by activating the drq pin during a data transfer command. the fifo is enabled directly by asserting dack and ad- dresses need not be valid. cs can be held inactive during dma transfers. 3.0 drive interface the 82077AA has integrated all of the logic needed to interface to a floppy disk or tape drives which use floppy interface. all drive outputs have 40 ma drive capability and all inputs use a receive buffer with hysteresis. the internal analog data separator re- quires no external components, yet allows for an ex- tremely wide capture range with high levels of read- data jitter, and isv. the designer needs only to run the 82077AA disk drive signals to the disk or tape drive connector. 12
82077AA 3.1 cable interface the invert pin selects between using the internal buffers on the 82077AA or user supplied inverting buffers. invert pulled to v cc disables the internal buffers; pulled to ground will enable them. there is no need to use external buffers with the 82077AA in typical pc applications. the polarity of the densel pin is controlled through the ident pin, after hardware reset. for 5.25 drives a high on densel tells the drive that either the 500 kbps or 1 mbps data rate is selected. for some 3.5 drives the polarity of densel changes to a low for high data rates. see table 2-6 densel encoding for ident pin settings. additionally, the two types of drives have different electrical interfaces. generally, the 5.25 drive uses open collector drivers and the 3.5 drives (as used on ps/2) use totem-pole drivers. the output buffers on the 82077AA do not change between open col- lector or totem-pole, they are always totem-pole. for design information on interfacing 5.25 and 3.5 drives to a single 82077AA, refer to section 9. 3.2 data separator the function of the data separator is to lock onto the incoming serial read data. when lock is achieved the serial front end logic of the chip is provided with a clock which is synchronized to the read data. the synchronized clock, called data window, is used to internally sample the serial data. one state of data window is used to sample the data portion of the bit cell, and the alternate state samples the clock por- tion. serial to parallel conversion logic separates the read data into clock and data bytes. to support reliable disk/tape reads the data separa- tor must track fluctuations in the read data frequen- cy. frequency errors primarily arise from two sourc- es: motor rotation speed variation and instanta- neous speed variation (isv). a second condition, and one that opposes the ability to track frequency shifts is the response to bit jitter. the internal data separator consists of two analog phase lock loops (plls) as shown in figure 3-1. the two plls are referred to as the reference pll and the data pll. the reference pll (the master pll) is used to bias the data pll (the slave pll). the refer- ence pll adjusts the data pll's operating point as a function of process, junction temperature and supply voltage. using this architecture it was possible to eliminate the need for external trim components. 290166 4 figure 3-1. data separator block diagram 13
82077AA phase lock loop overview 290166 5 figure 3-2. data pll figure 3-2 shows the data pll. the reference pll has control over the loop gain by its influence on the charge pump and the vco. in addition the reference pll controls the loop filter time constant. as a result the closed loop transfer function of the data pll is controlled, and immune to the first order, to environ- mental factors and process variation. systems with analog plls are often very sensitive to noise. in the design of this data separator many steps were taken to avoid noise sensitivity problems. the analog section of the chip has a separate vss pin (avss) which should be connected externally to a noise free ground. this provides a clean basis for vss referenced signals. in addition many analog cir- cuit features were employed to make the overall sys- tem as insensitive to noise as possible. 3.2.1 jitter tolerance the jitter immunity of the system is dominated by the data pll's response to phase impulses. this is mea- sured as a percentage of the theoretical data win- dow by dividing the maximum readable bit shift by a (/4 bitcell distance. for instance, if the maximum al- lowable bit shift is 300 ns for a 500 kbps data stream, the jitter tolerance is 60%. the graph in fig- ures 12-1 thru 12-4 and 13-1 thru 13-4 of the data separator characteristics sections illustrate the jitter tolerance of the 82077AA across each frequency range. 3.2.2 locktime (tlock) the lock, or settling time of the data pll is designed to be 64 bit times. this corresponds to 8 sync bytes in the mfm mode. this value assumes that the sync field jitter is 5% the bit cell or less. this level of jitter should be easily achieved for a constant bit pattern, since intersymbol interference should be equal, thus nearly eliminating random bit shifting. 3.2.3 capture range capture range is the maximum frequency range over which the data separator will acquire phase lock with the incoming rddata signal. in a floppy disk environment, this frequency variation is com- posed of two components: drive motor speed error and isv. frequency is a factor which may determine the maximum level of the isv (instantaneous speed variation) component. in general, as frequency in- creases the allowed magnitude of the isv compo- nent will decrease. when determining the capture range requirements, the designer should take the maximum amount of frequency error for the disk drive and double it to account for media switching between drives. 14
82077AA 290166 6 note: ps0,1 are 8272a control signals but are not available as outputs on the 82077AA. figure 3-3. precompensation block diagram 3.2.4 reference filter to provide a clean bias voltage for the internal data separator, two pins have been provided to filter this signal. it is recommended to place a 0.0047 uf ca- pacitor between hifil and lofil to filter the refer- ence signal. a smaller capacitance will reduce the effectiveness of the filter and could result in a lower jitter tolerance. conversely, a larger capacitance has the potential to further improve jitter tolerance, but will result in an increased settling time after a change in data rate. for instance, a filter capacitor of 0.005 uf will yield a settling time of approximately 500 microseconds. since hifil generates a relative- ly low current signal (approximately 10 ua), care also needs to be taken to avoid external leakage on this pin. the quality of the capacitor, solder flux, grease, and dirt can all impact the amount of leakage on the board. 3.3 write precompensation the write precompensation logic is used to minimize bit shifts in the rddata stream from the disk drive. the shifting of bits is a known phenomena of mag- netic media and is dependent upon the disk media and the floppy drive. the 82077AA monitors the bit stream that is being sent to the drive. the data patterns that require pre- compensation are well known. depending upon the pattern, the bit is shifted either early or late (or not at all) relative to the surrounding bits. figure 3-3 is a block diagram of the internal circuit. the top block is a 13-bit shift register with the no delay tap being in the center. this allows 6 levels of early and late shifting with respect to nominal. the shift register is clocked at the main clock rate (24 mhz). the output is fed into 2 multiplexorseone for early and one for late. a final stage of multiple- xors combines the early, late and normal data stream back into one which is the wrdata output. 4.0 controller phases for simplicity, command handling in the 82077AA can be divided into three phases: command, execu- tion and result. each phase is described in the fol- lowing secions. 4.1 command phase after a reset, the 82077AA enters the command phase and is ready to accept a command from the host. for each of the commands, a defined set of command code bytes and parameter bytes has to be written to the 82077AA before the command phase is complete (please refer to section 5.0 for the command descriptions). these bytes of data must be transferred in the order prescribed. before writing to the 82077AA, the host must exam- ine the rqm and dio bits of the main status regis- ter. rqm, dio must be equal to ``1'' and ``0'' respec- tively before command bytes may be written. rqm is set false by the 82077AA after each write cycle until the received byte is processed. the 82077AA as- serts rqm again to request each parameter byte of 15
82077AA the command, unless an illegal command condition is detected. after the last parameter byte is re- ceived, rqm remains ``0'', and the 82077AA auto- matically enters the next phase as defined by the command definition. the fifo is disabled during the command phase to retain compatibility with the 8272a, and to provide for the proper handling of the ``invalid command'' condition. 4.2 execution phase all data transfers to or from the 82077AA occur dur- ing the execution phase, which can proceed in dma or non-dma mode as indicated in the specify command. each data byte is transferred by an int or drq de- pending on the dma mode. the configure com- mand can enable the fifo and set the fifo thresh- old value. the following paragraphs detail the operation of the fifo flow control. in these descriptions, k thresh- old l is defined as the number of bytes available to the 82077AA when service is requested from the host, and ranges from 1 to 16. the parameter fi- fothr which the user programs is one less, and ranges from 0 to 15. a low threshold value (i.e. 2) results in longer peri- ods of time between service requests, but requires faster servicing of the request, for both read and write cases. the host reads (writes) from (to) the fifo until empty (full), then the transfer request goes inactive. the host must be very responsive to the service request. this is the desired case for use with a ``fast'' system. a high value of threshold (i.e. 12) is used with a ``sluggish'' system by affording a long latency period after a service request, but results in more frequent service requests. 4.2.1 non-dma mode, transfers from the fifo to the host the int pin and rqm bits in the main status regis- ter are activated when the fifo contains (16 k threshold l ) bytes, or the last bytes of a full sector transfer have been placed in the fifo. the int pin can be used for interrupt driven systems and rqm can be used for polled sytems. the host must re- spond to the request by reading data from the fifo. this process is repeated until the last byte is trans- ferred out of the fifo. the 82077AA will deactivate the int pin and rqm bit when the fifo becomes empty. 4.2.2 non-dma mode, transfers from the host to the fifo the int pin and rqm bit in the main status register are activated upon entering the execution phase of data transfer commands. the host must respond to the request by writing data into the fifo. the int pin and rqm bit remain true until the fifo becomes full. they are set true again when the fifo has k threshold l bytes remaining in the fifo. the int pin will also be deactivated if tc and dack y both go inactive. the 82077AA enters the result phase after the last byte is taken by the 82077AA from the fifo (i.e. fifo empty condition). 4.2.3 dma mode, transfers from the fifo to the host the 82077AA activates the drq pin when the fifo contains (16 k threshold l ) bytes, or the last byte of a full sector transfer has been placed in the fifo. the dma controller must respond to the request by reading data from the fifo. the 82077AA will deac- tivate the drq pin when the fifo becomes empty. drq goes inactive after dack y goes active for the last byte of a data transfer (or on the active edge of rd y , on the last byte, if no edge is present on dack y ). a data underrun may occur if drq is not removed in time to prevent an unwanted cycle. 16
82077AA 4.2.4 dma mode, transfers from the host to the fifo the 82077AA activates the drq pin when entering the execution phase of the data transfer commands. the dma controller must respond by activating the dack y and wr y pins and placing data in the fifo. drq remains active until the fifo becomes full. drq is again set true when the fifo has k threshold l bytes remaining in the fifo. the 82077AA will also deactivate the drq pin when tc becomes true (qualified by dack y ), indicating that no more data is required. drq goes inactive after dack y goes active for the last byte of a data trans- fer (or on the active edge of wr y of the last byte, if no edge is present on dack y ). a data overrun may occur if drq is not removed in time to prevent an unwanted cycle. 4.2.5 data transfer termination the 82077AA supports terminal count explicitly through the tc pin and implicitly through the under- run/overrun and end-of-track (eot) functions. for full sector transfers, the eot parameter can define the last sector to be transferred in a single or multi- sector transfer. if the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the 82077AA will continue to complete the sector as if a hardware tc was re- ceived. the only difference between these implicit functions and tc is that they return ``abnormal termi- nation'' result status. such status indications can be ignored if they were expected. note that when the host is sending data to the fifo of the 82077AA, the internal sector count will be complete when 82077AA reads the last byte from its side of the fifo. there may be a delay in the remov- al of the transfer request signal of up to the time taken for the 82077AA to read the last 16 bytes from the fifo. the host must tolerate this delay. 4.3 result phase the generation of int determines the beginning of the result phase. for each of the commands, a de- fined set of result bytes has to be read from the 82077AA before the result phase is complete. (re- fer to section 5.0 on command descriptions.) these bytes of data must be read out for another command to start. rqm and dio must both equal ``1'' before the result bytes may be read from the fifo. after all the result bytes have been read, the rqm and dio bits switch to ``1'' and ``0'' respectively, and the cb bit is cleared. this indicates that the 82077AA is ready to accept the next command. 5.0 command set/descriptions commands can be written whenever the 82077AA is in the command phase. each command has a unique set of needed parameters and status results. the 82077AA checks to see that the first byte is a valid command and, if valid, proceeds with the com- mand. if it was invalid, the next time the rqm bit in the msr register is a ``1'' the dio and cb bits will also be ``1'', indicating the fifo must be read. a result byte of 80h will be read out of the fifo, indi- cating an invalid command was issued. after reading the result byte from the fifo the 82077AA will re- turn to the command phase. table 5-1 is a summary of the command set. 17
82077AA table 5-1. 82077AA command set phase r/w data bus remarks d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data command w mt mfm sk 0 0 1 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution w h w r w n w eot w gpl w dtl execution data transfer between the fdd and system result r st 0 status information after command execution r st 1 r st 2 r c r h sector id information after command execution r r r n read deleted data command w mt mfm sk 0 1 1 0 0 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution w h w r w n w eot w gpl w dtl execution data transfer between the fdd and system result r st 0 status information after command execution r st 1 r st 2 r c r h sector id information after command execution r r r n write data command w mt mfm 0 0 0 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution w h w r w n w eot w gpl w dtl execution data transfer between the system and fdd result r st 0 status information after command execution r st 1 r st 2 r c r h sector id information after command execution r r r n 18
82077AA table 5-1. 82077AA command set (continued) phase r/w data bus remarks d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 write deleted data command w mt mfm 0 0 1 0 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution w h w r w n w eot w gpl w dtl execution data transfer between the fdd and system result r st 0 status information after command execution r st 1 r st 2 r c r h sector id information after command execution r r r n read track command w 0 mfm 0 0 0 0 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution w h w r w n w eot w gpl w dtl execution data transfer between the fdd and system. fdc reads all of cylinders contents from index hole to eot result r st 0 status information after command execution r st 1 r st 2 r c r h sector id information after command execution r r r n verify command w mt mfm sk 1 0 1 1 0 command codes w ec 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution w h w r w n w eot w gpl w dtl/sc execution no data transfer takes place result r st 0 status information after command execution r st 1 r st 2 r c r h sector id information after command execution r r r n version command w 0 0 0 1 0 0 0 0 command code result r 1 0 0 1 0 0 0 0 enhanced controller 19
82077AA table 5-1. 82077AA command set (continued) phase r/w data bus remarks d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 format track command w 0 mfm 0 0 1 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w n bytes/sector w sc sectors/cylinder w gpl gap 3 w d filler byte execution for each w c input sector sector w h parameters repeat: w r w n 82077AA formats an entire cylinder result r st 0 status information after command execution r st 1 r st 2 r undefined r undefined r undefined r undefined scan equal command w mt mfm sk 1 0 0 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information w h prior to command w r execution w n w eot w gpl w stp execution data compared between the fdd and main-system result r st 0 status information r st 1 after command r st 2 execution r c r h sector id information r r after command r n execution scan low or equal command w mt mfm sk 1 1 0 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information w h prior to command w r execution w n w eot w gpl w stp execution data command between the fdd and main-system 20
82077AA table 5-1. 82077AA command set (continued) phase r/w data bus remarks d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 scan low or equal (continued) result r st 0 status information r st 1 after command r st 2 execution r c r h sector id information r r after command r n execution scan high or equal command w mt mfm sk 1 1 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information w h prior to command w r execution w n w eot w gpl w stp execution data compared between the fdd and main-system result r st 0 status id information r st 1 after command r st 2 execution r c r h sector id information r r after command r n execution recalibrate command w 0 0 0 0 0 1 1 1 command codes w 0 0 0 0 0 0 ds1 ds0 execution head retracted to track 0 interrupt sense interrupt status command w 0 0 0 0 1 0 0 0 command codes result r st 0 status information at the end of each seek operation r pcn specify command w 0 0 0 0 0 0 1 1 command codes w srt hut w hlt nd sense drive status command w 0 0 0 0 0 1 0 0 command codes w 0 0 0 0 0 hds ds1 ds0 result r st 3 status information about fdd seek command w 0 0 0 0 1 1 1 1 command codes w 0 0 0 0 0 hds ds1 ds0 w ncn execution head is positioned over proper cylinder on diskette configure command w 0 0 0 1 0 0 1 1 configure information w00000000 w 0 eis efifo poll fifothr w pretrk 21
82077AA table 5-1. 82077AA command set (continued) phase r/w data bus remarks d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 relative seek command w 1 dir 0 0 1 1 1 1 w 0 0 0 0 0 hds ds1 ds0 w rcn dumpreg command w 0 0 0 0 1 1 1 0 * note execution registers placed in fifo result r pcn-drive 0 r pcn-drive 1 r pcn-drive 2 r pcn-drive 3 r srt hut r hlt nd r sc/eot r lock 0 d 3 d 2 d 1 d 0 gap wgate r 0 eis efifo poll fifothr r pretrk read id command w 0 mfm 0 0 1 0 1 0 commands w 0 0 0 0 0 hds ds1 ds0 execution the first correct id information on the cylinder is stored in data register result r st 0 status information after command execution r st 1 r st 2 r c r h disk status after the command has completed. r r r n perpendicular mode command w 0 0 0 1 0 0 1 0 command codes wow 0 d 3 d 2 d 1 d0 gap wgate lock command w lock 0 0 1 0 1 0 0 command code result r 0 0 0 lock 0 0 0 0 invalid command w invalid codes invalid command codes (noop e 82077AA goes into standby state) result r st 0 st 0 e 80h sc is returned if the last command that was issued was the format command. eot is returned if the last command was a read or write. note: these bits are used internally only. they are not reflected in the drive select pins. it is the users responsibility to maintain correspondence between these bits and the drive select pins (dor). parameter abbreviations symbol description c cylinder address. the currently select- ed cylinder address, 0 to 255. d 0 ,d 1 drive select 0-3. designates which d 2 ,d 3 drives are perpendicular drives, a ``1'' indicating perpendicular drive. symbol description d data pattern. the pattern to be written in each sector data field during formatting. dir direction control. if this bit is 0, then the head will step out from the spindle during a relative seek. if set to a 1, the head will step in toward the spindle. 22
82077AA symbol description ds0, ds1 disk drive select. ds1 ds0 0 0 drive 0 0 1 drive 1 1 0 drive 2 1 1 drive 3 dtl special sector size. by setting n to zero (00), dtl may be used to control the number of bytes transferred in disk read/write commands. the sector size (n e 0) is set to 128. if the actual sector (on the diskette) is larger than dtl, the re- mainder of the actual sector is read but is not passed to the host during read com- mands; during write commands, the re- mainder of the actual sector is written with all zero bytes. the crc check code is calculated with the actual sector. when n is not zero, dtl has no meaning and should be set to ff hex. ec enable count. when this bit is ``1'' the ``dtl'' parameter of the verify command becomes sc (number of sectors per track). efifo enable fifo. when this bit is 0, the fifo is enabled. a ``1'' puts the 82077AA in the 8272a compatible mode where the fifo is disabled. eis enable implied seek. when set, a seek operation will be performed before exe- cuting any read or write command that re- quires the c parameter in the command phase. a ``0'' disables the implied seek. eot end of track. the final sector number of the current track. gap alters gap 2 length when using perpen- dicular mode. gpl gap length. the gap 3 size. (gap 3 is the space between sectors excluding the vco synchronization field). h/hds head address. selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector id field. hlt head load time. the time interval that 82077AA waits after loading the head and before initiating a read or write opera- tion. refer to the specify command for actual delays. hut head unload time. the time interval from the end of the execution phase (of a read or write command) until the head is un- loaded. refer to the specify command for actual delays. symbol description lock lock defines whether efifo, fifothr, and pretrk parameters of the con- figure command can be reset to their default values by a ``software reset'' (reset made by setting the proper bit in the dsr or dor registers). mfm mfm mode selector. a one selects the double density (mfm) mode. mt multi-track selector. when set, this flag selects the multi-track operating mode. in this mode, the 82077AA treats a com- plete cylinder, under head 0 and 1, as a single track. the 82077AA operates as if this expanded track started at the first sector under head 0 and ended at the last sector under head 1. with this flag set, a multitrack read or write operation will automatically continue to the first sec- tor under head 1 when the 82077AA fin- ishes operating on the last sector under head 0. n sector size code. this specifies the num- ber of bytes in a sector. if this parameter is ``00'', then the sector size is 128 bytes. the number of bytes transferred is deter- mined by the dtl parameter. otherwise the sector size is (2 raised to the ``n'th'' power) times 128. all values up to ``07'' hex are allowable. ``07''h would equal a sector size of 16k. it is the users respon- sibility to not select combinations that are not possible with the drive. n sector size 00 128 bytes 01 256 bytes 02 512 bytes 03 1024 bytes .. ... 07 16 kbytes ncn new cylinder number. the desired cylin- der number. nd non-dma mode flag. when set to 1, indi- cates that the 82077AA is to operate in the non-dma mode. in this mode, the host is interrupted for each data transfer. when set to 0, the 82077AA operates in dma mode, interfacing to a dma control- ler by means of the drq and dack y signals. ow the bits denoted d 0 ,d 1 ,d 2 , and d 3 of the perpendicular mode command can only be overwritten when the ow bit is set to ``1''. 23
82077AA symbol description pcn present cylinder number. the current po- sition of the head at the completion of sense interrupt status command. poll polling disable. when set, the internal polling routine is disabled. when clear, polling is enabled. pretrk precompensation start track number. programmable from track 00 to ffh. r sector address. the sector number to be read or written. in multi-sector transfers, this parameter specifies the sector num- ber of the first sector to be read or writ- ten. rcn relative cylinder number. relative cylin- der offset from present cylinder as used by the relative seek command. sc number of sectors. the number of sec- tors to be initialized by the format command. the number of sectors to be verified during a verify command, when ec is set. sk skip flag. when set to 1, sectors contain- ing a deleted data address mark will auto- matically be skipped during the execution of read data. if read deleted is ex- ecuted, only sectors with a deleted ad- dress mark will be accessed. when set to ``0'', the sector is read or written the same as the read and write commands. srt step rate interval. the time interval be- tween step pulses issued by the 82077AA. programmable from 0.5 to 8 milliseconds, in increments of 0.5 ms at the 1 mbit data rate. refer to the speci- fy command for actual delays. status register 0 3. registers within the st0 82077AA that store status information af- st1 ter a command has been executed. this st2 status information is available to the host st3 during the result phase after command execution. wgate write gate alters timing of we, to allow for pre-erase loads in perpendicular drives. 5.1 data transfer commands all of the read data, write data and verify type commands use the same parameter bytes and return the same results information. the only differ- ence being the coding of bits 0 4 in the first byte. an implied seek will be executed if the feature was enabled by the configure command. this seek is completely transparent to the user. the drive busy bit for the drive will go active in the main status reg- ister during the seek portion of the command. if the seek portion fails, it will be reflected in the results status normally returned for a read/write data command. status register 0 (st0) would contain the error code and c would contain the cylinder on which the seek failed. 5.1.1 read data a set of nine (9) bytes is required to place the 82077AA into the read data mode. after the read data command has been issued, the 82077AA loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the specify command), and begins reading id address marks and id fields. when the sector address read off the diskette matches with the sector address specified in the command, the 82077AA reads the sector's data field and transfers the data to the fifo. after completion of the read operation from the cur- rent sector, the sector address is incremented by one, and the data from the next logical sector is read and output via the fifo. this continuous read func- tion is called ``multi-sector read operation''. upon receipt of tc, or an implied tc (fifo overrun/un- derrun), the 82077AA stops sending data, but will continue to read data from the current sector, check the crc bytes, and at the end of the sector termi- nate the read data command. n determines the number of bytes per sector (see table 5-2 below). if n is set to zero, the sector size is set to 128. the dtl value determines the number of bytes to be transferred. if dtl is less than 128, the 82077AA transfers the specified number of bytes to the host. for reads, it continues to read the entire 128 byte sector and checks for crc errors. for writes it completes the 128 byte sector by filling in zeroes. if n is not set to 00 hex, dtl should be set to ff hex, and has no impact on the number of bytes transferred. table 5-2. sector sizes n sector size 00 128 bytes 01 256 bytes 02 512 bytes 03 1024 bytes .. ... 07 16 kbytes the amount of data which can be handled with a single command to the 82077AA depends upon mt (multi-track) and n (number of bytes/sector). 24
82077AA table 5-3. effects of mt and n bits mt n max. transfer final sector capacity read from disk 0 1 256 c 26 e 6,656 26 at side 0 or 1 1 1 256 c 52 e 13,312 26 at side 1 0 2 512 c 15 e 7,680 15 at side 0 or 1 1 2 512 c 30 e 15,360 15 at side 1 0 3 1024 c 8 e 8,192 8 at side 0 or 1 1 3 1024 c 16 e 16,384 16 at side 1 the multi-track function (mt) allows the 82077AA to read data from both sides of the diskette. for a particular cylinder, data will be transferred starting at sector 1, side 0 and completing at the last sector of the same track at side 1. if the host terminates a read or write operation in the 82077AA, then the id information in the result phase is dependent upon the state of the mt bit and eot byte. refer to table 5-6. at the completion of the read data command, the head is not unloaded until after the head unload time interval (specified in the specify command) has elapsed. if the host issues another command before the head unloads then the head settling time may be saved between subsequent reads. if the 82077AA detects a pulse on the idx pin twice without finding the specified sector (meaning that the diskette's index hole passes through index de- tect logic in the drive twice), the 82077AA sets the ic code in status register 0 to ``01'' (abnormal ter- mination), and sets the nd bit in status register 1 to ``1'' indicating a sector not found, and terminates the read data command. after reading the id and data fields in each sector, the 82077AA checks the crc bytes. if a crc error occurs in the id or data field, the 82077AA sets the ic code in status register 0 to ``01'' (abnormal ter- mination), sets the de bit flag in status register 1 to `'1'', sets the dd bit in status register 2 to ``1'' if crc is incorrect in the id field, and terminates the read data command. table 5-4 describes the affect of the sk bit on the read data command execution and results. table 5-4. skip bit vs read data command sk bit data address results value mark type sector cm bit description of encountered read? of st2 set? results 0 normal data yes no normal termination. 0 deleted data yes yes address not incremented. next sector not searched for. 1 normal data yes no normal termination. 1 deleted data no yes normal termination sector not read (``skipped''). except where noted in table 5-4, the c or r value of the sector address is automatically incremented (see table 5-6). 5.1.2 read deleted data this command is the same as the read data com- mand, only it operates on sectors that contain a de- leted data address mark at the beginning of a data field. table 5-5 describes the affect of the sk bit on the read deleted data command execution and re- sults. table 5-5. skip bit vs read deleted data command sk bit data address results value mark type sector cm bit of description encountered read? st2 set? of results 0 normal data yes yes address not incremented. next sector not searched for. 0 deleted data yes no normal termination. 1 normal data no yes normal termination sector not read (``skipped''). 1 deleted data yes no normal termination. except where noted in table 5-5 above, the c or r value of the sector address is automatically incre- mented (see table 5-6). 25
82077AA table 5-6. result phase table mt head final sector transferred id information at result phase to host chrn 0 less than eot nc nc r a 1nc 0 equal to eot c a 1nc 01 nc 1 less than eot nc nc r a 1nc equal to eot c a 1nc 01 nc 0 less than eot nc nc r a 1nc 1 equal to eot nc lsb 01 nc 1 less than eot nc nc r a 1nc equal to eot c a 1 lsb 01 nc nc: no change, the same value as the one at the beginning of command execution. lsb: least significant bit, the lsb of h is complemented. 5.1.3 read track this command is similar to the read data com- mand except that the entire data field is read contin- uously from each of the sectors of a track. immedi- ately after encountering a pulse on the idx pin, the 82077AA starts to read all data fields on the track as continuous blocks of data without regard to logical sector numbers. if the 82077AA finds an error in the id or data crc check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the command. the 82077AA com- pares the id information read from each sector with the specified value in the command, and sets the nd flag of status register 1 to a ``1'' if there is no comparison. multi-track or skip operations are not allowed with this command. the mt and sk bits (bits d7 and d5 of the first command byte respec- tively) should always be set to ``0''. this command terminates when the eot specified number of sectors have been read. if the 82077AA does not find an id address mark on the diskette after the second occurrence of a pulse on the idx pin, then it sets the ic code in status register 0 to ``01'' (abnormal termination), sets the ma bit in status register 1 to ``1'', and terminates the com- mand. 5.1.4 write data after the write data command has been issued, the 82077AA loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defined in the specify command), and begins reading id fields. when the sector address read from the diskette matches the sector address speci- fied in the command, the 82077AA reads the data from the host via the fifo, and writes it to the sec- tor's data field. after writing data into the current sector, the 82077AA computes the crc value and writes it into the crc field at the end of the sector transfer. the sector number stored in ``r'' is incremented by one, and the 82077AA continues writing to the next data field. the 82077AA continues this ``multi-sector write operation''. upon receipt of a terminal count signal or if a fifo over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. the 82077AA reads the id field of each sector and checks the crc bytes. if it detects a crc error in one of the id fields, it sets the ic code in status register 0 to ``01'' (abnormal termination), sets the de bit of status register 1 to ``1'', and terminates the write data command. the write data command operates in much the same manner as the read data command. the following items are the same. please refer to the read data command for details: # transfer capacity # en (end of cylinder) bit # nd (no data) bit # head load, unload time interval # id information when the host terminates the com- mand. # definition of dtl when n e 0 and when n does not e 0. 5.1.5 write deleted data this command is almost the same as the write data command except that a deleted data ad- dress mark is written at the beginning of the data field instead of the normal data address mark. this command is typically used to mark a bad sector con- taining an error on the floppy disk. 5.1.6 verify the verify command is used to verify the data stored on a disk. this command acts exactly like a read data command except that no data is trans- ferred to the host. data is read from the disk, crc 26
82077AA computed and checked against the previously stored value. because no data is transferred to the host, tc (pin 25) cannot be used to terminate this command. by setting the ec bit to ``1'' an implicit tc will be issued to the 82077AA. this implicit tc will occur when the sc value has decrement to 0 (an sc value of 0 will verify 256 sectors). this command can also be ter- minated by setting the ec bit to ``0'' and the eot value equal to the final sector to be checked. if ec is set to ``0'' dtl/sc should be programmed to 0ffh. refer to table 5-6 and table 5-7 for information concerning the values of mt and ec versus sc and eot value. definitions: y sectors per side e number of formatted sectors per each side of the disk. y sectors remaining e number of formatted sec- tors left which can be read, including side 1 of the disk if mt is set to ``1''. 5.1.7 format track the format command allows an entire track to be formatted. after a pulse from the idx pin is detected, the 82077AA starts writing data on the disk including gaps, address marks, id fields and data fields, per the ibm system 34 (mfm). the particular values that will be written to the gap and data field are con- trolled by the values programmed into n, sc, gpl, and d which are specified by the host during the command phase. the data field of the sector is filled with the data byte specified by d. the id field for each sector is supplied by the host; that is, four data bytes per sector are needed by the 82077AA for c, h, r, and n (cylinder, head, sector number and sec- tor size respectively). after formatting each sector, the host must send new values for c, h, r and n to the 82077AA for the next sector on the track. the r value (sector num- ber) is the only value that must be changed by the host after each sector is formatted. this allows the disk to be formatted with nonsequential sector ad- dresses (interleaving). this incrementing and for- matting continues for the whole track until the 82077AA encounters a pulse on the idx pin again and it terminates the command. table 5-8 contains typical values for gap fields which are dependent upon the size of the sector and the number of sectors on each track. actual values can vary due to drive electronics. table 5-7. verify command result phase table mt ec sc/eot value termination result 00sc e dtl successful termination eot s y sectors per side result phase valid 00sc e dtl unsuccessful termination eot l y sectors per side result phase invalid 01sc s y sectors remaining successful termination and result phase valid eot s y sectors per side 01sc l y sectors remaining unsuccessful termination or result phase invalid eot l y sectors per side 10sc e dtl successful termination eot s y sectors per side result phase valid 10sc e dtl unsuccessful termination eot l y sectors per side result phase invalid 11sc s y sectors remaining successful termination and result phase valid eot s y sectors per side 11sc l y sectors remaining unsuccessful termination or result phase invalid eot l y sectors per side note: if mt is set to ``1'' and the sc value is greater than the number of remaining formatted sectors on side 0, verifying will continue on side 1 of the disk. 27
82077AA table 5-8. typical values for formatting sector size n sc gpl1 gpl2 256 01 12 0a 0c 256 01 10 20 32 512 * 02 09 2a 50 5.25 drive mfm 1024 03 04 80 f0 2048 04 02 c8 ff 4096 05 01 c8 ff ... ... 256 1 0f 0e 36 3.5 drive mfm 512 ** 209 1b 54 1024 3 05 35 74 gpl1 e suggested gpl values in read and write commands to avoid splice point between data field and id field of contigu- ous sections. gpl2 e suggested gpl value in format track command. * pc-at values (typical) ** ps/2 values (typical). applies with 1.0 mb and 2.0 mb drives. note: all values except sector size are in hex. 5.1.7.1 format fields gap 4a sync iam gap 1 sync idam c h s n c gap 2 sync data am c 80x 12x 3x fc 50x 12x 3x fe y d e o r 22x 12x 3x fb data r gap 3 gap 4b 4e 00 c2 4e 00 a1 lcc4e00 a1 f8 c figure 5-1. system 34 format double density gap 4a sync iam gap 1 sync idam c h s n c gap 2 sync data am c 80x 12x 3x fc 50x 12x 3x fe y d e o r 41x 12x 3x fb data r gap 3 gap 4b 4e 00 c2 4e 00 a1 lcc4e00 a1 f8 c figure 5-2. perpendicular format 28
82077AA 5.1.8 scan commands the scan commands allow data which is being read from the diskette to be compared against data which is being supplied from the main system (proc- essor in non-dma mode, and dma controller in dma mode). the fdc compares the data on a byte- by-byte basis, and looks for a sector on data which meets the conditions of d fdd e d processor ,d fdd s d processor ,ord fdd t d processor . ones comple- ment arithmetic is used for comparison (ff e larg- est number, 00 e smallest number). after a whole sector of data is compared, if the conditions are not met, the sector number is incremented (r a stp x r), and the scan operation is continued. the scan operation continues until one of the following conditions occur; the conditions for scan are met (equal, low, or high), the last sector on the track is reached (eot), or the terminal count signal is re- ceived. if the conditions for scan are met then the fdc sets the sh (scan hit) flag of status register 2 to a 1 (high), and terminates the scan command. if the table 5-9. scan status codes command status register 2 comments bit 2 e sn bit 3 e sh scan equal 0 1 d fdd e d processor 10d fdd i d processor scan low or equal 0 1 d fdd e d processor 00d fdd k d processor 10d fdd p d processor scan high or equal 0 1 d fdd e d processor 00d fdd l d processor 10d fdd o d processor conditions for scan are not met between the starting sector (as specified by r) and the last sector on the cylinder (eot), then the fdc sets the sn (scan not satisfied) flag of status register 2 to a 1 (high), and terminates the scan command. the receipt of a terminal count signal from the processor or dma controller during the scan operation will cause the fdc to complete the comparison of the particu- lar byte which is in process, and then to terminate the command. table 10 shows the status of bits sh and sn under various conditions of scan. if the fdc encounters a deleted data address mark on one of the sectors (and sk e 0), then it regards the sector as the last sector on the cylinder, sets cm (control mark) flag of status register 2 t o a 1 (high) and terminates the command. if sk e 1, the fdc skips the sector with the deleted address mark, and reads the next sector. in the second case (sk e 1) the fdc sets the cm (control mark) flag on status register 2 t o a 1 (high) in order to show that a delet- ed sector had been encountered. when either the stp (contiguous sectors stp e 01, or alternate sectors stp e 02 sectors are read) or the mt (multi-track) are programmed, it is neces- sary to remember that the last sector on the track must be read. for example, if stp e 02, mt e 0, the sectors are numbered sequentially 1 through 26, and we start the scan command at sector 21; the following will happen. sectors 21, 23, and 25 will be read, then the next sector (26) will be skipped and the index hole will be encountered before the eot value of 26 can be read. this will result in an abnor- mal termination of the command. if the eot had been set at 25 or the scanning started at sector 20, then the scan command would be completed in a normal manner. during the scan command data is supplied by either the processor or dma controller for comparison against the data read from the diskette. in order to avoid having the or (over run) flag set in status register 1, it is necessary to have the data available in less than 13 m s (mfm mode). if an overrun oc- curs the fdc terminates the command. 29
82077AA 5.2 control commands control commands differ from the other commands in that no data transfer takes place. three com- mands generate an interrupt when complete; read id, recalibrate and seek. the other control commands do not generate an interrupt. 5.2.1 read id the read id command is used to find the present position of the recording heads. the 82077AA stores the values from the first id field it is able to read into its registers. if the 82077AA does not find an id address mark on the diskette after the second occurrence of a pulse on the idx pin, it then sets the ic code in status register 0 to ``01'' (abnormal ter- mination), sets the ma bit in status register 1 to `'1'', and terminates the command. the following commands will generate an interrupt upon completion. they do not return any result bytes. it is highly recommended that control com- mands be followed by the sense interrupt status command. otherwise, valuable interrupt status information will be lost. 5.2.2 recalibrate this command causes the read/write head within the 82077AA to retract to the track 0 position. the 82077AA clears the contents of the pcn counter, and checks the status of the trk0 pin from the fdd. as long as the trk0 pin is low, the dir pin remains 0 and step pulses are issued. when the trk0 pin goes high, the se bit in status register 0 is set to ``1'', and the command is terminated. if the trk0 pin is still low after 79 step pulses have been issued, the 82077AA sets the se and the ec bits of status register 0 to ``1'', and terminates the com- mand. disks capable of handling more than 80 tracks per side may require more than one recali- brate command to return the head back to physi- cal track 0. the recalibrate command does not have a re- sult phase. sense interrupt status command must be issued after the recalibrate command to effectively terminate it and to provide verification of the head position (pcn). during the command phase of the recalibrate operation, the 82077AA is in the busy state, but during the execution phase it is in a non busy state. at this time another recali- brate command may be issued, and in this man- ner, parallel recalibrate operations may be done on up to 4 drives at once. upon power up, the software must issue a recali- brate command to properly initialize all drives and the controller. 5.2.3 seek the read/write head within the drive is moved from track to track under the control of the seek com- mand. the 82077AA compares the pcn which is the current head position with the ncn and performs the following operation if there is a difference: epcn k ncn: direction signal to drive set to ``1'' (step in), and issues step pulses. epcn l ncn: direction signal to drive set to ``0'' (step out), and issues step pulses. the rate at which step pulses are issued is con- trolled by srt (stepping rate time) in the specify command. after each step pulse is issued, ncn is compared against pcn, and when ncn e pcn, then the se bit in status register 0 is set to ``1'', and the command is terminated. during the command phase of the seek or recali- brate operation, the 82077AA is in the busy state, but during the execution phase it is in the non busy state. 30
82077AA note that if implied seek is not enabled, the read and write commands should be preceded by: 1) seek command; step to the proper track 2) sense interrupt terminate the seek status command; command 3) read id. verify head is on proper track 4) issue read/write command. the seek command does not have a result phase. therefore, it is highly recommended that the sense interrupt status command be issued after the seek command to terminate it and to provide verifi- cation of the head position (pcn). the h bit (head address) in st0 will always return a ``0''. when exit- ing powerdown mode, the 82077AA clears the pcn value and the status information to zero. prior to issuing the powerdown command, it is highly recommended that the user service all pending in- terrupts through the sense interrupt status command. 5.2.4 sense interrupt status an interrupt signal on int pin is generated by the 82077AA for one of the following reasons: 1. upon entering the result phase of: a. read data command b. read track command c. read id command d. read deleted data command e. write data command f. format track command g. write deleted data command h. verify command 2. end of seek, relative seek or recali- brate command 3. 82077AA requires a data transfer during the exe- cution phase in the non-dma mode the sense interrupt status command resets the interrupt signal and via the ic code and se bit of status register 0, identifies the cause of the inter- rupt. if a sense interrupt status command is issued when no active interrupt condition is present, the status register st0 will return a value of 80h (invalid command). table 5-9. interrupt identification se ic interrupt due to 0 11 polling 1 00 normal termination of seek or recalibrate command 1 01 abnormal termination of seek or recalibrate command the seek, relative seek and the recali- brate commands have no result phase. sense interrupt status command must be issued im- mediately after these commands to terminate them and to provide verification of the head position (pcn). the h (head address) bit in st0 will always return a ``0''. if a sense interrupt status is not issued, the drive, will continue to be busy and may effect the operation of the next command. 5.2.5 sense drive status sense drive status obtains drive status infor- mation. it has no execution phase and goes directly to the result phase from the command phase. status register 3 contains the drive status in- formation. 5.2.6 specify the specify command sets the initial values for each of the three internal timers. the hut (head unload time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. the srt (step rate time) defines the time interval between adjacent step pulses. note that the spacing between the first and second step pulses may be shorter than the remain- ing step pulses. the hlt (head load time) defines the time between the head load signal goes high and the read, write operation starts. the values change with the data rate speed selection and are documented in table 5-10. 31
82077AA table 5-10. drive control delays (ms) hut srt 1m 500k 300k 250k 1m 500k 300k 250k 0 128 256 426 512 8.0 16 26.7 32 1 8 16 26.7 32 7.5 15 25 30 .. .. .. .. .. .. .. .. .. e 112 224 373 448 1.0 2 3.33 4 f 120 240 400 480 0.5 1 1.67 2 hlt 1m 500k 300k 250k 00 128 256 426 512 01 1 2 3.3 4 02 2 4 6.7 8 .. .. .. .. . 7f 126 252 420 504 7f 127 254 423 508 the choice of dma or non-dma operations is made by the nd bit. when this bit is ``1'', the non- dma mode is selected, and when nd is ``0'', the dma mode is selected. in dma mode, data transfers are signalled by the drq pin. non-dma mode uses the rqm bit and the int pin to signal data transfers. 5.2.7 configure issued to select the special features of the 82077AA. a configure command need not be is- sued if the default values of the 82077AA meet the system requirements. configure default values: eis eno implied seeks efifo efifo disabled poll epolling enabled fifothr efifo threshold set to 1 byte pretrk epre-compensation set to track 0 eis eenable implied seek. when set to ``1'', the 82077AA will perform a seek operation before exe- cuting a read or write command. defaults to no im- plied seek. efifo ea ``1'' puts the fifo into the 8272a com- patible mode where the fifo is disabled. this means data transfers are asked for on a byte by byte basis. defaults to ``1'', fifo disabled. the threshold defaults to one. poll edisable polling of the drives. defaults to ``0'', polling enabled. when enabled, a single interrupt is generated after a reset. no polling is performed while the drive head is loaded and the head unload delay has not expired. fifothr ethe fifo threshold in the execution phase of read or write commands. this is program- mable from 1 to 16 bytes. defaults to one byte. a ``00'' selects one byte ``0f'' selects 16 bytes. pretrk epre-compensation start track number. programmable from track 0 to 255. defaults to track 0. a ``00'' selects track 0, ``ff'' selects 255. 5.2.8 version the version command checks to see if the con- troller is an enhanced type or the older type (8272a/ 765a). a value of 90 h is returned as the result byte, defining an enhanced fdd controller is in use. no interrupts are generated. 5.2.9 relative seek the command is coded the same as for seek, ex- cept for the msb of the first byte and the dir bit. dir head step direction control. dir action 0 step head out 1 step head in rcn relative cylinder number that determines how many tracks to step the head in or out from the current track number. the relative seek command differs from the seek command in that it steps the head the abso- lute number of tracks specified in the command in- stead of making a comparison against an internal register. the seek command is good for drives that support a maximum of 256 tracks. relative seeks cannot be overlapped with other relative seeks. only one relative seek can be active at a time. bit 4 of status register 0 (ec) will be set if relative seek attempts to step outward beyond track 0. 32
82077AA as an example, assume that a floppy drive has 300 useable tracks and that the host needs to read track 300 and the head is on any track (0 255). if a seek command was issued, the head would stop at track 255. if a relative seek command was issued, the 82077AA would move the head the specified num- ber of tracks, regardless of the internal cylinder posi- tion register (but would increment the register). if the head had been on track 40 (d), the maximum track that the 82077AA could position the head on using relative seek, would be 296 (d), the initial track, a 256 (d). the maximum count that the head can be moved with a single relative seek command is 256 (d). the internal register, pcn, would overflow as the cylinder number crossed track 255 and would con- tain 40 (d). the resulting pcn value is thus (ncn a pcn) mod 256. functionally, the 82077AA starts counting from 0 again as the track number goes above 255(d). it is the users responsibility to com- pensate 82077AA functions (precompensation track number) when accessing tracks greater than 255. the 82077AA does not keep track that it is working in an ``extended track area'' (greater than 255). any command issued would use the current pcn value except for the recalibrate command which only looks for the track0 signal. recalibrate would return an error if the head was farther than 79 due to its limitation of issuing a maximum 80 step pulses. the user simply needs to issue a second recali- brate command. the seek command and implied seeks will function correctly within the 44 (d) track (299 255) area of the ``extended track area''. it is the users responsibility not to issue a new track posi- tion that would exceed the maximum track that is present in the extended area. to return to the standard floppy range (0 255) of tracks, a relative seek would be issued to cross the track 255 boundary. a relative seek can be used instead of the nor- mal seek but the host is required to calculate the difference between the current head location and the new (target) head location. this may require the host to issue a read id command to ensure that the head is physically on the track that software as- sumes it to be. different 82077AA commands will return different cylinder results which may be difficult to keep track of with software without the read id command. 5.2.10 dumpreg the dumpreg command is designed to support system run-time diagnostics and application soft- ware development and debug. 5.2.11 perpendicular mode command the perpendicular mode command should be issued prior to executing read/write/format commands that access a disk drive with perpendicu- lar recording capability. with this command, the length of the gap2 field and vco enable timing can be altered to accommodate the unique requirements of these drives. table 5-11 describes the effects of the wgate and gap bits for the perpendicular mode command. upon a reset, the 82077AA will default to the conventional mode (wgate e 0, gap e 0). table 5-11 effects of wgate and gap bits vco low length of portion of gap2 gap2 vco gap wgate mode time after gap2 format written by write low time for index pulse field data operation read operations 0 0 conventional mode 33 bytes 22 bytes 0 bytes 24 bytes 0 1 perpendicular mode 33 bytes 22 bytes 19 bytes 24 bytes (500 kbps data rate) 1 0 reserved 33 bytes 22 bytes 0 bytes 24 bytes (conventional) 1 1 perpendicular mode 18 bytes 41 bytes 38 bytes 43 bytes (1 mbps data rate) 33
82077AA selection of the 500 kbps and 1 mbps perpendicular modes is independent of the actual data rate select- ed in the data rate select register. the user must ensure that the two data rates remain consistent. the gap2 and vco timing requirements for perpen- dicular recording type drives are dictated by the de- sign of the read/write head. in the design of this head, a pre-erase head precedes the normal read/ write head by a distance of 200 micrometers. this works out to about 38 bytes at a 1 mbps recording density. whenever the write head is enabled by the write gate signal the pre-erase head is also activat- ed at the same time. thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be precondi- tioned with the pre-erase head since it has not yet been activated. to accommodate this head activa- tion and deactivation time, the gap2 field is expand- ed to a length of 41 bytes. the format field shown in figure 5-2 illustrates the change in the gap2 field size for the perpendicular format. on the read back by the 82077AA, the controller must begin synchronization at the beginning of the sync field. for the conventional mode, the internal pll vco is enabled (vcoen) approximately 24 bytes from the start of the gap2 field. but when the controller operates in the 1 mbps perpendicular mode (wgate e 1, gap e 1), vcoen goes active after 43 bytes to accommodate the increased gap2 field size. for both cases, an approximate 2 byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation. for the write data case, the 82077AA activates write gate at the beginning of the sync field under the conventional mode. the controller then writes a new sync field, data address mark, data field, and crc as shown in figure 5-1. with the pre-erase head of the perpendicular drive, the write head must be activated in the gap2 field to insure a proper write of the new sync field. for the 1 mbps perpen- dicular mode (wgate e 1, gap e 1), 38 bytes will be written in the gap2 space. since the bit density is proportional to the data rate, 19 bytes will be written in the gap2 field for the 500 kbps perpendicular mode (wgate e 1, gap e 0). it should be noted that none of the alterations in gap2 size, vco timing, or write gate timing affect normal program flow. the information provided here is just for background purposes and is not needed for normal operation. once the perpendicular mode command is invoked, 82077AA software be- havior from the user standpoint is unchanged. 5.3 command set enhancements the perpendicular mode and dumpreg com- mands were enhanced along with the addition of a new lock command. these enhancements are ex- plained in this section of the data sheet. the com- mands were enhanced/added in order to provide protection against older software application pack- age which could inadvertently cause system com- patibility problems. the modifications/addition are fully backward compatible with the older 82077AAs which do not support the enhancements. all 82077AAs will support these enhancements as of q1/1991. for more information regarding which 82077AA do or do not support the enhancements please contact your local intel sales office. 5.3.1 perpendicular mode the perpendicular mode command is en- hanced to allow the system designers to designate specific drives as perpendicular recording drives. this enhancement is made so that the system de- signer does not have to worry about older applica- tion software packages which bypass their system's fdc (floppy disk controller) routines. the enhance- ment will also allow data transfers between conven- tional and perpendicular drives without having to is- sue perpendicular mode commands between the accesses of the two different drives, nor having to change write pre-compensation values. the fol- lowing is an explanation of how this enhancement is implemented: old perpendicular mode command: phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 perpendicular mode command w 0 00100 1 0 command w 000000gap wgate code note: for the definition of gap and wgate bits see table 5-11 and section 5.2.11 of the data sheet. for the enhanced perpendicular mode command definition see table 5-1. 34
82077AA with the old implementation, the user must properly program both the perpendicular mode com- mand and write pre-compensation value before ac- cessing either a conventional or perpendicular drive. these programmed values apply to all drives (d0 d3) which the 82077AA may access. it should also be noted that any form of reset ``hardware'' or ``software'' will configure the perpendicular mode command for conventional mode (gap and wgate e ``0''). with the enhanced implementation, both the gap and wgate bits have the same affects as the old implementation except for when they are both pro- grammed for value of ``0'' (conventional mode). for the case when both gap and wgate equal ``0'' the perpendicular mode command will have the following effect on the 82077AA: 1) if any of the new bits d0, d1, d2, and d3 are programmed to ``1'' the corresponding drive will automatically be pro- grammed for perpendicular mode (ie: gap2 being written during a write operation, the programmed data rate will determine the length of gap2.), and data will be written with 0 ns write pre-compensa- tion. 2) any of the new bits (d0 d3) that are pro- grammed for ``0'' the designated drive will be pro- grammed for conventional mode and data will be written with the currently programmed write pre- compensation value. 3) bits d0, d1, d2, and d3 can only be over written when the ow bit is written as a ``1''. the status of these bits can be determined by interpreting the eighth result byte of the enhanced dumpreg command (see section 5.3.3). (note: if either the gap or wgate bit is a ``1'', then bits d0 d3 are ignored.) ``software'' and ``hardware'' reset will have the following effects on the enhanced perpendicu- lar mode command: 1) ``software'' resets (reset via dor or dsr reg- isters) will only clear gap and wgate bits to ``0'', d3, d2, d1, and d0 will retain their previously programmed values. 2) ``hardware'' resets (reset via pin 32) will clear all bits (gap, wgate, d0, d1, d2, and d3) to ``0'' (all drives conventional mode). 5.3.2 lock in order to protect a system with long dma latencies against older application software packages that can disable the 82077AA's fifo the following lock command has been added to the 82077AA's com- mand set: [ note: this command should only be used by the system's fdc routines, and isvs (inde- pendent software vendors) should refrain from us- ing it. if an isv's application calls for having the 82077AA fifo disabled a configure command should be used to toggle the efifo (enable fifo) bit. isv can determine the value of the lock bit by interpreting the eighth result byte of an dumpreg command (see section 5.3.3). ] the lock command defines whether efifo, fifothr, and pretrk parameters of the con- figure command can be reset by the dor and dsr registers. when the lock bit is set to a ``1'' all subsequent ``software'' resets by the dor and dsr registers will not change the previously set pa- rameter values in the configure command. when the lock bit is set to a ``0'' ``software'' resets by the dor or dsr registers will return these parame- ters to their default values (see section 5.2.7). all ``hardware'' resets by pin 32 will set the lock bit to a ``0'' value, and will return efifo, fifothr, and pretrk to their default values. a status byte is re- turned immediately after issuing the command byte. this status byte reflects the value of the lock bit set by the command byte. (note: no interrupts are gen- erated at the end of this command.) 5.3.3 enhanced dumpreg command to accommodate the new lock command and en- hanced perpendicular mode command the eighth result byte of dumpreg command has been modified in the following manner: phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 dumpreg eighth result byte old result r e undefined e enhanced r lock 0 d3 d2 d1 d0 gap wgate notes: 1. data bit 7 reflects the status of the new lock bit set by the lock command. 2. data bits d0 d5 reflect the status for bits d3, d2, d1, d0, gap and wgate set by the perpendicular mode command. 35
82077AA 6.0 status register encoding the contents of these registers are available only through a command sequence. 6.1 status register 0 bit symbol name description no. 7, 6 ic interrupt 00-normal termination of command. the specified command code was properly executed and completed without error. 01-abnormal termination of command. command execution was started, but was not successfully completed. 10-invalid command. the requested command could not be executed. 11-abnormal termination caused by polling. 5 se seek end the 82077AA completed a seek or recalibrate command, or a read or write with implied seek command. 4 ec equipment the trk0 pin failed to become a ``1'' after: check 1. 80 step pulses in the recalibrate command. 2. the relative seek command causes the 82077AA to step outward beyond track 0. 3 e e unused. this bit is always ``0''. 2 h head address the current head address. 1, 0 ds1, 0 drive select the current selected drive. 6.2 status register 1 bit symbol name description no. 7 en end of the 82077AA tried to access a sector beyond the final sector cylinder of the track (255d). will be set if tc is not issued after read or write data command. 6 e e unused. this bit is always ``0''. 5 de data error the 82077AA detected a crc error in either the id field or the data field of a sector. 4 or overrun/ becomes set if the 82077AA does not receive cpu or dma underrun service within the required time interval, resulting in data overrun or underrun. 3 e e unused. this bit is always ``0''. 2 nd no data any one of the following: 1. read data, read deleted data command, the 82077AA did not find the specified sector. 2. read id command, the 82077AA cannot read the id field without an error. 3. read track command, the 82077AA cannot find the proper sector sequence. 1 nw not writable wp pin became a ``1'' while the 82077AA is executing a write data, write deleted data, or format track command. 0 ma missing any one of the following: address mark 1. the 82077AA did not detect an id address mark at the specified track after encountering the index pulse from the idx pin twice. 2. the 82077AA cannot detect a data address mark or a deleted data address mark on the specified track. 36
82077AA 6.3 status register 2 bit symbol name description no. 7 e e unused. this bit is always ``0''. 6 cm control mark any one of the following: 1. read data command, the 82077AA encounters a deleted data address mark. 2. read deleted data command, the 82077AA encounters a data address mark. 5 dd data error the 82077AA detected a crc error in the data field. in data field. 4 wc wrong the track address from the sector id field is different from the track address maintained inside the 82077AA. cylinder 3 e e unused. this bit is always ``0''. 2 e e unused. this bit is always ``0''. 1 bc bad cylinder the track address from the sector id field is different from the track address maintained inside the 82077AA and is equal to ff hex which indicates a bad track with a hard error according to the ibm soft-sectored format. 0 md missing data the 82077AA cannot detect a data address mark or a deleted data address mark. address mark 6.4 status register 3 bit symbol name description no. 7 e e unused. this bit is always ``0''. 6 wp write indicates the status of the wp pin. protected 5 e e unused. this bit is always ``1''. 4 t0 track 0 indicates the status of the trk0 pin. 3 e e unused. this bit is always ``1''. 2 hd head address indicates the status of the hdsel pin. 1, 0 ds1, 0 drive select indicates the status of the ds1, ds0 pins. 7.0 compatibility the 82077AA was designed with software compati- bility in mind. it is a fully backwards compatible solu- tion with the older generation 8272a and nec765a/ b disk controllers. the 82077AA also implements on-board registers for compatibility with the personal system/2s as well as pc/at and pc/xt floppy disk controller subsystems. upon a hardware reset of the 82077AA, all registers, functions and enhancements default to a ps/2, pc/at, or ps/2 model 30 com- patible operating mode depending on how the ident and mfm pins are sampled during hardware reset. 7.1 register set compatibility the register set contained within the 82077AA is a culmination of hardware registers based on the ar- chitectural growth of the ibm personal computer line. table 7-1 indicates the registers required for compatibility based on the type of computer. 37
82077AA table 7-1. 82077AA register support 82077AA 8272a 82072 pc/xt pc/at ps/2 mod register 30 sra x x srb x x dor x x x x msr x x x x x x dsr x data (fifo) x x x x x x dir x x x ccr x * xxx * ccr is emulated by dsr in an 82072 pc/at design. 7.2 ps/2 vs. at vs. model 30 mode to maintain compatibility between ps/2, pc/at, and model 30 environments the ident and mfm pins are provided. the 82077AA is placed into the proper mode of operations upon hardware reset with the appropriate settings of the ident and mfm pins. the proper settings of the ident and mfm pins are described in ident's pin description. differ- ences between the three modes are described in the following sections. 7.2.1 ps/2 mode ident strapped low causes the polarity of densel to be active low for high (500 kbps/1 mbps) data rates (typically used for 3.5 drives). this polalrity of densel assumes invert y to be low. a compre- hensive description of densel behavior is given in table 2-6. the dmagate bit in the digital output register (dor) will not cause the drq or int output signals to tristate. this maintains consistency with the oper- ation of the floppy disk controller subsystem in the ps/2 architecture. tc is an active low input signal that is internally qual- ified by dack being active low. 7.2.2 pc/at mode ident strapped high causes the polarity of densel to be active high for high (500 kbps/1 mbps) data rates (typically used for 5.25 drives). this polarity of densel assumes invert y to be low. a com- prehensive description of densel behavior is given in table 2-6. if the dmagate bit is written to a ``0'' in the digital output register (dor), drq and int will tristate. if dmagate is written to a ``1'', then drq and int will be driven appropriately by the 82077AA. tc is an active high input signal that is internally qualified by dack y being active low. 7.2.3 model 30 mode ident strapped low causes the polarity of densel to be active low for high (500 kbps/1 mbps) data rates (typically used for 3.5 drives). this polarity of densel assumes invert y to be low. a compre- hensive description of densel behavior is given in table 2-6. dmagate and tc function the same as in pc/at mode. 7.3 compatibility with the fifo the fifo of the 82077AA is designed to be trans- parent to non-fifo disk controller software devel- oped on the older generation 8272a standard. oper- ation of the 82077AA fifo can be broken down into two tiers of compatibility. for first tier compatibility, the fifo is left in the default disabled condition upon a ``hardware'' reset (via pin 32). in this mode the fifo operates in a byte mode and provides complete compability with non-fifo based soft- ware. for second tier compatibility, the fifo is en- abled via the configure command. when the fifo is enabled, it will temporarily enter a byte mode during the command and result phase of disk con- troller operation. this allows for compatible opera- tion when interrogating the main status register (msr) for the purpose of transferring a byte at a time to or from the disk controller. for normal disk controller applications, the system designer can still take advantage of the fifo for time critical data transfers during the execution phase and not create any conflicts with non-fifo software during the command or result phase. in some instances, use of the fifo in any form has conflicted with certain specialized software. an ex- ample of a compatibility conflict using the fifo is with software that monitors the progress of a data transfer during the execution phase. if the software assumed the disk controller was operating in a sin- gle byte mode and counted the number of bytes transferred to or from the disk controller to trigger some time dependent event on the disk media (i.e. head position over a specific data field), the same software will not have an identical time relationship if the fifo is enabled. this is because the fifo al- lows data to be queued up, and then burst trans- 38
82077AA ferred across the host bus. to accommodate soft- ware of this type, it is recommended that the fifo be disabled. 7.4 drive polling the 82077AA supports the polling mode of the older generation 8272a. this mode is enabled upon a re- set and can be disabled via the configure com- mand. this mode is supported for the sole purpose of providing backwards compatibility with software that expects it's presence. the intended purpose of drive polling dates back to 8 drives as a means to monitor any change in status for each disk drive present in the system. each of the drives is selected for a period of time and its ready signal sampled. after a delay, the next drive is selected. since the 82077AA does not support ready in this capacity (internally tied true), the polling sequence is only simulated and does not affect the drive select lines (ds0 ds3) when it is active. if enabled, it occurs whenever the 82077AA is waiting for a command or during seeks and re- calibrates (but not implied seeks). each drive is assumed to be not ready after a reset and a ``ready'' value for each drive is saved in an internal register as the simulated drive is polled. an interrupt will be generated on the first polling loop because of the initial ``not ready'' status. this interrupt must be followed with a sense interrupt status com- mand from the host to clear the interrupt condition for each of the four logical drives. 8.0 programming guidelines programming the 82077AA is identical to any other 8272a compatible disk controller with the exception of some additional commands. for the new designer it is useful to provide some guidelines on how to program the 82077AA. a typical disk operation in- volves more than issuing a command and waiting for the results. the control of the floppy disk drive is a low level operation that requires software interven- tion at different stages. new commands and fea- tures have been added to the 82077AA to reduce the complexity of this software interface. 8.1 command and result phase handshaking before a command or parameter byte can be issued to the 82077AA, the main status register (msr) must be interrogated for a ready status and proper fifo direction. a typical floppy controller device driver should contain a subroutine for sending com- mand or parameter bytes. for this discussion, the routine will be called ``send e byte'' with the flow- chart shown in figure 8-1. 290166 22 figure 8-1. send e byte routine 39
82077AA the routine loops until rqm is 1 and dio is 0 indi- cating a ready status and fifo direction is inward. if this condition is true, the 82077AA is ready to accept a command or parameter byte. a timeout counter is used to insure software response within a reason- able amount of time in case of no response by the 82077AA. as a note, the programmer must be care- ful how the maximum delay is chosen to avoid un- necessary timeouts. for example, if a new command is issued when the 82077AA is in the middle of a polling routine, the msr will not indicate a ready status for the next parameter byte until the polling sequence completes the loop. this could cause a delay between the first and second bytes of up to 250 m s( @ 250 kbps). if polling is disabled, this maxi- mum delay is 175 m s. there should also be enough timeout margin to accommodate a shift of the soft- ware to a higher speed system. a timeout value that results in satisfactory operation on a 16 mhz cpu might fail when the software is moved to a system with a 25 mhz cpu. a recommended solution is to derive the timeout counter from a system hardware counter that is fixed in frequency from cpu clock to cpu clock. for reading result bytes from the 82077AA, a similar routine is used. figure 8-2 illustrates the flowchart for the routine ``get e byte''. the msr is polled until rqm is 1 and dio is 1, which indicates a ready status and outward fifo direction. at this point, the host can read a byte from the fifo. as in the send e byte routine, a timout counter should be in- corporated in case of a disk controller lock-up condi- tion. for example, if a disk was not inserted into the disk drive at the time of a read operation, the con- troller would fail to receive the index pulse and lock- up since the index pulses are required for termina- tion of the execution phase. 8.2 initialization initializing the 82077AA involves setting up the ap- propriate configuration after a reset. parameters set by the specify command are undefined after a system reset and will need to be reinitialized. con- figure command parameters default to a known state after a system reset but will need to be reinitial- ized if the system requirements are different from the default settings. the flowchart for the recom- mended initialization sequence of the 82077AA is shown in figure 8-3. 290166 23 figure 8-2. get e byte routine 40
82077AA following a reset of the 82077AA, the configuration control register (ccr) should be reinitialized for the appropriate data rate. an external reset via the re- set pin will cause the data rate and write precom- pensation values to default to 250 kbps (10b) and 125 ns (000b) respectively. since the 125 ns write precompensation value is optimal for the 5 (/4 and 3 (/2 disk drive environment, most applications will not require the value to be changed in the initializa- tion sequence. as a note, a software reset issued via the dor or dsr will not affect the data rate or write precompensation values. but it is recommended as a safe programming practice to always program the data rate after a reset, regardless of the type. since polling is enabled after a reset of the 82077AA, four sense interrupt status com- mands need to be issued afterwards to clear the status flags for each drive. the flowchart in figure 8- 3 illustrates how the software clears each of the four interrupt status flags internally queued by the 82077AA. it should be noted that although four sense interrupt status commands are is- sued, the int pin is only active until the first sense interrupt status command is executed. 290166 24 figure 8-3. initialization flowchart 41
82077AA as a note, if the configure command is issued within 250 m s of the trailing edge of reset ( @ 1 mbps), the polling mode of the 82077AA can be dis- abled before the polling initiated interrupt occurs. since polling stops when the 82077AA enters the command phase, it is only time critical up to the first byte of the configure command. if disabled in time, the system software no longer needs to issue the four sense interrupt status commands to clear the internal interrupt flags normally caused by polling. the configure command should also be issued if the system requirements are different from the de- fault settings (as described in section 5.2.7). for ex- ample, the configure command can be used to enable the fifo, set the threshold, and enable im- plied seeks. the non-dma mode flag, step rate (srt), head load (hlt), and head unload times (hut) programmed by the specify command do not default to a known state after a reset. this behavior is consistent with the 8272a and has been preserved here for compat- ibility. thus, it is necessary to always issue a speci- fy command in the initialization routine. 8.3 recalibrates and seeks commands that position the disk head are different from the typical read/write/format command in the sense that there is no result phase. once a recalibrate, seek, or relative seek com- mand has been issued, the 82077AA will return a ready status in the main status register (msr) and perform the head positioning operation as a back- ground task. when the seek is complete, the 82077AA will assert the int signal to request serv- ice. a sense interrupt status command should then be asserted to clear the interrupt and read the status of the operation. since the drive and motor enable signals are directly controlled through the digital output register (dor) on the 82077AA, a write to the dor will need to precede the recali- brate or seek command if the drive and motor is not already enabled. figure 8-4 shows the flow chart for this operation. 290166 25 figure 8-4. recalibrate and seek operations 42
82077AA 8.4 read/write data operations a read or write data operation requires several steps to complete successfully. the motor needs to be turned on, the head positioned to the correct cylin- der, the dma controller initialized, the read or write command initiated, and an error recovery scheme implemented. the flowchart in figure 8-5 highlights a recommended algorithm for performing a read or write data operation. before data can be transferred to or from the disk- ette, the disk drive motor must be brought up to speed. for most 3 (/2 disk drives, the spin-up time is 300 ms, while the 5 (/4 drive usually requires about 500 ms due to the increased moment of inertia asso- ciated with the larger diameter diskette. one technique for minimizing the motor spin-up de- lay in the read data case is to begin the read opera- tion immediately after the motor is turned on. when the motor is not initially up to speed, the internal data separator will fail to lock onto the incoming data stream and report a failure in the status registers. the read operation is then repeated until successful status is obtained. there is no risk of a data integrity problem since the data field is crc validated. but, it is not recommended to use this technique for the write data operation even though it requires suc- cessful reading of the id field before the write takes place. the data separator performance of the 82077AA is such that locking to the data stream could take place while the motor speed variation is still significant. this could result in errors when an attempt is made to read the disk media by other disk controllers that have a narrower incoming data stream frequency bandwidth. after the motor has been turned on, the matching data rate for the media inserted into the disk drive should then be programmed to the 82077AA via the configuration control register (ccr). the 82077AA is designed to allow a different data rate to be pro- grammed arbitrarily without disrupting the integrity of the device. in some applications, it is required to au- tomatically determine the recorded data rate of the inserted media. one technique for doing this is to perform a read id operation at each available data rate until a successful status is returned in the result phase. if implied seeks are not enabled, the disk drive head must be positioned over the correct cylinder by exe- cuting a seek command. after the seek is com- plete, a head settling time needs to be asserted be- fore the read or write operation begins. for most drives, this delay should be a minimum of 15 ms. when using implied seeks, the minimum head set- tling time can be enforced by the head load time (hlt) parameter designated in the specify com- mand. for example, a hlt value of 8 will yield an effective head settling time of 16 ms for a pro- grammed data rate of 500 kbps. of course if the head is already positioned over the correct cylinder, the head settling time does not need to be enforced. the dma controller is then initialized for the data transfer and the read or write command is executed. typically the dma controller will assert terminal count (tc) when the data transfer is complete. the 82077AA will then complete the current data trans- fer and assert the int signal signifying it has entered the result phase. the result phase can also be en- tered by the 82077AA if an error is encountered or the last sector number equals the end of track (eot) parameter. based on the algorithm in figure 8-5, if an error is encountered after reading the result bytes, two more retries are performed by reinitializing the dma con- troller and re-issuing the read or write data com- mand. a persisting failure could indicate the seek operation did not achieve proper alignment between the head and the track. the disk head should then be recalibrated and the seek repeated for a maxi- mum of two more tries. unsuccessful operation after this point should be reported as a disk failure to the operating system. 8.5 formatting the disk formatting procedure involves positioning the head on each track and creating a fixed format field used for organizing the data fields. the flow- chart in figure 8-6 highlights the typical format pro- cedure. 43
82077AA 290166 26 figure 8-5. read/write operation 44
82077AA 290166 27 figure 8-6 formatting 45
82077AA after the motor has been turned on and the correct data rate programmed, the disk head is recalibrated to track 0. the disk is then allowed to come up to speed via a 500 ms delay. it is important the disk speed has stabilized before the actual formatting to avoid any data rate frequency variations. since the format fields contain critical information used by the data separator of the disk controller for synchroniza- tion purposes, frequency stability of the data stream is imperative for media interchangeability among dif- ferent systems. the id field data created on the disk during the for- mat process is provided by the dma controller dur- ing the execution phase. the dma controller is ini- tialized to send the c, h, r and n values for each sector id field. for example, to format cylinder 7, on head 1, with 9 sectors, and a sector size of 2 (512 bytes), the dma controller should be programmed to transfer 36 bytes (9 sector s x 4 bytes per sector) with the following data field: 7,1,1,2, 7,1,2,2, 7,1,3,2, . . . 7,1,9,2. since the values provided to the 82077AA during the execution phase of the format command are directly recorded as the id fields on the disk, the data contents can be arbitrary. some forms of copy protection have been implemented by taking advantage of this capability. after each head for a cylinder has been formatted, a seek operation to the next cylinder is performed and the format process is repeated. since the format track command does not have implied seek capa- bility, the seek command must be used. also, as discussed in section 8-2, the head settling time needs to be adhered to after each seek operation. 8.6 verifies in some applications, the sector data needs to be verified immediately after each write operation. the verify technique historically used with the 8272a or 82072 disk controller involved reinitializing the dma controller to perform a read transfer or verify transfer (dack y is asserted but not rd y ) immediately after each write operation. a read command is then to be issued to the disk controller and the resulting status indicates if the crc validated the previously written data. this technique has the drawback of requiring additional software intervention by having to repro- gram the dma controller between each sector write operation. the 82077AA supports this older verify technique but also provides a new verify com- mand that does not require the use of the dma con- troller. to verify a write data transfer or format track opera- tion using the verify command, the software sim- ply issues the command with the same format as a read data command but without the support of the dma controller. the 82077AA will then perform a disk read operation without a host data transfer. the crc will be calculated for each sector read and compared against the value stored on the disk. when the verify command is complete, the status register will report any detected crc errors. 9.0 design applications 9.1 pc/at floppy disk controller this section presents a design application of a pc/ at compatible floppy disk controller. with an 82077AA, a 24 mhz crystal, a resistor package, and a device chip select, a complete floppy disk control- ler can be built. the 82077AA integrates all the nec- essary building blocks for a reliable and low cost solution. but before we discuss the design applica- tion using the 82077AA, it is helpful to describe the architecture of the original ibm pc/at floppy disk controller design that uses the 8272a. 9.1.1 pc/at floppy disk controller architecture the standard ibm pc/at floppy disk controller us- ing the 8272a requires 34 devices for a complete solution. the block diagram in figure 9-1 illustrates the complexity of the disk controller. a major portion of this logic involves the design of the data separa- tor. the reliability of the disk controller is primarily dictated by the performance and stability of the data separator. discrete board level analog phase lock loops generally offer good bit jitter margins but suffer from instability and tuning problems in the manufac- turing stage if not carefully designed. while digital data separator designs offer stability and generally a lower chip count, they suffer from poor performance in the recovery of data. 46
82077AA 290166 28 figure 9-1. standard ibm pc/at floppy disk controller table 9-1 indicates the drive and media types the ibm pc/at disk controller can support. this re- quires the data separator to operate at three differ- ent data rates: 250 kbps, 300 kbps and 500 kbps. clocks to the data separator and disk controller need to be prescaled correspondingly to accommo- date each of these data rates. the clock prescaling is controlled by the data rate select register (dsr). supporting all three data rates can compromise the performance of the phase lock loop (pll) if steps are not taken in the design to adjust the perform- ance parameters of the pll with the data rate. table 9-1. standard pc/at drives and media formats capacity drive data sectors cylinders speed rate 360 kbyte 300 rpm 250 kbps 9 40 * 360 kbyte 360 rpm 300 kbps 9 40 1.2 mbyte 360 rpm 500 kbps 15 80 * 360 kbyte diskette in a 1.2 mbyte drive. 47
82077AA the pc/at disk controller provides direct control of the drive selects and motors via the digital output register (dor). as a result, drive selects on the 8272a are not utilized. this places drive selection and motor speed-up control responsibility with the software. the dor is also used to perform a soft- ware reset of the disk controller and tristate the drq2 and irq6 output signals on the pc bus. the design of the disk controller also requires ad- dress decode logic for the disk controller and regis- ter set, buffering for both the disk interface and pc bus, support for write precompensation and monitor- ing of the disk change signal via a separate read only register (dir). an i/o address map of the com- plete register set for the pc/at floppy disk control- ler is shown in table 9-2. table 9-2. i/o address map for the pc/at i/o access description address type 3f0h e unused 3f1h e unused 3f2h write digital output register 3f3h e unused 3f4h read main status register 3f5h read/write data register 3f6h e unused 3f7h write data rate select register 3f7h read digital input register 9.1.2 82077AA pc/at solution the 82077AA integrates the entire pc/at controller design with the exception of the address decode on a single chip. the schematic for this solution is shown in figure 9-2. the chip select for the 82077AA is generated by a 16l8 pal that is pro- grammed to decode addresses 03f0h thru 03f7h when aen (address enable) is low. the program- ming equation for the pal is shown in a abel file format in figure 9-3. an alternative address decode solution could be provided by using a 74ls133 13 input nand gate and 74ls04 inverter to decode a3 a14 and aen. although the pc/at allows for a 64k i/o address space, decoding down to a 32k i/o address space is sufficient with the existing base of add-in cards. a direct connection between the disk interface and the 82077AA is provided by on-chip output buffers with a 40 ma sink capability. open collector outputs from the disk drive are terminated at the disk con- troller with a 150 x resistor pack. the 82077AA disk interface inputs contain a schmitt trigger input struc- ture for higher noise immunity. the host interface is a similar direct connection with 12 ma sink capabili- ties on db0 db7, int and drq. 48
82077AA figure 9-2. 82077AA pc/at floppy disk controller * typical values for 5.25 inch disk drives. for 3.5 inch disk drives, use 1 k x resistors. 290166 29 49
82077AA module pcat077 logic; title `82077AA pc/at floppy disk controller'; pcat077 device `p16l8'; gnd,vcc pin 10,20; sa3,sa4,sa5,sa6,sa7,sa8,sa9,sa10 pin 1,2,3,4,5,6,7,8; sa11,sa12,sa13,sa14,sa15,aen pin 9,11,13,14,15,16; cs077 pin 12; equations `` chip select for the 82077AA (3f0h e 3f7h) cs077 4 !(!sa15 & !sa14 & !sa13 & !sa12 & !sa11 & !sa10 & sa9 & sa8 & sa7 & sa6 & sa5 & sa4 & !sa3 & !aen); end pcat077 logic figure 9-3. pal equation file for a pc/at compatible fdc board 9.2 3.5 drive interfacing the 82077AA is designed to interface to both 3.5 and 5.25 disk drives. this is facilitated by the 82077AA by orienting ident to get the proper polar- ity of densel for the disk drive being used. typical- ly densel is active high for high (500 kbps/ 1 mbps) data rates on 5.25 drives. and densel is typically active low for high data rates on 3.5 drives. a complete description of how to orient ident to get the proper polarity for densel is giv- en in table 2-6. 9.2.1 3.5 drives under the at mode when interfacing the 82077AA floppy disk controller with a 3.5 disk drive in a pc/at application, it is possible that two design changes will need to be implemented for the design discussed in section 9.1. most 3.5 disk drives incorporate a totem pole interface structure as opposed to open collector. outputs of the disk drive will drive both high or low voltage levels when the drive is selected, and float only when the drive has been deselected. these to- tem pole outputs generally can only sink or source 4 ma of current. as a result, it is recommended to replace the 150 x termination resistor pack with a 4.7 k x package to pull floating signals inactive. some other 3.5 drives do have an open collector interface, but have limited sink capability. in these cases, the drive manufacturer manuals usually sug- gest a 1 k x termination. a second possible change required under ``at mode'' operation involves high capacity 3.5 disk drives that utilize a density select signal to switch between media recorded at a 250 kbps and 500 kbps data rate. the polarity of this signal is typi- cally inverted for 3.5 drives versus 5.25 drives. thus, an inverter can be added between the den- sel output of the 82077AA and the disk drive inter- face connector when using 3.5 drives. 50
82077AA but drives that do not support both data rates or drives with an automatic density detection feature via an optical sensor do not require the use of the densel signal. another method is to change the polarity of ident with a drive select signal. oring reset with the drive select signal (ds0 3) used for the 3.5 disk drive will produce the proper polarity for densel (assuming invert y is low). 9.2.2 3.5 drives under the ps/2 modes if ident is strapped to ground, the densel output signal polarity will reflect a typical 3.5 drive mode of operation. that is, densel will be high for 250 kbps or 300 kbps and low for 500 kbps or 1 mbps (as- suming invert y is low). thus the only change from the disk interface shown in figure 9-2 is to re- place the 150 x termination resistor pack with a val- ue of about 10 k x . this will prevent excessive cur- rent consumption on the cmos inputs of the 82077AA by pulling them inactive when the drive(s) are deselected. 9.2.3 combining 5.25 and 3.5 drives if 5.25 and 3.5 drives are to be combined in a design, then steps need to be taken to avoid conten- tion problems on the disk interface. since 3.5 drives do not have a large sink capability, the 150 x termination resistor pack required by 5.25 drives cannot be used with the 3.5 drive. to accommo- date both drives with the same disk controller, the outputs of the 3.5 drive should be buffered before connecting to the 82077AA disk interface inputs. the 82077AA inputs are then connected to the nec- essary resistive termination load for the 5.25 inter- face. the block diagram in figure 9-4 highlights how a combined interface could be designed. in this exam- ple, the 5.25 drive is connected to drive select 0 (ds0) and the 3.5 drive is connected to drive select 1 (ds1). ds1 is also used to enable a 74ls244 buff- er on the output signals of the 3.5 drive. the drive select logic of the 82077AA is mutually exclusive and prevents the activation of the buffer and 5.25 drive at the same time. since the 74ls244 has an i ol of 24 ma, the termination resistor should be in- creased to 220 x . this could impact the reliability of the 5.25 drive interface if the cable lengths are greater than 5 feet. to accommodate the polarity reversal of the den- sel signal for 3.5 drives, it is routed through an inverter for the 3.5 drive interface. a 1 k x pull-up should be placed on the output of the inverter to satisfy the i oh requirements for the 3.5 drive when using a 74ls04. 290166 30 figure 9-4. combined 3.5 and 5.25 drive interface 51
82077AA 10.0 d.c. specifications 10.1 absolute maximum ratings storage temperature b 65 cto a 150 c supply voltage b 0.5 to a 8.0v voltage on any input gnd b 2v to 6.5v voltage on any outputgnd b 0.5v to vcc a 0.5v power dissipation 1 watt notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. 10.2 d.c. characteristics t a e 0 cto e 70 c, v cc ea 5v g 10%, v ss e av ss e 0v symbol parameter min max unit test conditions v ilc input low voltage, x1 b 0.5 0.8 v v ihc input high voltage, x1 3.9 v cc a 0.5 v v il input low voltage b 0.5 0.8 v (all pins except x1) v ih input high voltage 2.0 v cc a 0.5 v (all pins except x1) v ol output low voltage 0.4 v i ol e 2.5 ma mfm drate0 1 0.4 v i ol e 6.0 ma db0 7, int and drq 0.4 v i ol e 12 ma me0 3, ds0 3, dir, stp 0.4 v i ol e 40 ma wrdata, we, hdsel and densel v oh output high voltage 3.0 v i oh eb 2.5 ma mfm all other outputs 3.0 v i oh eb 4.0 ma all outputs v cc b 0.4 v i oh eb 100 m a v cc supply current (total) i cc1 1 mbps data rate, v il e v ss ,v ih e v cc 45 ma (notes 1, 2) i cc2 1 mbps data rate, v il e 0.45, v ih e 2.4 50 ma (notes 1, 2) i cc3 500 kbps data rate, v il e v ss ,v ih e v cc 35 ma (notes 1, 2) i cc4 500 kbps data rate, v il e 0.45, v ih e 2.4 40 ma (notes 1, 2) i ccsb i cc in powerdown 1.5 ma (note 3) i il input load current 10 m av in e v cc (all input pins) b 10 m av in e 0v i ofl data bus output float leakage g 10 m a 0.45 k v out k v cc notes: 1. the data bus are the only inputs that may be floated. 2. tested while reading a sync field of ``00''. outputs not connected to d.c. loads. 3. v il e v ss ,v ih e v cc ; outputs not connected to d.c. loads. 52
82077AA capacitance c in input capacitance 10 pf f e 1 mhz, t a e 25 c c in1 clock input capacitance 20 pf sampled, not 100% tested c i/o input/output capacitance 20 pf note: all pins except pins under test are tied to ac ground. load circuit 82077AA 290166 7 c load e 50 pf for all logic outputs, 100 pf for the data bus. a. c. testing input, output waveform 290166 8 11.0 a.c. specifications t a e 0 cto70 c, v cc ea 5v g 10%, v ss e av ss e 0v symbol parameter min max unit clock timings t1 clock rise time 10 ns clock fall time 10 ns t2 clock high time (7) 16 26 ns t3 clock low time (7) 16 26 ns t4 clock period 41.66 41.66 ns t5 internal clock period (3) host read cycles t7 address setup to rd 5ns t8 rd pulse width 90 ns t9 address hold from rd 0 ns t10 data valid from rd (12) 80 ns t11 command inactive 60 ns t12 output float delay 35 ns t13 int delay from rd t5 a 125 ns t14 data hold from rd 5ns 53
82077AA a.c. specifications (continued) t a e 0 cto70 c, v cc ea 5v g 10%, v ss e av ss e 0v symbol parameter min max unit host write cycles t15 address setup to wr 5ns t16 wr pulse width 90 ns t17 address hold from wr 0 ns t18 command inactive 60 ns t19 data setup to wr 70 ns t20 data hold from wr 0 ns t21 int delay from wr t5 a 125 ns dma cycles t22 drq cycle period (1) 6.5 m s t23 dack to drq inactive 75 ns t24 rd to drq inactive (4) 100 ns t25 dack setup to rd ,wr 5ns t26 dack hold from rd, wr 0 ns t27 drq to rd ,wr active (1) 06 m s t28 terminal count width (10) 50 ns t29 tc to drq inactive 150 ns reset t30 ``hardware'' reset width (5) 170 t4 t30a ``software'' reset width (5) (note 11) m s t31 reset to control inactive 2 m s write data timing t32 write data width (6) ns drive control t35 dir setup to step (14) 1.0 m s t36 dir hold from step 10 m s t37 step active time (high) 2.5 m s t38 step cycle time (2) m s t39 index pulse width 5 t5 t41 we to hdsel change (note 13) ms 54
82077AA a.c. specifications (continued) t a e 0 cto70 c, v cc ea 5v g 10%, v ss e av ss e 0v symbol parameter min max unit read data timing t40 read data pulse width 50 ns f44 pll data rate 82077AA-1, 82077AA (15) 1m bit/s 82077AA-5 (15) 500k bit/s t44 data rate period 1/f44 tlock lockup time 64 t44 notes: 1. this timing is for fifo threshold e 1. when fifo threshold is n bytes, the value should be multiplied by n and subtract 1.5 m s. the value shown is for 1 mbps, scales linearly with data rate. 2. this value can range from 0.5 ms to 8.0 ms and is dependent upon data rate and the specify command value. 3. many timings are a function of the selected data rate. the nominal values for the internal clock period (t5) for the various data rates are: 1 mbps 3 x oscillator period e 125 ns 500 kbps 6 x oscillator period e 250 ns 300 kbps 10 x oscillator period e 420 ns 250 kbps 12 x oscillator period e 500 ns 4. if dack transitions before rd , then this specification is ignored. if there is no transition on dack , then this becomes the drq inactive delay. 5. reset requires a stable oscillator to meet the minimum active period. 6. based on the internal clock period (t 5 ). for various data rates, the write data width minimum values are: 1 mbps 5 x oscillator period b 50 ns e 150 ns 500 kbps 10 x oscillator period b 50 ns e 360 ns 300 kbps 16 x oscillator period b 50 ns e 615 ns 250 kbps 19 x oscillator period b 50 ns e 740 ns 7. test points for clock high time are 3.5v. due to transitional times, clock high time max and clock low time max cannot be met simultaneously. clock high time min and clock low time max cannot be met simultaneously. 8. based on internal clock period (t 5 ). 9. jitter tolerance is defined as: maximum bit shift from nominal position 1/4 period of nominal data rate c 100% it is a measure of the allowable bit jitter that may be present and still be correctly detected. the data separator jitter tolerance is measured under dynamic conditions that jitters the bit stream according to a reverse precompensation algo- rithm. 10. tc width is defined as the time that both tc and dack are active. 11. the minimum reset active period for a software reset is dependent on the data rate, after the 82077AA has been properly reset using the t30 spec. the minimum software reset period then becomes: 1 mbps 21 x t4 e 0.875 m s 500 kbps 42 x t4 e 1.75 m s 300 kbps 70 x t4 e 2.9 m s 250 kbps 84 x t4 e 3.5 m s 12. status register's status bits which are not latched may be updated during a host read operation. 13. the minimum mfm values for we to hdsel change (t41) for the various data rates are: 1 mbps 0.5 ms a [ 8 x gpl ] 500 kbps 1.0 ms a [ 16 x gpl ] 300 kbps 1.6 ms a [ 26.66 x gpl ] 250 kbps 2.0 ms a [ 32 x gpl ] gpl is the size of gap 3 defined in the sixth byte of a write command. 55
82077AA 14. this timing is a function of the selected data rate as follows: 1 mbps 1.0 m s min 500 kbps 2.0 m s min 300 kbps 3.3 m s min 250 kbps 4.0 m s min 15. part specification supported feature tape drive mode perpendicular drive support 82077AA-1 x x 82077AA x 82077AA-5 clock timings 290166 9 host read cycles 290166 10 56
82077AA host write cycles 290166 11 dma cycles 290166 12 terminal count 290166 13 57
82077AA reset 290166 14 note: mfm(0) refers to the mfm pin left open during hardware reset. write data timing 290166 15 note: invert high. 58
82077AA drive control 290166 16 note: for overlapped seeks, only one step pulse per drive selection is issued. non-overlapped seeks will issue all programmed step pulses. invert high. internal pll 290166 17 note: invert high. 59
82077AA 12.0 data separator characteristics for floppy disk mode 290166 32 figure 12-1. typical jitter tolerance vs data rate (capture range) (250 kbps) 290166 33 figure 12-2. typical jitter tolerance vs data rate (capture range) (300 kbps) 290166 34 figure 12-3. typical jitter tolerance vs data rate (capture range) (500 kbps) 290166 35 figure 12-4. typical jitter tolerance vs data rate (capture range) (1 mbps), 82077AA-1 jitter tolerance measured in percent. see datasheet e section 3.2.1 capture range expressed as a percent of data rate, i.e., g 3%. # e test points: 250, 300, 500 kbps, 1 mbps are center, g 3% @ 68% jitter, g 5% @ 65% jitter test points are tested at temperature and v cc limits. refer to the datasheet. typical conditions are: room temperature, nominal v cc . 60
82077AA 13.0 data separator characteristics for tape drive mode 290166 36 figure 13-1. typical jitter tolerance vs data rate (capture range) ( g 0% isv, 500 kbps) 290166 37 figure 13-2. typical jitter tolerance vs data rate (capture range) ( g 0% isv, 1 mbps) 290166 38 figure 13-3. typical jitter tolerance vs data rate (capture range) ( g 3% isv, 500 kbps) 290166 39 figure 13-4. typical jitter tolerance vs data rate (capture range) ( g 3% isv, 1 mbps) notes: 1. jitter tolerance measured in percent. see datasheetesection 3.2.1 capture range expressed as a percent of data rate, i.e., g 5%. 2. typical conditions are: room temperature, nominal v cc . 14.0 82077AA 68-lead plcc package thermal characteristics t a typical values ambient i ja i jc t c t j i cc v cc temp. ( c/w) ( c/w) ( c) ( c) (ma) (v) ( c) 70 75 75 30 5.0 36 5 notes: case temperature formula: t c e t a a p [ i ja b i jc ] junction temperature formula: t j e t c a p [ i jc ] p e power dissipated i jc e thermal resistance from the junction to the case. i ja e thermal resistance from the junction to the ambient. i cc : outputs not connected to d.c. loads. 61
82077AA 15.0 revision summary 82077AA revision summary the following changes have been made since revision 007: all references to the fm mode have been removed. the 82077AA does not support the fm mode. the following change has been made since revision 006: 1. the 82077AA does not support the fm mode. the following changes have been made since revision 005: title page first paragraph, last sentence deleted and replaced with: the 82077AA is available in three versionse82077AA-5, 82077AA and 82077AA-1. 82077AA-1 has all features listed in the data sheet. it supports both tapes drives and 4 mb floppy drives. the 82077AA supports 4 mb floppy drives and is capable of operation at all dates rates through 1 mbps. the 82077AA-5 supports 500/300/250 kbps data rates for high and low density floppy drives. section 2.3 new sentence added to end of paragraph. this sentence reads, ``cs can be held inactive during dma transfers.'' section 5.0 addition of scan equal, scan low or equal, and scan high or equal to table 5-1. section 5.1.8 new section added, titled ``scan commands''. 62

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