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june 2010 doc id 16490 rev 2 1/29 1 STM6513 dual push-button smart reset tm with dual reset outputs and user-selectable setup delay features dual smart reset push-button inputs with user-selectable extended reset setup delay (by three-state input logic): t src = 2, 6, 10 s (min.) capacitor-adjustable reset pulse duration (t rec1 ) power-on reset dual reset output (rst1 is active-high, push- pull type, rst2 is active-low, open-drain) factory-programmable thresholds to monitor v cc in the range of 1.575 to 4.625 v typ. operating voltage 1.0 v (active-low output valid) to 5.5 v low supply current 3 a operating temperature: industrial grade ?40 c to +85 c tdfn8 package: 2 mm x 2 mm x 0.75 mm rohs compliant applications mobile phones, smartphones e-books mp3 players games portable navigation devices any application that requires delayed reset push-button(s) response for improved system stability. tdfn8 (dg) 2 mm x 2 mm www.st.com
contents STM6513 2/29 doc id 16490 rev 2 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 power supply (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 ground (v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 smart reset inputs (sr0 , sr1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 user-programmable smart reset delay (tsr pin) . . . . . . . . . . . . . . . . . . 8 3.5 reset outputs (rst1, rst2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.6 adjustable output reset timeout period input pin (trec adj ) . . . . . . . . . . . 8 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10 tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12 package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM6513 list of tables doc id 16490 rev 2 3/29 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. t rec1 programmed by an ideal external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. dc and ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. possible v cc voltage thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. tdfn ? 8-lead 2 x 2 x 0.75 mm, 0.5 mm package mechanical data . . . . . . . . . . . . . . . . . 21 table 8. parameter for landing pattern - tdfn ? 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 22 table 9. carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12. package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
list of figures STM6513 4/29 doc id 16490 rev 2 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. smart reset delay t src vs. temperature and supply voltage v cc , tsr = v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. output reset timeout period t rec2 vs. temperature and supply voltage v cc (t rec option e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. supply current i cc vs. temperature and supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. reset voltage v rst (falling) vs. temperature (threshold option s, 2.925 v typ.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. input leakage current, tsr pin, logic low vs. temperature and supply voltage v cc . . . . . . 14 figure 11. input leakage current, tsr pin, logic high vs. temperature and supply voltage v cc . . . . . 15 figure 12. ac testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. tdfn - 8-lead, 2 x 2 x 0.75 mm, 0.5 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14. landing pattern - tdfn ? 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 22 figure 15. carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 16. reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 17. tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 18. pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 19. package marking area, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM6513 description doc id 16490 rev 2 5/29 1 description the STM6513 has two separate delayed smart reset inputs (sr0 , sr1 ) which when taken low simultaneously provide three user-selectable delayed smart reset setup time (t src ) options of 2 s, 6 s and 10 s. these are selected through a three-state tsr input pin: when connected to ground, t src = 2 s; when left open, t src = 6 s; when connected to v cc , t src = 10 s (all the times are minimum). there are two reset outputs, both going active simultaneously after both the smart reset inputs were held active for the selected t src delay time. the first reset output, rst1, is active-high, push-pull; the second reset output, rst2 , is active-low, open-drain requiring an external pull-up resistor. the duration of the output reset pulses is independently programmable: t rec1 is user-programmable (by external capacitor c trec ), t rec2 is factory-programmed to 210 ms (typ.), with the option of 360 ms typ. additionally, the v cc is monitored and if it drops below the selected v rst threshold, both the reset outputs go active and remain so while v cc is below the v rst threshold, plus the defined duration of the reset pulse t rec on each output. smart reset devices the smart reset device family stm65xx provides a useful feature that ensures inadvertent short reset push-button closures do not cause system resets. this is done by implementing extended smart reset input delay (t src ). once the valid smart reset input levels and setup delay are met, the device generates an output reset pulse with user-programmable timeout period (t rec ). the smart reset inputs can be also connected to the applications interrupt to allow the control of both the interrupt pin and the hard reset functions. if the push-buttons are closed for a short time, the processor is only inte rrupted. if the system still does not respond properly, holding the push-buttons for the extended setup time (t src ) causes hard reset of the processor through the reset outputs. the smart reset feature helps significantly increase system stab ility. the stm65xx family of smart reset devices consists of low current microprocessor reset circuits targeted at applications such as mp3 players, navigation, smartphones or mobile phones; generally any application that requires delayed reset push-button(s) response for improved system stability. the stm65xx devices feature single or dual smart reset inputs (sr). the delayed smart reset setup time (t src ) options of 2 s, 6 s and 10 s (all min.) are adjustable by an external capacitor on the src pin or selectable by three-state logic. the delayed setup period ignores switch closures shorter than t src , thus preventing unwanted resets. the stm65xx devices have active-low (optionally active-high) open-drain reset (rst ) output(s) with or without internal pull-up resistor or push-pull as output options, with factory- programmed or capacitor-adjustable or push-buttons defined output reset pulse duration, with or without power-on reset function. some devices also have an undervoltage monitoring feature: the reset output is also asserted when the monitored supply voltage v cc drops below the specified threshold. the reset output remains asserted for the reset timeout period (t rec ) after the monitored supply voltage goes above the specified threshold.
description STM6513 6/29 doc id 16490 rev 2 figure 1. logic diagram figure 2. pin connections am00372 v cc rst1 rst2 v ss STM6513 sr0 sr1 tsr trec adj am00373 rst2 trec adj tsr 1 2 3 stm 6513 4 8 7 6 5 rst1 v ss v cc sr1 sr0
STM6513 device overview doc id 16490 rev 2 7/29 2 device overview table 1. signal names symbol input/output description rst1 output first reset output, active-high, push-pull. r st2 output second reset output, active-low, open-drain. s r0 input primary push-button smart reset input. active-low. s r1 input secondary push-button smart reset input. active-low. tsr input a three-state smart reset input delay setup control. when connected to ground, t src = 2 s; when left open, t src = 6 s; when connected to v cc , t src = 10 s (all times are minimum). tsr is a dc-type input, intended to be either permanently grounded, permanently connected to v cc or permanently left open. if left open, for improved system glitch immunity it is strongly recommended to connect a 0.1 f decoupling ceramic capacitor between the tsr and v ss pins. trec adj input input pin for t rec1 reset pulse duration adjustment. connect an external capacitor c trec to this pin to determine t rec1 ; t rec2 is factory- programmed. v cc supply positive supply voltage input. power supply for the device and an input for the monitored supply voltage. a 0.1 f decoupling ceramic capacitor is recommended to be connected between v cc and v ss pins. v ss supply ground
pin descriptions STM6513 8/29 doc id 16490 rev 2 3 pin descriptions 3.1 power supply (v cc ) this pin is used to provide the power to the smart reset device and to monitor the power supply. a 0.1 f decoupling ceramic capacitor is recommended to be connected between v cc and v ss pins. 3.2 ground (v ss ) this is the ground for the device and all supplies. 3.3 smart reset inputs (sr0 , sr1 ) push-button smart reset inputs. both inputs need to be held active at the same time for at least t src to activate the reset outputs. when only one smart reset input is used, connect the unused one permanently to v ss . 3.4 user-programmable smart reset delay (tsr pin) used to allow the user to program the setup time before the push-buttons action is validated by reset output. controlled by different voltage levels on the tsr pin: when connected to ground, t src = 2 s; when left open, t src = 6 s; when connected to v cc , t src = 10 s (all times are minimum). tsr is a dc-type input, intended to be either permanently grounded, permanently connected to v cc or permanently left open. if left open, for improved system glitch immunity it is strongly recommended to connect a 0.1 f decoupling ceramic capacitor between the tsr and v ss pins. 3.5 reset outputs (rst1, rst2 ) reset outputs, rst1 active-high, push-pull type, rst2 active-low, open-drain. 3.6 adjustable output reset timeout period input pin (trec adj ) the output reset timeout period (t rec1 ) on rst1 is adjustable by connecting an external capacitor c trec to the trec adj pin. calculated t rec and c trec examples are given in ta b l e 2 . refer also to ta ble 5 .
STM6513 pin descriptions doc id 16490 rev 2 9/29 table 2. t rec1 programmed by an ideal external capacitor c trec value (f) t rec1 (ms) (1)(2) 1. at 25 c. example calculations based on an ideal capacitor. during application design and component selection it should be considered that the current flowing into the external t rec programming capacitor (c trec ) is on the order of 100 na, therefore a low-leakage capacitor (ceramic or film capacitor) should be used and placed as close as possible to the trec adj pin. also an adequate low-leakage pcb environment should be ensured to prevent t rec accuracy from being affected. a recommended minimum value of c trec is 0.001 f. 2. in case of repeated activations of the internal t rec timer, an interval of 10 ms min. is needed between t rec intervals to fully discharge c trec , so that the next t rec1 is as specified. closest common c trec value (f) min. typ. max. 0.001 10 15 20 0.001 0.002 20 30 40 0.0022 0.01 100 150 200 0.01 0.014 140 210 280 0.015 0.028 280 420 560 0.027 0.056 560 840 1120 0.056 0.112 1120 1680 2240 0.12
block diagram STM6513 10/29 doc id 16490 rev 2 4 block diagram figure 3. block diagram am00374v2 v cc sr1 sr0 tsr trec adj rst2 rst1 v ref i ref t src t rec1 t rec2 sr logic three-state selector oscillator + ?
STM6513 block diagram doc id 16490 rev 2 11/29 STM6513 hookup with rst1 and rst2 , bridging the ps_hold reset pulse during the microprocessor reset initiated by the STM6513 smart reset device: figure 4. typical application diagram figure 5. timing waveforms am00375a v cc pmu seq. logic ld00 ... ld07 pwr sw power key rst_n ps_hold v reg STM6513 tsr trec adj rst1 (pp) rst2 (od) sr0 sr1 v reg (pu resistor) mcu rst ps_hold gpio1 gpion keyn key1 forces ps_hold high during reset period c trec 100 k factory - programmed t rec2 t rec1 t rec1 t src t rec2 am00376v2 por initiated sr0, sr1 rst2 (od) rst1 (pp) by c trec (210 ms) (~1 s) (~1 s) smart reset? initiated (210 ms)
typical operating characteristics STM6513 12/29 doc id 16490 rev 2 5 typical operating characteristics figure 6. smart reset delay t src vs. temperature and supply voltage v cc , tsr = v ss 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature [?c] t src [s] 5.5 v 3.3 v am00632
STM6513 typical operating characteristics doc id 16490 rev 2 13/29 figure 7. output reset timeout period t rec2 vs. temperature and supply voltage v cc (t rec option e) figure 8. supply current i cc vs. temperature and supply voltage v cc 140 160 180 200 220 240 260 280 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature [?c] t rec2 [ms] 5.5 v 3.3 v am00633 0 1 2 3 4 5 6 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature [?c] i cc [a] 5.5 v 3.3 v am00634
typical operating characteristics STM6513 14/29 doc id 16490 rev 2 figure 9. reset voltage v rst (falling) vs. temperature (threshold option s, 2.925 v typ.) figure 10. input leakage current, tsr pin, logic low vs. temperature and supply voltage v cc 2.89 2.9 2.91 2.92 2.93 2.94 2.95 2.96 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature [?c] v rst , falling [v] am00635 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature [?c] i li(tsr) , lo [a] 5.5 v 3.3 v 2 v am00636
STM6513 typical operating characteristics doc id 16490 rev 2 15/29 figure 11. input leakage current, tsr pin, logic high vs. temperature and supply voltage v cc ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature [?c] i li(tsr) , hi [a] 5.5 v 3.3 v 2 v am00637
maximum rating STM6513 16/29 doc id 16490 rev 2 6 maximum rating stressing the device above the rating listed in the table 3: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 3. absolute maximum ratings symbol parameter value unit t stg storage temperature (v cc off) ?55 to +150 c t sld (1) 1. reflow at peak temperature of 260 c. the time above 255 c must not exceed 30 s. lead solder temperature for 10 seconds 260 c ja thermal resistance (junction to ambient) tdfn8 149.0 c/w v io input or output voltage ?0.3 to 5.5 (2) 2. for rst1 ?0.3 to v cc +0.3 v only. v v cc supply voltage ?0.3 to 7 v
STM6513 dc and ac parameters doc id 16490 rev 2 17/29 7 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the table 5: dc and ac characteristics that follow, are derived from tests performed under the measurement conditions summarized in table 4.: operating and measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 12. ac testing input/output waveforms table 4. operating and measurement conditions parameter value unit v cc supply voltage 1.0 to 5.5 v ambient operating temperature (t a ) ?40 to +85 c input rise and fall times 5ns input pulse voltages 0.2 to 0.8 v cc v input and output timing ref. voltages 0.3 to 0.7 v cc v 0.8 v cc 0.2 v cc 0.7 v cc 0.3 v cc am00478
dc and ac parameters STM6513 18/29 doc id 16490 rev 2 table 5. dc and ac characteristics symbol parameter test conditions (1) min. typ. (2) max. units v cc supply voltage range reset output valid - active-low 1.0 5.5 v reset output valid - active-high 1.2 5.5 v i cc supply current (v cc ) v cc = 3.0 v, tsr left open (3) 35a v cc = 5.0 v, tsr left open 4 6 a v ol reset output voltage low v cc 4.5 v, sinking 3.2 ma 0.3 v v cc 3.3 v, sinking 2.5 ma 0.3 v v cc 1.0 v, sinking 0.1 ma 0.3 v v oh reset output voltage high, rst1 v cc 4.5 v, i source = 0.8 ma 0.8 v cc v v cc 2.7 v, i source = 0.5 ma 0.8 v cc v v cc 1.2 v, i source = 0.05 ma 0.8 v cc v v rst fixed voltage trip point for v cc monitoring (refer to ta b l e 6 ) ?40 to +85 c v rst ?2.5% v rst v rst +2.5% v 25 c v rst ?2.0% v rst v rst +2.0% v v hyst hysteresis of v rst l, m 0.5% t, s, r, z, y, w, v 1% v cc to reset delay (4) v cc falling from (v rst + 100 mv) to (v rst - 100 mv) at 10 mv/s 20 s t rec2 output reset timeout period on rst2 , factory-programmed option e 140 210 280 ms option f 240 360 480 ms t rec1 user-adjustable output reset timeout period on rst1 refer to ta b l e 2 . 10 000 x c trec (f) 15 000 x c trec (f) 20 000 x c trec (f) ms
STM6513 dc and ac parameters doc id 16490 rev 2 19/29 smart reset inputs (srx ) t src smart reset delay tsr = v ss 22.53s tsr = floating 6 7.5 9 s tsr = v cc 10 12.5 15 s v il sr0 , s r1 input voltage low v ss ?0.3 0.3 v cc v v ih sr0 , sr1 input voltage high 0.7 v cc 5.5 v input glitch immunity (5) corresponds to the actual t src t src s i li(sr) input leakage current (sr0 , sr1 pins) ?1 1 a i li(tsr) input leakage current (tsr pin) ?5 7 a 1. valid for ambient operating temperature: t a = ?40 to +85 c; v cc = 1.0 v to 5.5 v (except where noted). 2. typical value is at 25 c and v cc = 3.3 v unless otherwise noted. 3. for devices with v rst < 3.0 v. 4. guaranteed by design. 5. input glitch immunity is equal to t src (when both sr inputs are low), otherwise infinite. table 5. dc and ac characteristics (continued) symbol parameter test conditions (1) min. typ. (2) max. units table 6. possible v cc voltage thresholds v cc monitoring threshold v rst typ. 2.5% (?40 c to +85 c) 2.0% (25 c) unit min. max. min. max. l (falling) 4.625 4.509 4.741 4.533 4.718 v m (falling) 4.375 4.266 4.484 4.288 4.463 v t (falling) 3.075 2.998 3.152 3.014 3.137 v s (falling) 2.925 2.852 2.998 2.867 2.984 v r (falling) 2.625 2.559 2.691 2.573 2.678 v z (falling) 2.313 2.255 2.371 2.267 2.359 v y (falling) 2.188 2.133 2.243 2.144 2.232 v w (falling) 1.665 1.623 1.707 1.632 1.698 v v (falling) 1.575 1.536 1.614 1.544 1.607 v
package mechanical data STM6513 20/29 doc id 16490 rev 2 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. figure 13. tdfn - 8-lead, 2 x 2 x 0.75 mm, 0.5 mm pitch e l bottom view 8 5 pin#1 id 1 pin 1 index area 4 b e 0.10 c a a1 plane seating top view 2x 2x d pin 1 index area 0.10 c 0.10 c 0.08 c 0.10 c a b b a c tdfn-8l side view
STM6513 package mechanical data doc id 16490 rev 2 21/29 table 7. tdfn ? 8-lead 2 x 2 x 0.75 mm, 0.5 mm package mechanical data symbol dimension (mm) dimension (inches) min. nom. max. min. nom. max. a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 d bsc 1.9 2.00 2.1 0.075 0.079 0.083 e bsc 1.9 2.00 2.1 0.075 0.079 0.083 e 0.50 0.020 l 0.45 0.55 0.65 0.018 0.022 0.026
package footprint STM6513 22/29 doc id 16490 rev 2 9 package footprint figure 14. landing pattern - tdfn ? 8-lead 2 x 2 mm without thermal pad table 8. parameter for landing pattern - tdfn ? 8-lead 2 x 2 mm package parameter description dimension (mm) min. nom. max. l contact length 1.05 ? 1.15 b contact width 0.25 ? 0.30 e max. land pattern y-direction ? 2.85 ? e1 contact gap spacing ? 0.65 ? d max. land pattern x-direction ? 1.75 ? p contact pitch ? 0.5 ? am00441 d p e1 e l b
STM6513 tape and reel information doc id 16490 rev 2 23/29 10 tape and reel information figure 15. carrier tape t k 0 p 1 a 0 b 0 p 2 p 0 center lines of cavity w e f d to p c o ve r tape user direction of feed am03073v2 table 9. carrier tape dimensions package w d e p 0 p 2 fa 0 b 0 k 0 p 1 tunit bulk qty. tdfn8 8.00 +0.30 ?0.10 1.50 +0.10/ ?0.00 1.75 0.10 4.00 0.10 2.00 0.10 3.50 0.05 2.30 0.05 2.30 0.05 1.00 0.05 4.00 0.10 0.250 0.05 mm 3000
tape and reel information STM6513 24/29 doc id 16490 rev 2 figure 16. reel dimensions table 10. reel dimensions tape sizes a max. b min. c d min. n min. g t max. 8 mm 180 (7 inches) 1.50 13.0 +/? 0.20 20.20 60 8.4 +2/?0 14.40 a d b c n t am00443 40 mm min. acces hole at slot location tape slot in core for tape start 25 mm min width full radius g measured at hub
STM6513 tape and reel information doc id 16490 rev 2 25/29 figure 17. tape trailer/leader figure 18. pin 1 orientation note: 1 drawings are not to scale. 2 all dimensions are in mm, unless otherwise noted. leade r trailer 10 0 mm min. start 160 mm min. 400 mm min. end am00444 to p cover tape user direction of feed sealed with cover tape no components no components components am00442 user direction of feed
part numbering STM6513 26/29 doc id 16490 rev 2 11 part numbering table 11. ordering information scheme for other options, voltage threshold values etc. or for more information on any aspect of this device, please contact the st sales office nearest you. example: STM6513 v e i e dg 6 f device type STM6513 reset (v cc monitoring threshold) voltage v rst l = 4.625 v (typ., falling) m = 4.375 v t = 3.075 v s = 2.925 v r = 2.625 v z = 2.313 v y = 2.188 v w = 1.665 v v = 1.575 v smart reset setup delay (t src ); presence of internal input pull-up on all smart reset inputs (sr0 , sr1 ) e = 2 or 6 or 10 s min., user-programmed (three-state); no input pull-up outputs type i = rst1 active-high, push-pull, rst2 active-low, open-drain, no pull-up reset timeout period (t rec ) e = t rec1 user-programmable (external capacitor), t rec2 factory-programmed (210 ms typ.) f = t rec1 user-programmable (external capacitor), t rec2 factory-programmed (360 ms typ.) package dg = tdfn8 - 2 x 2 x 0.75 mm, 0.5 mm pitch temperature range 6 = ?40 c to +85 c shipping method f = ecopack ? package, tape and reel
STM6513 package marking information doc id 16490 rev 2 27/29 12 package marking information note: al = active-low, ah = active-high; pp = push-pull, od = open-drain, pu = internal pull-up resistor, npu = no internal pull-up resistor. figure 19. package marking area, top view table 12. package marking full part number t src delay control smart reset inputs type v rst rst1 output type t rec1 programming rst2 output type t rec2 option topmark STM6513veiedg6f tsr al, npu v ah, pp c trec al, od, npu e 9ah STM6513seiedg6f tsr al, npu s ah, pp c trec al, od, npu e 9sh STM6513reiedg6f tsr al, npu r ah, pp c trec al, od, npu e 9rh am00479 a bc d e topmark a = dot (pin 1 reference) b = assembly plant (p) c = assembly year (y, 0-9): 9 = 2009 etc. d = assembly work week (ww, 01 to 52): 20 = ww20 etc. e = marking area (topmark)
revision history STM6513 28/29 doc id 16490 rev 2 13 revision history table 13. document revision history date revision changes 22-oct-2009 1 initial release. 21-jun-2010 2 updated title, features , applications , replaced ?smart reset? by ?smart reset?? and ?smart reset?, updated section 1 , ta b l e 1 , section 3 , ta b l e 2 , figure 3 , figure 5 , figure 6 , ta b l e 3 , ta b l e 5 to ta b l e 8 , ta b l e 1 1 and ta b l e 1 2 .
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