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S5935 pci product data book for marketing and application information contact: applied micro circuits corporation 6290 sequence drive san diego, ca 92121-4358 (800) 755-2622 (619) 450-9333 fax (619) 450-9885 http://www.amcc.com a pplied m icro c ircuits c orporation
the material in this document supersedes all previous documentation issued for any of the products included herein. copyright ? 1999 applied micro circuits corporation printed in u.s.a./pciprod-1299 amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. amcc and matchmaker are registereded trademarks of applied micro circuits corporation. all other product names are trademarks, registered trademarks, or servicemarks of their respective owners.
i 1. architectural overview ...................................................................................................... ......... 1-1 introduction to the pci local bus .............................................................................................. ........... 1-1 S5935 architecture ............................................................................................................. ................... 1-2 S5935 register architecture .................................................................................................... ............. 1-2 pci configuration registers .................................................................................................... ............. 1-2 pci operation registers ........................................................................................................ ............... 1-3 add-on bus operation registers ................................................................................................. ........ 1-3 non-volatile memory interface .................................................................................................. ............ 1-3 mailbox operation .............................................................................................................. ................... 1-4 pass-thru operation ............................................................................................................ ................. 1-5 fifo pci bus mastering operation ............................................................................................... ....... 1-5 2. signal descriptions ......................................................................................................... ................ 2-9 signal type definition ......................................................................................................... .................. 2-9 address and data pins C pci local bus .......................................................................................... .. 2-10 pci bus interface signals ...................................................................................................... ............. 2-10 system pins C pci local bus .................................................................................................... .......... 2-11 interface control pins C pci bus signal ................................................................................... 2-11 arbitration pins (bus masters only) C pci local bus .............................................................. 2-12 error reporting pins C pci local bus ..................................................................................... 2-12 interrupt pin C pci local bus .................................................................................................. 2-12 non-volatile memory interface signals .......................................................................................... ..... 2-13 serial nv devices .............................................................................................................. ....... 2-13 byte-wide nv devices ........................................................................................................... .. 2-13 add-on bus interface signals ................................................................................................... .......... 2-14 register access pins ........................................................................................................... .... 2-14 fifo access pins ............................................................................................................... ..... 2-15 pass-thru interface pins ....................................................................................................... .. 2-15 system pins .................................................................................................................... ......... 2-16 3. pci configuration registers ................................................................................................. .... 3-17 pci configuration space header ................................................................................................. ....... 3-18 vendor identification register (vid) ........................................................................................... ......... 3-19 device identification register (did) ........................................................................................... ......... 3-20 pci command register (pcicmd) .................................................................................................. .. 3-21 pci status register (pcists) ................................................................................................... ......... 3-23 revision identification register (rid) ......................................................................................... ........ 3-25 class code register (clcd) ..................................................................................................... ......... 3-26 cache line size register (caln) ................................................................................................ ...... 3-30 latency timer register (lat) ................................................................................................... .......... 3-31 header type register (hdr) ..................................................................................................... ......... 3-32 built-in self-test register (bist) ............................................................................................. ........... 3-33 base address registers (badr) .................................................................................................. ...... 3-34 expansion rom base address register (xrom) .............................................................................. 3-38 interrupt line register (intln) ................................................................................................ ........... 3-40 interrupt pin register (intpin) ................................................................................................ .......... 3-41 c ontents
ii minimum grant register (mingnt) ................................................................................................ ... 3-42 maximum latency register (maxlat) .............................................................................................. . 3-43 4. pci bus operation registers ................................................................................................. ..... 4-45 outgoing mailbox registers (omb) ............................................................................................... ..... 4-46 incoming mailbox registers (imb) ............................................................................................... ....... 4-46 fifo register port (fifo) ...................................................................................................... ............ 4-46 pci controlled bus master write address register (mwar) ............................................................. 4-47 pci controlled bus master write transfer count register (mwtc) .................................................. 4-48 pci controlled bus master read address register (mrar) ............................................................. 4-49 pci controlled bus master read transfer count register (mrtc) ................................................... 4-50 mailbox empty full/status register (mbef) ...................................................................................... . 4-51 interrupt control/status register (intcsr) ..................................................................................... ... 4-53 master control/status register (mcsr) .......................................................................................... ... 4-57 5. add-on bus operation registers ............................................................................................. 5 -61 add-on incoming mailbox registers (aimbx) .................................................................................... 5- 62 add-on outgoing mailbox registers (aombx) ................................................................................... 5-6 2 add-on fifo register port (afifo) .............................................................................................. .... 5-62 add-on controlled bus master write address register (mwar) ....................................................... 5-63 add-on pass-thru address register (apta) ..................................................................................... 5- 64 add-on pass-thru data register (aptd) .......................................................................................... 5-64 add-on controlled bus master read address register (mrar) ....................................................... 5-65 add-on empty/full status register (ambef) .................................................................................... 5- 66 add-on interrupt control/status register (aint) ............................................................................... 5 -68 add-on general control/status register (agcsts) ......................................................................... 5-71 add-on controlled bus master write transfer count register (mwtc) ............................................ 5-74 add-on controlled bus master read transfer count register (mrtc) ............................................ 5-75 6. initialization .............................................................................................................. ....................... 6-77 pci reset ...................................................................................................................... ...................... 6-77 loading from byte-wide nv memories ............................................................................................. .. 6-77 loading from serial nv memories ................................................................................................ ...... 6-78 pci bus configuration cycles ................................................................................................... .......... 6-80 expansion bios roms ............................................................................................................ .......... 6-82 7. pci bus interface ........................................................................................................... ................. 7-85 pci bus transactions ........................................................................................................... .............. 7-86 pci burst transfers ............................................................................................................ ..... 7-86 pci read transfers ............................................................................................................. .... 7-88 pci write transfers ............................................................................................................ ..... 7-89 master-initiated termination ................................................................................................... . 7-89 normal cycle completion ........................................................................................................ 7-89 initiator preemption ........................................................................................................... ...... 7-90 master abort ................................................................................................................... ......... 7-91 target-initiated termination ................................................................................................... .. 7-91
iii target disconnects ............................................................................................................. ..... 7-92 target requested retries ....................................................................................................... . 7-93 target aborts .................................................................................................................. ......... 7-93 pci bus mastership ............................................................................................................ ............... 7-95 bus mastership latency components ..................................................................................... 7-95 bus arbitration ................................................................................................................ ......... 7-95 bus acquisition ................................................................................................................ ........ 7-96 target latency ................................................................................................................. ........ 7-96 target locking ................................................................................................................. ........ 7-96 pci bus interrupts ............................................................................................................. .................. 7-98 pci bus parity errors .......................................................................................................... ................ 7-98 8. add-on bus interface ........................................................................................................ ............ 8-99 add-on operation register accesses ............................................................................................. ... 8-99 add-on interface signals ....................................................................................................... . 8-99 system signals ................................................................................................................. ....... 8-99 register access signals ........................................................................................................ .. 8-99 asynchronous register accesses ......................................................................................... 8-100 synchronous fifo and pass-thru data register accesses ................................................. 8-100 nv memory accesses through the add-on general control/status register ....................... 8-100 mailbox bus interface .......................................................................................................... ............. 8-100 mailbox interrupts ............................................................................................................. ..... 8-103 fifo bus interface ............................................................................................................. ............... 8-103 fifo direct access inputs ..................................................................................................... 8 -103 fifo status signals ............................................................................................................ .. 8-103 fifo control signals ........................................................................................................... .. 8-103 pass-thru bus interface ........................................................................................................ ........... 8-103 pass-thru status indicators .................................................................................................. 8- 104 pass-thru control inputs ....................................................................................................... 8-104 non-volatile memory interface .................................................................................................. ........ 8-104 non-volatile memory interface signals ................................................................................. 8-104 accessing non-volatile memory ............................................................................................ 8-105 nv memory device timing requirements .............................................................................. 8-107 9. mailbox overview ............................................................................................................ ............. 9-109 functional description ......................................................................................................... ............. 9-109 mailbox empty/full conditions ............................................................................................... 9-1 10 mailbox interrupts ............................................................................................................. ...... 9-110 add-on outgoing mailbox 4, byte 3 access ........................................................................... 9-110 bus interface .................................................................................................................. .................... 9-111 pci bus interface .............................................................................................................. ..... 9-111 add-on bus interface ........................................................................................................... .. 9-111 8-bit and 16-bit add-on interfaces ......................................................................................... 9-11 1 configuration .................................................................................................................. .................... 9-112 mailbox status ................................................................................................................. ....... 9-112 mailbox interrupts ............................................................................................................. ...... 9-113
iv 10. fifo overview .............................................................................................................. .................10-117 functional description ......................................................................................................... ............ 10-117 fifo buffer management and endian conversion .............................................................. 10-117 fifo advance conditions ..................................................................................................... 10- 117 endian conversion .............................................................................................................. . 10-118 64-bit endian conversion ..................................................................................................... 10 -119 add-on fifo status indicators ........................................................................................... 10-120 add-on fifo control signals .............................................................................................. 10-120 pci bus mastering with the fifo ........................................................................................ 10-120 add-on initiated bus mastering ........................................................................................... 10-120 pci initiated bus mastering ................................................................................................. 10- 121 address and transfer count registers ............................................................................... 10-121 bus mastering fifo management schemes ...................................................................... 10-121 fifo bus master cycle priority ........................................................................................... 10-122 fifo generated bus master interrupts ............................................................................... 10-122 bus interface .................................................................................................................. ................. 10-122 fifo pci interface (target mode) ....................................................................................... 10-122 fifo pci interface (initiator mode) ..................................................................................... 10-123 fifo pci bus master reads ............................................................................................... 10-125 fifo pci bus master writes ............................................................................................... 10-125 add-on bus interface .......................................................................................................... 1 0-125 add-on fifo register accesses ........................................................................................ 10-125 add-on fifo direct access mode ...................................................................................... 10-126 additional status/control signals for add-on initiated bus mastering ................................ 10-127 fifo generated add-on interrupts ..................................................................................... 10-128 8-bit and 16-bit fifo add-on interfaces ............................................................................. 10-128 configuration .................................................................................................................. ................. 10-129 fifo setup during initialization ........................................................................................... 10-1 29 fifo status and control bits ............................................................................................... 10-1 29 pci initiated fifo bus mastering setup ............................................................................. 10-130 add-on initiated fifo bus mastering setup ....................................................................... 10-131 11. pass-thru overview ......................................................................................................... .........11-133 functional description ......................................................................................................... ............ 11-133 pass-thru transfers ............................................................................................................ . 11-133 pass-thru status/control signals ........................................................................................ 11-134 pass-thru add-on data bus sizing ..................................................................................... 11-134 bus interface .................................................................................................................. .................. 11-134 pci bus interface .............................................................................................................. ... 11-134 pci pass-thru single cycle accesses ................................................................................. 11-134 pci pass-thru burst accesses ............................................................................................ 11-134 pci retry conditions ........................................................................................................... . 11-134 pci write retries .............................................................................................................. .... 11-134 pci read retries ............................................................................................................... ... 11-136 add-on bus interface ........................................................................................................... 11-136 single cycle pass-thru writes ............................................................................................. 11-13 6
v single cycle pass-thru read s ............................................................................................ . 1 1-138 pass-thru burst w rite s ....................................................................................................... . 1 1-139 pass-thru burst read s ....................................................................................................... . 1 1-143 add-on pass-thru disconnect operatio n ........................................................................... . 1 1-147 8-bit and 16-bit pass-thr u add-on bus interfac e ............................................................... . 1 1-148 configuratio n ................................................................................................................................... . 1 1-151 S5935 bas e address register definitio n ............................................................................. . 1 1-151 creating a pass-thru regio n .............................................................................................. . 1 1-151 accessing a pass-thru regio n ........................................................................................... . 1 1-152 12. electrical characteristic s ............................................................................................... . 12-153 absolute maximum rating s ........................................................................................................... . 12-153 dc characteristic s ......................................................................................................................... . 12-153 pci bus signal s ............................................................................................................................. . 12-154 add-on bus signal s ........................................................................................................... . 12-155 ac characteristic s ......................................................................................................................... . 12-156 pci bu s t iming s ................................................................................................................. . 12-156 add-on bu s t iming s ........................................................................................................... . 12-158 synchronous rdfifo # t imin g ........................................................................................... . 12-159 synchronous wrfifo # t imin g .......................................................................................... . 12-160 asynchronous rd# registe r access t imin g ...................................................................... . 12-161 asynchronous wr# registe r access t imin g ..................................................................... . 12-162 synchronous rd# fif o t imin g .......................................................................................... . 12-163 synchronous multiple rd# fif o t imin g ............................................................................ . 12-164 synchronous wr# fif o t imin g ......................................................................................... . 12-165 synchronous multiple wr# fif o t imin g ........................................................................... . 12-166 t arget S5935 pass-thru interfac e t iming s ........................................................................ . 12-167 t arget byte-wide nv memory interfac e t iming s ................................................................. . 12-169 t arget interrup t t iming s ...................................................................................................... . 12-171 13. pinou t and p ackage inform a tio n ...................................................................................... . 13-173 S5935 pinout and pi n assignment C 160 pqf p ............................................................................ . 13-173 S5935 pinout and pi n assignment C 20 8 tqf p ............................................................................ . 13-174 package physical dimensions C 160 pqf p .................................................................................. . 13-177 package physical dimensions C 20 8 tqf p .................................................................................. . 13-181 ordering informatio n ...................................................................................................................... . 13-190
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1-1 architectural overview S5935 ? features ? pci 2.1 compliant master/slave device ? full 132 mbytes/sec transfer rate ? supports new intel 440bx/gx chipsets ? supports new winnt service pack 2 & 3 ? pci bus operation dc to 33 mhz ? 8/16/32 bit add-on user bus ? four definable pass-thru data channels ? two 32 byte internal fifos w/dma ? synchronous add-on bus operation ? mail box registers w/byte level status ? direct mail box data strobe/interrupts ? direct pci & add-on interrupt pins ? optional non-volatile memory boot loading ? optional expansion bios/post code applications ? high speed networking ? digital video applications ? i/o communications ports ? high speed data input/output ? multimedia communications ? memory interfaces ? high speed data acquisition ? data encryption/decryption ? intel i960 interface ? general purpose pci interfacing ? existent s5933 design upgrades description the pci local bus concept was developed to break the pc data i/o bottleneck and clearly opens the door to increasing system speed and expansion capabilities. the pci local bus moves high speed peripherals from the i/o bus and places them closer to the systems processor bus, providing faster data transfers between the processor and peripherals. the pci local bus also addresses the industrys need for a bus standard which is not directly dependent on the speed, size and type of system processor. it represents the first microproces- sor independent bus offering performance more than adequate for the most demanding applications such as full-motion video. applied micro circuits corporation (amcc), the pre- mier supplier of single chip solutions, has developed the S5935 to solve the problem of interfacing applications to the pci local bus while offering support for newer pci chipsets and operating systems. the S5935 is a powerful and flexible pci controller supporting several levels of interface sophistication. at the lowest level, it can serve simply as a pci bus target with modest transfer requirements. for high-performance applica- tions, the S5935 can become a bus master to attain the pci local bus peak transfer capability of 132 mbytes/ sec. the S5935 pci controller also maintains drop-in compatibility for upgrading many existent s5933 de- signs requiring migration into new motherboard archi- tectures, pci bioss and software operating systems. pci local bus user application satellite receiver/ modem proprietary backplane graphics/ mpeg/ grabber isdn fddi atm i/o audio serial/parallel nvram configuration space expansion bios amcc add-on local bus interface logic mux/demux buffers S5935 status registers configuration registers mailboxes fifos bus master transfer count & address registers pass-thru data & address registers 2.1 pci local bus interface logic mux/demux buffers read/write control figure 1. S5935 block diagram
1-2 architectural overview S5935 add-on bus control s5933 register access pass-thru control/access serial bus config/bios opt. pci local bus S5935 control add-on data bus direct fifo access byte wide config/bios opt. bpclk rdfifo# sysrst# irq# wrfifo# dq[31:0] select# adr[6:2] be[3:0]# rd# wr# ptatn# ptburst# ptnum[1:0]# ptbe[3:0]# ptadr# ptwr ptrdy# rdempty wrfull ea[15:0] eq[7:0] ewr#/sda erd#/scl pclk inta# rst# ad[31:0] c/be[3:0]# frame# devsel# irdy# trdy# idsel# stop# lock# par perr# serr# S5935 gnt# req# mode snv the S5935 is an off-the-shelf, low-cost, standard prod- uct, which is pci 2.1 compliant. and, since amcc is a member of the pci special interest group, the S5935 has been tested on various manufacturers pci motherboards, chip sets, pci bioss and operating systems. this removes the burden of compliance and compatibility testing from the designer and thus signifi- cantly reduces development time. utilizing the S5935 allows the designer to focus on the actual application, not debugging the pci interface. the S5935 allows special direct data accessing be- tween the pci bus and the user application through implementation of four definable pass-thru data chan- nels. each data channel is implemented by defining a host memory segment size and 8/16/32-bit user bus width. the addition of two 32 byte fifos, also used in S5935 bus mastering applications, provides further versatility to data transfer capabilities. fifo dma trans- fers are supported using address and transfer count registers. four 32-bit mailbox registers coupled with a status register and extensive interrupt capabilities provide flexible user command or message transfers between the two buses. in addition, the S5935 also allows use of an external serial, or byte-wide non- volatile memory to perform any pre-boot initialization requirements and to provide custom expansion bios or post code capability. S5935 architecture the block diagram in figure 1 above shows the major functional elements within the S5935. the S5935 pro- vides three physical bus interfaces: the pci local bus, the user local bus referred to as the add-on local bus and the optional serial and byte-wide non-volatile memory buses. data movement between buses can take place through mailbox registers or the fifo data channel, or a user can define and enable one or more of the four pass-thru data channels. S5935 bus master or dma data transfers to and from the pci local bus are performed through the fifo data channel under either host or add-on software control or add-on hardware control using dedicated S5935 signal pins. the S5935 signal pins are shown in figure 2. the pci local bus signals are detailed on the left side; add-on local bus signal are detailed on the right side. all additional S5935 device control signals are shown on the lower right side. the S5935 supports a two wire serial nvram bus and a byte-wide eprom/flash bus. this allows the de- signer to customize the S5935 configuration by loading setup information on system power-up. S5935 register architecture control and configuration of the add-on local bus, and the S5935 itself, is performed through three primary groups of registers. these groups consist of pci con- figuration registers, pci operation registers and add- on operation registers. these registers are user configurable through either their associated bus or from an external non-volatile memory device. this section will provide a brief overview of each of these register groups and the optional non-volatile interface. pci configuration registers all pci compliant devices are required to provide a group of configuration registers for the host system. these registers are polled during power up initialization and contain specific device and add-in card product information including vendor id, device id, revision and the amount of memory required for product opera- tion. the S5935 can either load these registers with default values or initialize them from an external non- volatile memory area called configuration space. the S5935 can accommodate a total of 256 bytes of exter- nal memory for this purpose. the first 64 bytes is reserved for user defined configuration data which is loaded into the pci configuration registers during power-up initialization. the remaining 192 bytes may be used to implement an expansion bios or contain add-in card post code. table 1 shows all the S5935 pci configuration registers. figure 2.
1-3 architectural overview S5935 pci operation registers the second group of registers are the pci operation registers shown in table 2. this group consists of sixteen 32-bit (dword) registers accessible to the host processor from the pci local bus. these are the main registers through which the pci host configures S5935 operation and communicates with the add-on local bus. these registers encompass the pci bus incoming and outgoing mailboxes, fifo data channel, bus master address and count registers, pass-thru data channel registers and S5935 device status and control registers. add-on bus operation registers the third and last register group consists of the add-on operation registers, shown in table 3. this group of eighteen 32-bit (dword) registers is accessible to the add-on local bus. these are the main registers through which the add-on logic configures S5935 operation and communicates with the pci local bus. these registers encompass the add-on bus mailboxes, add- on fifo, dma address/count registers (when add- on initiated bus mastering), pass-thru registers and status/control registers. non-volatile memory interface the S5935 contains a set of pci configuration regis- ters. these registers can be initialized with default values or with designer specified values contained in an external nvram. the nvram can be either a serial (2 kbytes, maximum) or a byte-wide device (64 kbytes, maximum). the optional nvram allows the add-on card manufac- turer to initialize the S5935 with his specific vendor id and device id numbers along with desired S5935 operation characteristics. the non-volatile memory fea- ture also provides for the expansion bios and post code (power-on-self-test) options on the pci bus. 3 e t y b 2 e t y b 1 e t y b 0 e t y b s s e r d d a d i e c i v e dd i r o d n e vh 0 0 s u t a t s i c pd n a m m o c i c ph 4 0 e d o c s s a l cd i n o i s i v e rh 8 0 t s e t f l e s n i - t l i u be p y t r e d a e hr e m i t y c n e t a le z i s e n i l e h c a ch c 0 0 r e t s i g e r s s e r d d a e s a bh 0 1 1 r e t s i g e r s s e r d d a e s a bh 4 1 2 r e t s i g e r s s e r d d a e s a bh 8 1 3 r e t s i g e r s s e r d d a e s a bh c 1 4 r e t s i g e r s s e r d d a e s a bh 0 2 d e v r e s e rh 4 2 e c a p s d e v r e s e rh 8 2 e c a p s d e v r e s e rh c 2 s s e r d d a e s a b m o r n o i s n a p x eh 0 3 e c a p s d e v r e s e rh 4 3 e c a p s d e v r e s e rh 8 3 y c n e t a l . x a mt n a r g . n i mn i p t p u r r r e t n ie n i l t p u r r e t n ih c 3 table 1. pci configuration registers s r e t s i g e r n o i t a r e p o i c p s s e r d d a t e s f f o ) 1 b m o ( 1 r e t s i g e r x o b l i a m g n i o g t u oh 0 0 ) 2 b m o ( 2 r e t s i g e r x o b l i a m g n i o g t u oh 4 0 ) 3 b m o ( 3 r e t s i g e r x o b l i a m g n i o g t u oh 8 0 ) 4 b m o ( 4 r e t s i g e r x o b l i a m g n i o g t u oh c 0 ) 1 b m i ( 1 r e t s i g e r x o b l i a m g n i m o c n ih 0 1 ) 2 b m i ( 2 r e t s i g e r x o b l i a m g n i m o c n ih 4 1 ) 3 b m i ( 3 r e t s i g e r x o b l i a m g n i m o c n ih 8 1 ) 4 b m i ( 4 r e t s i g e r x o b l i a m g n i m o c n ih c 1 ) o f i f ( ) l a n o i t c e r i d i b ( t r o p r e t s i g e r o f i fh 0 2 ) r a w m ( r e t s i g e r s s e r d d a e t i r w r e t s a mh 4 2 ) c t w m ( r e t s i g e r t n u o c r e f s n a r t e t i r w r e t s a mh 8 2 ) r a r m ( r e t s i g e r s s e r d d a d a e r r e t s a mh c 2 ) c t r m ( r e t s i g e r t n u o c r e f s n a r t d a e r r e t s a mh 0 3 ) f e b m ( r e t s i g e r s u t a t s l l u f / y t p m e x o b l i a mh 4 3 ) r s c t n i ( r e t s i g e r s u t a t s / l o r t n o c t p u r r e t n ih 8 3 ) r s c m ( r e t s i g e r s u t a t s / l o r t n o c r e t s a m s u bh c 3 table 2. pci operation registers
1-4 architectural overview S5935 pci local bus mailbox status register S5935 add-on local bus pci mb1 byte 0 pci mb2 byte 0 pci mb3 byte 0 pci mb4 byte 0 pci mb1 byte 1 pci mb2 byte 1 pci mb3 byte 1 pci mb4 byte 1 pci mb1 byte 2 pci mb2 byte 2 pci mb3 byte 2 pci mb4 byte 2 pci mb1 byte 3 pci mb2 byte 3 pci mb3 byte 3 pci mb4 byte 3 add mb1 byte 0 add mb2 byte 0 add mb3 byte 0 add mb4 byte 0 add mb1 byte 1 add mb2 byte 1 add mb3 byte 1 add mb4 byte 1 add mb1 byte 2 add mb2 byte 2 add mb3 byte 2 add mb4 byte 2 add mb1 byte 3 add mb2 byte 3 add mb3 byte 3 add mb4 byte 3 mailbox operation the mailbox registers are divided into two four dword sets. each set is dedicated to one bus for transferring data to the other bus. figure 3 below shows a block diagram of the mailbox section of the S5935. the provision of mailbox registers provides an easy path for the transfer of user information (command, status or parametric data) between the two buses. an empty/full indication for each mailbox register, at the byte level, is determined by polling a status register accessible to both the pci and add-on buses. providing mailbox byte level empty/full indications allows for greater flexibility in 8-, 16- or 32-bit system interfaces. i.e., transferring a single byte to an 8-bit add-on bus without requiring the assembling or disassembling of 32-bit data. the generation of interrupts from mailbox registers is equivalent with the commonly known doorbell interrupt technique. bit locations configured within the S5935s operation registers select a mailbox and mailbox byte which is to generate an interrupt when full or touched. a mailbox interrupt control register is then used to enable interrupt generation and to select if the interrupt is to be generated on the pci or add-on local bus. pci local bus interrupts may also be generated from direct hardware interfacing due to a unique amcc feature. a dedicated mailbox byte is directly accessible via a set of hardware device signal pins. a mailbox load signal pin latches add-on bus data directly into the mailbox initiating a pci bus interrupt if enabled. mailbox data may also be read in a similar manner. this option is shared with the byte wide non-volatile memory signal pins. the S5935 must use the serial nvram for the direct mailbox option signal pins to be available or they are assigned to the byte wide at power up. s r e t s i g e r n o i t a r e p o s u b n o - d d a s s e r d d a ) 1 b m i a ( 1 r e t s i g e r x o b l i a m g n i m o c n ih 0 0 ) 2 b m i a ( 2 r e t s i g e r x o b l i a m g n i m o c n ih 4 0 ) 3 b m i a ( 3 r e t s i g e r x o b l i a m g n i m o c n ih 8 0 ) 4 b m i a ( 4 r e t s i g e r x o b l i a m g n i m o c n ih c 0 ) 1 b m o a ( 1 r e t s i g e r x o b l i a m g n i o g t u oh 0 1 ) 2 b m o a ( 2 r e t s i g e r x o b l i a m g n i o g t u oh 4 1 ) 3 b m o a ( 3 r e t s i g e r x o b l i a m g n i o g t u oh 8 1 ) 4 b m o a ( 4 r e t s i g e r x o b l i a m g n i o g t u oh c 1 ) o f i f a ( t r o p o f i fh 0 2 ) r a w m ( r e t s i g e r s s e r d d a e t i r w r e t s a m s u bh 4 2 ) a t p a ( r e t s i g e r s s e r d d a u r h t - s s a ph 8 2 ) d t p a ( r e t s i g e r a t a d u r h t - s s a ph c 2 ) r a r m ( r e t s i g e r s s e r d d a d a e r r e t s a m s u bh 0 3 ) f e b m a ( r e t s i g e r s u t a t s l l u f / y t p m e x o b l i a mh 4 3 ) t n i a ( r e t s i g e r s u t a t s / l o r t n o c t p u r r e t n ih 8 3 ) r c r a ( r e t s i g e r s u t a t s / l o r t n o c l a r e n e gh c 3 ) c t w m ( t n u o c r e f s n a r t e t i r w r e t s a m s u bh 8 5 ) c t r m ( t n u o c r e f s n a r t d a e r r e t s a m s u bh c 5 table 3. add-on bus operation registers figure 3.
1-5 architectural overview S5935 pci local bus S5935 add-on pass-thru read data add-on pass-thru write data add-on local bus address latch add-on pass- thru address register pass-thru operation pass-thru operation executes pci bus cycles in real time with the add-on bus. this allows the pci bus to directly read or write to add-on resources. the S5935 allows the designer to declare up to four individual pass-thru regions. each region may be defined as 8, 16-, or 32-bits wide, mapped into host memory or i/o space and may be up to 512mb bytes in size. figure 4 right shows a block diagram of the S5935 pass-thru architecture. pass-thru operations are performed in pci target only mode, making this data channel useful for converting existing isa or eisa designs over to the fast pci architecture. the pass-thru data channel utilizes sepa- rate add-on bus signal pins to reflect a pci bus read or write request. add-on logic decodes these signals to determine if it must read or write data to the S5935 to satisfy the request. information decoded includes pci request occurring, the byte lanes involved, the specific pass-thru region accessed and if the request is a burst or single-cycle access. all requested pass-thru ad- dress and data information is passed via add-on op- eration registers. pass-thru operation supports single pci data cycles and pci data bursts. during pci burst operations, the S5935 is capable of transferring data at the full pci bandwidth. should slower add-on logic be implemented, the S5935 automatically issues pci bus waits or a host retry indication until the requested transfer is satisfied. fifo pci bus mastering operation fifo pci bus master data transfers are processed by one of two 8-dword fifos. the fifo block diagram is shown in figure 5. the particular fifo selected for a data transfer is dependent only on the direction of data flow and is completely transparent to the user. internal S5935 decode logic selects the fifo that is dedicated to transferring data to the other bus. the way data is transferred by a fifo, is determined by operation and configuration registers contained within the S5935. a fifo may be configured for either pci or add-on initiated bus mastering with programmable byte advance conditions, read vs. write priorities and add-on bus widths. advance conditions allow the fifo to implement 8-, 16- or 32-bit bus widths. configuring the S5935 for bus master operation enables separate address and data count registers, which are loaded with the pci memory address location and number of bytes to be read or written. this is accomplished by either the host cpu or add-on logic. data can be transferred between the two buses transparent to the pci host processor, however, the add-on logic is required to service the S5935 add-on local bus. an indication of transfer completion can be seen by polling a status register done bit or S5935 signal pin or enabling a transfer count = 0 interrupt to either bus. further fifo configuration bits select 16, 32, or 64 bit endian conversion options for incoming and outgoing data. endian conversion allows an add-on processor and the host to transfer data in their native endian format. other configuration bits determine if the add-on local bus width is 8, 16 or 32 bits. 16-bit bus configura- tions internally steer fifo data from the upper 16 bits of the dword and then to the lower 16-bits on alternate accesses. fifo pointers are then updated when appro- priate bytes are accessed. other methods are available for 8-bit or 16-bit add-ons. efficient fifo management configuration schemes unique to the amcc S5935 specify how full or empty a fifo must be before it requests the pci local bus. these criteria include bus requests when any of the 8 dwords are empty, or when four or more dwords are empty. this allows the designer to control how often the S5935 requests the bus. the S5935 always at- tempts to perform burst operations to empty or fill the fifos. further fifo capabilities over the standard register access methods allow for direct hardware fifo access. this is provided through separate access pins on the S5935. other status output pins allow for easily cascading external fifos to the add-on design. figure 4.
1-6 architectural overview S5935 pci local bus 32-bit master write address register S5935 add-on local bus b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 b0 b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 endian converter 32-bit master read address register 30-bit master read count register b0 b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 b0 b0 b0 b0 b1 b1 b1 b1 b2 b2 b2 b2 b3 b3 b3 b3 endian converter b0 28-bit master write count register figure 5.
1-7 architectural overview S5935 figure 8. s5933 pin assignment ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 c/be0# c/be1# c/be2# c/be3# req# gnt# frame# devsel# irdy# trdy# idsel stop# lock# par perr# serr# clk rst# inta# mode rsvd snv dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 add-on local bus 100 99 98 96 95 94 92 88 86 84 83 82 80 79 78 76 157 145 133 125 117 105 93 85 77 65 53 45 37 25 13 5 140 124 126 68 67 66 64 132 87 63 62 60 75 74 72 123 122 116 118 119 120 114 112 107 108 115 bpclk irq# sysrst# adr2 adr3 adr4 adr5 adr6 be0# be1# be#2 be3#/adr1 select# wr# rd# ptnum0 ptnum1 ptbe0# ptbe1# ptbe2# ptbe3# ptatn# ptburst# ptadr# ptwr ptrdy# wrfull wrfifo# rdempty rdfifo# ea0 ea1 ea2 ea3 ea4 ea5 ea6 ea7 ea8 ea9 ea10 ea11 ea12 ea13 fwe/ea14 frf/ea15 eq0 eq1 eq2 eq3 fwc#/eq4 frc#/eq5 amren/eq6 amwen/eq7 ewr#/sda erd#/scl 103 102 106 104 57 61 69 73 81 89 97 101 109 113 121 129 137 141 149 153 1 9 17 21 29 33 41 49 127 128 add-on local bus controls add-on local bus register controls pass-thru data controls nvram data bus 56 55 54 52 48 47 46 44 42 40 39 38 36 35 34 32 14 12 8 7 6 4 3 2 158 156 155 154 152 148 147 146 43 28 15 159 144 143 16 20 18 19 160 22 23 27 24 26 142 139 58 59 138 135 vss vss vss vss vss vss vss vss vdd vdd vdd vdd vdd vdd vdd vdd 10 30 50 70 90 110 130 150 11 31 51 71 91 111 131 151 fifo data controls byte wide nvram data pci local bus device controls power & ground S5935 matchmaker
1-8 architectural overview S5935 [this page intentionally left blank.]
2-9 signal descriptions S5935 signal type definition the following signal type definitions [in, out, t/s, s/t/s and o/d] are taken from revision 2.1 of the pci local bus specification. in input is a standard input-only signal. out totem pole output is a standard active driver. t/s tri-state ? is a bidirectional, tristate input/output pin. s/t/s sustained tri-state is an active low tristate signal owned and driven by one and only one agent at a time. the agent that drives an s/t/s pin low must drive it high for at least one clock before letting it float. a new agent cannot start driving a s/t/s signal any sooner than one clock after the previous owner tri-states it. a pullup is required to sustain the inactive state until another agent drives it, and must be provided by the central source. o/d open drain allows multiple devices to share as a wire-or. note that a # symbol at the end of a signal name denotes that the active state occurs when the signal is at a low voltage. when no # symbol is present, the signal is active high. figure 1. S5935 signal pins ? pclk inta# rst# ad[31:0] c/be[3:0]# req# gnt# frame# devsel# irdy# trdy# idsel stop# lock# par# perr# serr# mode rsvd snv bpclk irq# sysrst dq[31:0] select# adr[6:2] be[3:0]# rd# wr# ptatn# ptburst# ptnum[1:0] ptbe[3:0]# ptadr# ptwr ptrdy# rdfifo# wrfifo# rdempty wrfull ea[15:0] eq[7:0] ewr#/sda erd#/scl add-on bus control s5933 register access pass-thru control/ access serial config/bios opt. direct fifo access byte wide config/bios opt. pci 2.1 local bus S5935 control S5935 add-on data bus
2-10 signal descriptions S5935 pci bus interface signals signal type description address and data pins pci local bus ad[31:00] t/s local bus address/data lines. address and data are multiplexed on the same pins. each bus operation consists of an address phase followed by one or more data phases. address phases are identified when the control signal, frame#, is asserted. data transfers occur during those clock cycles in which control signals irdy# and trdy# are both asserted. c/be[3:0]# t/s bus command and byte enables. these are multiplexed on the same pins. during the address phase of a bus operation, these pins identify the bus command, as shown in the table below. during the data phase of a bus operation, these pins are used as byte enables, with c/be[0]# enabling byte 0 (least significant byte) and c/ be[3]# enabling byte 3 (most significant byte). c/be[3:0]# description (during address phase) 0000 interrupt acknowledge 0001 special cycle 0010 i/o read 0011 i/o write 0100 reserved 0101 reserved 0110 memory read 0111 memory write 1000 reserved 1001 reserved 1010 configuration read 1011 configuration write 1100 memory read - multiple 1101 dual address cycle 1110 memory read line 1111 memory write and invalidate par t/s parity. this signal is even parity across the entire ad[31:00] field along with the c/ be[3:0]# field. the parity is stable in the clock following the address phase and is sourced by the master. during the data phase for write operations, the bus master sources this signal on the clock following irdy# active; during the data phase for read operations, this signal is sourced by the target and is valid on the clock following trdy# active. the par signal therefore has the same timing as ad[31:00}, delayed by one clock.
2-11 signal descriptions S5935 signal type description system pins pci local bus signal type description interface control pins pci bus signal clk in clock. the rising edge of this signal is the reference upon which all other signals are based, with the exception of rst# and the interrupt (irqa#-). the maximum fre- quency for this signal is 33 mhz and the minimum is dc (0 hz). rst# in reset. this signal is used to bring all other signals within this device to a known, consistent state. all pci bus interface output signals are not driven (tri-stated), and open drain signals such as serr# are floated. frame# s/t/s frame. this signal is driven by the current bus master and identifies both the begin- ning and duration of a bus operation. when frame# is first asserted, it indicates that a bus transaction is beginning and that valid addresses and a corresponding bus command are present on the ad[31:00] and c/be[3:0] lines. frame# remains as- serted during the data transfer portion of a bus operation and is deasserted to signify the final data phase. irdy# s/t/s initiator ready. this signal is sourced by the bus master and indicates that the bus master is able to complete the current data phase of a bus transaction. for write operations, it indicates that valid data is on the ad[31:00] pins. wait states occur until both trdy# and irdy# are asserted together. trdy# s/t/s target ready. this signal is sourced by the selected target and indicates that the target is able to complete the current data phase of a bus transaction. for read operations, it indicates that the target is providing valid data on the ad[31:00] pins. wait states occur until both trdy# and irdy# are asserted together. stop# s/t/s stop. the stop signal is sourced by the selected target and conveys a request to the bus master to stop the current transaction. lock# in lock. the lock signal provides for the exclusive use of a resource. the S5935 may be locked as a target by one master at a time. the S5935 cannot lock a target when it is a master. idsel in initialization device select. this pin is used as a chip select during configuration read or write operations. devsel# s/t/s device select. this signal is sourced by an active target upon decoding that its address and bus commands are valid. for bus masters, it indicates whether any device has decoded the current bus cycle.
2-12 signal descriptions S5935 arbitration pins (bus masters only) pci local bus signal type description error reporting pins pci local bus signal type description interrupt pin pci local bus signal type description req# out request. this signal is sourced by an agent wishing to become the bus master. it is a point-to-point signal and each master has its own req#. gnt# in grant. the gnt# signal is a dedicated, point-to-point signal provided to each poten- tial bus master and signifies that access to the bus has been granted. perr# s/t/s parity error. this pin is used for reporting parity errors during the data portion of a bus transaction for all cycles except a special cycle. it is sourced by the agent receiving data and driven active two clocks following the detection of the error. this signal is driven inactive (high) for one clock cycle prior to returning to the tri-state condition. serr# o/d system error. this pin is used for reporting address parity errors, data parity errors on special cycle commands, or any error condition having a catastrophic system impact. inta# o/d interrupt a. this pin is a level sensitive, low active interrupt to the host. the inta# interrupt must be used for any single function device requiring an interrupt capability.
2-13 signal descriptions S5935 non-volatile memory interface signals this signal grouping provides for connection to external non-volatile memories. either a serial or byte-wide device may be used. the serial interface shares the read and write control pins used for interfacing with byte-wide memory devices. since it is intended that only one (serial or byte wide) configuration be used in any given implementation, separate descriptions are provided for each. the S5935 provides the pins necessary to interface to a byte wide non-volatile memory. when they are connected to a properly configured serial memory, these byte wide interface pins assume alternate functions. these alternate functions include added external fifo status flags, fifo reset control, add-on control for bus mastering and a hardware interface mailbox port. byte-wide nv devices signal type description scl t/s serial clock. this output is intended to drive a two-wire serial interface and functions as the buss master. it is intended that this signal be directly connected to one or more inexpensive serial non-volatile rams or eeproms. this pin is shared with the byte wide interface signal, erd#. sda t/s serial data/address. this bidirectional pin is used to transfer addresses and data to or from a serial nvram or eeprom. it is an open drain output and intended to be wire-ored with all other devices on the serial bus using a 4.7k external pull-up resistor. this pin is shared with the byte wide interface signal, ewr#. snv in serial non-volatile device. this input, when high, indicates a serial boot device or no boot device is present. when this pin is low, a byte-wide boot device is present. serial nv devices signal type description ea[15:00] t/s external nv memory address. these signals connect directly to the external bios (or eeprom) or eprom address pins ea0 through ea15. the pci interface controller assembles 32-bit-wide accesses through multiple read cycles of the 8-bit device. the address space from 0040h through 007fh is used to preload and initialize the pci configuration registers. should an external nv memory be used, the minimum size required is 128 bytes and the maximum is 64k bytes. when a serial memory is connected to the S5935, the pins ea[7:0] are reconfigured to become a hardware add- on to pci mailbox register with the ea8 pin as the mailbox load clock. also, the ea15 signal pin will provide an indication that the pci to add-on fifo is full (frf#), and the ea14 signal pin will indicate whether the add-on to pci fifo is empty (fwe#). erd# out external nv memory read control. this pin is asserted during read operations involv- ing the external non-volatile memory. data is transferred into the S5935 during the low to high transition of erd#. this pin is shared with the serial external memory interface signal, scl. ewr# t/s external nv memory write control. this pin is asserted during write operations involv- ing the external non-volatile memory. data is presented on pins eq[7:0] along with its address on pins ea[15:0] throughout the entire assertion of ewr#. this pin is shared with the serial external memory interface signal, sda. eq[7:0] t/s external memory data bus. these pins are used to directly connect with the data pins of an external non-volatile memory. when a serial memory is connected to the S5935, the pins eq4, eq5, eq6 and eq7 become reconfigured to provide signal pins for bus mastering control from the add-on interface. note: scl and sda are not controlled by flt#.
2-14 signal descriptions S5935 add-on bus interface signals the following sets of signals represent the interface pins available for the add-on function. there are four groups: register access, fifo access, pass-thru mode pins, and general system pins. register access pins dq[31:00] t/s datapath dq0Cdq31. these pins represent the datapath for the add-on peripherals data bus. they provide the interface to the controllers fifo and other registers. when mode=v cc , only dq[15:00] are used. dq[31:0] have internal pull-up resistors. adr[6:2] in add-on addresses. these signals are the address lines to select which of the 16 dword registers within the controller is desired for a given read or write cycle, as shown in the table below. adr[6:2] register name 00000 add-on incoming mailbox reg. 1 00001 add-on incoming mailbox reg. 2 00010 add-on incoming mailbox reg. 3 00011 add-on incoming mailbox reg. 4 00100 add-on outgoing mailbox reg. 1 00101 add-on outgoing mailbox reg. 2 00110 add-on outgoing mailbox reg. 3 00111 add-on outgoing mailbox reg. 4 01000 add-on fifo port 01001 bus master write address register 01010 add-on pass-thru address 01011 add-on pass-thru data 01100 bus master read address register 01101 add-on mailbox empty/full status 01110 add-on interrupt control 01111 add-on general control/status register 10110 bus master write transfer count 10111 bus master read transfer count be3# or adr1 in byte enable 3 (32-bit mode) or adr1 (16 bit mode). this pin is used in conjunction with the read or write strobes (rd# or wr#) and the add-on select signal, select#. as a byte enable, it is necessary to have this pin asserted to perform write operations to the register identified by adr[6:2] bit locations d24 through d31; for read operations it controls the dq[31:24] output drive. be[2:0]# in byte enable 2 through 0. these pins provide for individual byte control during register read or write operations. be2# controls activity over dq[23:dq16], be1# controls dq[15:8], and be0# controls dq[7:0]. during read operations they control the output drive for each of their respective byte lanes; for write operations they serve as a required enable to perform the modification of each byte lane. select# in select for the add-on interface. this signal must be driven low for any write or read access to the add-on interface registers. this signal must be stable during the assertion of command signals wr# or rd#. wr# in write strobe. this pin, when asserted in conjunction with the select# pin, causes the writing of one of the internal registers. the specific register and operand size are identified through address pins adr[6:2] and the byte enables, be[3:0]#. rd# in read strobe. this pin, when asserted in conjunction with the select# pin, causes the reading of one of the internal registers. the specific register and operand size are identified through address pins adr[6:2] and the byte enables be[3:0]#. mode in this pin control whether the S5935 data accesses on the dq bus are to be 32-bits wide (mode = low) or 16-bits wide (mode = high). when in the 16 bit mode, the signal be3# is reassigned as the address signal adr1. signal type description
2-15 signal descriptions S5935 fifo access pins signal type description wrfifo# in write fifo. this signal provides a method to directly write the fifo without having to generate the select# signal or the adr[6:2] value of [01000b] to access the fifo. access width is either 32 bits or 16 bits depending on the data bus size available. this signal is intended for implementing pci dma transfers with the add-on system. rdfifo# in read fifo. this signal provides a method to directly read the fifo without having to generate the select# signal or the adr[6:2] value of [01000b] to access the fifo. access width is either 32 bits or 16 bits, depending on the data bus size defined by the mode pin. this signal is intended for implementing pci dma transfers with the add-on system. wrfull out write fifo full. this pin indicates whether the add-on-to-pci bus fifo is able to accept more data. this pin is intended to be used to implement dma hardware on the add-on system bus. a logic low output from this pin can be used to represent a dma write (add-on to-pci fifo) request. rdempty out read fifo empty. this pin indicates whether the read fifo (pci-to-add-on fifo) contains data. this pin is intended to be used by the add-on system to control dma transfers from the pci bus to the add-on system bus. a logic low from this pin can be used to represent a dma (pci-to-add-on fifo) request. pass-thru interface pins signal type description ptatn# out pass-thru attention. this signal identifies that an active pci bus cycle has been decoded and data must be read from or written to the pass-thru data register. ptburst# out pass-thru burst. this signal identifies pci bus operations involving the current pass- thru cycle as requesting burst access. ptrdy# in pass-thru ready. this input indicates when add-on logic has completed a pass- thru cycle and another may be initiated. ptnum[1:0] out pass-thru number. these signals identify which of the four base address registers decoded a pass-thru bus activity. these bits are only meaningful when signal ptatn# is active. a value of 00 corresponds to base address register 1, a value of 01 for base address register 2, and so on. ptbe[3:0]# out pass-thru byte enables. these signals indicate which bytes are requested for a given pass-thru operation. they are valid during the presence of signal ptatn# active. ptadr# in pass-thru address. this signal causes the actual pass-thru requested address to be presented as outputs on the dq pins dq[31:0] for add-ons with 32-bit buses, or the low-order 16 bits for add-ons with 16-bit buses. it is necessary that all other bus control signals be in their inactive state during the assertion of ptadr#. the purpose of this signal is to provide the direct addressing of external add-on peripherals through use of the ptnum[1:0] and the low-order address bits presented on the dq bus with this pin active. ptwr out pass-thru write. this signal identifies whether a pass-thru operation is a read or write cycle. this signal is valid only when ptatn# is active.
2-16 signal descriptions S5935 system pins signal type description sysrst# out system reset. this low active output is a buffered form of the pci bus reset, rst#. it is not synchronized to any clock within the pci interface controller. additionally, this signal can be invoked through software from the pci host interface. bpclk out buffered pci clock. this output is a buffered form of the pci bus clock and, as such, has all of the behavioral characteristics of the pci clock (i.e., dc-to-33 mhz capability). irq# out interrupt. this pin is used to signal the add-on system that a significant event has occurred as a result of activity within the pci controller. rsvd in reserved. this pin must be left open at all times.
3-17 pci configuration registers S5935 table 1. configuration registers configuration abbreviation register name address offset 00hC01h vid vendor identification 02hC03h did device identification 04hC05h pcicmd pci command register 06hC07h pcists pci status register 08h rid revision identification register 09hC0bh clcd class code register 0ch caln cache line size register 0dh lat master latency timer 0eh hdr header type 0fh bist built-in self-test 10hC27h badr0-badr5 base address registers (0-5) 28hC2fh reserved 30h exrom expansion rom base address 34hC3bh reserved 3ch intln interrupt line 3dh intpin interrupt pin 3eh mingnt minimum grant 3fh maxlat maximum latency 40hCffh not used pci configuration registers each pci bus device contains a unique 256-byte region called its configuration header space. portions of this configuration header are mandatory in order for a pci agent to be in full compliance with the pci specification. this section describes each of the configuration space fieldsits address, default values, initialization options, and bit definitionsand also provides an explanation of its intended usage. ?
3-18 S5935 pci configuration registers pci configuration space header 00 04 08 0c 10 14 18 1c 20 24 28 2c 30 34 38 3c 31 23 24 16 15 8 7 latency timer interrupt pin min_gnt max_lat interrupt line expansion rom base address header type = 0 base address register #0 base address register #1 base address register #2 base address register #3 base address register #4 base address register #5 reserved = 0's reserved = 0's reserved = 0's reserved = 0's bist rev id cache line size vendor id command device id class code status 00 legend note: some registers are a combination of the above. see individual sections for full description. eprom is data source (read only) control function eprom initialized ram (can be altered from pci port) eprom initialized ram (can be altered from add-on port) hard-wired to zeroes
3-19 pci configuration registers S5935 vendor identification register (vid) register name: vendor identification address offset: 00h-01h power-up value: 10e8h (amcc, applied micro circuits corp.) boot-load: external nvram offset 040h-41h attribute: read only (ro) size: 16 bits the vid register contains the vendor identification number. this number is assigned by the pci special interest group and is intended to uniquely identify any pci device. write operations from the pci inter- face have no effect on this register. after reset is removed, this field can be boot-loaded from the ex- ternal non-volatile device (if present and valid) so that other legitimate pci sig members can substitute their vendor identification number for this field. figure 1. vendor identification register table 2. vendor identification register bit description 15 0 10e8h vendor identification register (ro) 15:0 vendor identification number: this is a 16 bit-value assigned to amcc.
3-20 S5935 pci configuration registers device identification register (did) register name: device identification address offset: 02h-03h power-up value: 4750h (ascii hex for gp, general purpose) boot-load: external nvram offset 042h-43h attribute: read only size: 16 bits the did register contains the vendor-assigned de- vice identification number. this number is generated by amcc in compliance with the conditions of the pci specification. write operations from the pci in- terface have no effect on this register. after reset is removed, this field can be boot-loaded from the ex- ternal non-volatile device (if present and valid) so that other legitimate pci sig members can substitute their own device identification number for this field. 15 0 device identification register (ro) 4750h figure 2. device identification register bit description table 3. device identification register 15:0 device identification number: this is a 16-bit value initially assigned by amcc for applications using the amcc vendor id.
3-21 pci configuration registers S5935 pci controller pci command register (pcicmd) register name: pci command address offset: 04h-05h power-up value: 0000h boot-load: not used attribute: read/write (r/w on 6 bits, read only for all others) size: 16 bits figure 3. pci command register this 16-bit register contains the pci command. the function of this register is defined by the pci specifi- cation and its implementation is required of all pci devices. only six of the ten fields are used by this device; those which are not used are hardwired to 0. the definitions for all fields are provided here for completeness. 15 0 reserved = 00's fast back-to-back serre wait cycle enable parity error enable palette snoop enable memory write and invalidate enable special cycle enable bus master enable memory access enable i/o access enable x0 0x000 x x x 1 2 3 4 5 6 7 8 9
3-22 S5935 pci configuration registers table 4. pci command register 15:10 reserved. equals all 0s. 9 fast back-to-back enable. the S5935 does not support this function. this bit must be set to zero. this bit is cleared to a 0 upon reset#. 8 system error enable. when this bit is set to 1, it permits the S5935 controller to drive the open drain output pin, serr#. this bit is cleared to 0 upon reset#. the serr# pin driven active normally signifies a parity error on the address/control bus. 7 wait cycle enable. this bit controls whether this device does address/data stepping. since the S5935 controller never uses stepping, it is hardwired to 0. 6 parity error enable. this bit, when set to a one, allows this controller to check for parity errors. when a parity error is detected, the pci bus signal perr# is asserted. this bit is cleared (parity testing disabled) upon the assertion of reset#. 5 palette snoop enable. this bit is not supported by the S5935 controller and is hardwired to 0. this feature is used solely for pci-based vga devices. 4 memory write and invalidate enable. this bit allows certain bus master devices to use the memory write and invalidate pci bus command when set to 1. when set to 0, masters must use the memory write command instead. the S5935 controller does not support this command when operated as a master and therefore it is hardwired to 0. 3 special cycle enable. devices which are capable of monitoring special cycles can do so when this bit is set to 1. the S5935 controller does not monitor (or generate) special cycles and this bit is hardwired to 0. 2 bus master enable. this bit, when set to a one, allows the S5935 controller to function as a bus master. this bit is initialized to 0 upon the assertion of signal pin reset#. 1 memory space enable. this bit allows the S5935 controller to decode and respond as a target for memory regions that may be defined in one of the five base address registers. this bit is initialized to 0 upon the assertion of signal pin reset#. 0 i/o space enable. this bit allows the S5935 controller to decode and respond as a target to i/o cycles which are to regions defined by any one of the five base address registers. this bit is initialized to 0 upon the assertion of signal pin reset#. bit description
3-23 pci configuration registers S5935 pci status register (pcists) register name: pci status address offset: 06h-07h power-up value: 0080h boot-load: not used attribute: read only (ro), read/write clear (r/wc) size: 16 bits figure 4. pci status register 70 x 0 0 x x x 6 x x reserved (ro) signaled target abort (r/wc) received target abort (r/wc) received master abort (r/wc) signaled system error (r/wc) detected parity error (r/wc) 0 15 14 13 12 11 10 9 8 reserved (ro) = 00's fast back-to-back (ro) data parity reported (r/wc) devsel# timing status (ro) 0 0 = fast (s5933) 0 1 = medium 1 0 = slow 1 1 = reserved this 16-bit register contains the pci status informa- tion. the function of this register is defined by the pci specification and its implementation is required of all pci devices. only some of the bits are used by this device; those which are not used are hardwired to 0. most status bits within this register are desig- nated as write clear, meaning that in order to clear a given bit, the bit must be written as a 1. all bits written with a 0 are left unchanged. these bits are identified in figure 4 as (r/wc). those which are read only are shown as (ro) in figure 4.
3-24 S5935 pci configuration registers bit description table 5. pci status register 15 detected parity error. this bit is set whenever a parity error is detected. it functions independently from the state of command register bit 6. this bit may be cleared by writing a 1 to this location. 14 signaled system error. this bit is set whenever the device asserts the signal serr#. this bit can be reset by writing a 1 to this location. 13 received master abort. this bit is set whenever a bus master abort occurs. this bit can be reset by writing a 1 to this location. 12 received target abort. this bit is set whenever this device has one of its own initiated cycles terminated by the currently addressed target. this bit can be reset by writing a 1 to this location. 11 signaled target abort. this bit is set whenever this device aborts a cycle when addressed as a target. this bit can be reset by writing a 1 to this location. 10:9 device select timing. these bits are read-only and define the signal behavior of devsel# from this device when accessed as a target. 8 data parity reported. this bit is set upon the detection of a data parity error for a transfer involving the S5935 device as the master. the parity error enable bit (d6 of the command register) must be set in order for this bit to be set. once set, it can only be cleared by either writing a 1 to this location or by the assertion of the signal reset#. 7 fast back-to-back capable. when equal to 1, this indicates that the device can accept fast back-to- back cycles as a target. 6:0 reserved. equal all 0s.
3-25 pci configuration registers S5935 revision identification register (rid) register name: revision identification address offset: 08h power-up value: 00h boot-load: external nvram/eprom offset 048h attribute: read only size: 8 bits the rid register contains the revision identification number. this field is initially cleared. write operations from the pci interface have no effect on this register. after reset is removed, this field can be boot-loaded from the external non-volatile device (if present and valid) so that another value may be used. bit description 7:0 revision identification number. initialized to zeros, this register may be loaded to the value in non- volatile memory at offset 048h. table 6. revision identification register figure 5. revision identification register 7 0 00h revision identification number (ro)
3-26 S5935 pci configuration registers class code register (clcd) register name: class code address offset: 09h-0bh power-up value: ff0000h boot-load: external nvram offset 049h-4bh attribute: read only size: 24 bits this 24-bit, read-only register is divided into three one-byte fields: the base class resides at location 0bh, the sub-class at 0ah, and the programming in- terface at 09h. the default setting for the base class is all ones (ffh), which indicates that the device does not fit into the thirteen base classes defined in the pci local bus specification. it is possible, how- ever, through use of the external non-volatile memory, to implement one of the defined class codes described in table 7 below. for devices that fall within the seven defined class codes, sub-classes are also assigned. tables 8 through 20 describe each of the sub-class codes for base codes 00h through 0ch, respectively. 7 0 sub-class 7 0 7 0 base class prog i/f (bit) (offset) @09h @0ah @0bh figure 6. class code register base-class description 00h early, pre-2.0 pci specification devices 01h mass storage controller 02h network controller 03h display controller 04h multimedia device 05h memory controller 06h bridge device 07h simple communication controller 08h base system peripherals 09h input devices 0ah docking stations 0bh processors 0ch serial bus controllers 0d-feh reserved ffh device does not fit defined class codes (default) table 7. defined base class codes sub-class prog i/f description 00h 00h all devices other than vga 01h 00h vga-compatible device table 8. base class code 00h: early, pre-2.0 specification devices
3-27 pci configuration registers S5935 sub-class prog i/f description 00h 00h ram memory controller 01h 00h flash memory controller 80h 00h other memory controller sub-class prog i/f description 00h 00h scsi controller 01h xxh ide controller 02h 00h floppy disk controller 03h 00h ipi controller 04h 00h raid controller 80h 00h other mass storage controller sub-class prog i/f description 00h 00h ethernet controller 01h 00h token ring controller 02h 00h fddi controller 03h 00h atm controller 80h 00h other network controller table 10. base class code 02h: network controllers sub-class prog i/f description 00h 00h vga-compatible controller 00h 01h 8514 compatible controller 01h 00h xga controller 80h 00h other display controller table 11. base class code 03h: display controllers table 13. base class code 05h: memory controllers sub-class prog i/f description 00h 00h video device 01h 00h audio device 80h 00h other multimedia device table 12. base class code 04h: multimedia devices table 9. base class code 01h: mass storage controllers
3-28 S5935 pci configuration registers sub-class prog i/f description 00h 00h host/pci bridge 01h 00h pci/isa bridge 02h 00h pci/eisa bridge 03h 00h pci/micro channel bridge 04h 00h pci/pci bridge 05h 00h pci/pcmcia bridge 06h 00h nubus bridge 07h 00h cardbus bridge 80h 00h other bridge type table 14. base class code 06h: bridge devices sub-class prog i/f description 00h 00h generic xt compatible serial controller 01h 16450 compatible serial controller 02h 16550 compatible serial controller 01h 00h parallel port 01h bidirectional parallel port 02h ecp 1.x compliant parallel port 80h 00h other communications device table 15. base class code 07h: simple communications controllers sub-class prog i/f description 00h 00h generic 8259 pic 01h isa pic 02h eisa pic 01h 00h generic 8237 dma controller 01h isa dma controller 02h eisa dma controller 02h 00h generic 8254 system timer 01h isa system timer 02h eisa system timers (2 timers) 03h 00h generic rtc controller 01h isa rtc controller 80h 00h other system peripheral table 16. base class code 08h: base system peripherals
3-29 pci configuration registers S5935 sub-class prog i/f description 00h 00h keyboard controller 01h 00h digitizer (pen) 02h 00h mouse controller 80h 00h other input controller table 17. base class code 09h: input devices sub-class prog i/f description 00h 00h generic docking station 80h 00h other type of docking station table 18. base class code 0ah: docking stations sub-class prog i/f description 00h 00h intel386? 01h 00h intel486? 02h 00h pentium? 10h 00h alpha? 40h 00h co-processor table 19. base class code 0bh: processors sub-class prog i/f description 00 00h firewire? (ieee 1394) 01h 00h access.bus 02h 00h ssa table 20. base class code 0ch: serial bus controllers
3-30 S5935 pci configuration registers cache line size register (caln) register name: cache line size address offset: 0ch power-up value: 00h, hardwired boot-load: not used attribute: read only size: 8 bits this register is hardwired to 0. the cache line con- figuration register is used by the system to define the cache line size in doubleword (64-bit) increments. this controller does not use the memory write and invalidate pci bus cycle commands when operating in the bus master mode, and therefore does not inter- nally require this register. when operating in the tar- get mode, this controller does not have the connections necessary to snoop the pci bus and accordingly cannot employ this register in the detec- tion of burst transfers that cross a line boundary. figure 7. cache line size register 7 0 00h cache line size (ro)
3-31 pci configuration registers S5935 latency timer register (lat) register name: latency timer address offset: 0dh power-up value: 00h boot-load: external nvram offset 04dh attribute: read/write, bits 7:3; read only bits 2:0 size: 8 bits the latency timer register has meaning only when this controller is used as a bus master and pertains to the number of pci bus clocks that this master will be guaranteed. the nonzero value for this register is internally decremented after this device has been granted the bus and has begun to assert frame#. prior to this latency timer count reaching zero, this device can ignore the removal of the bus grant and may continue the use of the bus for data transfers. 7 0 latency timer value (r/w) # of clocks x 8 0 1 0 2 0 3 x 4 x 5 x 6 x x bit value figure 8. latency timer register
3-32 S5935 pci configuration registers header type register (hdr) register name: header type address offset: 0eh power-up value: 00h boot-load: external nvram offset 04eh attribute: read only size: 8 bits this register consists of two fields: bits 6:0 define the format for bytes 10h through 3fh of the device con- figuration header, and bit 7 establishes whether this device represents a single function (bit 7 = 0) or a multifunction (bit 7 = 1) pci bus agent. the S5935 is a single function pci device. figure 9. header type register 7 0 single/multi-function device (read only) 0 = single function 1 = multi-function 1 2 3 4 5 6 x bit value 00h format field (read only)
3-33 pci configuration registers S5935 built-in self-test register (bist) register name: built-in self-test address offset: 0fh power-up value: 00h boot-load: external nvram/eprom offset 04fh attribute: d7, d5-0 read only, d6 as pci bus write only size: 8 bits the built-in self-test (bist) register permits the implementation of custom, user-specific diagnostics. this register has four fields as depicted in figure 10. bit 7, when set signifies that this device supports a built-in self test. when bit 7 is set, writing a 1 to bit 6 will commence the self test. in actuality, writing a 1 to bit 6 produces an interrupt to the add-on interface. bit 6 will remain set until cleared by a write operation to this register from the add-on bus interface. when bit 6 is reset it is interpreted as completion of the self- test and an error is indicated by a non-zero value for the completion code (bits 3:0). figure 10. built-in self test register table 21. built-in self-test register bit description 7 bist capable. this bit indicates that the add-on device supports a built-in self-test when a one is returned. a zero should be returned if this self test feature is not desired. this field is read only from the pci interface. 6 start bist. writing a 1 to this bit indicates that the self-test should commence. this bit can only be written when bit 7 is a 1. when bit 6 becomes set, an interrupt is issued to the add-on interface. other than through the reset pin, bit 6 can only be cleared by a write to this element from the add-on bus interface as outlined in section 6.5. the pci bus specification requires that this bit be cleared within 2 seconds after being set, or the device will be failed. 5:4 reserved. these bits are reserved. this field will always return zeros. 3:0 completion code. this field provides a method for detailing a device-specific error. it is considered valid when the start bist field (bit 6) changes from 1 to 0. an all-zero value for the completion code indicates successful completion. 7 0 x 1 x 2 x 3 x 4 0 5 0 6 0 x bit value user defined completion code (ro) reserved (ro) start bist (wo) bist capable (ro)
3-34 S5935 pci configuration registers base address registers (badr) register name: base address address offset: 10h, 14h, 18h, 1ch, 20h, 24h power-up value: ffffffc1h for offset 10h; 00000000h for all others boot-load: external nvram offset 050h, 54h, 58h, 5ch, 60h (badr0-4) attribute: high bits read/write; low bits read only size: 32 bits the base address registers provide a mechanism for assigning memory or i/o space for the add-on func- tion. the actual location(s) the add-on function is to respond to is determined by first interrogating these registers to ascertain the size or space desired, and then writing the high-order field of each register to place it physically in the systems address space. bit zero of each field is used to select whether the space required is to be decoded as memory (bit 0 = 0) or i/o (bit 0 = 1). since this pci controller has 16 dwords of internal operating registers, the base address register at offset 10h is assigned to them. the re- maining five base address registers can only be used by boot-loading them from the external nvram inter- face. badr5 register is not implemented and will re- turn all 0s. determining base address size the address space defined by a given base address register is determined by writing all 1s to a given base address register from the pci bus and then reading that register back. the number of 0s returned starting from d4 for memory space and d2 for i/o space toward the high-order bits reveals the amount of address space desired. tables 23 and 24 list the possible returned values and their corresponding size for both memory and i/o, respectively. included in the table are the nvram/eprom boot values which correspond to a given assigned size. a register re- turning all zeros is disabled. assigning the base address after a base address has been sized as described in the preceding paragraph, the region associated with that base address register (the high order one bits) can physically locate it in memory (or i/o) space. for example, the first base address register returns ffffffc1h indicating an i/o space (d0=1) and is then written with the value 00000300h. this means that the controllers internal registers can be selected for i/o addresses between 00000300h through 0000033fh, in this example. the base address value must be on a natural binary boundary for the required size (example 300h, 340h, 380h etc.; 338h would not be allowable). figure 11b. base address register i/o figure 11a. base address register memory 31 0 x 1 0 2 bit value i/o space indicator (ro) reserved (ro) programmable (r/w) 31 30 29 0 x 1 x 2 x 3 x 4 see page 3-157 bit value memory space indicator (ro) 0 = memory 1 = i/o type (ro) 00-locate anywhere (32) 01-below 1 mb 10-locate anywhere (64) 11-reserved programmable (r/w) prefetchable (ro) }
3-35 pci configuration registers S5935 table 22a. base address register memory (bit 0 = 0) 31:4 base address location. these bits are used to position the decoded region in memory space. only bits which return a 1 after being written as 1 are usable for this purpose. except for base address register 0, these bits are individually enabled by the contents sourced from the external boot memory. 3 prefetchable. when set as a 1, this bit signifies that this region of memory can be cached. cachable regions can only be located within the region altered through pci bus memory writes. this bit, when set, also implies that all read operations will return the data associated for all bytes regardless of the byte enables. memory space which cannot support this behavior should leave this bit in the zero state. for base addresses 1 through 4, this bit is set by the reset pin and later initialized by the external boot memory (if present). base address register 0 always has this bit set to 0. this bit is read only from the pci interface. 2:1 memory type. these two bits identify whether the memory space is 32 or 64 bits wide and if the space location is restricted to be within the first megabyte of memory space. the table below describes the encoding: bits description 2 1 0 0 region is 32 bits wide and can be located anywhere in 32 bit memory space. 0 1 region is 32 bits wide and must be mapped below the first mbyte of memory space. 1 0 region is 64 bits wide and can be mapped anywhere within 64 bit memory space. (not supported by this controller.) 1 1 reserved. (not supported by this controller.) 1 the 64-bit memory space is not supported by this controller, so bit 2 should not be set. the only meaningful option is whether it is desired to position memory space anywhere within 32-bit memory space or restrain it to the first megabyte. for base addresses 1 through 5, this bit is set by the reset pin and later initialized by the external boot memory (if present). 0 space indicator = 0. when set to 0, this bit identifies a base address region as a memory space and the remaining bits in the base address register are defined as shown in table 22a. bit description table 22b. base address register i/o (bit 0 = 1) bit description 31:2 base address location. these bits are used to position the decoded region in i/o space. only bits which return a 1 after being written as 1 are usable for this purpose. except for base address 0, these bits are individually enabled by the contents sourced from the external boot memory (eprom or nvram). 1 reserved. this bit should be zero. (note: disabled base address registers will return all zeros for the entire register location, bits 31 through 0). 0 space indicator = 1. when one this bit identifies a base address region as an i/o space and the remaining bits in the base address register have the definition as shown in table 11b.
3-36 S5935 pci configuration registers response size in bytes [eprom boot value] 1 00000000h none - disabled 00000000h or bios missing 2,3 fffffff0h 16 bytes (4 dwords) fffffff0h ffffffe0h 32 bytes (8 dwords) ffffffe0h ffffffc0h 64 bytes (16 dwords) ffffffc0h ffffff80h 128 bytes (32 dwords) ffffff80h ffffff00h 256 bytes (64 dwords) ffffff00h fffffe00h 512 bytes (128 dwords) fffffe00h fffffc00h 1k bytes (256 dwords) fffffc00h fffff800h 2k bytes (512 dwords) fffff800h fffff000h 4k bytes (1k dwords) fffff000h ffffe000h 8k bytes (2k dwords) ffffe000h ffffc000h 16k bytes (4k dwords) ffffc000h ffff8000h 32k bytes (8k dwords) ffff8000h ffff0000h 64k bytes (16k dwords) ffff0000h fffe0000h 128k bytes (32k dwords) fffe0000h fffc0000h 256k bytes (64k dwords) fffc0000h fff80000h 512k bytes (128k dwords) fff80000h fff00000h 1m bytes (256k dwords) fff00000h ffe00000h 2m bytes (512k dwords) ffe00000h ffc00000h 4m bytes (1m dwords) ffc00000h ff800000h 8m bytes (2m dwords) ff800000h ff000000h 16m bytes (4m dwords) ff000000h fe000000h 32m bytes (8m dwords) fe000000h fc000000h 64m bytes (16m dwords) fc000000h f8000000h 128m bytes (32m dwords) f8000000h f0000000h 256m bytes (64m dwords) f0000000h e0000000h 512m bytes (128m dwords) e0000000h table 23. read response (memory assigned) to an all-ones write operation to a base address register 1. the two most significant bits define bus width for badr1:4 in pass-thru operation). 2. bits d3, d2 and d1 may be set to indicate other attributes for the memory space. see text for details. 3. badr5 register is not implemented and will return all 0s.
3-37 pci configuration registers S5935 response size in bytes [eprom boot value] 00000000h none - disabled 00000000h or bios missing 3 fffffffdh 4 bytes (1 dwords) fffffffdh fffffff9h 8 bytes (2 dwords) fffffff9h fffffff1h 16 bytes (4 dwords) fffffff1h ffffffe1h 32 bytes (8 dwords) ffffffe1h ffffffc1h 64 bytes (16 dwords) ffffffc1h 4 ffffff81h 128 bytes (32 dwords) ffffff81h ffffff01h 256 bytes (64 dwords) ffffff01h table 24. read response (i/o assigned) to an all-ones write operation to a base address register 4. base address register 0 (at offset) 10h powers up as ffffffc1h. this default assignment allows usage without an external boot memory. should an eprom or nvram be used, the base address can be boot loaded to become a memory space (ffffffc0h or ffffffc2h).
3-38 S5935 pci configuration registers expansion rom base address register (xrom) register name: expansion rom base address address offset: 30h power-up value: 00000000h boot-load: external nvram offset 70h attribute: bits 31:11, bit 0 read/write; bits 10:1 read only size: 32 bits 31 0 0 0 1 10 bit value address decode enable (rw) 0=disabled 1=enabled reserved (ro) programmable (r/w) 11 figure 12. expansion rom base address register the expansion base address rom register provides a mechanism for assigning a space within physical memory for an expansion rom. access from the pci bus to the memory space defined by this register will cause one or more accesses to the S5935 control- lers external bios rom (or nvram) interface. since pci bus accesses to the rom may be 32 bits wide, repeated operations to the rom are generated by the S5935 and the wider data is assembled internal to the S5935 controller and then transferred to the pci bus by the S5935. table 25. expansion rom base address register bit description 31:11 expansion rom base address location. these bits are used to position the decoded region in memory space. only bits which return a 1 after being written as 1 are usable for this purpose. these bits are individually enabled by the contents sourced from the external boot memory (eprom or nvram). the desired size for the rom memory is determined by writing all ones to this register and then reading back the contents. the number of bits returned as zeros, in order from least significant to most significant bit, indicates the size of the expansion rom. this controller limits the expansion rom area to 64k bytes. the allowable returned values after all ones are written to this register are shown in table 26. 10:1 reserved. all zeros. 0 address decode enable. the expansion rom address decoder is enabled or disabled with this bit. when this bit is set, the decoder is enabled; when this bit is zero, the decoder is disabled. it is required that the pci command register also have the memory decode enabled for this bit to have an effect.
3-39 pci configuration registers S5935 response size in bytes [eprom boot value] 00000000h none - disabled 00000000h or bios missing fffff801h 2k bytes (512 dwords) fffff801h fffff001h 4k bytes (1k dwords) fffff001h ffffe001h 8k bytes (2k dwords) ffffe001h ffffc001h 16k bytes (4k dwords) ffffc001h ffff8001h 32k bytes (8k dwords) ffff8001h ffff0001h 64k bytes (16k dwords) ffff0001h table 26. read response to expansion rom base address register (after all-ones written)
3-40 S5935 pci configuration registers interrupt line register (intln) register name: interrupt line address offset: 3ch power-up value: ffh boot-load: external nvram offset 7ch attribute: read/write size: 8 bit this register indicates the interrupt routing for the S5935 controller. the ultimate value for this register is system-architecture specific. for x86 based pcs, the values in this register correspond with the estab- lished interrupt numbers associated with the dual 8259 controllers used in those machines. in x86- based pc systems, the values of 0 to 15 correspond with the irq numbers 0 through 15, and the values from 16 to 254 are reserved. the value of 255 (the controllers default power-up value) signifies either unknown or no connection for the system inter- rupt. this register is boot-loaded from the external boot memory, if present, and may be written by the pci interface. 7 0 1 ffh 5 bit value 6 42 3 figure 13. interrupt line register
3-41 pci configuration registers S5935 interrupt pin register (intpin) register name: interrupt pin address offset: 3dh power-up value: 01h boot-load: external nvram offset 7dh attribute: read only size: 8 bits figure 14. interrupt pin register 7 0 1 5 bit value 6 42 3 0 0 0 0 0 x x x reserved (all zeroes-ro) pin number 0 0 0 none 0 0 1 inta# 0 1 0 intb# 0 1 1 intc# 1 0 0 intd# 1 0 1 reserved 1 1 x reserved this register identifies which pci interrupt, if any, is connected to the controllers pci interrupt pins. the allowable values are 0 (no interrupts), 1 (inta#), 2 (intb#), 3 (intc#), and 4 (intd#). the default power-up value assumes inta#.
3-42 S5935 pci configuration registers minimum grant register (mingnt) register name: minimum grant address offset: 3eh power-up value: 00h boot-load: external nvram offset 7eh attribute: read only size: 8 bits this register may be optionally used by bus masters to specify how long a burst period the device needs. a value of zero indicates that the bus master has no stringent requirement. the units defined by the least significant bit are in 250-ns increments. this register is treated as information only and has no further implementation within this device. values other than zero are possible when an external boot memory is used. figure 15. minimum grant register 7 0 value x 250ns (ro) 00-no requirement 01-ffh 1 2 3 4 5 6 0 bit value 000 0 0 00
3-43 pci configuration registers S5935 maximum latency register (maxlat) register name: maximum latency address offset: 3fh power-up value: 00h boot-load: external nvram offset 7fh attribute: read only size: 8 bits this register may be optionally used by bus masters to specify how often this device needs pci bus ac- cess. a value of zero indicates that the bus master has no stringent requirement. the units defined by the least significant bit are in 250-ns increments. this register is treated as information only and has no further implementation within this device. values other than zero are possible when an external boot memory is used. figure 16. maximum latency register 7 0 value x 250ns (ro) 00-no requirement 01-ffh 1 2 3 4 5 6 0 bit value 000 0 0 00
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4-45 pci bus operation registers S5935 address offset abbreviation register name 00h omb1 outgoing mailbox register 1 04h omb2 outgoing mailbox register 2 08h omb3 outgoing mailbox register 3 0ch omb4 outgoing mailbox register 4 10h imb1 incoming mailbox register 1 14h imb2 incoming mailbox register 2 18h imb3 incoming mailbox register 3 1ch imb4 incoming mailbox register 4 20h fifo fifo register port (bidirectional) 24h mwar master write address register 28h mwtc master write transfer count register 2ch mrar master read address register 30h mrtc master read transfer count register 34h mbef mailbox empty/full status 38h intcsr interrupt control/status register 3ch mcsr bus master control/status register table 1. operation registers pci bus ? pci bus operation registers the pci bus operation registers are mapped as 16 consecutive dword registers located at the address space (i/o or memory) specified by the base address register 0. these locations are the primary method of communi- cation between the pci and add-on buses. data, software-defined commands and command parameters can be either exchanged through the mailboxes, transferred through the fifo in blocks under program control, or transferred using the fifos under bus master control. table 1 lists the pci bus operation registers.
4-46 pci bus operation registers S5935 outgoing mailbox registers (omb) register names: outgoing mailboxes 1-4 pci address offset: 00h, 04h, 08h, 0ch power-up value: xxxxxxxxh attribute: read/write size: 32 bits these four dword registers provide a method for sending command or parameter data to the add-on system. pci bus operations to these registers may be in any width (byte, word, or dword). writing to these registers can be a source for add-on bus inter- rupts (if desired) by enabling their interrupt genera- tion through the use of the add-ons interrupt control/ status register. incoming mailbox registers (imb) register names: incoming mailboxes 1-4 pci address offset: 10h, 14h, 18h, 1ch power-up value: xxxxxxxxh attribute: read only size: 32 bits these four dword registers provide a method for receiving user defined data from the add-on system. pci bus read operations to these registers may be in any width (byte, word, or dword). only read opera- tions are supported. reading from these registers can optionally cause an add-on bus interrupt (if desired) by enabling their interrupt generation through the use of the add-ons interrupt control/status register. mailbox 4, byte 3 only exists as device pins on the S5935 devices when used with a serial nonvolatile memory. this location provides access to the bidirectional fifo. separate registers are used when reading from or writing to the fifo. accordingly, it is not pos- sible to read what was written to this location. the fifo registers are implicitly involved in all bus master operations and, as such, should not be accessed during active bus master transfers. when operating upon the fifos with software program transfers in- volving word or byte operations, the endian sequence of the fifo should be established as described un- der fifo endian conversion management in order to preserve the internal fifo data ordering and flag management. the fifos fullness may be observed by reading the master control- status registeror mcsr register. fifo register port (fifo) register name: fifo port pci address offset: 20h power-up value: xxxxxxxxh attribute: read/write size: 32 bits
4-47 pci bus operation registers S5935 pci controlled bus master write address register (mwar) register name: master write address pci address offset: 24h power-up value: 00000000h attribute: read/write size: 32 bits this register is used to establish the pci address for data moving from the add-on bus to the pci bus during pci bus memory write operations. it consists of a 30-bit counter with the low-order two bits hardwired as zeros. transfers may be any non-zero byte length as defined by the transfer count register, mwtc, and must begin on a dword boundary. this dword boundary starting constraint is placed upon this controllers pci bus master transfers so that byte lane alignment can be maintained between the S5935 controllers internal fifo data path, the add-on interface, and the pci bus. note: applications which require a non-dword starting boundary will need to move the first few bytes under software program control (and without using the fifo) to establish a dword boundary. after the dword boundary is established the S5935 can begin the task of pci bus master data transfers. the master write address register is continually up- dated during the transfer process and will always be pointing to the next unwritten location. reading of this register during a transfer process (done when the S5935 controller is functioning as a target, i.e. not a bus master) is permitted and may be used to monitor the progress of the transfer. during the address phase for bus master write transfers, the two least significant bits presented on the pci bus pins ad[31:0] will always be zero. this identifies to the target memory that the burst address sequence will be in a linear order rather than in an intel 486 or pentium? cache line fill sequence. also, the pci bus address bit a1 will always be zero when this control- ler is the bus master. this signifies to the target that the S5935 controller is burst capable and that the target should not arbitrarily disconnect after the first data phase of this operation. under certain circumstances, mwar can be ac- cessed from the add-on bus instead of the pci bus. see add-on initiated bus mastering. 31 0 0 1 0 2 bit value dword address (ro) write transfer address (r/w) figure 1. pci controlled bus master write address register
4-48 pci bus operation registers S5935 pci controlled bus master write transfer count register (mwtc) register name: master write transfer count pci address offset: 28h power-up value: 00000000h attribute: read/write size: 32 bits the master write transfer count register is used to convey to the S5935 controller the actual number of bytes that are to be transferred. the value in this register is decremented with each bus master pci write operation until the transfer count reaches zero. upon reaching zero, the transfer operation ceases and an interrupt may be optionally generated to ei- ther the pci or add-on bus interface. transfers which are not whole multiples of dwords in size result in a partial word ending cycle. this partial word ending cycle is possible since all bus master trans- fers for this controller are required to begin on a dword boundary. under certain circumstances, mwtc can be ac- cessed from the add-on bus instead of the pci bus. see add-on initiated bus mastering. 31 0 25 bit value transfer count in bytes (r/w) reserved = o's (ro) 26 00 figure 2. pci controlled bus master write transfer count register
4-49 pci bus operation registers S5935 pci controlled bus master read address register (mrar) register name: master read address pci address offset: 2ch power-up value: 00000000h attribute: read/write size: 32 bits this register is used to establish the pci address for data moving to the add-on bus from the pci bus during pci bus memory read operations. it consists of a 30-bit counter with the low-order two bits hardwired as zeros. transfers may be any non-zero byte length as defined by the transfer count register, mrtc (section 5.7) and must begin on a dword boundary. this dword boundary starting constraint is placed upon this controllers pci bus master trans- fers so that byte lane alignment can be maintained between the S5935 controllers internal fifo data path, the add-on interface and the pci bus. note: applications which require a non-dword starting boundary will need to move the first few bytes under software program control (and without using the fifo) to establish a dword boundary. after the dword boundary is established the S5935 can begin the task of pci bus master data transfers. the master read address register is continually up- dated during the transfer process and will always be pointing to the next unread location. reading of this register during a transfer process (done when the S5935 controller is functioning as a targeti.e., not a bus master) is permitted and may be used to monitor the progress of the transfer. during the address phase for bus master read transfers, the two least significant bits presented on the pci bus ad[31:0] will always be zero. this identifies to the target memory that the burst address sequence will be in a linear order rather than in an intel 486 or pentium? cache line fill sequence. also, the pci bus address bit a1 will always be zero when this controller is the bus master. this signifies to the target that the con- troller is burst capable and that the target should not arbitrarily disconnect after the first data phase of this operation. under certain circumstances, mrar can be ac- cessed from the add-on bus instead of the pci bus. 31 0 0 1 0 2 bit value dword address (ro) read transfer address (r/w) figure 3. pci controlled bus master read address register
4-50 pci bus operation registers S5935 pci controlled bus master read transfer count register (mrtc) register name: master read transfer count pci address offset: 30h power-up value: 00000000h attribute: read/write size: 32 bits the master read transfer count register is used to convey to the pci controller the actual number of bytes that are to be transferred. the value in this register is decremented with each bus master pci read operation until the transfer count reaches zero. upon reaching zero, the transfer operation ceases and an interrupt may be optionally generated to ei- ther the pci or add-on bus interface. transfers which are not whole multiples of dwords in size result in a partial word ending cycle. this partial word ending cycle is possible since all bus master trans- fers for this controller are required to begin on a dword boundary. under certain circumstances, mrtc can be ac- cessed from the add-on bus instead of the pci bus. 31 0 25 bit value transfer count in bytes (r/w) reserved = 0's (ro) 26 00 figure 4. pci controlled bus master read transfer count register
4-51 pci bus operation registers S5935 mailbox empty full/status register (mbef) register name: mailbox empty/full status pci address offset: 34h power-up value: 00000000h attribute: read only size: 32 bits this register provides empty/full visibility of each byte within the mailboxes. the empty/full status for the outgoing mailboxes is displayed on the low-order 16 bits and the empty/full status for the incoming mail- boxes is presented on the high-order 16 bits. a value of 1 signifies that a given mailbox has been written by one bus interface but has not yet been read by the corresponding destination interface. a pci bus in- coming mailbox is defined as one in which data trav- els from the add-on bus into the pci bus, and an outgoing mailbox is defined as one where data trav- els out from the pci bus to the add-on interface. 31 0 15 bit value outgoing mailbox status (ro) incoming mailbox status (ro) 16 figure 5. mailbox empty/full status register
4-52 pci bus operation registers S5935 table 2. mailbox empty/full status register bit description 31:16 incoming mailbox status. this field indicates which incoming mailbox registers have been written by the add-on interface but have not yet been read by the pci bus. each bit location corre- sponds to a specific byte within one of the four incoming mailboxes. a value of one for each bit signifies that the specified mailbox byte is full, and a value of zero signifies empty. the mapping of these status bits to bytes within each mailbox is as follows: bit 31 = incoming mailbox 4 byte 3 bit 30 = incoming mailbox 4 byte 2 bit 29 = incoming mailbox 4 byte 1 bit 28 = incoming mailbox 4 byte 0 bit 27 = incoming mailbox 3 byte 3 bit 26 = incoming mailbox 3 byte 2 bit 25 = incoming mailbox 3 byte 1 bit 24 = incoming mailbox 3 byte 0 bit 23 = incoming mailbox 2 byte 3 bit 22 = incoming mailbox 2 byte 2 bit 21 = incoming mailbox 2 byte 1 bit 20 = incoming mailbox 2 byte 0 bit 19 = incoming mailbox 1 byte 3 bit 18 = incoming mailbox 1 byte 2 bit 17 = incoming mailbox 1 byte 1 bit 16 = incoming mailbox 1 byte 0 15:00 outgoing mailbox status. this field indicates which out going mail box registers have been written by the pci bus interface but have not yet been read by the add-on bus. each bit location corresponds to a specific byte within one of the four outgoing mailboxes. a value of one for each bit signifies that the specified mailbox byte is full, and a value of zero signifies empty. the mapping of these status bits to bytes within each mailbox is as follows: bit 15 = outgoing mailbox 4 byte 3 bit 14 = outgoing mailbox 4 byte 2 bit 13 = outgoing mailbox 4 byte 1 bit 12 = outgoing mailbox 4 byte 0 bit 11 = outgoing mailbox 3 byte 3 bit 10 = outgoing mailbox 3 byte 2 bit 09 = outgoing mailbox 3 byte 1 bit 08 = outgoing mailbox 3 byte 0 bit 07 = outgoing mailbox 2 byte 3 bit 06 = outgoing mailbox 2 byte 2 bit 05 = outgoing mailbox 2 byte 1 bit 04 = outgoing mailbox 2 byte 0 bit 03 = outgoing mailbox 1 byte 3 bit 02 = outgoing mailbox 1 byte 2 bit 01 = outgoing mailbox 1 byte 1 bit 00 = outgoing mailbox 1 byte 0
4-53 pci bus operation registers S5935 interrupt control/status register (intcsr) register name: interrupt control and status pci address offset: 38h power-up value: 00000000h attribute: read/write (r/w), read/write_one_clear (r/wc) size: 32 bits this register provides the method for choosing which conditions are to produce an interrupt on the pci bus interface, a method for viewing the cause of the inter- rupt, and a method for acknowledging (removing) the interrupts assertion. interrupt sources: ? write transfer terminal count = zero ? read transfer terminal count = zero ? one of the outgoing mailboxes (1,2,3 or 4) becomes empty ? one of the incoming mailboxes (1,2,3 or 4) becomes full. ? target abort ? master abort figure 6. interrupt control/status register 31 0 15 14 12 8 4 bit value 16 21 23 24 fifo and endian control 0 read transfer complete (r/wc) write transfer complete (r/wc) incoming mailbox interrupt (r/wc) outgoing mailbox interrupt (r/wc) interrupt asserted (ro) target abort (r/wc) master abort (r/wc) 0 0 0 0 d4-d0 outgoing mailbox (goes empty) d4=enable interrrupt d3-d2=mailbox # 0 0=mailbox 1 0 1=mailbox 2 1 0=mailbox 3 1 1=mailbox 4 d1-d0=byte # 0 0=byte 0 0 1=byte 1 1 0=byte 2 1 1=byte 3 d12-d8 incoming mailbox (r/w) (becomes full) d12=enable interrupt d11-d10=mailbox 0 0=mailbox 1 0 1=mailbox 2 1 0=mailbox 3 1 1=mailbox 4 d9-d8=byte # 0 0=byte 0 0 1=byte 1 1 0=byte 2 1 1=byte 3 interrupt on write transfer complete interrupt on read transfer complete interrupt source (r/w) enable & selection actual interrupt interrupt selection
4-54 pci bus operation registers S5935 figure 7. fifo management and endian control byte 0 0 1 1 0 no conversion (default) 1 16 bit endian conv. 0 32 bit endian conv. 1 64 bit endian conv fifo advance control pci interface 0 0 byte 0 (default) 0 1 byte 1 1 0 byte 2 1 1 byte 3 fifo advance control add-on interface 0 0 byte 0 (default) 0 1 byte 1 1 0 byte 2 1 1 byte 3 outbound fifo pci add-on dword toggle 0 = bytes 0-3 (default) 1 = byte 4-7 (note1) inbound fifo add-on pci dword toggle 0 = bytes 0-3 (default) 1 = byte 4-7 note 1: d24 and d25 must be also "1" 31 30 29 28 27 26 25 24 1
4-55 pci bus operation registers S5935 table 3. interrupt control/status register bit description 31:24 fifo and endian control. 23 interrupt asserted. this read only status bit indicates that one or more of the four possible interrupt conditions is present. this bit is nothing more than the oring of the interrupt conditions described by bits 19 through 16 of this register. 22 reserved. always zero. 21 target abort. this bit signifies that an interrupt has been generated due to the S5935 encountering a target abort during a pci bus cycle while the S5935 was the current bus master. this bit operates as read or write one clear. a write to this bit with the data of one will cause this bit to be reset, a write to this bit with the data of zero will not change the state of this bit. 20 master abort. this bit signifies that an interrupt has been generated due to the S5935 encountering a master abort on the pci bus. a master abort occurs when there is no target response to a pci bus cycle. this bit operates as read or write one clear. a write to this bit with the data of one will cause this bit be reset, a write to this bit with the data of zero will not change the state of this bit. 19 read transfer complete. this bit signifies that an interrupt has been generated due to the completion of a pci bus master operation involving the transfer of data from the pci bus to the add-on. this interrupt will occur when the master read transfer count register reaches zero. this bit operates as read or write one clear. a write to this bit with the data of one will cause this bit to be reset; a write to this bit with the data of zero will not change the state of this bit. 18 write transfer complete. this bit signifies that an interrupt has been generated due to the completion of a pci bus master operation involving the transfer of data to the pci bus from the add-on. this interrupt will occur when the master write transfer count register reaches zero. this bit operates as read or write one clear. a write to this bit with the data of one will cause this bit to be reset; a write to this bit with the data of zero will not change the state of this bit. 17 incoming mailbox interrupt. this bit is set when the mailbox selected by bits 12 through 8 of this register are written by the add-on interface. this bit operates as read or write one clear. a write to this bit with the data of one will cause this bit to be reset; a write to this bit with the data as zero will not change the state of this bit. 16 outgoing mailbox interrupt. this bit is set when the mailbox selected by bits 4 through 0 of this register is read by the add-on interface. this bit operates as read or write one clear. a write to this bit with the data of one will cause this bit to be reset; a write to this bit with the data of zero will not change the state of this bit. 15 interrupt on read transfer complete. this bit enables the occurrence of an interrupt when the read transfer count reaches zero. this bit is read/write. 14 interrupt on write transfer complete. this bit enables the occurrence of an interrupt when the write transfer count reaches zero. this bit is read/write. 13 reserved. always zero. 12 enable incoming mailbox interrupt. this bit allows a write from the incoming mailbox register identified by bits 11 through 8 to produce a pci interface interrupt. this bit is read/write. 11:10 incoming mailbox interrupt select. this field selects which of the four incoming mailboxes is to be the source for causing an incoming mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and [11]b selects mailbox 4. this field is read/write.
4-56 pci bus operation registers S5935 table 3. interrupt control/status register (continued) 9:8 incoming mailbox byte interrupt select. this field selects which byte of the mailbox selected by bits 10 and 11 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. this field is read/write. 7:5 reserved, always zero. 4 enable outgoing mailbox interrupt. this bit allows a read by the add-on of the outgoing mailbox register identified by bits 3 through 0 to produce a pci interface interrupt. this bit is read/write. 3:2 outgoing mailbox interrupt select. this field selects which of the four outgoing mailboxes is to be the source for causing an outgoing mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and [11]b selects mailbox 4. this field is read/write. 1:0 outgoing mailbox byte interrupt select. this field selects which byte of the mailbox selected by bits 3 and 2 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. this field is read/write. bit description
4-57 pci bus operation registers S5935 master control/status register (mcsr) register name: master control/status pci address offset: 3ch power-up value: 000000e6h attribute: read/write, read only, write only size: 32 bits this register provides for overall control of this de- vice. it is used to enable bus mastering for both data directions as well as providing a method to perform software resets. the following pci bus controls are available: ? write priority over read ? read priority over write ? write transfer enable ? write master requests on 4 or more fifo words available (full) ? read transfer enable ? read master requests on 4 or more fifo available (empty) ? assert reset to add-on ? reset add-on to pci fifo flags ? reset pci to add-on fifo flags ? reset mailbox empty full status flags ? write external non-volatile memory the following pci interface status flags are provided: ? pci to add-on fifo full ? pci to add-on fifo has four or more empty locations ? pci to add-on fifo empty ? add-on to pci fifo full ? add-on to pci fifo has four or more words loaded ? add-on to pci fifo empty ? pci to add-on transfer count = zero ? add-on to pci transfer count = zero figure 8. bus master control/status register 31 29 27 24 23 0 14 12 10 8 7 6 5 15 bit value fifo status (ro) d5=add-on to pci fifo empty d4=add-on to pci fifo 4+ words d3=add-on to pci fifo full d2=pci to add-on fifo empty d1=pci to add-on fifo 4+spaces d0=pci to add-on fifo full d7=add-on to pci transfer count equals zero (r0) d6=pci to add-on transfer count equals zero (r0) 16 0 write transfer control (r/w) (pci memory writes) d10=write transfer enable d9=fifo management scheme d8=write vs read priority reset controls (r/wc) d27=mailbox flags reset d26=add-on to pci fifo status flags reset d25=pci to add-on fifo status flags reset d24=add-on reset nv operation address/data memory read multiple enable = 1 disable = 0 read transfer control (r/w) (pci memory reads) d14=read transfer enable d13=fifo management scheme d12=read vs. write priority nvram access ctrl 0 0 control status
4-58 pci bus operation registers S5935 table 4. bus master control/status register bit description 31:29 nvram access control. this field provides a method for access to the optional external non-volatile memory. write operations are achieved by a sequence of byte operations involving these bits and the 8-bit field of bits 23 through 16. the sequence requires that the low-order address, high order address, and then a data byte are loaded in order. bit 31 of this field acts as a combined enable and ready for the access to the external memory. d31 must be written to a 1 before an access can begin, and subsequent accesses must wait for bit d31 to become zero (ready). d31 d30 d29 w/r 0 x x w inactive 1 0 0 w load low address byte 1 0 1 w load high address byte 1 1 0 w begin write 1 1 1 w begin read 0 x x r ready 1 x x r busy cautionary note: the nonvolatile memory interface is also available for access by the add-on interface. accesses by both the add-on and pci bus to the nv memory are not directly supported by the S5935 device. software must be designed to prevent the simultaneous access of nv memory to prevent data corruption within the memory and provide for accurate data retrieval. 28 fifo loop back mode. 27 mailbox flag reset. writing a one to this bit causes all mailbox status flags to become reset (empty). it is not necessary to write this bit as zero because it is used internally to produce a reset pulse. since reading of this bit will always produce zeros, this bit is write only. 26 add-on to pci fifo status reset. writing a one to this bit causes the add-on to pci (bus master memory writes) fifo empty flag to set indicating empty and the fifo full flag to reset and the fifo four plus word flag to reset. it is not necessary to write this bit as zero because it is used internally to produce a reset pulse. since reading of this bit will always produce zeros, this bit is write only. 25 pci to add-on fifo status reset. writing a one to this bit causes the pci to add-on (bus master memory reads) fifo empty flag to set indicating empty and the fifo full flag to reset and the fifo four plus words available flag to set. it is not necessary to write this bit as zero because it is used internally to produce a reset pulse. since reading of this bit will always produce zeros, this bit is write only. 24 add-on pin reset. writing a one to this bit causes the reset output pin to become active. writing a zero to this pin is necessary to remove the assertion of reset. this register bit is read/write. 23:16 non-volatile memory address/data port. this 8-bit field is used in conjunction with bit 31, 30 and 29 of this register to access the external non-volatile memory. the contents written are either low address, high address, or data as defined by bits 30 and 29. this register will contain the external non-volatile memory data when the proper read sequence for bits 31 through 29 is performed.
4-59 pci bus operation registers S5935 table 4. bus master control/status register (continued) bit description 15 enable memory read multiple during S5935 bus mastering mode. 14 read transfer enable. this bit must be set to a one for S5935 pci bus master read transfers to take place. writing a zero to this location will suspend an active transfer. an active transfer is one in which the transfer count is not zero. 13 read fifo management scheme. when set to a 1, this bit causes the controller to refrain from requesting the pci bus unless it has four or more vacant fifo locations to fill. once the controller is granted the pci bus or is in possession of the bus due to the write channel, this constraint is not meaningful. when this bit is zero the controller will request the pci bus if it has at least one vacant fifo word. 12 read versus write priority. this bit controls the priority of read transfers over write transfers. when set to a 1 with bit d8 as zero this indicates that read transfers always have priority over write transfers; when set to a one with d8 as one, this indicates that transfer priorities will alternate equally between read and writes. 11 reserved. always zero. 10 write transfer enable. this bit must be set to a one for pci bus master write transfers to take place. writing a zero to this location will suspend an active transfer. an active transfer is one in which the transfer count is not zero. 9 write fifo management scheme. when set to a one this bit causes the controller to refrain from requesting the pci bus unless it has four or more fifo locations filled. once the S5935 controller is granted the pci bus or is in possession of the bus due to the write channel, this constraint is not meaningful. when this bit is zero the controller will request the pci bus if it has at least one valid fifo word. 8 write versus read priority. this bit controls the priority of write transfers over read transfers. when set to a one with bit d12 as zero this indicates that write transfers always have priority over read transfers. this combination is not allowed, data integrity may be compromised. when set to a one with d12 as one, this indicates that transfer priorities will alternate equally between writes and reads. 7 add-on to pci transfer count equal zero (ro). this bit is a one to signify that the write transfer count is all zeros. 6 pci to add-on transfer count equals zero (ro). this bit is a one to signify that the read transfer count is all zeros. 5 add-on to pci fifo empty. this bit is a one when the add-on to pci bus fifo is completely empty. 4 add-on to pci 4+ words. this bit is a one when there are four or more fifo words valid within the add-on to pci bus fifo. 3 add-on to pci fifo full. this bit is a one when the add-on to pci bus fifo is completely full. 2 pci to add-on fifo empty. this bit is a one when the pci bus to add-on fifo is completely empty. 1 pci to add-on fifo 4+ spaces. this bit signifies that there are at least four empty words within the pci to add-on fifo. 0 pci to add-on fifo full. this bit is a one when the pci bus to add-on fifo is completely full.
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5-61 add-on bus operation registers S5935 add-on bus operation registers the add-on bus interface provides access to 18 dwords (72 bytes) of data, control and status infor- mation. all of these locations are accessed by assert- ing the add-on bus chip select pin (select#) in conjunction with either the read or write control strobes (signal pin rd# or wr#). access to the fifo can also be achieved through use of the dedicated pins, rdfifo# and wrfifo#. the dedicated pins for control of the fifo are provided to optionally implement direct memory access (dma) on the add- on bus, or to connect with an external fifo. this register group represents the primary method for communication between the add-on and pci buses as viewed by the add-on. the flexibility of this ar- rangement allows a number of user-defined software protocols to be built. for example, data, software as- signed commands, and command parameters can be exchanged between the pci and add-on buses us- ing either the mailboxes or fifos with or without handshaking interrupts. the register structure is very similar to that of the pci operation register set. the major difference between the pci bus and add-on bus register complement are the absence of bus master control registers (4) on the add-on side and the addition of two pass-through registers. table 1 lists the add-on interface registers. address abbreviation register name 00h aimb1 add-on incoming mailbox register #1 04h aimb2 add-on incoming mailbox register #2 08h aimb3 add-on incoming mailbox register #3 0ch aimb4 add-on incoming mailbox register #4 10h aomb1 add-on outgoing mailbox register #1 14h aomb2 add-on outgoing mailbox register #2 18h aomb3 add-on outgoing mailbox register #3 1ch aomb4 add-on outgoing mailbox register #4 20h afifo add-on fifo port 24h mwar 1 bus master write address register 28h apta add-on pass-through address 2ch aptd add-on pass-through data 30h mrar 1 bus master read address register 34h ambef add-on mailbox empty/full status 38h aint add-on interrupt control 3ch agcsts add-on general control and status register 58h mwtc 1 bus master write transfer count 5ch mrtc 1 bus master read transfer count table 1. operation registers add-on interface 1. see add-on initiated bus mastering. ?
5-62 add-on bus operation registers S5935 add-on incoming mailbox registers (aimbx) register names: add-on incoming mailboxes 1-4 add-on address offset: 00h, 04h, 08h, 0ch power-up value: xxxxxxxxh attribute: read only size: 32 bits add-on outgoing mailbox registers (aombx) register names: add-on outgoing mailboxes 1-4 add-on address offset: 10h, 14h, 18h, 1ch power-up value: xxxxxxxxh attribute: read/write size: 32 bits add-on fifo register port (afifo) register name: add-on fifo port add-on address offset: 20h power-up value: xxxxxxxxh attribute: read/write size: 32 bits this location provides access to the bidirectional fifo. separate registers are involved when reading and writing to this location. accordingly, it is not possible to read what was written to this location. the sequence of filling and emptying this fifo is established by the pci interface interrupt control and status register. the fifos fullness may be observed by reading the master control/status register or agcsts register additionally, two signal pins are provided which re- veal whether data is available (rdempty) or space to write into the fifo is available (wrfull). these signals may be used to interface with user supplied dma logic. caution must be exercised when using these flags for fifo transfers involving 64 bit endian conversion since the fifo must operate on dword pairs. these four dword registers provide a method for sending data, commands, or command parameters or status to the pci interface. add-on write opera- tions to these registers may be in any width (byte, word, or dword). these registers may also be read. writing to one of these registers can optionally cause a pci bus interrupt (if desired) when the pci interrupt control/status register is properly configured. mailbox 4, byte 3 only exists as device pins on the S5935 device when used with a serial nonvolatile memory. this byte is not available if a byte-wide nv memory is used. these four dword registers provide a method for receiving data, commands, or command parameters from the pci interface. add-on read operations to these registers may be in any width (byte, word, or dword). these registers are read-only. writes to this address space have no effect. reading from one of these registers can optionally cause a pci bus interrupt (if desired) when the pci interrupt control/ status register is properly configured.
5-63 add-on bus operation registers S5935 add-on controlled bus master write address register (mwar) register name: master write address add-on address offset: 24h power-up value: 00000000h attribute: read/write size: 32 bits this register is only accessible when add-on initiated bus mastering is enabled. this register is used to establish the pci address for data moving from the add-on bus to the pci bus during pci bus memory write operations. it consists of a 30-bit counter with the low-order two bits hardwired as zeros. transfers may be any non-zero byte length as defined by the transfer count register, mwtc and must begin on a dword boundary. this dword boundary starting constraint is placed upon this controllers pci bus master transfers so that byte lane alignment can be maintained between the S5935 controllers internal fifo data path, the add- on interface, and the pci bus. note: applications which require a non-dword starting boundary will need to move the first few bytes under software program control (and without using the fifo) to establish a dword boundary. after the dword boundary is established the S5935 can begin the task of pci bus master data transfers. the master write address register is continually up- dated during the transfer process and will always be pointing to the next unwritten location. reading of this register during a transfer process (done when the S5935 controller is functioning as a target, i.e. not a bus master) is permitted and may be used to monitor the progress of the transfer. during the address phase for bus master write transfers, the two least significant bits presented on the pci bus pins ad[31:0] will always be zero. this identifies to the target memory that the burst address sequence will be in a linear order rather than in an intel 486 or pentium? cache line fill sequence. also, the pci bus address bit a1 will always be zero when this control- ler is the bus master. this signifies to the target that the S5935 controller is burst capable and that the target should not arbitrarily disconnect after the first data phase of this operation. 31 0 0 1 0 2 bit value dword address (ro) write transfer address (r/w) figure 1. add-on controlled bus master write address register
5-64 add-on bus operation registers S5935 add-on pass-thru address register (apta) register name: add-on pass-thru address add-on address offset: 28h power-up value: xxxxxxxxh attribute: read only size: 32 bits this register is employed when a response is desired when one of the base address decode regions is selected during an active pci bus cycle. when one of the base address decode registers 1-4 encounters a pci bus cycle which selects the region defined by it, this device latches that current cycles active address and asserts the signal ptatn# (pass-thru atten- tion). wait states are generated on the pci bus until either data is transferred or the pci bus cycle is aborted by the initiator. this register provides a method for live data (regis- tered) transfers. intended uses include the emulating of other hardware as well as enabling the connection of existing external hardware to interface to the pci bus through the S5935. add-on pass-thru data register (aptd) register name: add-on pass-thru data add-on address offset: 2ch power-up value: xxxxxxxxh attribute: read/write size: 32 bits this register, along with apta described above, is employed when a response is desired should one of the base address decode regions become selected during an active pci bus cycle. when one of the base address decode registers 1-4 encounters a pci bus cycle which selects the region defined by it, the apta register will contain that current cycles active address and the device asserts the signal ptatn# (pass-thru atention). wait states are generated on the pci bus until this register is read (pci bus writes) or this register is written (pci bus reads).
5-65 add-on bus operation registers S5935 add-on controlled bus master read address register (mrar) register name: master read address add-on address offset: 30h power-up value: 00000000h attribute: read/write size: 32 bits this register is only accessible when add-on initiated bus mastering is enabled. this register is used to establish the pci address for data moving to the add-on bus from the pci bus during pci bus memory read operations. it consists of a 30-bit counter with the low-order two bits hardwired as zeros. transfers may be any non-zero byte length as defined by the transfer count register, mrtc and must begin on a dword boundary. this dword boundary starting constraint is placed upon this controllers pci bus master transfers so that byte lane alignment can be maintained between the s5395x controllers internal fifo data path, the add- on interface and the pci bus. note: applications which require a non-dword starting boundary will need to move the first few bytes under software program control (and without using the fifo) to establish a dword boundary. after the dword boundary is established the S5935 can begin the task of pci bus master data transfers. the master read address register is continually up- dated during the transfer process and will always be pointing to the next unread location. reading of this register during a transfer process (done when the S5935 controller is functioning as a targeti.e., not a bus master) is permitted and may be used to monitor the progress of the transfer. during the address phase for bus master read transfers, the two least significant bits presented on the pci bus ad[31:0] will always be zero. this identifies to the target memory that the burst address sequence will be in a linear order rather than in an intel 486 or pentium? cache line fill sequence. also, the pci bus address bit a1 will always be zero when this controller is the bus master. this signifies to the target that the con- troller is burst capable and that the target should not arbitrarily disconnect after the first data phase of this operation. under certain circumstances, mrar can be ac- cessed from the add-on bus instead of the pci bus. 31 0 0 1 0 2 bit value dword address (ro) read transfer address (r/w) figure 2. add-on controlled bus master read address register
5-66 add-on bus operation registers S5935 add-on empty/full status register (ambef) register name: add-on mailbox empty/full status add-on address offset: 34h power-up value: 00000000h attribute: read only size: 32 bits this register provides empty/full visibility of each byte within the mailboxes. the empty/full status for the outgoing mailboxes are displayed on the high order 16 bits and the empty/full status for the incoming mailboxes are presented on the low order 16 bits. a value of one signifies that a given mailbox had been written by the sourcing interface but had not yet been read by the corresponding destination interface. an incoming mailbox is defined as one in which data travels from the pci bus into the add-on bus and an outgoing mailbox is defined as one where data goes out from the add-on bus to the pci interface. figure 3. add-on mailbox empty/full status register 31 0 15 bit value incoming mailbox status (ro) outgoing mailbox status (ro) 16
5-67 add-on bus operation registers S5935 table 2. add-on mailbox empty/full status register bit description 31:16 outgoing mailbox status. this field indicates which outgoing mailbox registers have been written by the add-on bus interface but have not yet been read by the pci bus. each bit location corresponds to a specific byte within one of the four outgoing mailboxes. a value of one for each bit signifies that the specified mailbox byte is full, a value of zero signifies empty. the mapping of these status bits to bytes within each mailbox is as follows: bit 31 = outgoing mailbox 4 byte 3 bit 30 = outgoing mailbox 4 byte 2 bit 29 = outgoing mailbox 4 byte 1 bit 28 = outgoing mailbox 4 byte 0 bit 27 = outgoing mailbox 3 byte 3 bit 26 = outgoing mailbox 3 byte 2 bit 25 = outgoing mailbox 3 byte 1 bit 24 = outgoing mailbox 3 byte 0 bit 23 = outgoing mailbox 2 byte 3 bit 22 = outgoing mailbox 2 byte 2 bit 21 = outgoing mailbox 2 byte 1 bit 20 = outgoing mailbox 2 byte 0 bit 19 = outgoing mailbox 1 byte 3 bit 18 = outgoing mailbox 1 byte 2 bit 17 = outgoing mailbox 1 byte 1 bit 16 = outgoing mailbox 1 byte 0 15:00 incoming mailbox status. this field indicates which incoming mailbox registers have been written by the pci bus but not yet been read by the add-on interface. each bit location corresponds to a specific byte within one of the four incoming mailboxes. a value of one for each bit signifies that the specified mailbox byte is full, a value of zero signifies empty. the mapping of these status bits to bytes within each mailbox is as follows: bit 15 = incoming mailbox 4 byte 3 bit 14 = incoming mailbox 4 byte 2 bit 13 = incoming mailbox 4 byte 1 bit 12 = incoming mailbox 4 byte 0 bit 11 = incoming mailbox 3 byte 3 bit 10 = incoming mailbox 3 byte 2 bit 9 = incoming mailbox 3 byte 1 bit 8 = incoming mailbox 3 byte 0 bit 7 = incoming mailbox 2 byte 3 bit 6 = incoming mailbox 2 byte 2 bit 5 = incoming mailbox 2 byte 1 bit 4 = incoming mailbox 2 byte 0 bit 3 = incoming mailbox 1 byte 3 bit 2 = incoming mailbox 1 byte 2 bit 1 = incoming mailbox 1 byte 1 bit 0 = incoming mailbox 1 byte 0
5-68 add-on bus operation registers S5935 add-on interrupt control/ status register (aint) register name: add-on interrupt control and status add-on address offset: 38h power-up value: 00000000h attribute: read/write, read/write_one_clear size: 32 bits this register provides the method for choosing which conditions are to produce an interrupt on the add-on bus interface, a method for viewing the cause for the interrupt, and a method for acknowledging (remov- ing) the interrupts assertion. interrupt sources: ? one of the incoming mailboxes (1,2,3 or 4) becomes full. ? one of the outgoing mailboxes (1,2,3 or 4) becomes empty. ? built-in self test issued. ? write transfer count = zero ? read transfer count = zero ? target/master abort figure 4. add-on interrupt control/status register 31 24 23 20 1918 21 17 12 8 4 0 bit value d4-d0 incoming mailbox (becomes full) d4=enable interrrupt d3-d2=mailbox # 0 0=mailbox 1 0 1=mailbox 2 1 0=mailbox 3 1 1=mailbox 4 d0-d1=byte # 0 0=byte 0 0 1=byte 1 1 0=byte 2 1 1=byte 3 d12-d8 outgoing mailbox (r/w) (goes empty) d12=enable interrupt d11-d10=mailbox 0 0=mailbox 1 0 1=mailbox 2 1 0=mailbox 3 1 1=mailbox 4 d9-d8=byte # 0 0=byte 0 0 1=byte 1 1 0=byte 2 1 1=byte 3 16 15 14 0 0 0 0 0 0 0 0 0 0 interrupt asserted (ro) bus mastering error interrupt (r/wc) bist (r/wc) read transfer complete (r/wc) write transfer complete (r/wc) interrupt on read transfer complete outgoing mailbox interrupt (r/wc) incoming mailbox interrupt (r/wc) 0 0 0 interrupt source (r/w) enable & selection interrupt on write transfer complete interrupt status interrupt selection
5-69 add-on bus operation registers S5935 table 3. interrupt control/status register 31:24 reserved. always zero. 23 interrupt asserted. this read-only status bit indicates that one or more interrupt conditions is present. this bit is nothing more than the oring of the interrupt conditions described by bits, 20, 17 and 16 of this register. 22 reserved. always zero. 21 master/target abort. this bit signifies that an interrupt has been generated due to the S5935 encountering a master or target abort during an S5935 initiated pci bus cycle. this bit operates as read or write one clear. writing a one to this bit causes it to be cleared. writing a zero to this bit does nothing. 20 bist. built-in self-test interrupt. this interrupt occurs when a self test is initiated by the pci interface writing of the bist configuration register. this bit will stay set until cleared by writing a one to this location. self test completion codes may be passed to the pci bist register by writing to the agcsts register. 19 read transfer complete. this bit signifies that an interrupt has been generated due to the completion of a pci bus master operation involving the transfer of data from the pci bus to the add-on. this interrupt will occur when the master read transfer count register reaches zero. this bit operates as read or write one clear. a write to this bit with the data of one will cause this bit to be reset; a write to this bit with the data of zero will not change the state of this bit. 18 write transfer complete. this bit signifies that an interrupt has been generated due to the completion of a pci bus master operation involving the transfer of data to the pci bus from the add-on. this interrupt will occur when the master write transfer count register reaches zero. this bit operates as read or write one clear. a write to this bit with the data of one will cause this bit to be reset; a write to this bit with the data of zero will not change the state of this bit. 17 outgoing mailbox interrupt. this bit sets when the mailbox selected by bits 12 through 8 of this register is read by the pci interface. this bit operates as read or write one clear. a write to this bit with the data as one will cause this bit to be reset; a write to this bit with the data as zero will not change the state of this bit. 16 incoming mailbox interrupt. this bit sets when the mailbox selected by bits 4 through 0 of this register are written by the pci interface. this bit operates as read or write one clear. a write to this bit with the data of one will cause this bit to be reset; a write to this bit with the data as zero will not change the state of this bit. 15 interrupt on read transfer complete. this bit enables the occurrence of an interrupt when the read transfer count reaches zero. this bit is read/write. 14 interrupt on write transfer complete. this bit enables the occurrence of an interrupt when the write transfer count reaches zero. this bit is read/write. 13 reserved. always zero. 12 enable outgoing mailbox interrupt. this bit allows a read by the pci of the outgoing mailbox register identified by bits 11 through 8 to produce an add-on interface interrupt. this bit is read/write. 11:10 outgoing mailbox interrupt select. this field selects which of the four outgoing mailboxes is to be the source for causing an outgoing mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and [11]b selects mailbox 4. this field is read/write. 9:8 outgoing mailbox byte interrupt select. this field selects which byte of the mailbox selected by bits 11 and 10 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. this field is read/write. 7:5 reserved. always zero. bit description
5-70 add-on bus operation registers S5935 table 3. interrupt control/status register (continued) bit description 4 enable incoming mailbox interrupt. this bit allows a write from the pci bus to the incoming mailbox register identified by bits 3 through 0 to produce an add-on interface interrupt. this bit is read/write. 3:2 incoming mailbox interrupt select. this field selects which of the four incoming mailboxes is to be the source for causing an incoming mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and [11]b selects mailbox 4. this field is read/write. 1:0 incoming mailbox byte interrupt select. this field selects which byte of the mailbox selected by bits 3 and 2 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 2, and so on.
5-71 add-on bus operation registers S5935 31 29 28 27 25 24 23 0 12 11 6 75 bit value fifo status (ro) d5=pci to add-on fifo empty d4=pci to add-on 4+ spaces d3=pci to add-on fifo full d2=add-on to pci fifo empty d1=add-on to pci fifo 4+ words d0=add-on to pci fifo full 16 15 0 0 bist condition code ( r/w ) reset controls d27=mailbox flags d26=pci to add-on fifo status flags d25=add-on to pci fifo status flags nv operation address/data nvram access ctrl transfer count enable d6=read transfer count equals zero (ro) d7=write transfer count equals zero (ro) add-on general control/status register (agcsts) register name: add-on general control and status add-on address offset: 3ch power-up value: 000000f4h (pci initiated bus mastering) 00000034h (add-on initiated bus mastering) attribute: read/write, read only, write only size: 32 bits this register provides for overall control of the add- on portion of this device. it is used to provide a method to perform software resets of the mailbox and fifo flags. the following add-on controls are provided: ? reset pci to add-on fifo flags ? reset add-on to pci fifo flags ? reset mailbox empty full status flags ? write/read external non-volatile memory. the following status flags are provided to the add-on: ? add-on to pci fifo full ? add-on to pci fifo has four or more empty locations ? add-on to pci fifo empty ? pci to add-on fifo full ? pci to add-on fifo has four or more words loaded ? pci to add-on fifo empty figure 5. add-on general control/status register
5-72 add-on bus operation registers S5935 table 4. add-on general control/status register bit description 31:29 nvram/eprom access control. this field provides a method for access to the optional, external non-volatile memory. write operations are achieved by a sequence of byte operations involving these bits and the 8-bit field of bits 23 through 16. the sequence requires that the low-order address, high-order address, and then a data byte be loaded in order. bit 31 of this field acts as an enable/clock and ready for the access to the external memory. d31 must be written to a 1 before an access can begin, and subsequent accesses must wait for bit d31 to become zero (ready). d31 d30 d29 w/r 0 x x w inactive 1 0 0 w load low address byte 1 0 1 w load high address byte 1 1 0 w begin write 1 1 1 w begin read 0 x x r ready 1 x x r busy cautionary note: the non-volatile memory interface is also available for access by the pci bus interface. accesses by both the add-on and pci bus to the nv memory are not directly supported by this component. software must be designed to prevent the simultaneous access of nv memory to prevent data corruption within the memory and provide for accurate data retrieval. 28 transfer count enable. when set, transfer counts are used for add-on initiated bus master transfers. when clear, transfer counts are ignored. 27 mailbox flag reset. writing a 1 to this bit causes all mailbox status flags to become reset (empty). it is not necessary to write this bit as 0 because it is used internally to produce a reset pulse. since reading of this bit will always produce zeros, this bit is write only. 26 add-on to pci fifo status reset. writing a one to this bit causes the outbound (bus master writes) fifo empty flag to set indicating empty and the fifo full flag to reset and the fifo four plus words available flag to reset. it is not necessary to write this bit as zero because it is used internally to produce a reset pulse. since reading of this bit would always produce zeros, this bit is write only. 25 pci to add-on fifo status reset. writing a 1 to this bit causes the inbound (bus master reads) fifo empty flag to set indicating empty and the fifo full flag to reset and the fifo four plus spaces flag to set. it is not necessary to write this bit as 0 because it is used internally to produce a reset pulse. since reading of this bit would always produce zeros, this bit is write only. 24 reserved. always zero. 23:16 non-volatile memory address/data port. this 8-bit field is used in conjunction with bit 31, 30 and 29 of this register to access the external non-volatile memory. the contents written are either low address, high address, or data as defined by bits 30 and 29. this register will contain the external non-volatile memory data when the proper read sequence for bits 31 through 29 is performed. 15:12 bist condition code. this field is directly connected to the pci configuration self test register. bit 15 through 12 maps with the bist register bits 3 through 0, respectively. 11:8 reserved. always zero.
5-73 add-on bus operation registers S5935 7 add-on to pci transfer count equal zero (ro). this bit as a one signifies that the write transfer count is all zeros. only when add-on initiated bus mastering is enabled. 6 pci to add-on transfer count equals zero (ro). this bit as a one signifies that the read transfer count is all zeros. only when add-on initiated bus mastering is enabled. 5 pci to add-on fifo empty. this bit is a 1 when the pci to add-on fifo is empty. 4 pci to add-on fifo 4+ spaces. this bit is a 1 when there are four or more open spaces in the pci to add-on fifo. 3 pci to add-on fifo full. this bit is a 1 when the pci to add-on fifo is full. 2 add-on to pci fifo empty. this bit is a 1 when the add-on to pci fifo is empty. 1 add-on pci fifo 4+ words. this bit is a 1 when there are four or more full locations in the add- on to pci fifo. 0 add-on to pci fifo full. this bit is a 1 when the add-on to pci fifo is full. table 4. add-on general control/status register (continued) bit description
5-74 add-on bus operation registers S5935 add-on controlled bus master write transfer count register (mwtc) register name: master write transfer count add-on address offset: 58h power-up value: 00000000h attribute: read/write size: 32 bits this register is only accessible when add-on initiated bus mastering is enabled. the master write transfer count register is used to convey to the S5935 controller the actual number of bytes that are to be transferred. the value in this register is decremented with each bus master pci write operation until the transfer count reaches zero. upon reaching zero, the transfer operation ceases and an interrupt may be optionally generated to ei- ther the pci or add-on bus interface. transfers which are not whole multiples of dwords in size result in a partial word ending cycle. this partial word ending cycle is possible since all bus master trans- fers for this controller are required to begin on a dword boundary. 31 0 25 bit value transfer count in bytes (r/w) reserved = o's (ro) 26 00 figure 6. add-on controlled bus master write transfer count register
5-75 add-on bus operation registers S5935 add-on controlled bus master read transfer count register (mrtc) register name: master read transfer count add-on address offset: 5ch power-up value: 00000000h attribute: read/write size: 32 bits this register is only accessible when add-on initiated bus mastering is enabled. the master read transfer count register is used to convey to the pci controller the actual number of bytes that are to be transferred. the value in this register is decremented with each bus master pci read operation until the transfer count reaches zero. upon reaching zero, the transfer operation ceases and an interrupt may be optionally generated to ei- ther the pci or add-on bus interface. transfers which are not whole multiples of dwords in size result in a partial word ending cycle. this partial word ending cycle is possible since all bus master trans- fers for this controller are required to begin on a dword boundary. 31 0 25 bit value transfer count in bytes (r/w) reserved = 0's (ro) 26 00 figure 7. add-on controlled bus master read transfer count register
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6-77 initialization S5935 initialization all pci bus agents and bridges are required to imple- ment pci configuration registers. when multiple pci devices are present, these registers must be unique to each device in the system. the specified pci procedure for uniquely selecting a devices con- figuration space involves a dedicated signal, called idsel, connected to each motherboard pci bus de- vice and pci slot. the host executes configuration cycles after reset to each device on the pci bus. the configuration regis- ters provide information on pci agent operation and memory or i/o space requirements. these allow the pci bios to enable the device and locate it within system memory or i/o space. after a pci reset, the S5935 can be configured for a specific application by downloading device setup in- formation from an external non-volatile memory into the device configuration registers. the S5935 can also be used in a default configuration, with no external boot device. when using a non-volatile boot memory to customize operation, 64 bytes are required for S5935 setup in- formation. the rest of the boot device may be used to implement an expansion bios, if desired. some of the setup information is used to initialize the S5935 pci configuration registers, other information is not downloaded into registers, but is used to define S5935 operation (fifo interface, pass-thru opera- tion, etc.). pci reset immediately following the assertion of the pci rst# signal, the add-on reset output sysrst# is as- serted. immediately following the deassertion of rst#, sysrst# is deasserted. the add-on reset output may be used to initialize state machines, reset add-on microprocessors, or reset other add-on logic devices. all S5935 operation registers and configuration registers are initialized to their default states at re- set. the default values for the configuration regis- ters may be overwritten with the contents of an external nv boot memory during device initialization, allowing a custom device configuration. configuration accesses by the host cpu to the S5935 produce pci bus wait states until one of the following events oc- curs: ? the S5935 identifies that there is no valid boot memory (and default configuration register values are used). ? the S5935 finishes downloading all configura- tion information from a valid boot memory. loading from byte-wide nv memories the snv input on the S5935 indicates what type of external boot-load device is present (if any). if snv is tied low, a byte-wide nv memory is assumed. in this case, immediately after the pci bus reset is deasserted, the address 0040h is presented on the nv memory interface address bus ea[15:0]. eight pci clocks later (240 ns at 33 mhz), data is read from the nv memory data bus eq[7:0] and address 0041h is presented. after an additional eight pci clocks, data is again read from eq7:0. if both accesses read are all ones (ffh), it implies an illegal vendor id value, and the external nv memory is not valid or not present. in this situation, the amcc default configu- ration values are used. if either of the accesses to address 0040h and 0041h contain zeros (not ffh), the next accesses are to locations 0050h, 0051h, 0052h, and 0053h. at these locations, the data must be c0h (or c1h or c2h), ffh, e8h, and 10h, respectively, for the external nv memory to be valid. once a valid external nv memory has been recognized, it is read, sequentially, from location 0040h to 007fh. the appropriate data is loaded into the pci configuration registers as de- scribed in chapter 4. some of the boot device data is not downloaded into configuration registers, but is used to enable features and configure S5935 opera- tion. upon completion of this procedure, the boot- load sequence terminates and pci configuration accesses to the S5935 are acknowledged with the pci target ready (trdy#) output. table 1 lists the required nv memory contents for a valid configuration nv memory device. ?
6-78 initialization S5935 loading from serial nv memories snv tied high indicates that a serial nv memory (or no external device) is present. when serial nv memo- ries are used, data transfer is performed through a two-wire, bidirectional data transfer protocol as de- fined by commercial serial eeprom/flash offerings. these devices have the advantages of low pin counts, small package size, and economical price. a serial nv memory is considered valid if the first serial accesses contain the correct per-byte acknowl- edgments (see figure 3). if the serial per-byte ac- knowledgment is not observed, the S5935 determines that no external serial nv memory is present and the amcc default configuration register values are used. two pins are used to transfer data between the S5935 pci controller and the external serial memory: a serial clock pin, scl, and a serial data pin, sda. the serial clock pin is an output from the S5935, and the serial data pin is bidirectional. the serial clock is derived by dividing the pci bus clock by 512. this means that the frequency of the serial clock is ap- proximately 65 khz for a 33-mhz pci bus clock. note: when a serial boot device is used, ea9 is de- fined as a scl divide by control pin. if ea9 = 1 then scl = pclk/512 if ea9 = 0 then scl = pclk/8 this pin should be pulled high. table 1. valid external boot memory contents address 0040h-41h 0050h 0051 0052h 0053h data not ffffh c2h, c1h or c0h ffh e8h 10h notes this is the location that the s5933 pci controller will load a customized vendor id. (ffffh is an illegal vendor id.) this is the least significant byte of the region which initializes the base address register #0 of the s5933 configuration register (section 3.11). a value of c1h assigns the 16 dword locations of the pci operation registers into i/o space, a value of c0h defines memory space, a value of c2h defines memory space below 1 mbyte. required. required. required. communications with the serial memory involve sev- eral clock transitions. a start event signals the beginning of a transaction and is immediately fol- lowed by an address transfer. each address/data transfer consists of 8 bits of information followed by a 1-bit acknowledgment. when the exchange is com- plete, a stop event is issued. figure 1 shows the unique relationship defining both a start and stop event. figure 2 shows the required timing for ad- dress/data with respect to the serial clock. for random accesses, the sequence involves one clock to define the start of the sequence, eight clocks to send the slave address and read/write command, followed by a one-clock acknowledge, and so on. fig- ure 3 shows the sequence for a random write access requiring 29 serial clock transitions. at the clock speed for the S5935, this corresponds to one byte of data transferred approximately every 0.5 milliseconds. read accesses may be either random or sequential. ran- dom read access requires a dummy write to load the word address and require 39 serial clock transitions. figure 4 shows the sequence for a random byte read. to initialize the S5935 controllers pci configuration registers, the smallest serial device necessary is a 128 x 8 organization. although the S5935 controller only requires 64 bytes, these bytes must begin at a 64-byte address offset (0040h through 007fh). this offset constraint permits the configuration image to be shared with a memory containing expansion bios code and the necessary preamble to identify an ex- pansion bios. the largest serial device which may be used is 2 kbytes.
6-79 initialization S5935 figure 1. serial interface definition of start and stop scl sda start bit stop bit figure 2. serial interface clock/data relationship data stable data stable data change scl sda figure 3. serial interface byte access write slave address data 1010 word address * s t a r t a c k a c k a c k r/w 0 s t o p figure 4. serial interface byte access read slave address 1010 word address s t a r t a c k a c k r/w 0 data * a c k 1 slave address 1010 s t a r t a c k r/w s t o p
6-80 initialization S5935 pci bus configuration cycles cycles beginning with the assertion idsel and frame# along with the two configuration command states for c/be[3:0] (configuration read or write) ac- cess an individual devices configuration space. dur- ing the address phase of the configuration cycle just described, the values of ad0 and ad1 identify if the access is a type 0 configuration cycle or a type 1 configuration cycle. type 0 cycles have ad0 and ad1 equal to 0 and are used to access pci bus agents. type 1 configuration cycles are intended only for bridge devices and have ad0 as a 1 with ad1 as a 0 during the address phase. the S5935 pci device is a bus agent (not a bridge) and responds only to a type 0 configuration ac- cesses. figure 5 depicts the state of the ad bus during the address phase of a type 0 configuration access. the S5935 controller does not support the multiple function numbers field (ad[10:8]) and only responds to the all-zero function number value. the configuration registers for the S5935 pci control- ler can only be accessed under the following conditions: ? idsel high (pci slot unique signal which identifies access to configuration registers) along with frame# low. ? address bits a0 and a1 are 0 (identifies a type 0 configuration access). ? address bits a31-a11 are ignored. ? address bits a8, a9, and a10 are 0 (function number field of zero supported). ? command bits, c/be[3:0]# must identify a configuration cycle command (101x). figure 6 describes the signal timing relationships for configuration read cycles. figure 7 describes configu- ration write cycles. figure 5. pci ad bus definition during a type 0 configuration access function number reserved register number 00 31 11 10 8 7 2 1 0 type 0 00xxxxxx - internal register address (device id, etc.) only 000 value supported by this device.
6-81 initialization S5935 figure 6. type 0 configuration read cycles figure 7. type 0 configuration write cycles pci clock frame # ad [31:0] c/be [3:0]# irdy# trdy# idsel devsel# address (i) (i) (i) (i) (t) (i) (t) (t) data byte enables config. read cmd 1 2 3 4 note select condition if frame # still asserted during clock 2, controller asserts stop# during 3 driven by controller during clock 3 driven by controller during clocks 2,3 +4 driven by controller during clocks 2,3 +4 (i) = driven by initiator (t) = driven by target pci clock frame # ad [31:0] c/be [3:0]# irdy# trdy# idsel devsel# address data byte enables config write cmd 1 2 3 4 note select condition frame # deasserted in clock 2, signifies only one data phase driven by controller during clocks 2+3 driven by controller during clocks 2+3 (t) (i) (t) (i) (i) (i) (i) (i) = driven by initiator (t) = driven by target
6-82 initialization S5935 expansion bios roms this section provides an example of a typical pc- compatible expansion bios rom. address offsets 0040h through 007fh represent the portion of the external nv memory used to boot-load the S5935 controller. whether the expansion rom is intended to be executable code is determined by the contents of the first three locations (starting at offset 0h) and a byte checksum over the defined length. the defined length is specified in the byte at address offset 0002h. table 2 lists each field location by its address offset, its length, its value, and description. table 2. pc compatible expansion rom byte byte binary offset length value description example 0h 1 55h bios rom signature byte 1 55h 1h 1 aah bios rom signature byte 2 aah 2h 1 var. length in multiples of 512 bytes 01h 3h 4 var. entry point for init function. 7h-17h 17h var. reserved (application unique data) 18h-19h 2 var. pointer to pci data structure (see table 3) 20h-3fh 32h var user-defined the following represents the boot-load image for the S5935 controllers pci configuration register : 40h 2 [your vendor id] 10e8h 42h 2 [your device id] 4750h 44h 1 not used 45h 1 [bus master config.] 80h 46h 2 not used 48h 1 [your revision id] 00h 49h 3 [your class code] ff0000h 4ch 1 not used 4dh 1 [your latency timer #] 00h 4eh 1 [your header type] 00h 4fh 1 [self-test if desired] 80h or 00h 50h 1 c0h, c1h or c2h c0h, c1h or c2h 51h 1 ffh ffh 52h 1 e8h e8h 53h 1 10h 10h 54h 4 [base addr. #1] xxxxxxxxh 58h 4 [base addr. #2] xxxxxxxxh 5ch 4 [base addr. #3] xxxxxxxxh 60h 4 [base addr. #4] xxxxxxxxh 64h 4 [base addr. #5] xxxxxxxxh
6-83 initialization S5935 byte byte binary offset length value description example 68h 8 not used 70h 4 [expansion rom base addr.] (example shows 32k bytes) ffff8001h 74h 8 not used 7ch 1 [interrupt line] 0ch 7dh 1 [interrupt pin] 01h 7eh 1 [min-grant] 00h 7fh 1 [max_lat] 00h 80h application specific (1ffh), or (2ffh), or (3ffh), etc. byte checksum, location dependent on value for length field at offset 0002h. table 2. pc compatible expansion rom (continued) a 16-bit pointer at location 18h of the pc expansion rom identifies the start offset of the pci data struc- ture. the pci data structure is shown in table 3 and contains various vendor, product, and program evolu- tions. if a valid external nv memory is identified by the S5935, the pci data structure is used to config- ure the S5935. the pci data structure is not neces- sary for this device to operate. if no external nv memory is implemented, the S5935 boots with the default configuration values. byte byte binary offset length value description 0h 4 pcir signature, the ascii string pcir where p is at offset 0, c at offset 1, and so on. 4h 2 var. vendor identification 6h 2 var. device identification 8h 2 var. pointer to vital product data ah 2 var. pci data structure length (starts with signature field) ch 1 var. pci data structure revision (=0 for this definition) dh 3 var. class code 10h 2 var. image length 12h 2 var. revision level 14h 1 var. code type 15h 1 var. indicator (bit d7=1 signifies last image) 16h 2 0000h reserved table 3. pci data structure note: if a serial bios rom is used, the access time for large serial devices should be considered, since it may cause a lengthy system delay during initializa- tion. for example, a 2-kbyte serial device takes about 1 second to be read. many systems, even when bios roms are ultimately shadowed into sys- tem ram, may read this memory space twice (once to validate its size and checksum, and once to move it into ram). execution directly from a serial bios rom, although possible, may be unacceptably slow.
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7-85 pci bus interface S5935 pci bus interface this section describes the various events which oc- cur on the S5935 pci bus interface. since the S5935 controller functions as both a target (slave) and an initiator (master), signal timing detail is given for both situations this section presents the signal relation- ships involved in performing basic read or write trans- fers on the pci bus and also describes the different ways these cycles may complete. pci bus transactions because the pci bus has multiplexed address/data pins, ad[31:0], each pci bus transaction consists of two phases: address and data. an address phase is defined by the clock period when the signal frame# transitions from inactive (high) to active (low). during the address phase, a bus command is also driven by the initiator on signal pins c/be[3:0]#. if the command indicates a pci read, the clock cycle following the ad- dress phase is used to perform a bus turn-around cycle. a turn-around cycle is a clock period in which the ad bus is not driven by the initiator or the target device. this is used to avoid pci bus contention. for a write command, a turn-around cycle is not needed, and the bus goes directly from the address phase to the data phase. all pci bus transactions consist of an address phase (described above), followed by one or more data phases. the address phase is only one pci clock long and the bus cycle information (address and command) is latched internally by the S5935. the number of data phases depends on how many data transfers are de- sired or are possible with a given initiator-target pair. a data phase consists of at least one pci clock. frame# is deasserted to indicate that the final data phase of a pci cycle is occurring. wait states may be added to any data phase (each wait state is one pci clock). the pci bus command presented on the c/be[3:0]# pins during the address phase can represent 16 pos- sible states. table 1 lists the pci commands and identi- fies those which are supported by the S5935 controller as a target and those which may be produced by the S5935 controller as an initiator. a yes in the sup- ported as target column in table 1 indicates the S5935 controller asserts the signal devsel# when that command is issued along with the appropriate pci ad- dress. two commands are supported by the S5935 controller as an initiator: memory read and memory write. the completion or termination of a pci cycle can be signaled in several ways. in most cases, the comple- tion of the final data phase is indicated by the asser- tion of ready signals from both the target (trdy#) and initiator (irdy#) while frame# is inactive. in some cases, the target is not be able to continue or support a burst transfer and asserts the stop# sig- nal. this is referred to as a target disconnect. there are also cases where an addressed device does not exist, and the signal devsel# never becomes ac- tive. when no devsel# is asserted in response to a pci cycle, the initiator is responsible for ending the cycle. this is referred to as a master abort. the bus is returned to the idle phase when both frame# and irdy# are deasserted. table 1. supported pci bus commands supported supported c/be[3:0]# command type as target as initiator 0000 interrupt acknowledge no no 0001 special cycle no no 0010 i/o read yes no 0011 i/o write yes no 0100 reserved no no 0101 reserved no no 0110 memory read yes yes 0111 memory write yes yes 1000 reserved no no 1001 reserved no no 1010 configuration read yes no 1011 configuration write yes no 1100 memory read multiple yes 1 no 3 1101 reserved no no 1110 memory read line yes 1 no 1111 memory write & invalidate yes 2 no 1. memory read multiple and read line are treated as memory reads. 2. memory write & invalidate commands are treated as memory writes. 3. must be enabled by bit 15 mcsr. ?
7-86 pci bus interface S5935 pci burst transfers the pci bus, by default, expects burst transfers to be executed. to successfully perform a burst transfer, both the initiator and target must order their burst address sequence in an identical fashion. there are two different ordering schemes: linear address incrementing and 80486 cache line fill sequencing. the exact ordering scheme for a bus transaction is defined by the state of the two least significant ad lines during the address phase. the decoding for these lines is shown below: ad[1:0] burst order 0 0 linear sequence 0 1 reserved 1 0 cacheline wrap mode 1 1 reserved the S5935 supports both the linear and the cache line burst ordering. when the S5935 controller is an initiator, it always employs a linear ordering. some accesses to the S5935 controller (as a target) can not be burst transfers. for example, the S5935 does not allow burst transfers when accesses are made to the configuration or operation registers (in- cluding the fifo as a target). attempts to perform burst transfers to these regions cause stop# to be asserted during the first data phase. the S5935 com- pletes the initial data phase successfully, but assert- ing stop# indicates that the next access needs to be a completely new cycle. accesses to memory or i/ o regions defined by the base address registers 1-4 may be bursts, if desired. pci read transfers the S5935 responds to pci bus memory or i/o read transfers when it is selected (target). as a pci bus initiator, the S5935 controller may also produce pci bus memory read operations. figure 1 depicts the fastest burst read transfer pos- sible for the pci bus. the timings shown in figure 1 are representative of the S5935 as a pci initiator with a fast, zero-wait-state memory target. the signals driven by the S5935 during the transfer are frame#, c/be[3:0]#, and irdy#. the signals driven by the target are devsel# and trdy#. ad[31:0] are driven by both the target and initiator during read transactions (only one during any given clock). clock period 2 is a required bus turn-around clock which ensures bus contention between the initiator and tar- get does not occur. targets drive devsel# and trdy# after the end of the address phase (boundary of clock periods 1 and 2 of figure 1). trdy# is not driven until the target can provide valid data for the pci read. when the S5935 becomes the pci initiator, it attempts to per- form sustained zero-wait state burst reads until one of the following occurs: ? the memory target aborts the transfer ? pci bus grant (gnt#) is removed ? the pci to add-on fifo becomes full ? a higher priority (add-on to pci) S5935 transfer is pending (if programmed for priority) ? the read transfer byte count reaches zero ? bus mastering is disabled from the add-on interface figure 1. zero wait state burst read pci bus transfer (S5935 as initiator) 12 3 45 pci clock frame # ad [31:0] c/be [3:0]# irdy# trdy# devsel# address data (2) data (3) (t) (t) (t) data (1) byte en (2) byte en (3) (i) = driven by initiator (t) = driven by target byte enables (1) bus command (i) (t) (i) (i) (i) (t) 6
7-87 pci bus interface S5935 read accesses from the S5935 operation registers (S5935 as a target) are shown in figure 2. the S5935 conditionally asserts stop# in clock period 3 if the initiator keeps frame# asserted during clock period 2 with irdy# asserted (indicating a burst is being attempted). wait states may be added by the initiator by not asserting the signal irdy# during clock 3 and beyond. if frame# remains asserted, but irdy# is not asserted, the initiator is just adding wait states, not necessarily attempting a burst. there is only one condition where accesses to S5935 operation registers do not return trdy# but do as- sert stop#. this is called a target-initiated termina- tion or target disconnect and occurs when a read attempt is made to an empty S5935 fifo. the asser- tion of stop# without the assertion of trdy# indi- cates that the initiator should retry the operation later. when burst read transfers are attempted to the S5935 operation registers, stop# is asserted during the first data transfer to indicate to the initiator that no further transfers (data phases) are possible. this is a target-initiated termination where the target discon- nects after the first data transfer. figure 3 shows the signal relationships during a burst read attempt to the S5935 operation registers. figure 2. single data phase pci bus read of S5935 registers (S5935 as target) frame # ad [31:0] c/be [3:0]# irdy# trdy# devsel# stop# address data byte enables bus command 1 2 3 45 (i) (i) (i) (t) (t) (t) (i) (t) (i) = driven by initiator (t) = driven by target figure 3. burst pci bus read attempt to S5935 registers (S5935 as target) pci clock frame # ad [31:0] c/be [3:0]# irdy# trdy# devsel# stop# address data byte enables (1) 1 2 3 45 (i) (i) (t) (t) (t) (t) (i) (i) be (2) bus command (i) = driven by initiator (t) = driven by target
7-88 pci bus interface S5935 pci write transfers write transfers on the pci bus are one clock period shorter than read transfers. this is because the ad[31:0] bus does not require a turn-around cycle between the address and data phases. when the S5935 is accessed (target), it responds to a pci bus memory or i/o transfers. as a pci initiator, the S5935 controller can also execute pci memory write opera- tions. the timing diagram in figure 4 represents an S5935 initiator pci write operation transferring to a fast, zero-wait-state memory target. the signals driven by the S5935 during the transfer are frame#, ad[31:0], c/be[3:0]#, and irdy#. the signals driven by the target are devsel# and trdy#. as with pci reads, targets assert devsel# and trdy# after the clock defining the end of the address phase (bound- ary of clock periods 1 and 2 of figure 4). trdy# is not driven until the target has accepted the data for the pci write. when the S5935 becomes the pci initiator, it attempts sustained zero-wait state burst writes until one of the following occurs: ? the memory target aborts the transfer ? pci bus grant (gnt# is removed) ? the add-on to pci fifo becomes empty ? a higher priority (pci to add-on) S5935 transfer is pending (if programmed for priority) ? the write transfer byte count reaches zero ? bus mastering is disabled from the add-on interface write accesses to the S5935 operation registers (S5935 as a target) are shown in figure 5. here, the S5935 asserts the signal stop# in clock period 3. stop# is asserted because the S5935 supports fast, zero-wait-state write cycles but does not support burst writes to operation registers. wait states may be added by the initiator by not asserting the signal irdy# during clock 2 and beyond. there is only one condition where writes to S5935 operation registers do not return trdy# (but do assert stop#). this is called a target-initiated termination or target discon- nect and occurs when a write attempt is made to a full S5935 fifo. as with the read transfers, the as- sertion of stop# without the assertion of trdy# indicates the initiator should retry the operation later. pci clock frame # ad [31:0] c/be [3:0]# irdy# trdy# devsel# address data 1 byte en 1 1 2 3 45 (i) (i) (t) (t) (i) (i) byte en 3 byte en 2 data 2 data 3 * bus command = memory write data transfer #1 data transfer #2 data transfer #3 6 bus command* (i) = driven by initiator (t) = driven by target figure 4. zero wait state burst write pci bus transfer (S5935 as initiator)
7-89 pci bus interface S5935 master-initiated termination occasionally, a pci transfer must be terminated by the initiator. typically, the initiator terminates a trans- fer upon the successful completion of the transfer. sometimes, the initiators bus mastership is relin- quished by the bus arbiter (gnt# is removed), often because another device requires bus ownership. this is called initiator preemption and is discussed in later sections. when the S5935 is an initiator and does not observe a devsel# response to its assertion of frame#, it terminates the cycle (master abort). normal cycle completion a successful data transfer occurs when both the ini- tiator and target assert their respective ready signals, irdy# and trdy#. the last data phase is indicated by the initiator when frame# is deasserted during a data transfer. a normal cycle completion occurred if the target does not assert stop#. figure 6 shows the signal relationships defining a normal transfer completion. figure 6. master-initiated, normal completion (S5935 as either target or initiator) figure 5. single data phase pci bus write of S5935 registers (S5935 as target) pci clock frame # irdy# trdy# devsel# 1 2 3 (t) (t) (i) (t) normal completion (i) (i) = driven by initiator (t) = driven by target stop# pci clock frame # ad [31:0] c/be [3:0]# irdy# trdy# devsel# stop# address data 1 byte en 1 bus command 1 2 3 45 (i) (i) (t) (t) (i) (i) byte en 2 data 2 data transfer #1 no data transferred 6 (t) if burst attempt (i) = driven by initiator (t) = driven by target
7-90 pci bus interface S5935 initiator preemption a pci initiator (bus master) is said to be preempted when the system platform deasserts the initiators bus grant signal, gnt#, while it still requests the bus (req# asserted). this situation occurs if the initiators latency timer expires and the system plat- form (bus arbitrator) has a bus master request from another device. the S5935 master latency timer register controls the S5935 responsiveness to the re- moval of a bus grant (preemption). the presence of a master latency timer register can cause two pre- emption situations: 1) removal of gnt# when the latency timer is non-zero (S5935 is guaranteed to still own the bus). 2) removal of the gnt# after the latency timer has expired. the first situation is depicted in figure 7, when the latency timer has not expired. preemption with a zero or expired latency timer is shown in figure 8. figure 7. master initiated termination due to preemption and latency timer active (S5935 as master) pci clock gnt # frame irdy# trdy# s5933 latency timer 1 2 3 (t) (i) preemption data transferred (i) 5 4 data transferred data transferred data transferred 6 =3 =2 =1 =0 timeout sensed (i) = driven by initiator (t) = driven by target figure 8. master initiated termination due to preemption and latency timer expired (S5935 as master) pci clock gnt # frame irdy# trdy# latency timer 1 2 3 (t) (i) preemption data transferred (i) = 0 = 1 5 4 (i) = driven by initiator (t) = driven by target s5933
7-91 pci bus interface S5935 master abort pci accesses to nonexistent or disabled targets never observe devsel# being asserted. in this situ- ation, it is necessary for the initiator to abort the transaction (master abort). as an initiator, S5935 waits for six clock periods after asserting frame# to determine whether a master abort is required. these six clock periods allow slow targets, which may re- quire several bus clocks before being able to assert devsel#, to respond. it is also possible a pci bridge device is present which employs subtractive decoding. a device which does a subtractive decode asserts devsel#, claiming the cycle, when it sees that no other device has asserted it three clocks after the address phase. if devsel# is not asserted, the S5935 deasserts frame# (if asserted) upon the sixth clock period (figure 9). irdy# is deasserted by the S5935 during the next clock. the occurrence of a master abort causes the S5935 to set bit 13 (master abort) of the pci status register, indicating an error condition. target-initiated termination there are situations where the target may end a transfer prematurely. this is called target-initiated termination. target terminations fall into three cat- egories: disconnect, retry, and target abort. only the disconnect termination completes a data transfer. figure 9. master abort, no response pci clock frame # irdy# trdy# devsel# 1 2 3 4 5 fast device medium device slow device bridge device (subtractive decode) 67 8 (i) = driven by initiator (t) = driven by target (t) (t) (i) (i)
7-92 pci bus interface S5935 target disconnects there are many situations where a target may dis- connect. slow responding targets may disconnect to permit more efficient (faster) devices to be accessed while they prepare for the next data phase, or a tar- get may disconnect if it recognizes that the next data phase in a burst transfer is out of its address range. a target disconnects by asserting stop#, trdy#, and devsel# as shown in figures 10a and 10b. the initiator in figure 10a responds to the disconnect condition by deasserting frame# on the following clock but does not complete the data transfer until irdy# is asserted. this situation can only occur when the S5935 is a target. when the S5935 is an initiator, irdy# is always asserted during the data phase (no initiator wait states). the timing diagram in figure 10b applies to the S5935 as either a target disconnecting or an initiator with its target performing a disconnect. the S5935 performs a target discon- nect if a burst access is attempted to the pci opera- tion registers. figure 10b. target disconnect example 2 (irdy# asserted) figure 10a. target disconnect example 1 (irdy# deasserted) pci clock frame # irdy# trdy# stop# devsel# 1 2 3 data transferred target disconnect identified (t) (t) (t) (i) (i) (i) = driven by initiator (t) = driven by target pci clock frame # irdy# trdy# stop# devsel# 1 2 3 data transferred target disconnect signaled, data transferred (t) (t) (t) (i) (i) (i) = driven by initiator (t) = driven by target
7-93 pci bus interface S5935 target requested retries when the S5935 fifo registers are accessed (S5935 as a target) and data is unavailable (empty fifo) for read transfers or cannot be accepted for write transfers (full fifo), the S5935 immediately ter- minates the cycle by requesting a retry. the S5935 also initiates a retry for pass-thru writes where the add-on has not completed the preceding pass-thru write by asserting ptrdy#, and for pass-thru reads where the add-on cannot supply data within 8 pci clocks (16 clocks for the first data phase of a burst). a retry is requested by a target asserting both stop# and devsel# while trdy# is deasserted. figure 11 shows the behavior of the S5935 when performing a target-initiated retry. target aborts a target abort termination represents an error condi- tion where no number of retries will produce a suc- cessful target access. a target abort is uniquely identified by the target deasserting devsel# and trdy# while stop# is asserted. when a target per- forms an abort, it must also set bit 11 of its pci status register. the S5935 configuration and opera- tion registers never respond with a target abort when accessed. if the S5935 encounters this condition when operating as a pci initiator, the S5935 sets bit 12 (received target abort) in the pci status register. figure 12 depicts a target abort cycle. target termination types are summarized in table 2. termination devsel# stop# trdy# comment disconnect on on on data is transferred. transaction needs to be re-initiated to complete. retry on on off data was not transferred. transaction should be tried later. abort off on off data was not transferred. fatal error. table 2. target termination types figure 11. target-initiated retry pci clock frame # irdy# trdy# stop# devsel# 1 2 3 initiator sequences irdy# + frame# to return to idle state 45 target retry signaled (t) (t) (t) (i) (i) (i) = driven by initiator (t) = driven by target
7-94 pci bus interface S5935 figure 12. target abort example figure 13. pci bus arbitration and S5935 bus ownership example s5933 req# "other" req# s5933 gnt# "other" gnt# frame# ad[31:0] irdy# trdy# idle s5933 transaction idle (turn- around) "other", preempting master transaction s5933 transaction(s) idle (turn- around) 1 2 34 56 7 89 address data address data address data (i) = driven by initiator (t) = driven by target pci clock frame # irdy# trdy# stop# devsel# 1 2 3 target abort identified (t) (t) (t) (i) (i) (i) = driven by initiator (t) = driven by target
7-95 pci bus interface S5935 pci bus mastership when the S5935 requires pci bus mastership, it pre- sents a request via the req# signal. this signal is connected to the systems pci bus arbiter. only one initiator (bus master) may control the pci bus at a given time. the bus arbiter determines which initiator is given control of the bus. control is granted to a requesting device by the arbiter assert- ing that devices grant signal (gnt#). each req#/ gnt# signal pair is unique to a given pci agent. after asserting req#, the S5935 assumes bus own- ership on the first pci clock edge where its gnt# input is asserted along with frame# and irdy# deasserted (indicating no other device is generating pci bus cycles). once ownership is established by the S5935, it maintains ownership as long as the arbiter keeps its gnt# asserted. if gnt# is deasserted, the S5935 completes the current trans- action. the S5935 does this by deasserting frame# and then deasserting irdy# upon data transfer. fig- ure 13 shows a sequence where the S5935 is granted ownership of the bus and then is preempted by another master before the S5935 can finish its current transaction. bus mastership latency components it is often necessary for system designers to predict and guarantee that a minimum data transfer rate is sustainable to support a particular application. in the design of a bus mastering application, knowledge of the maximum delay a device might encounter from the time it requests the pci bus to the time in which it is actually granted the bus is desirable. this allows the design to provide adequate data buffering. the pci specification refers to this bus request to grant delay as arbitration latency. once a pci initiator has been granted the bus, the pci specification defines the delay from the grant to the new initiators assertion of frame# as the bus acquisition latency. afterwards, the delay from frame# asserted to target ready (trdy#) asserted is defined as target latency. figure 14 shows a time-line depicting the components of pci bus ac- cess latency. there are numerous configuration variations possible with the pci specification. a system designer can determine whether a bus master can support a criti- cal, timely transfer by establishing a specific configu- ration and by defining these latency values. the S5935, as an initiator, produces the fastest response allowable for its bus acquisition latency (gnt# to frame# asserted). the S5935 also implements the pci master latency timer. once granted the bus, the S5935 is guaranteed ownership for a minimum amount of time defined by the master latency timer. the S5935, as an initiator, cannot control the respon- siveness of a particular target nor the bus arbitration delay. the pci specification provides two mechanisms to control the amount of time a master may own the bus. one mechanism is through the master (master- initiated termination). the other is by the target and is achieved through a target-initiated disconnect. bus arbitration although the pci specification defines the condition that constitutes bus ownership, it does not provide rules to be used by the systems pci bus arbiter in deciding which master is to be granted the pci bus next. the arbitration priority scheme implemented by a system may be fixed, rotational, or custom. the arbitration latency is a function of the system, not the S5935. figure 14. pci bus access latency components bus access latency req# asserted gnt# asserted frame# asserted trdy# asserted --arbitration latency-- --bus acquisition-- latency --target latency--
7-96 pci bus interface S5935 bus acquisition once gnt# is asserted, giving bus ownership to the S5935, the S5935 must wait until the pci bus be- comes idle. this delay is called bus acquisition la- tency and involves the state of the signals frame# and irdy#. the current bus master must complete its current transaction before the S5935 may drive the bus. table 3 depicts the four possible combina- tions of frame# and irdy# with their interpretation. target latency the pci specification requires that a selected target relinquish the bus should an access to that target require more than eight pci clock periods (16 clocks for the first data phase in a burst). slow targets can exist within the pci specification by using the target initiated retry. this prevents slow target devices from potentially monopolizing the pci bus and also allows more accurate estimations for bus access latency. target locking it is possible for a pci bus master to obtain exclusive access to a target (locking) through use of the pci bus signal lock#. lock# is different from the other pci bus signals because its ownership may belong to any bus master, even if it does not currently have ownership of the pci bus. the ownership of lock#, if not already claimed by another master, may be achieved by the current pci bus master on the clock period following the initial assertion of frame#. fig- ure 15 describes the signal relationship for establish- ing a lock. the ownership of lock#, once established, persists even while other bus masters control the bus. ownership can only be relinquished by the master which originally established the lock. table 3. possible combinations of frame# and irdy# frame# irdy# description deasserted deasserted bus idle deasserted asserted the initiator is ready to complete the last data transfer of a transaction. asserted deasserted an initiator has a transaction in progress but is not able to complete the data transfer on this clock. asserted asserted an initiator has a transaction in progress and is able to complete a data transfer. figure 15. engaging the lock# signal pci clock frame # lock # ad[31:0] irdy# trdy# devsel# address data 1 2 3 45 target becomes locked lock mechanism available upon first access lock mechanism available lock established lock maintained bus idle still driven by previous owner (target is locked) 6 (t) (t) (t) (i) (i) (i) (i) = driven by initiator (t) = driven by target
7-97 pci bus interface S5935 targets selected with lock# deasserted during the assertion of frame# (clock period 1 of figure 15), which encounter the assertion of lock# during the following clock (clock period 2 of figure 15) are thereafter considered locked. a target, once locked, requires that subsequent accesses to it deassert lock# while frame# is asserted. figure 16 show a subsequent access to a locked target by the master which locked it. because lock# is owned by a single master, only that master is able to deassert it at the beginning of a transaction (allowing successful access to the locked target). a locked target can only be unlocked during the clock period following the last data transfer of a transaction when the lock# signal is deasserted. an unlocked target ignores lock# when it observes that lock# is already asserted during the first clock period of a transaction. this allows other masters to access other (unlocked) targets. if an access to a locked target is attempted by a master other than the one that locked it, the target responds with a retry request, as shown in figure 17. the S5935 responds to and supports bus masters which lock it as a target. when the S5935 is a bus master, it never attempts to lock a target, but it hon- ors a targets request for retry if that target is locked by another master. figure 16. access to a locked target by its owner pci clock frame # lock # ad [31:0] irdy# trdy# devsel# address data 1 2 3 45 condition which unlocks target locked target identifies owner data (t) (t) (i) (i) (i) (i) = driven by initiator (t) = driven by target figure 17. access attempt to a locked target pci clock frame # lock # ad [31:0] irdy# trdy# devsel# stop# address data 1 2 3 45 causes target retry termination locked target identifies that bus master is not its owner (t) (t) (t) (i) (i) (i) (i) = driven by initiator (t) = driven by target
7-98 pci bus interface S5935 pci bus interrupts the S5935 controller is able to generate pci bus inter- rupts by asserting the pci bus interrupt signal (inta#). inta# is a multisourced, wire-ored signal on the pci bus and is driven by an open drain output on the S5935. the assertion and deassertion of inta# have no fixed timing relationship with respect to the pci bus clock. once the S5935 asserts inta#, it re- mains asserted until the interrupt source is cleared by a write to the interrupt control/status register (intcsr). pci bus parity errors the pci specification defines two error-reporting sig- nals, perr# and serr#. these signals indicate a parity error condition on the signals ad[31:0], c/ be[3:0]#, and par. the validity of the par signal is delayed one clock period from its corresponding ad[31:0] and c/be[3:0]# signals. even parity exists when the total number of ones in the group of signals is equal to an even number. perr# is the error- reporting mechanism for parity errors that occur dur- ing the data phase for all but pci special cycle commands. serr# is the error-reporting mechanism for parity errors that occur during the address phase. the timing diagram in figure 18 shows the timing relationships between the signals ad[31:0], c/ be[3:0]#, par, perr# and serr#. the S5935 asserts serr# if it detects odd parity during an address phase, if enabled. the serr# enable bit is bit 8 in the S5935 pci command regis- ter. the odd parity error condition involves the state of signals ad[31:0] and c/be[3:0]# when frame# is first asserted and the par signal during the following clock. if an error is detected, the S5935 asserts serr# on the following (after par valid) clock. since many targets may observe an error on an ad- dress phase, the serr# signal is an open drain multisourced, wire-ored signal on the pci bus. the S5935 drives serr# low for one clock period when an address phase error is detected. once an serr error is detected by the S5935, the pci status regis- ter bit 14, system error, is set and remains until cleared through software or a hardware reset. the perr# signal is similar to the serr# with two differences: it reports errors for the data phase and is only asserted by the device receiving the data. the S5935 drives this signal (removed from tri-state) when it is the selected target for write transactions or when it is the current master for bus read transac- tions. the parity error conditions are only reflected by the perr# pin if the parity error enable bit (bit 6) of the pci command register is set. upon the detection of a data parity error, the detected parity error bit (bit 15) of the pci status register is set. unlike the perr# signal pin, this status bit sets regardless of the state of the pci command register parity error enable bit. an additional status bit (bit 8) called data parity reported of the pci status register is em- ployed to report parity errors that occur when the S5935 is the bus master. the data parity error re- ported status requires that the parity error enable bit be set in the pci command register. the assertion of perr# occurs two clock periods following the data transfer. this two-clock delay oc- curs because the par signal does not become valid until the clock following the transfer, and an addi- tional clock is provided to generate and assert perr# once an error is detected. perr# is only asserted for one clock cycle for each error sensed. the S5935 only qualifies the parity error detection during the actual data transfer portion of a data phase (when both irdy# and trdy# are asserted). figure 18. error reporting signals pci clock frame ad[31:0] c/be[3:0]# par serr# perr# 12 3 5 4 6 8 7 9 addr data byte enables data be's addr a a aa bb bb cmd cmd read transaction good good good good write transaction b a b a a b error error error error (t) (t) (i) (i) (i) (i) (i) (t) (t) (i) = driven by initiator (t) = driven by target
8-99 add-on bus interface S5935 add-on bus interface this chapter describes the add-on bus interface for the S5935. the S5935 is designed to support con- nection to a variety of microprocessor buses and/or peripheral devices. the add-on interface controls S5935 operation through the add-on operation reg- isters. these registers act as the pass-thru, fifo, non-volatile memory and mailbox interfaces as well as offering control and status information. depending on the register being accessed, the inter- face may be synchronous or asynchronous. to en- hance performance and simplify add-on logic design, some registers allow direct access with a single device input pin. the following sections de- scribe the various interfaces to the pci bus and how they are accessed from the add-on interface. add-on operation register accesses the S5935 add-on bus interface is very similar to that of a memory or peripheral device found in a microprocessor-based system. a 32-bit data bus with individual read and write strobes, a chip enable and byte enables are provided. other add-on interface signals are provided to simplify add-on logic design. accesses to the S5935 registers are done primarily synchronously to bpclk. for S5935 functions that are compatible with an add-on microprocessor inter- face, it is helpful to allow an asynchronous interface, as the processor may not operate at the pci bus clock frequency. add-on interface signals the add-on interface provides a small number of system signals to allow the add-on to monitor pci bus activity, indicate status conditions (interrupts), and allow add-on bus configuration. a standard bus interface is provided for add-on operation register accesses. system signals bpclk and sysrst# allow the add-on interface to monitor the pci bus status. bpclk is a buffered ver- sion of the pci clock. the pci clock can operate from 0 mhz to 33 mhz. sysrst# is a buffered ver- sion of the pci reset signal, and may also be toggled by host application software through bit 24 of the bus master control/status register (mcsr). irq# is the add-on interrupt output. this signal is active low and can indicate a number of conditions. add-on interrupts may be generated from the mail- box or fifo interfaces. the exact conditions which generate an interrupt are discussed in the mailbox and fifo chapters. the interrupt output is deasserted when acknowledged by an access to the add-on interrupt control/status register (aint). all interrupt sources are cleared by writing a one to the corresponding interrupt bit. the mode input on the add-on interface configures the datapath width for the add-on interface. mode low indicates a 32-bit data bus. mode high indicates a 16-bit data bus. for 16-bit operation, be3# is rede- fined as adr1, providing an extra address input. adr1 selects the low or high words of the 32-bit S5935 add-on operation registers. register access signals simple register accesses to the S5935 add-on op- eration registers take two forms: synchronous to bpclk and asynchronous. the following signals are required to complete a register access to the S5935. be[3:0]# byte enable inputs. these S5935 inputs identify valid byte lanes during add-on transac- tions. when mode is set for 16-bit operation, be2# is not defined and be3# becomes adr1. adr[6:2] address inputs. these address pins iden- tify the specific add-on operation register being accessed. when configured for 16-bit operation (mode=1), an additional input, adr1 is avail- able to allow the 32-bit operation registers to be accessed with two 16-bit cycles. rd# read strobe input. wr# write strobe input. select# chip select input. this input identifies a valid S5935 access. dq[31:0] bidirectional data bus. these i/o pins are the S5935 data bus. when configured for 16-bit operation, only dq[15:0] are valid. in addition, there are dedicated signals for fifo ac- cesses (rdfifo# and wrfifo#) and pass-thru ad- dress accesses (ptadr#). these are discussed separately in the fifo and pass-thru sections of this chapter. ?
8-100 add-on bus interface S5935 the internal interfaces of the S5935 allow add-on operation registers to be accessed asynchronous to bpclk (synchronous to the rising edge of the read or write strobe). the exception to this is the add-on general control/status register. this is due to the async nature of fifo status bits changing as the pci bus reads data. for pass-thru operations, the pass- thru data register accesses are synchronous to bpclk to support burst transfers. the fifo port is also accessed synchronous to bpclk. asynchronous register accesses for many add-on applications, add-on logic does not operate at the pci bus frequency. this is especially true for add-ons implementing a microprocessor, which may be operating at a lower (or higher) frequency. fig- ures 1 and 2 show asynchronous add-on operation register accesses. exact ac timings are detailed in the electrical and ac characteristics chapter (chapter 13). for asynchronous reads (figure 1), data is driven on the data bus when rd# is asserted. when rd# is not asserted, the dq[31:0] outputs float. a valid address and valid byte enables must be presented before cor- rect data is driven. rd# has both a minimum inactive time and a minimum active time for asynchronous ac- cesses. for asynchronous writes (figure 2), data is clocked into the S5935 on the rising edge of the wr# input. address, byte enables, and data must all meet setup and hold times relative to the rising edge or wr#. wr# has both a minimum inactive time and a mini- mum active time for asynchronous accesses synchronous fifo and pass-thru data register accesses to obtain the highest data transfer rates possible, add-on logic should operate synchronously with the pci clock. the buffered pci clock (bpclk) is pro- vided for this purpose. a synchronous interface with pass-thru mode or the fifo allows data to be trans- ferred at the maximum pci bus bandwidth (132 mbytes/sec) by allowing burst accesses with the add- on interface. the rd# and wr# inputs become en- ables, using bpclk to clock data into and out of registers. this section applies only to synchronous ac- cesses to the fifo (afifo) and pass-thru data (aptd) registers. figures 3 and 4 show single-cycle, synchronous fifo and pass-thru operation register accesses. exact ac timings are detailed in the electrical and ac characteristics chapter. for synchronous reads (figure 3), data is driven onto the data bus when rd# (or rdfifo#) is asserted. when rd# is not asserted, the dq[31:0] outputs float. the address, byte enable, and rd# inputs must meet setup and hold times relative to the rising edge of bpclk. burst reads may be performed by holding rd# low. for synchronous writes (figure 4), data is clocked into the register on the rising edge of bpclk. ad- dress, byte enables, and data must all meet setup and hold times relative to the rising edge or bpclk. burst writes may be performed by holding wr# (or wrfifo#) low. when holding wr# low, data is clocked in on each bpclk rising edge. nv memory accesses through the add-on general control/status register to access nv memory contents through the add-on general control/status register (agcsts), special considerations must be made. internally, all nv memory accesses by the S5935 are synchronized to a divided- down version of the pci bus clock. because of this, if nv memory accesses are performed through the agcsts register, the register access must be synchro- nized to bpclk. the rising edge rd# or wr# is still used to clock data, but these inputs along with the ad- dress and byte enables are synchronized to bpclk. accesses to agcsts for monitoring fifo or mailbox status, etc., may be done asynchronous to bpclk. mailbox bus interface the mailbox register names may need some clarifi- cation. for the add-on interface, an outgoing mail- box refers to a mailbox sending information to the pci bus. an incoming mailbox refers to a mailbox receiving information from the pci bus. an outgoing mailbox on the add-on interface is, internally, the same as the corresponding incoming mailbox on the pci interface and vice-versa.
8-101 add-on bus interface S5935 figure 1. asynchronous add-on operation register read figure 2. asynchronous add-on operation register write be[3:0]# dq[31:0] select# rd# adr[6:2] valid byte enables valid address valid data out be[3:0]# dq[31:0] select# wr# adr[6:2] valid byte enables valid address valid data in
8-102 add-on bus interface S5935 bpclk dq[31:0] rd# rdfifo# select# adr[6:2] be[3:0]# valid 2 valid data out 2 valid 1 valid data out 1 figure 3. synchronous fifo or pass-thru data register read figure 4. synchronous fifo or pass-thru data register write bpclk dq[31:0] wr# wrfifo# select# adr[6:2] be[3:0]# valid 2 valid data in 2 valid 1 valid data in 1
8-103 add-on bus interface S5935 mailbox interrupts mailboxes can be configured to generate add-on in- terrupts (irq#) and/or allow the add-on to generate pci interrupts (inta#). mailbox empty/full status con- ditions be can used to interrupt the add-on or pci host to indicate some action is required. an individual mailbox byte is selected to generate an interrupt when accessed. an outgoing mailbox becoming empty or an incoming mailbox becoming full asserts the interrupt output (if enabled). when used with a serial nv memory boot device, the mailboxes also provide a way to generate pci inter- rupts (inta#) through hardware. when a serial nv memory boot device is used, the device pin functions ea0 - ea8 are redefined. these pins then provide direct, external access to the add-on outgoing mail- box 4, byte 3 (which is also pci incoming mailbox 4, byte 3). fifo bus interface the fifo register on the add-on interface may only be accessed synchronously or asynchronously. lo- cation 45h, bits 6 and 5 in the nv memory boot device must be programmed to a 0 for correct operation. fifo direct access inputs rdfifo# and wrfifo# are referred to as fifo di- rect access inputs. asserting rdfifo# is function- ally identical to accessing the fifo with rd#, select#, be[3:0]#, and adr[6:2]. asserting wrfifo# is functionally identical to accessing the fifo with wr#, select#, be[3:0]#, and adr[6:2]. rd# and wr# must be deasserted when rdfifo# or wrfifo# is asserted, but select# may be as- serted. these inputs automatically drive the address (internally) to 20h and assert all byte enables. the adr[6:2] and be[3:0]# inputs are ignored when us- ing the fifo direct access inputs. rdfifo# and wrfifo# are useful for add-on designs which cas- cade an external fifo into the S5935 fifo or use dedicated external logic to access the fifo. direct access signals always access the fifo as 16- bits or 32-bits, whatever the mode pin is configured for. for 16-bit mode, two consecutive accesses fill or empty the 32-bit fifo register. fifo status signals the fifo status signals indicate to the add-on logic the current state of the S5935 fifo. a fifo status change caused by a pci fifo access is reflected one pci clock period after the pci access is com- pleted (trdy# asserted). a fifo status change caused by an add-on fifo access is reflected im- mediately (after a short propagation delay) after the access occurs. for add-on accesses, fifo status is updated after the rising edge of bpclk for synchro- nous interfaces or after the rising edge of the read or write strobe for asynchronous interfaces. fifo control signals for add-on initiated pci bus mastering, the fifo status reset controls fwc# (add-on to pci fifo clear) and frc# (pci to add-on fifo clear) are available. fwc# and frc# must be asserted for a minimum of one bpclk period to be recognized. these inputs are sampled at the rising edge of bpclk. these inputs should not be asserted unless the fifo is idle. asserting a fifo status reset input during a pci or add-on fifo access results in indeterminate operation. for add-on initiated bus master transfers, amren (add-on bus master read enable) and amwen (add- on bus master write enable) are used, in conjunction with the appropriate fifo status signals, to enable the S5935 to assert its pci bus request (req#). pass-thru bus interface the S5935 pass-thru interface is synchronous. the add-on pass-thru address (apta) and add-on pass-thru data (aptd) registers may be accessed pseudo-synchronously. although bpclk is used to clock data into and out of the pass-thru registers, accesses may be performed asynchronously. for reads, apta or aptd data re- mains valid as long as rd# (or ptadr#) is asserted. a new value is not driven until ptrdy# is asserted by add-on logic. for writes to aptd, data is clocked into the S5935 on every bpclk rising edge, but is not passed to the pci bus until ptrdy# is asserted. ptrdy# must by synchronized to bpclk.
8-104 add-on bus interface S5935 pass-thru status indicators the pass-thru status indicators indicate that a pass- thru access is in process and what action is required by the add-on logic to complete the access. all pass- thru status indicators are synchronous with the pci clock. pass-thru control inputs some pass-thru implementations may require an ad- dress corresponding to the pass-thru data. the add- on pass-thru address register (apta) contains the pci address for the pass-thru cycle. to allow access to the pass-thru address without generating an add- on read cycle, ptadr# is provided. ptadr# is a direct access input for the pass-thru address. assert- ing ptadr# is functionally identical to accessing the pass-thru address register with rd#, select#, be[3:0]#, and adr[6:2]. rd# and wr# must be deasserted when ptadr# is asserted, but select# may be asserted. these inputs automatically drive the address (internally) to 28h and assert all byte enables. the adr[6:2] and be[3:0]# are ignored when using the ptadr# direct access input. when ptadr# is asserted, the contents of the apta register are imme- diately driven onto the add-on data bus. the ptadr# direct access signal accesses the pass-thru address register as 16-bits or 32-bits, whatever the mode pin is configured for. for 16-bit mode, ptadr# only presents the lower 16-bits of the apta register. ptrdy# indicates that the add-on has completed the current pass-thru access. multiple add-on reads or writes may occur to the pass-thru data (aptd) register before asserting ptrdy#. this may be re- quired for 8-bit or 16-bit add-on interfaces using mul- tiple accesses to the 32-bit pass-thru data register. in some cases, the add-on bus may be 32-bits, but logic may require multiple bpclk periods to read or write data. in this situation, accesses may be ex- tended by holding off ptrdy#. ptrdy# must be synchronized to bpclk. non-volatile memory interface the S5935 allows read and write access to the nv memory device used for configuration. reads are necessary during device initialization as configuration information is downloaded into the S5935. if an ex- pansion bios is implemented in the nv memory, the host transfers (shadows) the code into system dram. writes are useful for in-field updates to ex- pansion bios code. this allows software to update the nv memory contents without altering hardware. non-volatile memory interface signals for serial nv memory devices, there are only two signals used to interface with nv memory. scl is the serial clock, and sda is the serial data line. the func- tionality of these signals is described in-detail in the pin description section of this book. the designer does not need to generate the timings for scl and sda. the S5935 automatically performs the correct serial access when programmed for for serial de- vices. for byte-wide nv memory devices, there is an 8-bit data bus (eq7:0), and a 16-bit address bus (ea15:0) dedicated for the nv memory interface. when a serial nv memory is implemented, many of these pins have alternate functions. the S5935 also has read (erd#) and write (ewr#) outputs to drive the oe# and wr# inputs on a byte-wide nv memory. the designer does not need to generate the timings for these outputs. the S5935 automatically performs the read and write accesses when programmed for byte wide de- vices.
8-105 add-on bus interface S5935 accessing non-volatile memory the nv memory, if implemented, can be accessed through the pci interface or the add-on interface. accesses from both the pci side and the add-on side must be synchronous with the pci clock (bpclk for the add-on). accesses to the nv memory from the pci interface are through the bus master control/status register (mcsr) pci operation reg- ister. accesses to the nv memory from the add-on interface are through the add-on general control/sta- tus register (agcsts) add-on operation register. accesses to the mcsr register are from the pci bus and are, therefore, automatically synchronous to the pci clock. accesses to the agcsts register from the add-on side must be synchronous with respect to bpclk. some nv memories may contain expansion rom bios code for use by the host software. during ini- tialization, the expansion bios is located within sys- tem memory. the starting location of the nv memory is stored in the expansion rom base address reg- ister in the S5935 pci configuration registers. a pci read from this region results in the S5935 performing four consecutive byte access to the nv memory de- vice. writes to the nv memory are not allowed by writing to this region. writes to the nv memory must be performed as described below. the S5935 contains two latches within the mcsr register to control and access the nvram. one is an 8 bit latch called the nvram address/data register which is used to hold nvram address and data in- formation. the other is a 3 bit latch called the nvram access control register which is used to direct the address and data information and to control the nvram itself. reading or writing to the nvram is performed through bits d31:29 of this register. these bits are enable and decode controls rather than a command or instruction to be executed. d31 of this register is the primary enable bit which allows all accesses to occur. when written to a 1, d31 enables the decode bits d30 and d29 to direct the data contained in the address/data latch, d23:16, to the low address, high address or data latches. d31 should be thought of as opening a door where as long as d31 = 1, then the door is open for address or data information to be altered. the table on page 5-16 of the S5935 data book shows the d31:29 bit combinations for reading, writing, and loading ad- dress/data information. additionally, d31 doubles as an S5935 status bit. a 1 indicates that the S5935 is currently busy reading or writing to the nvram. a 0 indicates a complete or inactive state. for the examples below, we will assume the S5935 is i/o mapped with a base address of fc00h. these examples will read one byte of the vendor id and write one byte to the vendor id. in fc00h + 3fh (offset of nvram access control register) until d31 = 0 (not busy). out fc00h + 3fh an 80h (cmd to load the low address byte). this sets decode bits and opens door for low address latch. out fc00h + 3eh (offset of address/data register) 40h (the low byte of the address desired) 40h goes into latch but is not latched yet. out fc00h + 3fh an a0h (cmd to load the high address byte). this latches the low address through changing the decode bits and opens the door for the high address latch. out fc00h + 3eh a 00h (the high byte of the address desired). 00h goes into the latch but is not latched yet. out fc00h + 3fh an 00h (inactive cmd). this latches the high address through the disabling d31, closes the door. out fc00h + 3eh data (the data byte to be written). data byte goes into the latch but is not latched yet. out fc00h + 3fh a c0h (cmd to write the data byte). this latches the data byte through changing the decode bits and begins to write nvram data operation. in fc00h + 3fh until d31 = 0 (not busy). out fc00h + 3fh an e0h (cmd to read the address latched). in fc00h + 3fh until d31 = 0 (not busy). in fc00h + 3eh the data. this example will write 1 byte from nvram location 0040h and read it back:
8-106 add-on bus interface S5935 in fc00h + 3fh (offset of nvram access control register) until d31 = 0 (not busy). out fc00h + 3fh an 80h (cmd to load the low address byte). this sets decode bits and opens door for low address latch. out fc00h + 3eh (offset of address/data register) 40h (the low byte of the address desired) 40h goes into latch but is not latched yet. out fc00h + 3fh an a0h (cmd to load the high address byte). this latches the low address through changing the decode bits and opens the door for the high address latch. out fc00h + 3eh a 00h (the high byte of the address desired) 00h goes into latch but is not latched yet. out fc00h + 3fh an e0h (cmd to read nvram data). this latches the high address through changing the decode bits and begins to read the nvram data operation. in fc00h + 3fh until d31 = 0 (not busy). in fc00h + 3eh the data. in fc00h + 3fh (offset of nvram access control register) until d31 = 0 (not busy). out fc00h + 3fh an 80h (cmd to load the low address byte). this sets decode bits and opens the door for low address latch. out fc00h + 3eh (offset of address/data register) 40h (the low byte of the address desired) 40h goes into latch but is not latched yet. out fc00h + 3eh (offset of address/data register) 41h (the low byte of the address desired) 41h goes into latch but is not latched yet. out fc00h + 3fh an a0h (cmd to load the high address byte). this latches the low address through changing the decode bits and opens the door for the high address latch. out fc00h + 3eh 00h (the high byte of the address desired) 00h goes into latch but is not latched yet. out fc00h + 3fh an e0h (cmd to read the address latched). this latches the high address through changing the decode bits and begins the read nvram data operation. in fc00h + 3fh until d31 = 0 (not busy). in fc00h + 3eh the data. notes: 1. latched addresses do not automatically increment after a read or write. they must be loaded with new values. 2. latched addresses remain after reads and writes. it is allowable to only update one address byte for the next access. 3. a processor may perform a one word write to load an address byte and control command simultaneously. this example will read 1 byte from nvram location 0040h: this example will read 1 byte from nvram location 0041h and contains an extra step to demonstrate d31 operation:
8-107 add-on bus interface S5935 timing spec. t = 30 ns read cycle time 8t(max) 240 ns address valid to data valid 7t?0(max) 200 ns address valid to read active t(max) 30 ns read active to data valid 6t?0(max) 170 ns read pulse width 6t(max) 180 ns data hold from read inactive 2 ns memory device requirements for read accesses figure 5. nv memory read operation data valid eq[7:0] (input) ea[15:0] (output) erd# (output) address valid t 35 t 36 t 37 t 39 t 38 t 41 t 40 nv memory device timing requirements for serial nv memory devices, the serial clock output frequency is the pci clock frequency divided by 512. this is approximately 65 khz (with a 33 mhz pci clock). any serial memory device that operates at this frequency is compatible with the S5935. for byte-wide accesses, the S5935 generates the waveforms shown in figures 5 and 6. figure 5 shows an nv memory read operation. figure 6 shows an nv memory write operation. read operations are always the same length. write operations, due to the charac- teristics of reprogrammable nv memory devices, may be controlled through a programming sequence.
8-108 add-on bus interface S5935 timing spec. t = 30 ns write cycle time 8t note 1 address valid to write active t(max) 30 ns data valid to write inactive 6t+10(max) 190 ns data hold from write inactive t(max) 30 ns write pulse width 6t(max) 180 ns write inactive note 2 2 ns memory device requirements for write accesses figure 6. nv memory write operation data valid eq[7:0] (output) ea[15:0] (output) ewr# (output) address valid t 42 t 43 t 44 t 39 t 46 t 45 t 38
9-109 mailbox overview S5935 mailbox overview the S5935 has eight 32-bit mailbox registers. the mail- boxes are useful for passing command and status infor- mation between the add-on and the pci bus. the pci interface has four incoming mailboxes (add-on to pci) and four outgoing mailboxes (pci to add-on). the add- on interface has four incoming mailboxes (pci to add- on) and four outgoing mailboxes (add-on to pci). the pci incoming and add-on outgoing mailboxes are the same, internally. the add-on incoming and pci outgo- ing mailboxes are also the same, internally. the mailbox status may be monitored in two ways. the pci and add-on interfaces each have a mailbox status register to indicate the empty/full status of bytes within the mailboxes. the mailboxes may also be configured to generate interrupts to the pci and/or add-on interface. one outgoing and one incoming mailbox on each interface can be configured to gen- erate inter rupts. functional description figure 1 shows a block diagram of the pci to add-on mailbox registers. add-on incoming mailbox read ac- cesses pass through an output interlock latch. this prevents a pci bus write to a pci outgoing mailbox from corrupting data being read by the add-on. fig- ure 2 shows a block diagram of the add-on to pci mailbox registers. pci incoming mailbox reads also pass through an interlocking mechanism. this pre- vents an add-on write to an outgoing mailbox from corrupting data being read by the pci bus. the fol- lowing sections describe the mailbox flag functionality and the mailbox interrupt capabilities. mailbox register add-on bus "incoming mailbox" select output interlock latch output driver add-on bus mailbox full s q d "o" load enable read enable en en add-on rd# select# empty/full ff q d q d pci bus "outgoing mailbox" selected read enable pci bus interface add-on interface "incoming mailbox" figure 1. block diagram - pci to add-on mailbox register figure 2. block diagram - add-on to pci mailbox register mailbox register pci "incoming mailbox" select output interlock latch add-on bus "outgoing mailbox" wr# select# pci bus "incoming mailbox" register decode of adr[6:2] be[3:0]# mailbox full "o" pci read pulse empty/full ff add-on write pulse selected read pulse en q s d qd qd pci bus interface add-on interface ?
9-110 mailbox overview S5935 mailbox empty/full conditions the pci and add-on interfaces each have a mailbox status register. the pci mailbox empty/full status (mbef) and add-on mailbox empty/full status (ambef) registers indicate the status of all bytes within the mailbox registers. a write to an outgoing mailbox sets the status bits for that mailbox. the byte enables determine which bytes within the mailbox be- come full (and which status bits are set). an outgoing mailbox for one interface is an incoming mailbox for the other. therefore, incoming mailbox status bits on one interface are identical to the corre- sponding outgoing mailbox status bits on the other interface. the following list shows the relationship be- tween the mailbox registers on the pci and add-on interfaces. pci interface add-on interface outgoing mailbox 1 = incoming mailbox 1 outgoing mailbox 2 = incoming mailbox 2 outgoing mailbox 3 = incoming mailbox 3 outgoing mailbox 4 = incoming mailbox 4 incoming mailbox 1 = outgoing mailbox 1 incoming mailbox 2 = outgoing mailbox 2 incoming mailbox 3 = outgoing mailbox 3 incoming mailbox 4 = outgoing mailbox 4 pci mailbox empty/full = add-on mailbox empty/full a write to an outgoing mailbox also writes data into the incoming mailbox on the other interface. it also sets the status bits for the outgoing mailbox and the status bits for the incoming mailbox on the other in- terface. reading the incoming mailbox clears all cor- responding status bits in the add-on and pci mailbox status registers (ambef and mbef). for example, a pci write is performed to the pci out- going mailbox 2, writing bytes 0 and 1 (be0# and be1# asserted). reading the pci mailbox empty/full status register (mbef) indicates that bits 4 and 5 are set. these bits indicate that outgoing mailbox 2, bytes 0 and 1 are full. reading the add-on mailbox empty/ full status register (ambef) shows that bits 4 and 5 in this register are also set, indicating add-on incom- ing mailbox 2, bytes 0 and 1 are full. an add-on read of incoming mailbox 2, bytes 0 and 1 clears the status bits in both the mbef and ambef status registers. to reset individual flags in the mbef and ambef registers, the corresponding byte must be read from the incoming mailbox. the pci and add-on mailbox status registers, mbef and ambef, are read-only. mailbox flags may be globally reset from either the pci interface or the add-on interface. the pci bus master control/status register (mcsr) and the add- on general control/status register (agcsts) each have a bit to reset all of the mailbox status flags. mailbox interrupts the designer has the option to generate interrupts to the pci and add-on interfaces when specific mailbox events occur. the pci and add-on interfaces can each define two conditions where interrupts may be generated. an interrupt can be generated when an incoming mailbox becomes full and/or when an outgo- ing mailbox becomes empty. a specific byte within a specific mailbox is selected to generate the interrupt. the conditions defined to generate interrupts to the pci interface do not have to be the same as the condi- tions defined for the add-on interface. interrupts are cleared through software. for incoming mailbox interrupts, when the specified byte becomes full, an interrupt is generated. the in- terrupt might be used to indicate command or status information has been provided, and must be read. for pci incoming mailbox interrupts, the S5935 as- serts the pci interrupt, inta#. for add-on incoming mailbox interrupts, the S5935 asserts the add-on in- terrupt, irq#. for outgoing mailbox interrupts, when the specified byte becomes empty, an interrupt is generated. the interrupt might be used to indicate that the other in- terface has received the last information sent and more may be written. for pci outgoing mailbox inter- rupts, the S5935 asserts the pci interrupt, inta#. for add-on outgoing mailbox interrupts, the S5935 asserts the add-on interrupt, irq#. add-on outgoing mailbox 4, byte 3 access pci incoming mailbox 4, byte 3 (add-on outgoing mailbox 4, byte 3) does not function exactly like the other mailbox bytes. when an a serial nv memory boot device or no external boot device is used, the S5935 pins ea7:0 are redefined to provide direct ex- ternal access to add-on outgoing mailbox 4, byte 3. ea8 is redefined to provide a load clock which may be used to generate a pci interrupt. the pins are redefined as follows: signal pin add-on outgoing mailbox ea0/emb0 mailbox 4, bit 24 ea1/emb1 mailbox 4, bit 25 ea2/emb2 mailbox 4, bit 26 ea3/emb3 mailbox 4, bit 27 ea4/emb4 mailbox 4, bit 28 ea5/emb5 mailbox 4, bit 29 ea6/emb6 mailbox 4, bit 30 ea7/emb7 mailbox 4, bit 31 ea8/embclk mailbox 4, byte 3 load clock
9-111 mailbox overview S5935 if the S5935 is programmed to generate a pci inter- rupt (inta#), on an add-on write to outgoing mailbox 4, byte 3, a rising edge on embclk generates a pci interrupt. the bits emb7:0 can be read by the pci bus interface by reading the pci incoming mailbox 4, byte 3. these bits are useful to indicate various con- ditions which may have caused the interrupt. when using the S5935 with a byte-wide boot device, the capability to generate pci interrupts with add-on hardware does not exist. in this configuration, pci incoming mailbox 4, byte 3 (add-on incoming mail- box 4, byte 3) cannot be used to transfer data from the add-on - it always returns zeros when read from the pci bus. this mailbox byte is sacrificed to allow the added functionality provided when a byte-wide boot device is not used. bus interface the mailboxes appear on the add-on and pci bus interfaces as eight operation registers. four are out- going mailboxes, four are incoming mailboxes. the mailboxes may be used to generate interrupts to each of the interfaces. the following sections de- scribe the add-on and pci bus interfaces for the mailbox registers. pci bus interface the mailboxes are only accessible with the S5935 as a pci target. the mailbox operation registers do not support burst accesses by an initiator. a pci initiator attempting to burst to the mailbox registers causes the S5935 to respond with a target disconnect with data. pci writes to full outgoing mailboxes overwrite data currently in that the mailbox. pci reads from empty incoming mailboxes return the data that was previ- ously contained in the mailbox. neither of these situa- tions cause a target retry or abort. pci incoming and outgoing mailbox interrupts are en- abled in the interrupt control/status register (intcsr). the mailboxes can generate a pci inter- rupt (inta#) under two conditions (individually en- abled). for an incoming mailbox full interrupt, inta# is asserted on the pci clock rising edge after the add-on mailbox write completes. for an outgoing mailbox empty interrupt, inta# is asserted on the pci clock rising edge after the add-on mailbox read completes (the rising edge of rd#). inta# is deasserted on the next pci clock rising edge after the pci access to clear the mailbox interrupt com- pletes (trdy# deasserted). add-on bus interface the add-on mailbox interface behaves similar to the pci bus interface. add-on writes to full outgoing mailboxes overwrite data currently in that mailbox. pci reads from empty incoming mailboxes return the data that was previously contained in the mailbox. add-on incoming and outgoing mailbox interrupts are enabled in the add-on interrupt control/status reg- ister (aint). the mailboxes can generate the add-on irq# interrupt under two conditions (individually en- abled). for an incoming mailbox full interrupt, irq# is asserted one pci clock period after the pci mailbox write completes (trdy# deasserted). for an outgo- ing mailbox empty interrupt, irq# is asserted one pci clock period after the pci mailbox read com- pletes (trdy# deasserted). irq# is deasserted im- mediately when the add-on clears the mailbox interrupt. when the S5935 is used with a serial nv memory boot device or no external boot device, the device pins ea8:0 are redefined. ea7:0 become emb7:0 data in- puts and ea8 becomes embclk, a load clock. this configuration allows the add-on to generate pci inter- rupts with a low-to-high transition on embclk. the pci incoming mailbox interrupt must be enabled and set for mailbox 4, byte3 in the pci interrupt control/ status register (intcsr). embclk should begin high and be pulsed low, then high to be recognized. the rising edge of embclk generates the interrupt. the rising edge of embclk also latches in the values on emb7:0. the S5935 interrupt logic must be cleared (inta# deasserted) through intcsr before further embclk interrupts are recognized. 8-bit and 16-bit add-on interfaces some add-on designs may implement an 8-bit or 16- bit bus interface. the mailboxes do not require a 32- bit add-on interface. for 8-bit interfaces, the 8-bit data bus may be externally connected to all four bytes of the 32-bit add-on interface (dq 31:24, 23:16, 15:8, 7:0 are all connected). the add-on de- vice reading or writing the mailbox registers may ac- cess all mailbox bytes by cycling through the add-on byte enable inputs. a similar solution applies to 16-bit add-on buses. this solution works for add-ons which always use just 8-bit or just 16-bit accesses. if the mode pin is high, indicating a 16-bit add-on interface, the previous solution may be modified for an 8-bit interface. the difference is that adr1 must be toggled after the first two accesses to steer the S5935 internal data bus to the upper 16-bits of the mailboxes.
9-112 mailbox overview S5935 configuration the pci interface and the add-on interface each have four incoming mailboxes (imbx or aibmx) and four outgoing mailboxes (ombx or aombx) along with a single mailbox status register (mbef or ambef). out- going mailboxes are read/write, incoming mailboxes and the mailbox status registers are read-only. the following sections discuss the registers associ- ated with the mailboxes and accesses required for different modes of mailbox operation. mailbox status every byte in each mailbox has a status bit in the mailbox empty/full status registers (mbef and ambef). writing a particular byte into an outgoing mailbox sets the corresponding status bit in both the mbef and ambef registers. a read of a full byte in a mailbox clears the status bit. the mbef and ambef are read-only. status bits cannot cleared by writes to the status registers. the S5935 allows the mailbox status bits to be reset through software. the bus master control/status (mcsr) pci operation register and the add-on gen- eral control/status (agcsts) add-on operation reg- ister each have a bit to reset mailbox status. writing a 1 to mailbox flag reset bit in the mcsr or the agcsts register immediately clears all bits in the both the mbef and ambef registers. writing a 0 has no effect. the mailbox flag reset bit is write-only. the flag bits should be monitored when transferring data through the mailboxes. checking the mailbox status before performing an operation prevents data from being lost or corrupted. the following se- quences are suggested for pci mailbox operations using status polling (interrupts disabled): reading a pci incoming mailbox: 1) check mailbox status. read the mailbox status register to determine if any information has been passed from the add-on interface. mbef bits 31:16 if a bit is set, valid data is contained in the corresponding mailbox byte. 2) read mailbox(es). read the mailbox bytes which mbef indicates are full. this automatically resets the status bits in the mbef and ambef registers. imbx bits 31:0 mailbox data. writing a pci outgoing mailbox: 1) check mailbox status. read the mailbox status register to determine if information previously written to the mailbox has been read by the add-on interface. writes to full mailbox bytes overwrite data currently in the mailbox (if not already read by the add-on interface). repeat until the byte(s) to be written are empty. mbef bits 15:0 if a bit is set, valid data is contained in the corresponding mailbox byte and has not been read by the add-on. 2) write mailbox(es). write to the outgoing mailbox byte(s). ombx bits 31:0 mailbox data.
9-113 mailbox overview S5935 mailbox operations for the add-on interface are functionally identical. the following sequences are suggested for add-on mailbox operations using status polling (interrupts disabled): reading an add-on incoming mailbox: 1) check mailbox status. read the mailbox status register to determine if any information has been passed from the pci interface. ambef bits 15:0 if a bit is set, valid data is contained in the corresponding mailbox byte. 2) read mailbox(es). read the mailbox bytes which ambef indicates are full. this automatically resets the status bits in the ambef and mbef registers. aimbx bits 31:0 mailbox data. writing an add-on outgoing mailbox: 1) check mailbox status. read the mailbox status register to determine if information previously written to the mailbox has been read by the pci interface. writes to full mailbox bytes overwrite data currently in the mailbox (if not already read by the pci interface). repeat until the byte(s) to be written are empty. ambef bits 31:16 if a bit is set, valid data is contained in the corresponding mailbox byte and has not been read by the pci bus. 2) write mailbox(es). write to the outgoing mailbox byte(s). aombx bits 31:0 mailbox data. mailbox interrupts although polling status is useful, in some cases, polling requires continuous actions by the processor reading or writing the mailbox. mailbox interrupt capabilities are provided to avoid much of the processor overhead required by continuously polling status bits. the add-on and pci interface can each generate interrupts on an incoming mailbox condition and/or an outgoing mailbox condition. these can be individually enabled/disabled. a specific byte in one incoming mailbox and one outgoing mailbox is identified to generate the interrupt(s). the tasks required to setup mailbox interrupts are shown below: enabling pci mailbox interrupts: 1) enable pci outgoing mailbox interrupts. a specific byte within one of the outgoing mailboxes is identi- fied to assert inta# when read by the add-on interface. intcsr bit 4 enable outgoing mailbox interrupts intcsr bits 3:2 identify mailbox to generate interrupt intcsr bits 1:0 identify mailbox byte to generate interrupt 2) enable pci incoming mailbox interrupts. a specific byte within one of the incoming mailboxes is identified to assert inta# when written by the add-on interface. intcsr bit 12 enable incoming mailbox interrupts intcsr bits 11:10 identify mailbox to generate interrupt intcsr bits 9:8 identify mailbox byte to generate interrupt
9-114 mailbox overview S5935 enabling add-on mailbox interrupts: 1) enable add-on outgoing mailbox interrupts. a specific byte within one of the outgoing mailboxes is identified to assert irq# when read by the pci interface. aint bit 12 enable outgoing mailbox interrupts aint bits 11:10 identify mailbox to generate interrupt aint bits 9:8 identify mailbox byte to generate interrupt 2) enable add-on incoming mailbox interrupts. a specific byte within one of the incoming mailboxes is identified to assert irq# when written by the pci interface. aint bit 4 enable incoming mailbox interrupts aint bits 3:2 identify mailbox to generate interrupt aint bits 1:0 identify mailbox byte to generate interrupt with either the add-on or pci interface, these two steps can be performed with a single access to the appropriate register. they are shown separately here for clarity. once interrupts are enabled, the interrupt service routine must access the mailboxes and clear the interrupt source. a particular application may not require all of the steps shown. for instance, a design may only use incoming mailbox interrupts and not require support for outgoing mailbox interrupts. the interrupt service routine tasks are shown below: servicing a pci mailbox interrupt (inta#): 1) identify the interrupt source(s). multiple interrupt sources are available on the S5935. the interrupt service routine must verify that a mailbox generated the interrupt (and not some other interrupt source). intcsr bit 16 pci outgoing mailbox interrupt indicator intcsr bit 17 pci incoming mailbox interrupt indicator 2) check mailbox status. the mailbox status bits indicate which mailbox bytes must be read or written. mbef bits 31:16 full pci incoming mailbox bytes mbef bits 15:0 empty pci outgoing mailbox bytes 3) access the mailbox. based on the contents of mbef, mailboxes are read or written. reading an incoming mailbox byte clears the corresponding status bit in mbef. ombx bits 31:0 pci outgoing mailboxes imbx bits 31:0 pci incoming mailboxes 4) clear the interrupt source. the pci inta# signal is deasserted by clearing the interrupt request. the request is cleared by writing a 1 to the appropriate bit. intcsr bit 16 clear pci outgoing mailbox interrupt intcsr bit 17 clear pci incoming mailbox interrupt
9-115 mailbox overview S5935 servicing an add-on mailbox interrupt (irq#): 1) identify the interrupt source(s). multiple interrupt sources are available on the S5935. the interrupt service routine must verify that a mailbox generated the interrupt (and not some other interrupt source). aint bit 16 add-on incoming mailbox interrupt indicator aint bit 17 add-on outgoing mailbox interrupt indicator 2) check mailbox status. the mailbox status bits indicate which mailbox bytes must be read or written. ambef bits 31:16 empty add-on outgoing mailbox bytes ambef bits 15:0 full add-on incoming mailbox bytes 3) access the mailbox. based on the contents of ambef, mailboxes are read or written. reading an incoming mailbox byte clears the corresponding status bit in ambef. aimbx bits 31:0 add-on incoming mailboxes aombx bits 31:0 add-on outgoing mailboxes 4) clear the interrupt source. the add-on irq# signal is deasserted by clearing the interrupt request. the request is cleared by writing a 1 to the appropriate bit. aint bit 16 clear add-on incoming mailbox interrupt aint bit 17 clear add-on outgoing mailbox interrupt in both cases, step 3 involves accessing the mailbox. to allow the incoming mailbox interrupt logic to be cleared, the mailbox status bit must also be cleared. reading an incoming mailbox clears the status bits. another option for clearing the status bits is to use the mailbox flag reset bit in the mcsr and agcsts registers, but this clears all status bits, not just for a single mailbox or mailbox byte. for outgoing mailbox interrupts, the read of a mailbox register is what generated the interrupt; this ensures the status bits are already clear.
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10-117 fifo overview S5935 fifo overview the S5935 has two internal fifos. one fifo is for pci bus to add-on bus, the other fifo is for add-on bus to pci bus transfers. each of these has eight 32- bit registers. the fifos are both addressed through a single pci/add-on operation register offset, but which internal fifo is accessed is determined by whether the access is a read or write. the fifo may be either a pci target or a pci initia- tor. as a target, the fifo allows a pci bus master to access add-on data. the fifo also allows the S5935 to become a pci initiator. read and write ad- dress registers and transfer count registers allow the S5935 to perform dma transfers across the pci bus. the fifo may act as initiator and a target at different times in the same application. the fifo can be configured to support various add- on bus configurations. fifo status and control signals allow simple cascading into an external fifo, the add- on bus can be 8-, 16-, or 32-bits wide, and data endian conversion is optional to support any type of add-on cpu. pci and add-on interrupt capabilities are available to support bus mastering through the fifo. functional description the S5935 fifo interface allows a high degree of functionality and flexibility. different fifo manage- ment schemes, endian conversion schemes, and ad- vance conditions allow for a wide variety of add-on interfaces. applications may implement the fifo as either a pci target or program it to enable the S5935 to be a pci initiator (bus master). the following sec- tions describe, on a functional level, the capabilities of the S5935 fifo interface. fifo buffer management and endian conversion the S5935 provides a high degree of flexibility for controlling the data flow through the fifo. each fifo (pci to add-on and add-on to pci) has a spe- cific fifo advance condition. for fifo writes, the byte which signifies a location is full is configurable. for fifo reads, the byte which signifies a location is empty is configurable. this ability is useful for trans- ferring data through the fifo with add-ons which are not 32-bits wide. endian conversion may also be performed on data passing through the fifo. fifo advance conditions the specific byte lane used to advance the fifo, when accessed, is determined individually for each fifo interface (pci and add-on). the control bits to set the advance condition are d29:26 of the interrupt control/status register (intcsr) in the pci opera- tion registers (figure 1). the default fifo advance condition is set to byte 0. with the default setting, a write to the fifo with be0# asserted indicates that the fifo location is now full, advancing the fifo pointer to the next location. be0# does not have to be the only byte enable asserted. note, the fifo advance condition may be different for the pci to add-on fifo and the add-on to pci fifo directions. figure 1. intcsr fifo advance and endian control bits intcsr 0 0 1 1 0 no conversion (default) 1 16 bit endian conv. 0 32 bit endian conv. 1 64 bit endian conv fifo advance control pci interface 0 0 byte 0 (default) 0 1 byte 1 1 0 byte 2 1 1 byte 3 fifo advance control add-on interface 0 0 byte 0 (default) 0 1 byte 1 1 0 byte 2 1 1 byte 3 pci to add-on fifo pci add-on dword toggle 0 = bytes 0-3 (default) 1 = byte 4-7 (note1) add-on to pci fifo add-on pci dword toggle 0 = bytes 0-3 (default) 1 = byte 4-7 (note1) note 1: d24 and d25 must be also "1" 31 30 29 28 27 26 25 24 ?
10-118 fifo overview S5935 the configurable fifo advance condition may be used to transfer data to and from add-on interfaces which are not 32-bits wide. for a 16-bit add-on bus, the add-on to pci fifo advance condition can be set to byte 2. this allows a 16-bit write to the lower 16- bits of the fifo register (bytes 0 and 1) and a second write to the upper 16-bits of the fifo register (bytes 2 and 3). the fifo does not advance until the second access. this allows the add-on to operate with 16-bit data, while the pci bus maintains a 32-bit data path. notes: 1. during operation, the intcsr fifo advance condition bits (d29:26) should only be changed when the fifo is empty and is idle on both the add-on and pci interfaces. endian conversion bits d31:30 and d25:24 of the intcsr pci opera- tion register control endian conversion operations for the fifo (figure 1). when endian conversion is per- formed, it affects data passing in either direction through the fifo interface. figures 2a and 2b show 16-bit and 32-bit endian conversion. it is important to note that endian conversion is performed on data be- fore it enters the fifo. this affects the fifo ad- vance condition. example: the fifo is configured to perform 32-bit endian conversion on data, and the fifo advance condition is set to byte 0. byte 3 is written into the fifo (be3# asserted). after the endian conversion, byte 3 becomes byte 0, and the fifo advances. this behavior must be considered when not performing full 32-bit accesses to the fifo. notes: 1. during operation, the intcsr fifo endian conversion bits (d25:24) and 64-bit access bits (d31:30) should only be changed when the fifo is empty and is idle on both the add- on and pci interfaces. figure 2a. 16-bit endian conversion destination d 31-24 d 23-16 d 15-8 d 7-0 byte 3 byte 2 byte 1 byte 0 byte 3 byte 2 byte 1 byte 0 d 31-24 d 23-16 d 15-8 d 7-0 source figure 2b. 32-bit endian conversion destination d 31-24 d 23-16 d 15-8 d 7-0 byte 3 byte 2 byte 1 byte 0 byte 3 byte 2 byte 1 byte 0 d 31-24 d 23-16 d 15-8 d 7-0 source
10-119 fifo overview S5935 64-bit endian conversion because the S5935 interfaces to a 32-bit pci bus, special operation is required to handle 64-bit data endian conversion. figure 2c shows 64-bit endian conversion. the S5935 must know whether the lower 32-bits enter the fifo first or the upper 32-bits enter the fifo first. intcsr d31:30 identify which method is used by the application. these bits toggle after each 32-bit operation to indicate if half or all of a 64-bit data operation has been completed. the initial state of these bits establishes the loading and emptying order for 64-bit data during operation. figure 2c. 64-bit endian conversion destination d 31-24 d 23-16 d 15-8 d 7-0 byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 d 31-24 d 23-16 d 15-8 d 7-0 source byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 slr slr slr slr read order: bytes 3-0 first or bytes 7-4 first see text load order: bytes 3-0 first or, bytes 7-4 first see text
10-120 fifo overview S5935 add-on fifo status indicators the add-on interface implements fifo status pins to indicate the full and empty conditions of the pci to add-on and add-on to pci fifos. these may be used by the add-on to allow data transfers between the fifo and memory, a peripheral, or even a cas- caded external fifo. the rdempty and wrfull status outputs are always available to the add-on. additional status signals are multiplexed with the byte-wide, non-volatile memory interface pins. if the S5935 is configured for add-on initiated bus master- ing, these status signals also become available to the add-on. fifo status is also indicated by bits in the add-on general control/status and bus master con- trol/status registers. the table below lists all fifo status outputs and their functions. signal function rdempty indicates empty condition of the pci to add-on fifo wrfull indicates full condition of the add-on to pci fifo frf indicates full condition of the pci to add-on fifo 1 fwe indicates the empty condition of the add-on to pci fifo 1 1. these signals are only available when a serial non-volatile memory is used and the device is configured for add-on initiated bus mastering. add-on fifo control signals the add-on interface implements fifo control pins to manipulate the S5935 fifos. these may be used by add-on to control data transfer between the fifo and memory, a peripheral, or even a cascaded exter- nal fifo. the rdfifo# and wrfifo# inputs are always available. these pins allow direct access to the fifo without generating a standard add-on reg- ister access using rd#, wr#, select#, address pins and the byte enables. additional control signals are multiplexed with the byte-wide, non-volatile memory interface pins. if a se- rial non-volatile memory is used and the S5935 is configured for add-on initiated bus mastering, these control signals also become available. for pci initi- ated bus mastering, amren, amwen, frc#, and fwc# functionality is always available through bits in the bus master control/status and add-on general control/status registers. the fifo control inputs are listed below. signal function rdfifo# reads data from the pci to add-on fifo wrfifo# writes data into the add-on to pci fifo frc# reset pci to add-on fifo pointers and status indicators 1 fwc# reset add-on to pci fifo pointers and status indicators 1 amren enable bus mastering for add-on initiated pci reads 1 amwen enable bus mastering for add-on initiated pci writes 1 1. these signals are only available when a serial non-volatile memory is used and the S5935 is configured for add-on initiated bus mastering. pci bus mastering with the fifo the S5935 may initiate pci bus cycles through the fifo interface. the S5935 allows blocks of data to be transferred to and from the add-on by specifying a source/destination address on the pci bus and a transfer byte count. this dma capability allows data to be transferred across the pci bus without host cpu intervention. initiating a bus master transfer requires programming the appropriate address registers and transfer byte counts. this can be done from either the pci inter- face or the add-on interface. initiating bus master transfers from the add-on is advantageous because the host cpu does not have to intervene for the S5935 to become a pci initiator. at the end of a transfer the S5935 may generate an interrupt to ei- ther the pci bus (for pci initiated transfers) or add- on interface (for add-on initiated transfers). add-on initiated bus mastering if bit 7 in location 45h of an external serial non-vola- tile memory is zero, the master read address regis- ter (mrar), master write address register (mwar), master read transfer count (mrtc), and master write transfer count (mwtc) are accessible only from the add-on interface. add-on initiated bus mas- tering is not possible when a byte-wide boot device is used due to shared device pins. when configured for add-on initiated bus mastering, the S5935 transfers data until the transfer count reaches zero, or it may be configured to ignore the transfer count.
10-121 fifo overview S5935 for bus master transfers initiated by the add-on in- terface, some applications may not know the size of the data block to be transferred. to avoid constantly updating the transfer count register, the transfer count may be disabled. bit 28 in the add-on general control/status register (agcsts) performs this function. disabling the transfer count also disables the interrupt capabilities. regardless of whether add- on transfer count is enabled or disabled, the add-on master read enable (amren) and add-on master write enable (amwen) inputs control when the S5935 asserts or deasserts its request to the pci bus. when add-on transfer count is enabled, the S5935 will only request the bus when both the trans- fer count (read or write) is not zero and the appropri- ate enable line (amren or amwen) is active. for add-on initiated bus mastering, amwen and amren override the read and write bus mastering enable bits in the bus master control/status register (mcsr). pci initiated bus mastering if bit 7 in location 45h of the external non-volatile memory is one, the master read address register (mrar), master write address register (mwar), mas- ter read transfer count (mrtc), and master write transfer count (mwtc) are accessible only from the pci bus interface. in this configuration, the S5935 transfers data until the transfer count reaches zero. the transfer count cannot be disabled for pci initiated bus mastering. if no external nv memory boot device is used, the S5935 defaults to pci initiated bus mastering. address and transfer count registers the S5935 has two sets of registers used for bus master transfers. there are two operation registers for bus master read operations and two operation registers for bus master write operations. one opera- tion register is for the transfer address (mwar and mrar). the other operation register is for the trans- fer byte count (mwtc and mrtc). the address registers are written with the first ad- dress of the transfer before bus mastering is enabled. once a transfer begins, this register is automatically updated to reflect the address of the current transfer. if a pci target disconnects from an S5935 initiated cycle, the transfer is retried starting from the current address in the register. if bus grant (gnt#) is re- moved or bus mastering is disabled (using amren or amwen), the value in the address register reflects the next address to be accessed. transfers must be- gin on dword boundaries. the transfer count registers contain the number of bytes to be transferred. the transfer count may be written before or after bus mastering is enabled. if bus mastering is enabled, no transfer occurs until the transfer count is programmed with a non-zero value. once a transfer begins, this register is automatically updated to reflect the number of bytes remaining to be transferred. if the transfer count registers are dis- abled (for add-on initiated bus mastering), transfers begin as soon as bus mastering is enabled. although transfers must begin on dword bound- aries, transfer counts do not have to be multiples of four bytes. for example, if the write transfer count (mwtc) register is programmed with a value of 10 (decimal), the S5935 performs two dword writes and a third write with only be0# and be1# asserted. bus mastering fifo management schemes the S5935 provides flexibility in how the fifo is man- aged for bus mastering. the fifo management scheme determines when the S5935 requests the bus to initiate pci bus cycles. the management scheme is configurable for the pci to add-on and add-on to pci fifo (and may be different for each). bus mastering must be enabled for the management scheme to apply (via the enable bits or amren/amwen). for the pci to add-on fifo, there are two manage- ment options. the pci to add-on fifo management option is programmed through the bus master con- trol/status register (mcsr). the fifo can be pro- grammed to request the bus when any dword location is empty or only when four or more locations are empty. after the S5935 is granted control of the pci bus, the management scheme does not apply. the device continues to read as long as there is an open fifo location. when the pci to add-on fifo is full or bus mastering is disabled, the pci bus request is removed by the S5935. for the add-on to pci fifo, there are two manage- ment options. the add-on to pci fifo management option is programmed through the bus master con- trol/status register (mcsr). the fifo can be pro- grammed to request the bus when any dword location is full or only when four or more locations are full. after the S5935 is granted control of the pci bus, the management scheme does not apply. the device continues to write as long as there is data in the fifo. when the add-on to pci fifo is empty or bus mastering is disabled, the pci bus request is re- moved by the S5935.
10-122 fifo overview S5935 there are two special cases for the add-on to pci fifo management scheme. the first case is when the fifo is programmed to request the pci bus only when four or more locations are full, but the transfer count is less than 16 bytes. in this situation, the fifo ignores the management scheme and finishes trans- ferring the data. the second case is when the S5935 is configured for add-on initiated bus mastering with transfer counts disabled. in this situation, the fifo management scheme must be set to request the pci bus when one or more locations are full. amren and amwen may be used to implement a specific fifo management scheme. fifo bus master cycle priority in many applications, the fifo is used as a pci ini- tiator performing both pci reads and writes. this re- quires a priority scheme be implemented. what happens if the fifo condition for initiating a pci read and a pci write are both met? bits d12 and d8 in the bus master control/status register (mcsr) control the read and write cycle pri- ority, respectively. if these bits are both set or both clear, priority alternates, beginning with a read cycle. if the read priority is set and the write priority is clear, read cycles take priority. if the write priority is set and the read priority is clear, write cycles take priority. pri- ority arbitration is only done when neither fifo has control of the pci bus (the pci to add-on fifo would never interrupt an add-on to pci fifo transfer). fifo generated bus master interrupts interrupts may be generated under certain conditions from the fifo. if pci initiated bus mastering is used, inta# is generated to the pci interface. if add-on initiated bus mastering is used, irq# is generated to the add-on interface. interrupts may be disabled. fifo interrupts may be generated from one or more of the following during bus mastering: read transfer count reaches zero, write transfer count reaches zero, or an error occurs during bus mastering. error conditions in- clude a target or master abort on the pci bus. inter- rupts on pci error conditions are only enabled if one or both of the transfer count interrupts are enabled. the add-on interrupt control/status register (aint) or the interrupt control status register (intcsr) in- dicates the interrupt source. the interrupt service routine may read these registers to determine what action is required. as mailboxes are also capable of generating interrupts, this must also be considered in the service routine. interrupts are also cleared through these registers. bus interface the S5935 fifo may be accessed from the add-on interface or the pci interface. add-on fifo control and status signals allow a simple interface to the fifo with either an add-on cpu or programmable logic. the following section describes the pci and add-on interface behavior and hardware interface. fifo pci interface (target mode) the S5935 fifo may act as a standard pci target. fifo empty/full status may be determined by the pci initiator by reading the status bits in the pci bus master control/status register (mcsr). the fifo occupies a single 32-bit register location within the pci operation registers. a pci initiator may not perform burst accesses to a fifo as it is a single address . each data phase of a burst causes the pci initiator to increment its address counter (even though only the first address is driven at the beginning of the burst). the initiator keeps track of the current address in case a disconnect occurs. this allows the initiator to continue the burst from where the disconnect occurred. if the S5935 fifo initiated a disconnect during a pci burst to the fifo register, the burst would be resumed at an ad- dress other than the fifo location (because the ini- tiator address counter has incremented). the S5935 always signals a disconnect if a burst to any pci operation register is attempted. because the pci to add-on fifo and the add-on to pci fifo occupy a single location within the pci and add-on operation registers, which fifo is ac- cessed is determined by whether the access is a read or write. this means that once data is written into the fifo, the value written cannot be read back. for pci reads from the add-on to pci fifo, the S5935 asserts trdy# and completes the pci cycle (figure 3). if the pci bus attempts to read an empty fifo, the S5935 immediately issues a disconnect with retry (figure 4). the add-on to pci fifo status indicators change one pci clock after a pci read. for pci writes to the pci to add-on, the S5935 as- serts trdy# and completes the pci cycle (figure 5). if the pci bus attempts to write a full fifo, the S5935 immediately issues a disconnect with retry (figure 6). the pci to add-on fifo status indicators change one pci clock after a pci write.
10-123 fifo overview S5935 figure 3. pci read from a full S5935 fifo pci_clk pci signals add-on signals frame# ad[31:0] irdy# trdy# devsel# stop# wrfull fwe addr data figure 4. pci read from an empty S5935 fifo (target disconnect) pci_clk pci signals add-on signals frame# ad[31:0] irdy# trdy# devsel# stop# wrfull fwe addr data target disconnect with retry fifo pci interface (initiator mode) the S5935 can act as an initiator on the pci bus. this allows the device to gain control of the pci bus to transfer data to or from the fifo. internal address and transfer count registers control the number of pci transfers and the locations of the transfers. the following paragraphs assume the proper registers and bits are programmed to enable bus mastering . pci read and write transfers from the S5935 are very similar. the fifo management scheme determines when the S5935 asserts its pci bus request (req#). when bus grant (gnt#) is returned, the device be- gins running pci cycles. once the S5935 controls the bus, the fifo management scheme is not important. it only determines when pci bus control is initially requested. pci bus reads and writes are always per- formed as bursts by the S5935, if possible.
10-124 fifo overview S5935 pci_clk pci signals add-on signals frame# ad[31:0] irdy# trdy# devsel# stop# rdempty frf addr data pci_clk pci signals add-on signals frame# ad[31:0] irdy# trdy# devsel# stop# rdempty frf addr data target disconnect with retry figure 5. pci write to an empty S5935 fifo figure 6. pci write to a full S5935 fifo (target disconnect)
10-125 fifo overview S5935 fifo pci bus master reads for pci read transfers (filling the pci to add-on fifo), read cycles are performed until one of the following occurs: C bus master read transfer count register (mrtc), if used, reaches zero C the pci to add-on fifo is full C gnt# is removed by the pci bus arbiter C amren is deasserted if the transfer count is not zero, gnt# remains as- serted, and amren is asserted, the fifo continues to read data from the pci bus until there are no empty locations in the pci to add-on fifo. if the add-on can empty the fifo as quickly as it can be filled from the pci bus, very long bursts are possible. the S5935 deasserts req# when it completes the access to fill the last location in the fifo. once req# is deasserted, it will not be reasserted until the fifo management condition is met. fifo pci bus master writes for pci write transfers (emptying the add-on to pci fifo), write cycles are performed until one of the following occurs: C bus master write transfer count register (mwtc), if used, reaches zero C the add-on to pci fifo is empty C gnt# is removed by the pci bus arbiter C amwen is deasserted if the transfer count is not zero, gnt# remains as- serted, and amwen is asserted, the fifo continues to write data to the pci bus until there are is no data in the add-on to pci fifo. if the add-on can fill the fifo as quickly as it can be emptied to the pci bus, very long bursts are possible. the S5935 deasserts req# when it completes the access to transfer the last data in the fifo. once req# is deasserted, it will not be reas- serted until the fifo management condition is met. add-on bus interface the fifo register may be accessed in two ways from the add-on interface. it can be accessed through normal register accesses or directly with the rdfifo# and wrfifo# inputs. in addition, the fifo register can also be accessed synchronous to bpclk. the add-on interface also supports datapaths which are not 32-bits. the method used to access the fifo from the add-on interface is inde- pendent of whether the fifo is a pci pci target or a pci initiator. add-on fifo register accesses the fifo may be accessed from the add-on interface through the add-on fifo port register (afifo) read or write. this is offset 20h in the add-on operation registers. this register is accessed synchronous to bpclk. to access the fifo as a normal add-on op- eration register, adr[6:2], be[3:0]#, select#, and rd# or wr# are required.
10-126 fifo overview S5935 figure 7 shows a synchronous fifo register burst access. select# must meet setup and hold times relative to the rising edge of bpclk. rd# and select# both asserted enables the dq outputs, and the first data location (data 0) in the fifo is driven on to the bus. the fifo address and the byte enables must be valid before valid data is driven onto the dq bus. data 0 remains valid until the next rising edge of bpclk. the rising edge of bpclk causes the fifo pointer to advance to the next location (data 1). the next rising edge of bpclk also advances the fifo pointer to the next location (data 2). the status outputs reflect the fifo condition after it advances, and are updated off of the rising edge of bpclk. when rd# or select# is deasserted, the dq bus floats. the next time a valid fifo access occurs and rd# and select# are asserted, data 2 is presented on the dq bus (as there was no bpclk edge to advance the fifo). add-on fifo direct access mode instead of generating an address, byte enables, select# and a rd# or wr# strobe for every fifo access, the S5935 allows a simple, direct access mode. using rdfifo# and wrfifo# is functionally identical to per- forming a standard afifo port register access, but re- quires less logic to implement. accesses to the fifo register using the direct access signals are always 32- bits wide. the only exception to this is when the mode pin is configured for 16-bit operation. in this situation, all accesses are 16-bits wide. the rd# and wr# inputs must be inactive when rdfifo# or wrfifo# is active. the adr[6:2] and be[3:0]# inputs are ignored. rdfifo# and wrfifo# act as enables with bpclk acting as the clock. a synchronous interface allows higher data rates. figure 8 shows a synchronous fifo register direct burst access using rdfifo#. rdfifo# acts as an enable and the first data location (data 0) in the fifo is driven on to the bus when rdfifo# is asserted. data 0 remains valid until the next rising edge of bpclk. the rising edge of bpclk causes the fifo pointer to advance to the next location (data 1). the next rising edge of bpclk advances the fifo pointer to the next location (data 2). the status out- puts reflect the fifo condition after it advances, and are updated off of the rising edge of bpclk. when rdfifo# is deasserted, the dq bus floats. the next time rdfifo# is asserted, data 2 is presented on the dq bus (as there was no bpclk edge to advance the fifo). a synchronous fifo interface has the advantage of allowing data to be accessed more quickly (in bursts) by the add-on. as a target, if a full S5935 fifo is written (or an empty fifo is read) by a pci initiator, the S5935 requests a retry. the faster the add-on interface can empty (or fill) the fifo, the less often retries occur. with the S5935 as a pci initiator, a similar situation occurs. not emptying or filling the fifo quickly enough results in the S5935 giving up control of the pci bus. higher pci bus data transfer rates are possible through the fifo with a synchro- nous interface. figure 7. synchronous fifo register burst read access example be[3:0]# bpclk adr[6:2] dq[31:0] select# rd# rdempty valid byte enables fifo pointer advances valid address data 1 data 2 data 0 new status new status status before read
10-127 fifo overview S5935 additional status/control signals for add-on initiated bus mastering if a serial non-volatile memory is used to configure the S5935, and the device is configured for add-on initi- ated bus mastering, two additional fifo status signals and four additional control signals are available to the add-on interface. the frf and fwe outputs provide additional fifo status information. inputs frc#, fwc#, amren, and amwen provide additional fifo control. applications may use these signals to monitor/ control fifo flags and pci bus requests. these new signals are some of the lines that were used for byte- wide nvram interface, but now are reconfigured. the reconfigured lines are as follows: outputs: e_addr (15) frf fifo read full: indicates that the pci to add-on fifo is full. e_addr (14) fwe fifo write empty: indicates the last add-on to pci fifo . data has transferred to a final buffer and is queued for transfer, fifo is empty. inputs: eq (7) amwen add-on bus mastering write enable: this input is driven high to enable bus master writes. eq (6) amren add-on bus mastering read enable: this input is driven high to enable bus master reads. eq (5) frc# fifo read clear: this line is driven low to clear the pci to add-on fifo. eq (4) fwc# fifo write clear: this line is driven low to clear the add-on to pci fifo. frf (pci to add-on fifo full) and fwe (add-on to pci fifo empty) supplement the rdempty and wrfull status indicators. these additional status outputs provide additional fifo status information for add-on fifo control logic. figure 8. synchronous fifo register burst rdfifo# access example bpclk dq[31:0] rdfifo# rdempty data 1 data 2 data 0 fifo pointer advances status before read new status new status
10-128 fifo overview S5935 reset the pci to add-on or add-on to pci fifo flags. the fifo flags can always be reset with soft- ware through the add-on general control/status register (agcsts) or the bus master control/status register (mcsr), but these hardware inputs are use- ful for designs which do no implement a cpu on the add-on card. asserting the frc# input resets the pci to add-on fifo. asserting the fwc# input re- sets the add-on to pci fifo. the amren and amwen inputs allow add-on logic to individually enable and disable bus mastering for the pci to add-on and add-on to pci fifo. these inputs override the bus master control/status register (mcsr) bus master enable bits. the S5935 may re- quest the pci bus for the pci to add-on fifo when amren is asserted and may request the pci bus for the add-on to pci fifo when amwen is asserted. if amren or amwen is deasserted, the S5935 removes its pci bus request and gives up control of the bus. amren and amwen are useful for add-ons with external fifos cascaded into the S5935. for pci bus master write operations, the entire S5935 add- on to pci fifo and the external fifo may be filled before enabling bus mastering, providing a single long burst write rather than numerous short bursts. in some applications, the amount of data to be trans- ferred is not known. during read operations, the S5935, attempting to fill its pci to add-on fifo, may access up to eight memory locations beyond what is required by the add-on before it stops. in this situa- tion, amren can be deasserted to disable pci reads, and then frc# can be asserted to flush the unwanted data from the fifo. fifo generated add-on interrupts for add-on initiated bus mastering, the S5935 may be configured to generate interrupts to the add-on interface for the following situations: C read transfer count reaches zero C write transfer count reaches zero C an error occurred during the bus master trans- action the interrupt is posted to the add-on interface with the irq# output. a high-to-low transition on this out- put indicates an interrupt condition. because there is a single interrupt output and multiple interrupt condi- tions, the add-on interrupt control/status register (aint) must be read to determine the interrupt source. this register is also used to clear the inter- rupt, returning irq# to its high state. if mailbox inter- rupts are also used, this must be considered in the interrupt service routine. 8-bit and 16-bit fifo add-on interfaces the S5935 fifo may also be used to transfer data between the pci bus and 8-bit or 16-bit add-on inter- faces. this can be done using fifo advance condi- tions or the S5935 mode input pin. the fifo may be used as an 8-bit or 16-bit wide fifo. to use the fifo as an 8-bit interface, the ad- vance condition should be set for byte 0 (no data is transferred in the upper 3 bytes). to use the fifo as a 16-bit interface, the advance condition should be set for byte 1 (no data is transferred in the upper 2 bytes). this allows a simple add-on bus interface, but it has the disadvantage of not efficiently utilizing the pci bus bandwidth because the host is forced to perform 8-bit or 16-bit accesses to the fifo on the pci bus. this is the only way to communicate with an 8-bit add-on through the fifo without additional logic to steer byte lanes on the add-on data bus. pass-thru mode is more suited to 8-bit add-on inter- faces. implementing a 16-bit wide fifo is a reasonable so- lution, but to avoid wasting pci bus bandwidth, the best method is to allow the pci bus and the fifo to operate with 32-bit data. the S5935 can assemble or disassemble 32-bit quantities for the add-on inter- face. this is possible through the mode pin. when mode is low, the add-on data bus is 32-bits. when mode is high, the add-on data bus is 16-bits. when mode is configured for 16-bit operation, be3# be- comes adr1. with the fifo direct access signals (rdfifo# and wrfifo#), the mode pin must reflect the actual add-on data bus width. with mode = 16-bits, the S5935 automatically takes two consecutive, 16-bit add-on writes to the fifo and assembles a 32-bit value. fifo reads operate in the same manner. two consecutive add-on reads empty the 32-bit fifo register. the 16-bit data bus is internally steered to the lower and upper words of the 32-bit fifo register. one consideration needs to be taken when using the fifo direct access signals and letting the S5935 do byte lane steering internally. the default condition used to advance the fifo is byte 0. this must be changed to byte 2 or 3. when mode is configured for a 16-bit add-on bus, the first 16-bit cycle to the fifo always accesses the low 16-bits. if the fifo advance condition is left at byte 0, the fifo ad- vances after the first 16-bit cycle and the data in the upper 16-bits is directed to the next fifo location, shifting the data. the frc# and fwc# inputs allow add-on logic to
10-129 fifo overview S5935 some applications hold the rdfifo# and wrfifo# inputs active for a synchronous interface. in 16-bit mode, designs must avoid writing to a full fifo. the data for the write is lost, but the internal mechanism to direct the 16-bit external data bus to the upper 16- bits of the fifo register is triggered. this creates a situation where the fifo is out of step. the next 16- bit fifo write is directed to the upper 16-bits of the fifo, and the fifo advances incorrectly. the wrfull output should be used to gate the wrfifo# input to avoid this situation. a similar prob- lem can occur if add-on logic attempts to read an empty fifo in 16-bit mode. rdempty should be used to gate the rdfifo# input to avoid problems with the fifo getting out of step. in 32-bit mode (mode = low), these situations do not occur. if fifo accesses are done without the direct access signals with mode configured for 16-bits (using adr, select#, etc.), external hardware must toggle adr1 between consecutive 16-bit bus cycles. the fifo advance condition must be set to correspond to the order the application accesses the upper and lower words in the fifo register. configuration the fifo configuration takes place during initializa- tion and during operation. during initialization, the bus master register access rights are defined. during operation, fifo advance conditions, endian conver- sion, and bus mastering capabilities are defined. the following section describes the bits and registers which are involved with controlling and monitoring fifo operation. fifo setup during initialization location 45h in an external non-volatile memory may be used to configure the S5935 fifo during initializa- tion. if no external non-volatile memory is used, fifo operation is disabled. the value of bit 7 in location 45h determines if the address and transfer count registers used in bus mas- tering are accessible from the pci bus or from the add- on bus. once the configuration information is downloaded from non-volatile memory after reset, the bus mastering initialization method can not be changed. access to the bus master address and transfer count registers cannot be alternated between the pci bus and the add-on interface during operation. bits 6 and 5 in location 45h enable fifo register accesses using the rdfifo#, wrfifo#, rd# and wr# inputs synchronous to bpclk. for synchro- nous operation, rdfifo#, wrfifo#, rd# and wr# operate as enables, using bpclk to clock data. location 45h configuration bits bit 7 bus master register access 0 address and transfer count registers only accessible from the add-on interface 1 address and transfer count registers only accessible from the pci interface (default) bit 6 rdfifo#, rd# operation 0 enable - rdfifo# and rd# functions. 1 not allowed. must be 0. bit 5 wrfifo#, wr# operation 0 enable - wrfifo# and wr# functions. 1 not allowed. must be 0. bit 0 target latency timer enable 0 disable pci latency timer time out - will not disconnect with retry if cannot issue trdy in specified time 1 enable pci latency timer time out - will be pci 2.1 compliant fifo status and control bits the fifo status can be monitored and the fifo op- eration controlled from the pci operation registers and/or the add-on operation registers. the fifo register resides at offset 20h in the pci and add-on operation registers. the bus master control/status (mcsr) pci opera- tion register allows a pci host to monitor fifo activ- ity and control fifo operation. reset controls allow the pci to add-on fifo and add-on to pci fifo flags to be reset (individually). status bits indicate if the pci to add-on fifo is empty, has four or more open spaces, or is full. status bits also indicate if the add-on to pci fifo is empty, has four or more full locations or is full. finally, fifo pci bus mastering is monitored/controlled though this register.
10-130 fifo overview S5935 the add-on general control/status (agcsts) add- on operation register allows an add-on cpu to monitor fifo activity and control fifo operation. re- set controls allow the pci to add-on fifo and add- on to pci fifo flags to be reset (individually). status bits indicate if the pci to add-on fifo is empty, has four or more open spaces, or is full. status bits also indicate if the add-on to pci is empty, has four or more full spaces or is full. fifo bus mastering status may be monitored through this register, but all bus master configuration is through the mcsr pci op- eration register. pci initiated fifo bus mastering setup for pci initiated bus mastering, the pci host sets up the S5935 to perform bus master transfers. the fol- lowing tasks must be completed to setup fifo bus mastering: 1) define interrupt capabilities. the pci to add-on and/or add-on to pci fifo can generate a pci interrupt to the host when the transfer count reaches zero. intcsr bit 15 enable interrupt on read transfer count equal zero intcsr bit 14 enable interrupt on write transfer count equal zero 2) reset fifo flags. this may not be necessary, but if the state of the fifo flags is not known, they should be initialized. mcsr bit 26 reset add-on to pci fifo flags mcsr bit 25 reset pci to add-on fifo flags 3) define fifo management scheme. these bits define what fifo condition must exist for the pci bus request (req#) to be asserted by the S5935. mcsr bit 13 pci to add-on fifo management scheme mcsr bit 9 add-on to pci fifo management scheme 4) define pci to add-on and add-on to pci fifo priority. these bits determine which fifo has pri- ority if both meet the defined condition to request the pci bus. if these bits are the same, priority alternates, with read accesses occurring first. mcsr bit 12 read vs. write priority mcsr bit 8 write vs. read priority 5) define transfer source/destination address. these registers are written with the first address that is to be accessed by the S5935. these ad- dress registers are updated after each access to indicate the next address to be accessed. trans- fers must start on dword boundaries. mwar all bus master write address mrar all bus master read address 6) define transfer byte counts. these registers are written with the number of bytes to be trans- ferred. the transfer count does not have to be a multiple of four bytes. these registers are up- dated after each transfer to reflect the number of bytes remaining to be transferred. mwtc all write transfer byte count mrtc all read transfer byte count 7) enable bus mastering. once steps 1-6 are com- pleted, the fifo may operate as a pci bus mas- ter. read and write bus master operation may be independently enabled or disabled. mcsr bit 14 enable pci to add-on fifo bus mastering mcsr bit 10 enable add-on to pci fifo bus mastering the order of the tasks listed above is not particularly important. it is recommended that bus mastering be enabled as the last step. some applications may choose to leave bus mastering enabled and start transfers by writing a non-zero value to the transfer count registers. this also works, provided the entire transfer count is written in a single access. as a num- ber of the configuration bits and the two enable bits are all in the mcsr register, it may be most efficient for the fifo configuration bits to be set with the same register access that enables bus mastering.
10-131 fifo overview S5935 if interrupts are enabled, a host interrupt service rou- tine is also required. the service routine determines the source of the interrupt and resets the interrupt. as mailbox registers may also be configured to generate interrupts, the exact source of the interrupt is indi- cated in the pci interrupt control/status register (intcsr). typically, the interrupt service routine is used to setup the next transfer by writing new ad- dresses and transfer counts, but some applications may also require other actions. if read transfer or write transfer complete interrupts are enabled, mas- ter and target abort interrupts are automatically en- abled. these indicate a transfer error has occurred. writing a one to these bits clears the corresponding interrupt. intcsr bit 21 target abort caused interrupt intcsr bit 20 master abort caused interrupt intcsr bit 19 read transfer complete caused interrupt intcsr bit 18 write transfer complete caused interrupt add-on initiated fifo bus mastering setup for add-on initiated bus mastering, the add-on sets up the S5935 to perform bus master transfers. the following tasks must be completed to setup fifo bus mastering: 1) define transfer count abilities. for add-on initi- ated bus mastering, transfer counts may be ei- ther enabled or disabled. transfer counts for read and write operations cannot be individually enabled. agcsts bit 28 enable transfer count for read and write bus master transfers 2) define interrupt capabilities. the pci to add-on and/or add-on to pci fifo can generate an in- terrupt to the add-on when the transfer count reaches zero (if transfer counts are enabled). aint bit 15 enable interrupt on read transfer count equal zero aint bit 14 enable interrupt on write transfer count equal zero 3) reset fifo flags. this may not be necessary, but if the state of the fifo flags is not known, they should be initialized. agcsts bit 25 reset add-on to pci fifo flags agcsts bit 26 reset pci to add-on fifo flags 4) define fifo management scheme. these bits define what fifo condition must exist for the pci bus request (req#) to be asserted by the S5935. this must be programmed through the pci interface. mcsr bit 13 pci to add-on fifo management scheme mcsr bit 9 add-on to pci fifo management scheme 5) define pci to add-on and add-on to pci fifo priority. these bits determine which fifo has pri- ority if both meet the defined condition to request the pci bus. if these bits are the same, priority alternates, with read accesses occurring first. this must be programmed through the pci inter- face. mcsr bit 12 read vs. write priority mcsr bit 8 write vs. read priority 6) define transfer source/destination address. these registers are written with the first address that is to be accessed by the S5935. these ad- dress registers are updated after each access to indicate the next address to be accessed. trans- fers must start on dword boundaries. mwar all bus master write address mrar all bus master read address 7) define transfer byte counts. these registers are written with the number of bytes to be trans- ferred. the transfer count does not have to be a multiple of four bytes. these registers are up- dated after each transfer to reflect the number of bytes remaining to be transferred. if transfer counts are disabled, these registers do not need to be programmed. mwtc all write transfer byte count mrtc all read transfer byte count
10-132 fifo overview S5935 8) enable bus mastering. once steps 1-7 are com- pleted, the fifo may operate as a pci bus mas- ter. read and write bus master operation may be independently enabled or disabled. the amren and amwen inputs control bus master enabling for add-on initiated bus mastering. the mcsr bus master enable bits are ignored for add-on initiated bus mastering. it is recommended that bus mastering be enabled as the last step. some applications may choose to leave bus mastering enabled (amren and amwen as- serted) and start transfers by writing a non-zero value to the transfer count registers (if they are enabled). if interrupts are enabled, an add-on cpu interrupt service routine is also required. the service routine determines the source of the interrupt and resets the interrupt. as mailbox registers may also be config- ured to generate interrupts, the exact source of the interrup is indicated in the add-on interrupt control register (aint). typically, the interrupt service rou- tine is used to setup the next transfer by writing new addresses and transfer counts (if enabled), but some applications may also require other actions. if read transfer or write transfer complete interrupts are en- abled, the master/target abort interrupt is automati- cally enabled. these indicate a transfer error has oc- curred. writing a one to these bits clears the corre- sponding interrupt. aint bit 21 master/target abort caused interrupt aint bit 19 read transfer complete caused interrupt aint bit 18 write transfer complete caused interrupt
11-133 pass-thru overview S5935 pass-thru overview the S5935 provides a simple registered access port to the pci bus. using a handshaking protocol with add-on card logic, the pci bus directly accesses re- sources on the add-on. the pass-thru data transfer method is very useful for direct add-on memory ac- cess, or accessing registers within peripherals on an add-on board. pass-thru operation requires an ex- ternal nv memory boot device to define and configure the S5935 pass-thru regions. the S5935 provides four user-configurable pass- thru regions. each region corresponds to a pci con- figuration base address register (badr1-4). a region represents a block of address space (the block size is user-defined). each block can be mapped into memory or i/o space. memory mapped regions can request to be located below 1 mbyte (real mode address space for a pc). each region also has a configurable bus width for the add-on bus interface. an 8-, 16-, or 32-bit add-on interface may be selected, for use with a variety of add-on memory or peripheral devices. pass-thru features can be used only when the S5935 is a pci target. as a target, the S5935 pass- thru mode supports single data transfers as well as burst transfers. when accessed with burst transfers, the S5935 supports data transfers at the full pci bandwidth. the data transfer rate is only limited by the pci initiator performing the access and the speed of the add-on logic. functional description to provide the pci bus add-on with direct access to add-on resources, the S5935 has an internal pass- thru address register (apta), and a pass-thru data register (aptd). these registers are con- nected to both the pci bus interface and the add-on bus interface. this allows a pci initiator to perform pass-thru writes (data transferred from the pci bus to the add-on bus) or pass-thru reads (pci bus re- quests data from the add-on bus). the S5935 pass- thru interface supports both single cycle (one data phase) and burst accesses (multiple data phases). pass-thru transfers data transfers between the pci bus and the add-on using the pass-thru interface are implemented with a handshaking scheme. if the pci bus writes to an S5935 pass-thru region, add-on logic must read the data from the S5935 and store it on the add-on. if the pci bus reads from a pass-thru region, add-on logic must write data to the S5935. some applications may require that an address be passed to the add-on for pass-thru accesses. for example, a 4 kbyte pass-thru region on the pci bus may correspond to a 4 kbyte block of sram on the add-on card. if a pci initiator accessed this region, the add-on would need to know the offset within the memory device to access. the pass-thru address register (apta) allows the add-on to access ad- dress information for the current pci cycle. when the pci bus performs burst accesses, the apta register is updated by the S5935 to reflect the address of the current data phase. for pci writes to the add-on, the S5935 transfers the data from the pci bus into the pass-thru data register (aptd). the S5935 captures the data from the pci bus when trdy# is asserted. the pci bus then becomes available for other transfers. when the pass-thru data register becomes full, the S5935 as- serts the pass-thru status signals to indicate to the add-on that data is present. the add-on logic may read the data register and assert ptrdy# to indicate the current access is complete. until the current ac- cess completes, the S5935 responds to further pass- thru accesses with retries. for pci reads from the add-on, the S5935 asserts the pass-thru status signals to indicate to the add- on that data is required. the add-on logic should write to the pass-thru data register and assert ptrdy# to complete the access. the S5935 does not assert trdy# to the pci bus until ptrdy# is asserted by add-on logic. if the add-on cannot pro- vide data quickly enough, the S5935 signals a retry to the pci bus. this allows the pci bus to perform other tasks, rather than waiting for a slow target. ?
11-134 pass-thru overview S5935 pass-thru status/control signals the S5935 pass-thru registers are accessed using the standard add-on register access pins. the pass- thru address register (apta) can, optionally, be ac- cessed using a single, direct access input, ptadr#. pass-thru cycle status indicators are provided to control add-on logic based on the type of pass-thru access occurring (single cycle, burst, etc.). the fol- lowing signals are provided for pass-thru operation: signal function ptatn# this output indicates a pass-thru access is occurring ptburst# this output indicates the pass-thru access is a pci burst access ptnum[1:0] these outputs indicate which pass- thru region decoded the pci ad- dress ptbe[3:0]# these outputs indicate which data bytes are valid (pci writes), or requested (pci reads) ptwr this output indicates if the pass- thru access is a pci read or a write ptadr# when asserted, this input drives the pass-thru address register con- tents onto the add-on data bus ptrdy# when asserted, this input indicates the current pass-thru transfer has been completed by the add-on bpclk buffered pci bus clock output (to synchronize pass-thru data register accesses) pass-thru add-on data bus sizing many applications require an 8-bit or 16-bit add-on bus interface. pass-thru regions can be configured to support bus widths other than 32-bits. each pass- thru region can be defined, during initialization, as 8, 16-, or 32-bits. all of the regions do not need to be the same. this feature allows a simple interface to 8- and 16-bit add-on devices. to support alternate add-on bus widths, the S5935 performs internal data bus steering. this allows the add-on interface to assemble and disassemble 32- bit pci data using multiple add-on accesses to the pass-thru data register (aptd). the add-on byte enable inputs (be[3:0]#) are used to access the indi- vidual bytes or words within aptd. bus interface the pass-thru interface on the S5935 is a pci tar- get-only function. pass-thru operation allows pci ini- tiators to read or write resources on the add-on card. a pci initiator may access the add-on with single data phase cycles or multiple data phase bursts. the add-on interface implements pass-thru status and control signals used by logic to complete data transfers initiated by the pci bus. the pass-thru inter- face is designed to allow add-on logic to function with- out knowledge of pci bus activity. add-on logic only needs to react to the pass-thru status outputs. the S5935 pci interface independently interacts with the pci initiator to control data flow between the devices. the following sections describe the pci and add-on bus interfaces. the pci interface description pro- vides a basic overview of how the S5935 interacts with the pci bus, and may be useful in system de- bugging. the add-on interface description indicates functions required by add-on logic and details the pass-thru handshaking protocol. pci bus interface the S5935 decodes all pci bus cycle addresses. if the address associated with the current cycle is to one of S5935 pass-thru regions, devsel# is as- serted. if the pass-thru logic is currently idle (not busy finishing a previous pass-thru operation), the bus cycle type is decoded and the add-on pass-thru status outputs are set to initiate a transfer on the add-on side. if the pass-thru logic is currently busy completing a previous access, the S5935 signals a retry to pci initiator. the following sections describe the behavior of the pci interface for pass-thru accesses to the S5935. single cycle accesses, burst accesses, and target- initiated retries are detailed. pci pass-thru single cycle accesses single cycle transfers are the simplest pci bus trans- action. single cycle transfers have an address phase and a single data phase. the pci bus transaction starts when an initiator drives address and command information onto the pci bus and asserts frame#. the initiator always deasserts frame before the last data phase. for single cycle transfers, frame# is only asserted during the address phase (indicating the first data phase is also the last). when the S5935 sees frame# asserted, it samples the address and command information to determine if the bus transaction is intended for it. if the address is within one of the defined pass-thru regions, the S5935 accepts the transfer (assert devsel#), and stores the pci address in the pass-thru address register (apta).
11-135 pass-thru overview S5935 for pass-thru writes, the S5935 responds immedi- ately (asserting trdy#) and transfers the data from the pci bus into the pass-thru data register (aptd). the S5935 then indicates to the add-on in- terface that a pass-thru write is taking place and waits for add-on logic to read the aptd register and complete the transfer (assert ptrdy#). once the S5935 has captured the data from the pci bus, the transfer is finished from the pci bus perspective, and the pci bus becomes available for other transfers. for pass-thru reads, the S5935 indicates to the add- on interface that a pass-thru read is taking place and waits for add-on logic to write the pass-thru data register and complete the transfer (assert ptrdy#). the S5935 completes the cycle when data is written into the data register. if the add-on cannot complete the write quickly enough, the S5935 re- quests a retry from the initiator. see target-requested disconnect information. pci pass-thru burst accesses for pci pass-thru burst accesses, the S5935 cap- tures the pci address and determines if it falls into one of the defined pass-thru regions. accesses that fall into a pass-thru region are accepted by asserting devsel#. the S5935 monitors frame# and irdy# on the pci bus to identify burst accesses. if the pci initiator is performing a burst access, the pass-thru status indicators notify add-on logic. for pass-thru burst writes, the S5935 responds im- mediately (asserting trdy#). the S5935 transfers the first data phase of the burst into the pass-thru data register (aptd), and stores the pci address in the pass-thru address register (apta). the add- on interface completes the transfer and asserts ptrdy#. every time ptrdy# is asserted by the add-on, the S5935 begins the next data phase. the next data phase is latched into the data register. for burst accesses, apta is automatically incremented by the S5935 for each data phase. for pass-thru burst reads, the S5935 claims the pci cycle (asserting devsel#). the request for data is passed on to add-on logic and the pci address is stored in the apta register. the add-on interface completes the transfer and asserts ptrdy#. the S5935 then drives the requested data on the pci bus and asserts trdy# to begin the next data phase. the apta register is automatically incremented by the S5935 for each data phase. pci retry conditions in some applications, add-on logic may not be able to respond to pass-thru accesses quickly. in this situation, the S5935 disconnects from the pci bus, signaling a retry. this indicates that the initiator should try the access again at a later time. this al- lows other pci cycles to be run while the logic on the slow target completes the pass-thru access. ideally, when the initiator retries the access, the target has completed the access and can respond to the initia- tor. with many devices, particularly memories, the first access takes longer than subsequent accesses (as- suming they are sequential and not random). for this reason, the pci specification allows 16 clocks to re- spond to the first data phase of a pci cycle and 8 clocks for subsequent data phases (in the case of a burst) before a retry must be requested by the S5935. the S5935 also requests a retry if an initiator at- tempts to burst past the end of a pass-thru region. the S5935 updates the pass-thru address register (apta) for each data phase during bursts, and if the updated address is not within the current pass-thru region, a retry is requested. for example, a pci system may map a 512 byte pass-thru memory region to 0dc000h to 0dc1ffh. a pci initiator attempts a four dword burst with a starting address of 0dc1f8h. the first and second data phases complete (filling the dwords at 0dc1f8h and 0dc1fch), but the third data phase causes the S5935 to request a retry. this forces the initiator to present the address 0dc200h on the pci bus. if this address is part of another S5935 pass- thru region, the device accepts the access. pci write retries when the S5935 requests a retry for a pci pass- thru write, it indicates that the add-on is still com- pleting a previous pass-thru write access. the pass-thru address and data register contents (apta and aptd) are still required for the previous pass-thru operation and cannot be updated by the pci interface until the access completes (the add-on asserts ptrdy#). when the add-on is busy completing a pass-thru write, the S5935 requests an immediate retry for all pass-thru region accesses, allowing the pci bus to perform other operations. pci operation registers may be accessed while the add-on is still completing a pass-thru access. only pass-thru region ac- cesses receive retry requests.
11-136 pass-thru overview S5935 pci read retries when the S5935 requests a retry for a pci pass- thru read, it indicates that the add-on could not complete the read in the required time. the pass- thru data cannot be read by the pci interface until the add-on asserts ptrdy#, indicating the access is complete. if the retry occurs after the add-on has completed the pass-thru operation by writing the appropriate data into the pass-thru data register and asserting ptrdy#, the S5935 asserts devsel# and trdy# to complete the pci read. if the add-on still has not completed the pass-thru read, the S5935 waits for the required 16 clocks. if the add-on completes the access during this time, trdy# is asserted and the access is finished. if the add-on cannot complete the access within 16 clocks, another retry is requested. when the add-on is busy completing a pass-thru read, the S5935 requests an immediate retry for all pass-thru region accesses, except the region cur- rently completing the previous access. this allows the pci bus to perform other operations. the next access to the pass-thru region which initiated the retry must be to the same address which caused the retry. another initiator accessing the same pass-thru region causes the S5935 to respond with the original initiators data (for reads). S5935 pci operation reg- isters may be accessed while the add-on is still com- pleting a pass-thru access. only other pass-thru region accesses receive retry requests. add-on bus interface the pass-thru address and data registers can be ac- cessed as add-on operation registers. the interface to the pass-thru registers is described in. the pass- thru data register is updated on the rising edge of bpclk. for this reason, all pass-thru inputs must be synchronous to bpclk. in the following sections the add-on pass-thru interface is described for pass- thru single cycle accesses, burst accesses, target- requested retries, and when using 8-bit and 16-bit add-on data buses. single cycle pass-thru writes a single cycle pass-thru write operation occurs when a pci initiator writes a single value to a pass- thru region. pci single cycle transfers consists of an address phase and one data phase. during the ad- dress phase of the pci transfer, the S5935 stores the pci address into the pass-thru address register (apta). if the S5935 determines that the address is within one of its defined pass-thru regions, it cap- tures the pci data into the pass-thru data register (aptd). figure 1 shows a single cycle pass-thru write access (add-on read). the add-on must read the data stored in the aptd register and transfer it to its destination. note: rd# may be asserted for multiple clocks to allow interfacing with slow add-on devices. data re- mains valid until ptrdy# is asserted. note: for all add-on accesses using ptadr for address data when in 16 bit mode, adr[1] must be held low to get the low address word. bpclk 012345 0h 1 2ch 0h ptatn# ptburst# ptnum[1:0] ptwr ptbe[3:0]# select# adr[6:2] be[3:0]# rd# dq[31:0] ptrdy# pt data pci write cycle completed figure 1. single cycle pass-thru write
11-137 pass-thru overview S5935 clock 0: the pci bus cycle address information is stored in the S5935 pass-thru address register. clock 1: the pci address is recognized as a write to pass-thru region 1. the pci data is stored in the S5935 pass-thru data register. ptatn# is asserted to indicate a pass-thru access is occurring. clock 2: pass-thru status signals indicate what action is required by add-on logic. pass- thru status outputs are valid when ptatn# is active and are sampled by the add-on at the rising edge of clock 2. ptburst# deasserted. the access has a single data phase. ptnum[1:0] 01. indicates the pci access is to pass-thru region 1. ptwr asserted. the pass-thru access is a write. ptbe[3:0]# 0h. indicates the pass-thru access is 32-bits. select#, address and byte enable inputs are driven to read the pass-thru data register at offset 2ch. dq[31:0] are driven after rd# and select# are asserted. clock 3: if ptrdy# is asserted at the rising edge of clock 3, ptatn# is immediately deasserted and the pass-thru access is completed at clock 4. clock 4: if add-on logic requires more time to read the pass-thru data register (slower memory or peripherals), ptrdy# can be delayed, extending the cycle. with ptrdy# asserted at the rising edge of clock 4, ptatn# is deasserted and the pass-thru access is completed at clock 5. clock 5: ptatn# and ptburst# deasserted at the rising edge of clock 5 indicates the pass-thru access is complete. the S5935 can accept new pass-thru accesses from the pci bus at clock 6. figure 2 shows a single cycle pass-thru write using the pass-thru address information. this provides pci cycle address information to select a specific ad- dress location within an add-on memory or periph- eral. add-on logic must latch the address for use during the data transfer. typically, the entire 32-bit address is not required. the add-on may implement a scheme where only the required number of address bits are latched. it may also be useful to use the pass-thru region identifiers, ptnum[1:0] as address lines. for example, pass-thru region 1 might be a 64k block of sram for data, while pass-thru region 2 might be 64k of sram for code storage (down- loaded from the host during initialization). using ptnum0 as address line a16 allows two unique add-on memory regions to be defined. bpclk 0123456 0h 1 2ch 0h ptatn# ptburst# ptnum[1:0] ptwr ptbe[3:0]# select# adr[6:2] be[3:0]# rd# dq[31:0] ptrdy# ptadr# pt addr pt data pci write cycle completed figure 2. single cycle pass-thru write with ptadr#
11-138 pass-thru overview S5935 the add-on ptadr# input directly accesses the pass-thru address register and drives the contents onto the data bus (no bpclk rising edge is re- quired). the byte enables, address, and select# inputs are ignored when ptadr# is asserted. rd# and wr# must not be asserted when ptadr# is asserted. clock 0: the pci bus cycle address is stored in the S5935 pass-thru address register. clock 1: the pci address is recognized as an access to pass-thru region 1. pci data is stored in the S5935 pass-thru data register. ptatn# is asserted to indicate a pass-thru access is occurring. clock 2: pass-thru status signals indicate what action is required by add-on logic. pass- thru status outputs are valid when ptatn# is active and are sampled by the add-on at the rising edge of clock 2. ptburst# deasserted. the access has a single data phase. ptnum[1:0] 01. indicates the pci access is to pass-thru region 1. ptwr asserted. the pass-thru access is a write. ptbe[3:0]# 0h. indicate the pass-thru access is 32-bits. the ptadr# input is asserted to read the pass-thru address register. the byte en- able, address, and select# inputs are changed during this clock to select the pass- thru data register during clock cycle 3. clock 3: select#, byte enable, and the address inputs remain valid to read the pass-thru data register at offset 2ch. rd# is asserted to drive data register contents onto the dq bus. clock 4: if ptrdy# is asserted at the rising edge of clock 4, ptatn# is immediately deasserted and the pass-thru access is completed at clock 5. clock 5: if add-on logic requires more time to read the pass-thru data register (slower memory or peripherals), ptrdy# can be delayed, extending the cycle. ptrdy# asserted at the rising edge of clock 5 causes ptatn# to be immediately deasserted. clock 6: ptatn# and ptburst# deasserted at the rising edge of clock 6 indicates the pass-thru access is complete. the S5935 can accept new pass-thru accesses from the pci bus at clock 7. single cycle pass-thru reads a single cycle pass-thru read operation occurs when a pci initiator reads a single value from a pass-thru region. pci single cycle transfers consists of an ad- dress phase and a one data phase. during the ad- dress phase of the pci transfer, the S5935 stores the pci address into the pass-thru address register (apta). if the S5935 determines that the address is within one of its defined pass-thru regions, it indi- cates to the add-on that a write to the pass-thru data register (aptd) is required. figure 3 shows a single cycle pass-thru read access (add-on write) using ptadr#. the add-on reads data from a source on the add-on and writes it to the aptd register. clock 0: pci address information is stored in the S5935 pass-thru address register. the pci cycle is recognized as an access to pass- thru region 1. ptatn# is asserted by the S5935 to indicate a pass-thru access is occurring. clock 1: pass-thru status signals indicate what action is required by add-on logic. pass- thru status outputs are valid when ptatn# is active and are sampled by the add-on at the rising edge of clock 1. ptburst# deasserted. the access has a single data phase. ptnum[1:0] 01. indicates the pci access was to pass-thru region 1. ptwr deasserted. the pass-thru access is a read. ptbe[3:0]# 0h. indicate the pass-thru access is 32-bits. the ptadr# input is asserted to read the pass-thru address register. the byte en- able, address, and select# inputs are changed during this clock to select the pass- thru data register during clock cycle 3. clock 2: this clock is required to avoid contention on the dq bus. time must be allowed after ptadr# is deasserted for the dq outputs to float before add-on logic attempts to write to the pass-thru data register. clock 3: select#, byte enables, and the address inputs remain valid to write the pass-thru data register at offset 2ch. if wr# is asserted at the rising edge of clock 3, data on the dq bus is latched into aptd. if ptrdy# is asserted at the rising edge of clock 3, ptatn# is immediately deasserted and the pass-thru access is completed at clock 4.
11-139 pass-thru overview S5935 clock 4: if add-on logic requires more time to write the pass-thru data register (slower memory or peripherals), ptrdy# can be delayed, extending the cycle. ptrdy# asserted at the rising edge of clock 4 causes ptatn# to be immediately deasserted and the pass-thru access is completed at clock 5. clock 5: ptatn# and ptburst# deasserted at the rising edge of clock 5 indicates the pass-thru access is complete. the S5935 can accept new pass-thru accesses from the pci bus at clock 6. pass-thru burst writes a pass-thru burst write operation occurs when a pci initiator writes multiple values to a pass-thru region. a pci burst cycle consists of an address phase and multiple data phases. during the address phase of the pci transfer, the S5935 stores the pci address into the pass-thru address register (apta). if the S5935 determines that the address is within one of its defined pass-thru regions, it captures the pci data into the pass-thru data register (aptd). after the add-on completes each read from the pass-thru data register (asserts ptrdy#), the next data phase is initiated. figure 4 shows a 6 data phase pass-thru burst write (add-on read). in this case, the add-on asserts ptadr# and then reads multiple data phases from the S5935. this works well for add-on logic which supports burst cycles. if the add-on logic does not support burst accesses, ptadr# may be pulsed be- fore each data phase. the S5935 automatically in- crements the address in the apta register during pci burst cycles. in this example ptrdy# is always asserted, indicating add-on logic is capable of ac- cepting data at a rate of one dword per clock cycle. clock 0: pci address information is stored in the S5935 pass-thru address register. clock 1: the pci address is recognized as an access to pass-thru region 1. pci data for the first data phase is stored in the S5935 pass-thru data register. ptatn# is asserted by the S5935 to indicate a pass- thru access is occurring. clock 2: pass-thru status signals indicate what action is required by add-on logic. pass- thru status outputs are valid when ptatn# is active and are sampled by the add-on at the rising edge of clock 2. figure 3. single cycle pass-thru read with ptadr# bpclk 012345 0h 1 2ch 0h ptatn# ptburst# ptnum[1:0] ptwr ptbe[3:0]# select# adr[6:2] be[3:0]# wr# dq[31:0] ptrdy# ptadr# pt addr pt data pci read cycle completed data stored in pass-thru data register 6
11-140 pass-thru overview S5935 figure 4. pass-thru burst write 10 11 12 13 9 8 7 6 5 4 3 2 1 1 0 bpclk ptatn# ptburst# ptnum[1:0] ptwr ptbe[3:0]# 0h data1 pt addr data2 data3 data4 xxxx data5 data6 xxxx xxxx 2ch 0h select# adr[6:2] ptrdy# ptadr# be[3:0]# rd# dq[31:0] valid pci data on dq bus pci burst write completed
11-141 pass-thru overview S5935 ptburst# asserted. the access has a multiple data phases. ptnum[1:0] 01. indicates the pci access was to pass-thru region 1. ptwr asserted. the pass-thru access is a write. ptbe[3:0]# 0h. indicate the pass-thru access is 32-bits. the ptadr# input is asserted to read the pass-thru address register. the byte en- able, address, and select# inputs are changed during this clock to select the pass- thru data register during clock cycle 3. clock 3: select#, byte enables, and the address inputs remain driven to read the pass-thru data register at offset 2ch. rd# is asserted to drive data register contents onto the dq bus. clock 4: add-on logic uses the rising edge of clock 4 to store data 1 from the S5935. ptrdy# asserted at the rising edge of clock 4 completes the current data phase. data 2 is driven on the add-on bus. clock 5: add-on logic uses the rising edge of clock 5 to store data 2 from the S5935. ptrdy# asserted at the rising edge of clock 5 completes the current data phase. data 3 is driven on the add-on bus. clock 6: add-on logic uses the rising edge of clock 6 to store data 3 from the S5935. ptrdy# asserted at the rising edge of clock 6 completes the current data phase. on the pci bus, irdy# has been deasserted, causing ptatn# to be deasserted. this is how a pci initiator adds wait states, if it cannot provide data quickly enough. data on the add-on bus is not valid. clock 7: because ptatn# remains deasserted, add-on logic cannot store data at the rising edge of clock 7. ptatn# is reas- serted, indicating the pci initiator is no longer adding wait states. data 4 is driven on the add-on bus. clock 8: add-on logic uses the rising edge of clock 8 to store data 4 from the S5935. ptrdy# asserted at the rising edge of clock 8 completes the current data phase. on the pci bus, irdy# has been deasserted again, causing ptatn# to be deasserted. data on the add-on bus is not valid. clock 9: the pci initiator is still adding wait states. add-on logic cannot store data while ptatn# is deasserted. clock 10: because ptatn# remains deasserted, add-on logic cannot read data at the rising edge of clock 10. ptatn# is reasserted, indicating the pci initiator is no longer adding wait states. data 5 is driven on the add-on bus. clock 11: add-on logic uses the rising edge of clock 11 to store data 5 from the S5935. ptrdy# asserted at the rising edge of clock 11 completes the current data phase. data 6 is driven on the add-on bus. clock 12: add-on logic uses the rising edge of clock 12 to store data 6 from the S5935. ptrdy# asserted at the rising edge of clock 12 completes the final data phase clock 13: ptatn# and ptburst# deasserted at the rising edge of clock 13 indicates the pass-thru access is complete. the S5935 can accept new pass-thru accesses from the pci bus at clock 15. figure 5 also shows a 5 data phase pass-thru burst write, but the add-on logic uses ptrdy# to control the rate at which data is transferred. in many applica- tions, add-on logic is not fast enough to accept data at every bpclk rising edge (every 30 ns in a 33 mhz pci system). in this example, the add-on interface accepts data every other clock. in the example, rd# is asserted during the entire add-on burst, but it can be deasserted when ptrdy# is deasserted, the S5935 functions the same under both conditions. clock 0: pci address information is stored in the S5935 pass-thru address register. clock 1: the pci address is recognized as an access to pass-thru region 1. pci data for the first data phase is stored in the S5935 pass-thru data register. ptatn# is asserted by the S5935 to indicate a pass- thru access is occurring. clock 2: pass-thru status signals indicate what action is required by add-on logic. pass- thru status outputs are valid when ptatn# is active and are sampled by the add-on at the rising edge of clock 2. ptburst# asserted. the access has multiple data phases. ptnum[1:0] 01. indicates the pci access is to pass-thru region 1. ptwr asserted. the pass-thru access is a write. ptbe[3:0]# 0h. indicate the pass-thru access is 32-bits. the ptadr# input is asserted to read the
11-142 pass-thru overview S5935 figure 5. pass-thru burst writes controlled by ptrdy# 10 11 12 13 9 8 7 6 5 4 3 2 1 0 1 0 bpclk ptatn# ptburst# ptnum[1:0] ptwr ptbe[3:0]# 0h fh data1 pt addr data2 data3 data5 xxxx data4 2ch 0h select# adr[6:2] ptrdy# ptadr# be[3:0]# rd# dq[31:0] valid pci data on dq bus pci burst write completed
11-143 pass-thru overview S5935 pass-thru address register. the byte en- able, address, and select# inputs are changed during this clock to select the pass- thru data register during clock cycle 3. clock 3: select#, byte enable, and the address inputs remain driven to read the pass-thru data register at offset 2ch. rd# is asserted to drive data register contents onto the add-on data bus. clock 4: add-on logic uses the rising edge of clock 4 to store data 1 from the S5935. ptrdy# asserted at the rising edge of clock 4 completes the current data phase. data 2 is driven on the add-on bus. clock 5: add-on logic is not fast enough to store data 2 by the rising edge of clock 5. ptrdy# deasserted at the rising edge of clock 5 extends the current data phase and data 2 remains driven on the add-on bus. clock 6: add-on logic uses the rising edge of clock 6 to store data 2 from the S5935. ptrdy# asserted at the rising edge of clock 6 completes the current data phase. data 3 is driven on the add-on bus. clock 7: add-on logic is not fast enough to store data 3 by the rising edge of clock 7. ptrdy# deasserted at the rising edge of clock 7 extends the current data phase is and data 3 remains driven on the add-on bus. clock 8: add-on logic uses the rising edge of clock 8 to store data 3 from the S5935. ptrdy# asserted at the rising edge of clock 8 completes the current data phase. on the pci bus, irdy# has been deasserted, causing ptatn# to be deasserted. data on the add-on bus is not valid. clock 9: because ptatn# remains deasserted, add-on logic cannot store data at the rising edge of clock 9. ptatn# is reas- serted, indicating the pci initiator is no longer adding wait states. data 4 is driven on the add-on bus clock 10: add-on logic uses the rising edge of clock 10 to store data 4 from the S5935. ptrdy# asserted at the rising edge of clock 10 completes the current data phase. data 5 is driven on the add-on bus. ptburst# is deasserted, indicating that on the pci bus, the burst is complete except for the last data phase. since the data is double buffered, there may be one or two pieces of data available to the add- on when ptburst# becomes inactive. this example shows the single data available case. if another piece of data was available, then ptatn# would remain active instead of going inactive at clock 12. clock 11: add-on logic is not fast enough to store data 5 by the rising edge of clock 11. ptrdy# deasserted at the rising edge of clock 11 extends the data phase and data 5 remains driven on the add-on bus. clock 12: add-on logic uses the rising edge of clock 12 to store data 5 from the S5935. ptrdy# asserted at the rising edge of clock 12 completes the final data phase. clock 13: ptatn# deasserted at the rising edge of clock 13 indicates the pass-thru access is complete. the S5935 can accept new pass-thru accesses from the pci bus at clock 14. pass-thru burst reads a pass-thru burst read operation occurs when a pci initiator reads multiple dwords from a pass-thru re- gion. a burst transfer consists of a single address and a multiple data phases. during the address phase of the pci transfer, the S5935 stores the pci address into the pass-thru address register (apta). if the S5935 determines that the address is within one of its defined pass-thru regions, it indicates to the add-on that a write to the pass-thru data register (aptd) is required. figure 6 shows a 6 data phase pass-thru burst read access (add-on write) using ptadr#. clock 0: pci address information is stored in the S5935 pass-thru address register. the pci address is recognized as an access to pass-thru region 1. ptatn# is asserted by the S5935 to indicate a pass-thru access is occurring. ptburst# is asserted by the S5935, indicating the current pass-thru read is a burst. clock 1: pass-thru status signals indicate what action is required by add-on logic. pass- thru status outputs are valid when ptatn# is active and are sampled by the add-on at the rising edge of clock 2. ptburst# deasserted, the S5935 does not yet recognize a pci burst. ptnum[1:0] 01. indicates the pci access is to pass-thru region 1. ptwr deasserted. the pass-thru access is a read. ptbe[3:0]# 0h. indicate the pass-thru access is 32-bits.
11-144 pass-thru overview S5935 figure 6. pass-thru burst read 10 11 12 13 9 8 7 6 5 4 3 2 1 1 0 bpclk ptatn# ptburst# ptnum[1:0] ptwr ptbe[3:0]# 0h fh data1 data2 data4 data6 data5 2ch 0h select# adr[6:2] ptrdy# ptadr# be[3:0]# wr# dq[31:0] valid data written into data register pt addr data3 data7
11-145 pass-thru overview S5935 the ptadr# input is asserted to read the pass-thru address register. the byte en- able, address, and select# inputs are changed during this clock to select the pass- thru data register during clock cycle 3. clock 2: select#, byte enables, and the address inputs remain driven to read the pass-thru data register at offset 2ch. clock 3: wr# asserted at the rising edge of clock 3 writes data 1 into the S5935. ptrdy# asserted at the rising edge of clock 3 completes the current data phase. clock 4: wr# asserted at the rising edge of clock 4 writes data 2 into the S5935. ptrdy# asserted at the rising edge of clock 4 completes the current data phase. clock 5: wr# asserted at the rising edge of clock 5 writes data 3 into the S5935. ptrdy# asserted at the rising edge of clock 5 completes the current data phase. on the pci bus, irdy# has been deasserted, causing ptatn# to be deasserted. this is how a pci initiator adds wait states, if it cannot read data quickly enough. clock 6: ptatn# remains deasserted at the rising edge of clock 6. the add-on cannot write data 4 until ptatn# is asserted. ptatn# is reasserted during the cycle, indicating the pci initiator is no longer adding wait states. add-on logic continues to drive data 4 on the add-on bus. clock 7: wr# asserted at the rising edge of clock 7 writes data 4 into the S5935. ptrdy# asserted at the rising edge of clock 7 completes the current data phase. on the pci bus, irdy# has been deasserted, causing ptatn# to be deasserted. the pci initiator is adding wait states. clock 8: ptatn# remains deasserted at the rising edge of clock 8. the add-on cannot write data 5 until ptatn# is asserted. add-on logic continues to drive data 5 on the add-on bus. clock 9: ptatn# remains deasserted at the rising edge of clock 9. the add-on cannot write data 5 until ptatn# is asserted. add-on logic continues to drive data 5 on the add-on bus. ptatn# is reasserted during the cycle, indicating the pci initiator is done adding wait states. clock 10: wr# asserted at the rising edge of clock 10 writes data 5 into the S5935. ptrdy# asserted at the rising edge of clock 10 completes the current data phase. clock 11: wr# asserted at the rising edge of clock 11 writes data 6 into the S5935. ptrdy# asserted at the rising edge of clock 11 completes the final data phase. clock 12: ptburst# is deasserted at the rising edge of clock 12 indicating the pass-thru burst is complete. the S5935 can accept new pass-thru accesses from the pci bus at clock 14. any data written into the pass- thru data register is not required and is never passed to the pci interface (as ptrdy# is not asserted at the rising edge of clock 13). figure 7 also shows a 5 data phase pass-thru burst read, but the add-on logic uses ptrdy# to control the rate at which data is transferred. in many applica- tions, add-on logic is not fast enough to provide data every bpclk (every 30 ns in a 33 mhz pci system). in this example, the add-on interface writes data ev- ery other clock cycle. wr# is shown asserted during the entire add-on burst, but wr# can be deasserted when ptrdy# is deasserted, the S5935 functions the same under both conditions. clock 0: pci address information is stored in the S5935 pass-thru address register. the pci address is recognized as an access to pass- thru region 1. ptatn# is asserted by the S5935 to indicate a pass-thru access is occurring. ptburst# is asserted by the S5935, indicating the current pass-thru read is a burst. clock 1: pass-thru status signals indicate what action is required by add-on logic. pass- thru status outputs are valid when ptatn# is active and are sampled by the add-on at the rising edge of clock 2. ptburst# deasserted, the S5935 does not yet recognize a pci burst. ptnum[1:0] 01. indicates the pci access is to pass-thru region 1. ptwr deasserted. the pass-thru access is a read. ptbe[3:0]# 0h. indicate the pass-thru access is 32-bits. the ptadr# input is asserted to read the pass-thru address register. the byte en- able, address, and select# inputs are changed during this clock to select the pass- thru data register during clock cycle 3.
11-146 pass-thru overview S5935 figure 7. pci burst read controlled by ptrdy# 10 11 12 13 9 8 7 6 5 4 3 2 1 0 1 0 bpclk ptatn# ptburst# ptnum[1:0] ptwr ptbe[3:0]# 0h fh data1 pt addr data2 data3 data5 2ch 0h select# adr[6:2] ptrdy# ptadr# be[3:0]# wr# dq[31:0] valid data written into data register data4
11-147 pass-thru overview S5935 clock 2: select#, byte enable, and the address inputs remain driven to read the pass-thru data register at offset 2ch. clock 3: wr# asserted at the rising edge of clock 3 writes data 1 into the S5935. ptrdy# asserted at the rising edge of clock 3 completes the current data phase. clock 4: add-on logic drives data 2 on the add-on bus, but ptrdy# deasserted at the rising edge of clock 4 extends the current data phase. clock 5: wr# asserted at the rising edge of clock 5 writes data 2 into the S5935. ptrdy# asserted at the rising edge of clock 5 completes the current data phase. clock 6: add-on logic drives data 3 on the add-on bus, but ptrdy# deasserted at the rising edge of clock 6 extends the current data phase. clock 7: wr# asserted at the rising edge of clock 7 writes data 3 into the S5935. ptrdy# asserted at the rising edge of clock 7 completes the current data phase. on the pci bus, irdy# has been deasserted, causing ptatn# to be deasserted. this is how a pci initiator adds wait states, if it cannot read data quickly enough. clock 8: ptatn# remains deasserted at the rising edge of clock 8. the add-on cannot write data 4 until ptatn# is asserted. add-on logic continues to drive data 4 on the add-on bus. ptatn# is reasserted during the cycle, indicating the pci initiator is done adding wait states. clock 9: wr# asserted at the rising edge of clock 9 writes data 4 into the S5935. ptrdy# asserted at the rising edge of clock 9 completes the current data phase. clock 10: add-on logic drives data 5 on the add-on bus, but ptrdy# deasserted at the rising edge of clock 10 extends the current data phase. clock 11: ptatn# remains deasserted at the rising edge of clock 11. the add-on does not have to write data 5 until ptatn# is asserted. add-on logic continues to drive data 5 on the add-on bus. ptatn# is reasserted during the cycle, indicating the pci initiator is done adding wait states. clock 12: ptrdy# asserted at the rising edge of clock 12 completes the final data phase. any data written into the pass-thru data register is not required and is never passed to the pci interface (as ptrdy# is not asserted at the rising edge of clock 13). clock 13: ptatn# and ptburst# deasserted at the rising edge of clock 13 indicates the pass-thru access is complete. the S5935 can accept new pass-thru accesses from the pci bus at clock 14. add-on pass-thru disconnect operation slow pci targets are prevented from degrading pci bus performance. the pci specification allows only 16 clocks for a target to respond before it must re- quest a retry on single data phase accesses. for burst accesses, the first data phase is allowed 16 clocks to complete, all subsequent data phases are allowed 8 clocks each. this requirement allows other pci initiators to use the bus while the target request- ing the retry completes the original access. figure 8 shows the conditions that cause the S5935 to request a retry from a pci initiator on the first data phase of a pci read operation. frame# is asserted during the rising edge of pci clock 1. from this point, the S5935 has 16 clock cycles to respond to the initiator with trdy# (completing the cycle). frame# figure 8. target requested retry on the first pci data phase 18 17 16 15 4 3 2 1 17 16 15 14 3 2 1 pciclk frame# stop# bpclk ptatn# ptrdy# ptrdy# must be asserted by this time to present disconnecting ptrdy# asserted too late so s593x disconnects (asserts stop#)
11-148 pass-thru overview S5935 could remain asserted, indicating a burst read, but the retry request conditions are identical for a single data phase read and the first data phase of a burst read. bpclk is identical to pciclk, lagging by a propaga- tion delay of a few nanoseconds (see chapter 13). ptatn# is asserted on the add-on interface as soon as frame# is sampled active at a pciclk rising edge. after ptatn# is asserted, ptrdy# must be as- serted by the 15th bpclk rising edge to prevent the S5935 from requesting a retry. trdy# is asserted on the pci interface one clock cycle after ptrdy# is asserted on the add-on interface. if add-on logic does not return ptrdy# by the 15th bpclk rising edge, the S5935 asserts stop#, requesting a retry from the pci initiator. for pass-thru write operations, the S5935 never dis- connects on the first or second pci data phases of a burst. the first data and second phases are always accepted immediately by the S5935. no further ac- tion is required by the pci initiator. the only situation where the S5935 may respond to a pass-thru write with a retry request is after the second data phase of a pass-thru burst write. figure 9 shows the conditions required for the S5935 to request a retry after the second data phase of a burst transfer. this figure applies to both pass-thru burst read and write operations. the previous data phase is completed with the asser- tion of ptrdy# at the rising edge of bpclk 0. add- on logic must assert ptrdy# by the rising edge of bpclk 8 to prevent the S5935 from asserting stop#, requesting a retry. meeting this condition al- lows the S5935 to assert trdy# by the rising edge of pciclk 8, completing the data phase with requir- ing a retry. when the S5935 requests a retry, the pass-thru sta- tus indicators remain valid (allowing the add-on logic to complete the access). ptburst# is the exception to this. ptburst# is deasserted to indicate that there is currently no burst in progress on the pci bus. the other pass-thru status indicators remain valid until ptatn# is deasserted. figure 10 shows the add-on bus interface signals after the S5935 re- quests a retry. as long as ptatn# remains asserted, add-on logic should continue to transfer data. for pci read opera- tions, one add-on write operation is required after a retry request. after the add-on write, asserting ptrdy# deasserts ptatn#. for pass-thru write operations, one or two data transfers may remain after the S5935 signals a retry. two data transfers are possible because the S5935 has a double buffered pass-thru data register used for writes. a pci burst may have filled both registers before the S5935 requested a retry. ptatn# re- mains asserted until both are emptied. ptrdy# must be asserted after each read from the pass-thru data register. if both registers are full, ptatn# is deasserted only after ptrdy# is asserted the sec- ond time. the S5935 only accepts further pci ac- cesses after both registers are emptied. 8-bit and 16-bit pass-thru add-on bus interface the S5935 allows a simple interface to devices with 8-bit or 16-bit data buses. each pass-thru region may be defined as 8-, 16-, or 32-bits, depending on the contents of the nv memory boot device loaded into the pci base address configuration registers during initialization. the pass-thru add-on interface internally controls byte lane steering to allow access to the 32-bit pass-thru data register (aptd) from 8- bit or 16-bit add-on buses. figure 9. target requested retry after the first data phase of a burst operation 8 7 6 1 9 8 7 2 1 0 pciclk frame# stop# bpclk ptatn# ptrdy# latest assertion of ptrdy# to prevent disconnect ptrdy# asserted too late, results in disconnect pci data transfer
11-149 pass-thru overview S5935 figure 10. pass-thru signals after a target requested retry bpclk stop# 1 0h fh 2ch 0h ptatn# ptburst# ptnum[1:0] ptwr ptbe[3:0]# select# adr[6:2] be[3:0]# rd# dq[31:0] ptrdy# data internal byte lane steering may be used whether the mode input defines a 16-bit or 32-bit add-on interface. when a 16-bit add-on interface is used, the adr1 in- put is used in conjunction with the byte enables to steer data into the proper aptd register byte locations. if mode defines a 16-bit interface, only 16-bits of ad- dress are driven when ptadr# is asserted. if more than 16-bits of address are required, the pass-thru ad- dress register (apta) must be read with select#, rd#, byte enable and address inputs. two consecutive reads are required to latch all of the address information (one with adr1=0, one with adr1=1). regardless of mode, various data widths may be used. for pass-thru writes (add-on aptd reads), add-on logic must read the aptd register one byte or one word at a time (depending on the add-on bus width). the internal data bus is steered to the correct portion of aptd using the be[3:0]# inputs. table 1 shows the byte lane steering mechanism used by the S5935. the byten symbols indicate data bytes in the pass-thru data register. when a read is performed with a ben# input as- serted, the corresponding ptben# output is deasserted. add-on logic cycles through the byte en- ables to read the entire aptd register. once all data is read (ptbe[3:0]# are deasserted), ptrdy# is as- serted by the add-on, completing the access. for pass-thru reads (add-on aptd writes), the bytes requested by the pci initiator are indicated by the ptbe[3:0]# outputs. add-on logic uses the ptbe[3:0]# signals to determine which bytes must be written (and which bytes have already been written). for example, a 3 2 1 0 dq[31:24] aptd register read byte lane steering byte enables dq[23:16] dq[15:8] dq[7:0] x x x 0 byte3 byte2 byte1 byte0 x x 0 1 byte3 byte2 byte1 byte1 x 0 1 1 byte3 byte2 byte3 byte2 0 1 1 1 byte3 byte3 byte3 byte3 table 1. byte lane steering for pass-thru data register read (pci write) pt-bus width byte3 aptd register write byte lane steering defined byte2 byte1 byte0 32-bit data bus dq[31:24] dq[23:16] dq[15:8] dq[7:0] 16-bit data bus dq[15:8] dq[7:0] dq[15:8] dq[7:0] 8-bit data bus dq[7:0] dq[7:0] dq[7:0] dq[7:0] table 2. byte lane steering for pass-thru data register write (pci read) pci initiator performs a byte pass-thru read from an 8- bit pass-thru region with pci be2# asserted. on the add-on interface, ptbe2# is asserted, indicating that the pci initiator requires data in this byte. once the add-on writes aptd, byte 2, ptbe2# is deasserted, and the add-on may assert ptrdy#, completing the cycle. table 2 shows how the external add-on data bus is steered to the pass-thru data register bytes. this mechanism is determined by the pass-thru region bus width defined during initialization (see section 12.3). the byten symbols indicate data bytes in the pass- thru data register. for example, an 8-bit add-on write with be1# asserted results in the data on dq[7:0] being steered into byte1 of the aptd register.
11-150 pass-thru overview S5935 to write data into the aptd register, the ptben# output and the ben# input must both be asserted. the following describes how aptd register writes are controlled: write byte3 if ptbe3# and be3# are asserted write byte2 if ptbe2# and be2# are asserted write byte1 if ptbe1# and be1# are asserted write byte0 if ptbe0# and be0# are asserted after each byte is written into the pass-thru data register, its corresponding ptbe[3:0]# output is deasserted. this allows add-on logic to monitor which bytes have been written, and which bytes re- main to be written. when all bytes requested by the pci initiator have been written, the ptbe[3:0]# are all be deasserted, and the add-on asserts ptrdy#. figure 11 shows pass-thru operation for a region defined for an 8-bit add-on bus interface. as the 8-bit device is connected only to dq[7:0], the device must access aptd one byte at a time. the pci initiator has performed a 32-bit write of 08d49a30h to pass-thru region zero. ptbe[3:0]# are all asserted. at clock 1, the add-on begins read- ing the aptd register (asserting select#, adr[6:2], and rd#). add-on logic asserts be0#, and byte0 of aptd is driven on dq[7:0]. at the rising edge of clock 2, be0# is sampled by the S5935 and ptbe0# is deasserted. ptbe[3:1]# are still asserted. during clock 2, only be1# is activated, and byte1 of aptd is driven on dq[7:0]. at the rising edge of clock 3, be1# is sampled by the S5935 and ptbe1# is deasserted. ptbe[3:2]# are still asserted. this process continues until all bytes have been read from the aptd register. during clock 5, rd# is deasserted and ptrdy# is asserted. ptrdy# is sampled by the S5935 at the rising edge of clock 6, and the current data phase is completed. ptatn# is deasserted and new data can be written from the pci bus. in this example, the byte enables are asserted, sequentially, from be0# to be3#. this is not re- quired, bytes may be accessed in any order. new data is written by the pci initiator and is avail- able in the aptd register during clock 7. rd# is asserted and the byte enables are cycled again. with each new data from the pci bus, the add-on se- quences through the byte enables to access aptd via dq[7:0]. for 16-bit peripheral devices, the byte steering works in the same way. because the add-on data bus is 16-bits wide, only two 16-bit cycles are required to access the entire aptd register. two byte enables can be asserted during each access. in figure 11, rd# is held low and the byte enables are changed each clock. this assumes the add-on can accept data at one byte per clock. this is the fastest transfer possible. for slower devices, wait states may be added. as long as the byte enables remain in a given state, the corresponding byte of the aptd register is con- nected to the dq bus (the rd# or wr# pulse may also be lengthened). each access may be extended for slower add-on devices, but extending individual data phases for pass-thru cycles may result in the S5935 requesting retries by the initiator. 10 11 12 13 9 8 7 6 5 4 3 2 3ch 3ch 2ch fh 0h 1h 3h 7h fh 0h 1h 3h 7h fh 1 bpclk ptatn# ptwr ptbe[3:0]# ptnum[1:0] ptburst# fh bh eh dh 7h fh eh dh bh 7h fh d4h 30h 9ah 08h ddh cch bbh aah addr 0 select# be[3:0]# ptadr# ptrdy# adr[6:2] rd# dq[7:0] figure 11. pass-thru write to an 8-bit add-on device note: 8 bit mode bes are e, d, b, 7; 16 bit mode bes are c, 3.
11-151 pass-thru overview S5935 configuration the S5935 pass-thru interface utilizes four base ad- dress registers (badr1:4). each base address register corresponds to a pass-thru region. the contents of these registers during initialization deter- mine the characteristics of that particular pass-thru region. each region can be mapped to memory or i/o space. memory mapped devices can, optionally, be mapped below 1 mbyte and can be identified as prefetchable. both memory and i/o regions can be configured as 8-, 16-, or 32-bits wide. the designer has the option to use 1, 2, 3, 4 or none of the pass-thru regions. base address registers are loaded during initialization from the external non- volatile boot device. without an external boot device, the default value for the badr registers is zero (re- gion disabled). the base address registers are the only registers that define pass-thru operation. S5935 base address register definition some bits in the base address registers have specific functions. the following bits have special functions: d0 memory or i/o mapping. if this bit is clear, the region should be memory mapped. if this bit is set, the region should be i/o mapped. d2:1 location of a memory region. these bits request that the region be mapped in a particular part of memory. these bit definitions are only used for memory mapped regions. d2 d1 location 0 0 anywhere in 32-bit memory space 0 1 below 1 mbyte in memory space (real mode address space) 1 0 anywhere in 64-bit memory space (not valid for the S5935) 1 1 reserved d3 prefetchable. for memory mapped regions, the region can be defined as cacheable. if set, the region is cacheable. if this bit is clear, the region is not. d31:30 pass-thru region bus width. these two bits are used by the S5935 to define the data bus width for a pass-thru region. regard- less of the programming of other bits in the badr register, if d31:30 are zeros, the pass-thru region is disabled. d31 d30 add-on bus width 0 0 region disabled 0 1 8-bits 1 0 16-bits 1 1 32-bits badr1:4 bits d31:30 are used only by the S5935. when the host reads the base address registers during configuration cycles, they always return the same value as d29. if d29 is zero, d31:30 return zero, indicating the region is disabled. if d29 is one, d31:30 return one. this operation limits each pass- thru region to a maximum size of 512 mbytes of memory. for i/o mapped regions, the pci specification allows no more than 256 bytes per region. the S5935 al- lows larger regions to be requested by the add-on, but a pci bios will not allocate the i/o space and will probably disable the region. creating a pass-thru region page 3-40 describes the values that must be pro- grammed into the non-volatile boot device to request various block sizes and characteristics for pass-thru regions. after reset, the S5935 downloads the con- tents of the boot device locations 54h, 58h, 5ch, and 60h into masks for the corresponding base address registers. the following are some examples for vari- ous pass-thru region definitions: nv memory contents pass-thru region definition 54h = bffff002h pass-thru region 1 is a 4kbyte region, mapped below 1 mbyte in memory space with a 16-bit add-on data bus. this memory region is not cacheable. 58h = 3xxxxxxxh pass-thru region 2 is disabled. (d31:30 = 00.) 60h = ffffff81h pass-thru region 3 is a 32- bit, 128 byte i/o-mapped region. 64h = 00000000h pass-thru region 4 is dis- abled. during the pci bus configuration, the host cpu writes all ones to each base address register, and then reads the contents of the registers back. the mask downloaded from the boot device determines which bits are read back as zeros and which are read back as ones. the number of zeros read back indicates the amount of memory or i/o space a particular S5935 pass-thru region is requesting.
11-152 pass-thru overview S5935 after the host reads all base address registers in the system (as every pci device implements from one to six), the pci bios allocates memory and i/o space to each base address region. the host then writes the start address of each region back into the base ad- dress registers. the start address of a region is al- ways an integer multiple of the region size. for example, a 64 kbyte memory region is always mapped to begin on a 64k boundary in memory. it is important to note that no pci device can xbe abso- lutely located in system memory or i/o space. all map- ping is determined by the system, not the application. accessing a pass-thru region after the system is finished defining all base address regions within a system, each base address register contains a physical address. the application software must now find the location in memory or i/o space of its hardware. pci systems provide bios or operating system function calls for application software to find particular devices on the pci bus based on vendor id and device id values. this allows application software to access the devices configuration registers. the base address register values in the S5935s configuration space may then be read and stored for use by the program to access application hardware. the value in the base address registers is the physical address of the first location of that pass- thru region. some processor architectures allow this address to be used directly to access the pci device. for intel architecture systems, the physical address must be changed into a segment/offset combination. for real mode operation in an intel architecture sys- tem (device mapped below 1 mbyte in memory), creat- ing a segment/offset pair is relatively simple. to calculate a physical address, the cpu shifts the seg- ment register 4 bits to the left and adds the offset (resulting in a 20 bit physical address). the value in the base address register must be read and shifted 4 bits to the right. this is the segment value and should be stored in one of the segment registers. an offset of zero (stored in si, di or another offset register) ac- cesses the first location in the pass-thru region.
12-153 electrical characteristics S5935 absolute maximum ratings . pci input/output electrical characteristics symbol parameter min max units test conditions notes supply voltage 4.75 5.25 v input high voltage 2.0 v input low voltage ?.5 0.8 v input high leakage current 70 ua 1 input low leakage current 70 ua 1 output high voltage 2.4 v output low voltage 0.55 v 2 input pin capacitance 10 pf 3 clk pin capacitance 5 12 pf idsel pin capaticance 8 pf v cc v ih v il i il v oh v ol c in c clk c idsel v in = 2.7 v in = 0.5 i out = C2ma i out = 3ma, 6ma m m i ih r e t e m a r a pn i mx a ms t i n u e r u t a r e p m e t e g a r o t s5 5 C5 2 1 c v ( e g a t l o v y l p p u s c c )3 . 0 C0 . 7s t l o v e g a t l o v n i p t u p n i5 . 0 Cv c c 0 . 5 +s t l o v n o i t a p i s s i d r e w o p5 0 . 1 @ s t t a w z h m 3 3 dc characteristics the following table summarizes the required parameters defined by the pci specification as they apply to the S5935 controller. notes: 1. input leakage applies to all inputs and bi-directional buffers. 2. pci bus signals without pull-up resistors will provide the 3 ma output current. signals which require a pull-up resistor will provide 6 ma output current. 3. the pci specification limits all pci inputs not located on the motherboard to 10 pf (the clock is allowed to be 12 pf). ?
12-154 electrical characteristics S5935 pci bus signals the following table summarizes the pci bus dc parameters defined by the pci specification as they apply to the S5935 controller. l a n g i se p y tn o i t c e r i dx a ms t i n us e t o n k l ct u p n i # t s rt u p n i # a t n in i a r d n e p ot u p t u o4a m ] 0 : 1 3 [ d as / tl a n o i t c e r i d - i ba m # q e rs / tt u p t u o4a m # t n gt u p n i # ] 0 : 3 [ e b / cs / tl a n o i t c e r i d - i b4a m # l e s v e ds / t / sl a n o i t c e r i d - i ba m # e m a r fs / t / sl a n o i t c e r i d - i b4a m # y d r is / t / sl a n o i t c e r i d - i b4a m # y d r ts / t / sl a n o i t c e r i d - i b4a m # r r e ps / t / sl a n o i t c e r i d - i b4a m r a ps / tl a n o i t c e r i d - i b4a m # r r e sn i a r d n e p ot u p t u o4a m # p o t ss / t / sl a n o i t c e r i d - i b4a m # k c o lt u p n i l e s d it u p n i
12-155 electrical characteristics S5935 add-on bus signals the following table summarizes the add-on bus dc parameters as they apply to the S5935 controller. l a n g i se p y tn o i t c e r i dx a ms t i n us e t o n k l c pt u p t u o8a m # q r it u p t u o4a m # t s r s y st u p t u o4a m ] 2 : 6 [ r d at u p n i t c e l e st u p n i ] 2 : 6 [ r d at u p n i # ] 0 : 3 [ e bt u p n i # d rt u p n i # r wt u p n i ] 0 : 1 3 [ q ds / tl a n o i t c e r i d - i b4a m l l u f r wt u p t u o4a m y t p m e d rt u p t u o4a m # o f i f d rt u p n i # o f i f r wt u p n i # n t a t pt u p t u o4a m # t s r u b t pt u p t u o4a m # r d a t pt u p n i # y d r t pt u p n i r w t pt u p t u o4a m # ] 0 : 3 [ e b t pt u p t u o4a m ] 0 : 1 [ m u n t pt u p t u o4a m ] 0 : 7 [ q es / tl a n o i t c e r i d - i b1a m ] 0 : 8 [ a es / tt u p t u o1a m ] 9 : 5 1 [ a et u p t u o1a m e d o mt u p n i t s e tt u p t u o4a m # t l ft u p n i l c s / # d r et u p t u o1a m a d s / # r w es / tl a n o i t c e r i d - i b1a m
12-156 electrical characteristics S5935 ac characteristics pci bus timings notes: 1. minimum times are for unloaded outputs, maximum times are for 50 pf equivalent loads. functional operation range (v cc =5.0v 5%, 0?c to 70?c, 50 pf load on outputs) symbol tcl cycle time 30 ns t1 high time 12 ns t2 low time 12 ns t3 rise time (0.8v to 2.0v) 3 ns t4 fall time (2.0v to 0.8v) 3 ns t5 output valid delay (bussed signals) output valid delay (point-to-point signals) 2 2 11 12 ns note 1 t6 float to active delay 2 ns t7 active to float delay 28 ns t8 rising edge setup (bussed signals) rising edge setup (gnt#) rising edge setup (req#) 7 10 12 ns t9 hold from pci clock rising edge 0 ns t10 pciclk to bpclk delay 2 6.5 ns parameter min max units notes figure 1. pci clock timing t 1 v ih2 t 2 t 3 t 4 2.0 2.0 0.8 2.0 2.0 0.8 0.8 tcl
12-157 electrical characteristics S5935 figure 2. pci output timing figure 3. pci input timing pci clk t 8 t 9 input inputs valid pci clk output delay tri-state output t 5 t 6 1.5 1.5 1.5 1.5 t 7
12-158 electrical characteristics S5935 2.0 t 1 2.0 0.8 t 2 t 3 t 4 2.0 0.8 2.0 0.8 tcl v ih2 add-on bus timings figure 4. add-on clock timing t 8 pci clk bpclk figure 5. pass-thru clock relationship to pci clock t 10
12-159 electrical characteristics S5935 synchronous rdfifo# timing figure 6. synchronous rdfifo# timing l o b m y sr e t e m a r a pn i mx a ms t i n us e t o n t 4 4 1 e g d e g n i s i r k l c p b p t p u t e s # o f i f d r 86 2s n1 t 5 4 1 e m i t w o l # o f i f d r 8s n t 6 4 1 n e v i r d ] 0 : 1 3 [ q d o t w o l # o f i f d r 2 1s n t 8 4 1 t a o l f ] 0 : 1 3 [ q d o t h g i h # o f i f d r 3s n t 9 4 1 e g d e g n i s i r k l c p b m o r f d i l a v ] 0 : 1 3 [ q d 6 1s n3 t 5 6 1 e g d e g n i s i r k l c p b m o r f d i l a v y t p m e d r o f i f n o - d d a o t i c p 2 1s n2 t 6 6 1 e g d e g n i s i r k l c p b m o r f d i l a v f r f o f i f n o - d d a o t i c p 0 8s n functional operation range (v cc =5.0v 5%, 0?c to 70?c t a 50 pf loaf on outputs). notes: 1. min and max times are indicated to allow increased valid data time as shown by dashed lines. 2. state change of rdempty shown below is reference only. actual change would indicate no data 3 available. 3. valid applies after first access. first access is async with following as sync accesses. rdfifo# dq[31:0] t 165 rdempty frf 8ns old valid new valid t 166 bpclk 6ns 14ns t 144 t 146 1 t 144 max 10ns t 148 234 t 149
12-160 electrical characteristics S5935 synchronous wrfifo# timing functional operation range (v cc = 5.0v 5%, 0?c to 70?c t a 50 pf load on outputs). notes: 1. state change of wrfull shown below is reference only. actual change would indicate no data 3 written. figure 7. synchronous wrfifo# timing l o b m y sr e t e m a r a pn i mx a ms t i n us e t o n t 0 5 1 e g d e g n i s i r k l c p b o t p u t e s # o f i f r w 2 1s n t a 0 5 1 e g d e g n i s i r k l c p b o t e m i t d l o h # o f i f r w 0s n t 1 5 1 e g d e g n i s i r k l c p b o t p u t e s ] 0 : 1 3 [ q d 7 t a 1 5 1 e g d e g n i s i r k l c p b m o r f d l o h ] 0 : 1 3 [ q d 0 t 7 6 1 e g d e g n i s i r k l c p b m o r f d i l a v l l u f r w i c p o t n o - d d a 1 1s n1 t 8 6 1 e g d e g n i s i r k l c p b m o r f d i l a v e w f o f i f i c p o t n o - d d a 6 2s n wrfifo# dq[31:0] t 167 wrfull fwe 6ns old valid new valid t 168 bpclk t 150 t 151 1 2 3 t 150a
12-161 electrical characteristics S5935 asynchronous rd# register access timing functional operation range (v cc =5.0v 5%, 0?c to 70?c t a 50 pf load on outputs). figure 8 asynchronous rd# fifo timing l o b m y sr e t e m a r a pn i mx a ms t i n us e t o n t 0 1 1 e g d e g n i s i r # d r o t p u t e s # t c e l e s 0 1s n t a 4 1 1 e g d e g n i s i r # d r m o r f d l o h # t c e l e s 1 -s n t 4 1 1 e g d e g n i s i r # d r o t p u t e s ] 2 : 6 [ r d a 8 1s n t a 4 1 1 e g d e g n i s i r # d r m o r f d l o h ] 2 : 6 [ r d a 0 t 8 1 1 e g d e g n i s i r # d r o t p u t e s # ] 0 : 3 [ e b 2 1s n t a 8 1 1 e g d e g n i s i r # d r m o r f d l o h # ] 0 : 3 [ e b 0s n t 9 2 1 e m i t h g i h # d r 6 1s n t 0 3 1 e m i t w o l # d r 5 1s n t 3 3 1 e g d e g n i l l a f # d r m o r f d i l a v ] 0 : 1 3 [ q d 5 1s n t a 3 3 1 e g d e g n i s i r # d r m o r f d l o h ] 0 : 1 3 [ q d 3s n t 2 5 1 e g d e g n i s i r # d r m o r f d i l a v s u t a t s y t p m e d r 0 1s n t 3 5 1 e g d e g n i s i r # d r m o r f d i l a v s u t a t s f r f 5 7s n select# t 110 adr[6:2] be[3:0]# dq[31:0] rd# t 114 t 118 t 133 t 130 t 133a wrfull 5ns t 152 fwe t 153 t 129 rdempty frf
12-162 electrical characteristics S5935 asynchronous wr# register access timing figure 9. asynchronous wr# fifo timing l o b m y sr e t e m a r a pn i mx a ms t i n us e t o n t 1 1 1 e g d e g n i s i r # r w o t p u t e s # t c e l e s 7s n t a 1 1 1 e g d e g n i s i r # r w m o r f d l o h # t c e l e s 0s n t 5 1 1 e g d e g n i s i r # r w o t p u t e s ] 2 : 6 [ r d a 8s n t a 5 1 1 e g d e g n i s i r # r w m o r f d l o h ] 2 : 6 [ r d a 0s n t 9 1 1 e g d e g n i s i r # r w o t p u t e s # ] 0 : 3 [ e b 5s n t a 9 1 1 e g d e g n i s i r # r w m o r f d l o h # ] 0 : 3 [ e b 0s n t 1 3 1 e m i t h g i h # r w d b ts n t 2 3 1 e m i t w o l # r w 4s n t 4 3 1 e g d e g n i s i r # r w o t p u t e s ] 0 : 1 3 [ q d 2s n t a 4 3 1 e g d e g n i s i r # r w m o r f d l o h ] 0 : 1 3 [ q d 3s n t 4 5 1 e g d e g n i s i r # r w m o r f d i l a v s u t a t s l l u f r w 7 2s n t 5 5 1 e g d e g n i s i r # r w m o r f d i l a v s u t a t s e w f 0 4s n select# t 111 adr[6:2] be[3:0]# dq[31:0] wr# t 115 t 119 t 134 t 132 t 132a wrfull 13ns t 154 fwe t 155 functional operation range (v cc =5.0v 5%, 0?c to 70?c t 50 pf load on outputs).
12-163 electrical characteristics S5935 functional operation range (v cc =5.0v 5%, 0?c to 70?c t 50 pf load on outputs). synchronous rd# fifo timing figure 10. synchronous rd# fifo timing notes: 1. data is valid for 22ns for a 31ns t 124 rd# setup. 2. rd# and select# must both be asserted to dric=ve dq[31:0] - delay is from the last one asserted. 3. when increasing setup times, adr[6:2], be[3:0]#, select#, and rd# timing relations remain relative to each other as shown. 4. min and max are indicated to allow increased valid data time as shown by dashed lines. first accesses are async. l o b m y sr e t e m a r a pn i mx a ms t i n us e t o n t 2 1 1 e g d e g n i s i r k l c p b o t p u t e s # t c e l e s 0 10 3s n4 t a 2 1 1 e g d e g n i s i r k l c p b m o r f d l o h # t c e l e s 2s n t 6 1 1 e g d e g n i s i r k l c p b o t p u t e s ] 2 : 6 [ r d a 4 14 3s n4 t a 6 1 1 e g d e g n i s i r k l c p b m o r f d l o h ] 2 : 6 [ r d a 1s n t 0 2 1 e g d e g n i s i r k l c p b o t p u t e s # ] 0 : 3 [ e b 99 2s n4 t a 0 2 1 e g d e g n i s i r k l c p b m o r f d l o h # ] 0 : 3 [ e b 3s n t 5 2 1 n e v i r d ] 0 : 1 3 [ q d o t w o l # d r 7 1s n1 t 8 2 1 t a o l f ] 0 : 1 3 [ q d o t h g i h # d r 8s n t 6 5 1 e g d e g n i s i r k l c p b o t d i l a v s u t a t s y t p m e d r 3 1s n t 7 5 1 e g d e g n i s i r k l c p b o t d i l a v s u t a t s f r f 4 7s n t 4 2 1 e g d e g n i s i r k l c p b o t p u t e s # d r 1 11 3s n4 t a 4 2 1 e g d e g n i s i r k l c p b m o r f d l o h # d r 1s n t 7 2 1 e g d e g n i s i r k l c p b m o r f d i l a v ] 0 : 1 3 [ q d 6s n bpclk select# t 112 adr[6:2] be[3:0]# dq[31:0] rd# t 116 t 120a t 125 t 128 t 124a t 112a t 116a t 120 t 124 rdempty frf 5ns t 156 t 157 t 112 max
12-164 electrical characteristics S5935 synchronous multiple rd# fifo timing figure 11. synchronous rd# fifo timing bpclk select# adr[6:2] be[3:0] dq[31:0] rd# t 112 t 116 t 120 t 124 1 t 112a t 120a t 124a rdempty frf 3 2 4 5 6 7 8 11ns 5ns 2ns 5ns t 156 t 157 t 116a t 125
12-165 electrical characteristics S5935 synchronous wr# fifo timing functional operation range (v cc =5.0v 5%, 0?c to 70?c t a 50 pf load on outputs). figure 12. synchronous wr# fifo timing bpclk select# t 113 adr[6:2] be[3:0]# dq[31:0] wr# t 117 t 121 t 123 t 122 t 123a wrfull 3ns t 159 fwe 4ns t 160 l o b m y sr e t e m a r a pn i mx a ms t i n us e t o n t 3 1 1 e g d e g n i s i r k l c p b o t p u t e s # t c e l e s 9 1s n t a 3 1 1 e g d e g n i s i r k l c p b m o r f d l o h # t c e l e s 0s n t 7 1 1 e g d e g n i s i r k l c p b o t p u t e s ] 2 : 6 [ r d a 0 2s n t a 7 1 1 e g d e g n i s i r k l c p b m o r f d l o h ] 2 : 6 [ r d a 0s n t 1 2 1 e g d e g n i s i r k l c p b o t p u t e s # ] 0 : 3 [ e b 5 1s n t a 1 2 1 e g d e g n i s i r k l c p b m o r f d l o h # ] 0 : 3 [ e b 0s n t 3 2 1 e g d e g n i s i r k l c p b o t p u t e s ] 0 : 1 3 [ q d 2 1s n t a 3 2 1 e g d e g n i s i r k l c p b m o r f d l o h ] 0 : 1 3 [ q d 1s n t 2 2 1 e g d e g n i s i r k l c p b o t p u t e s # r w 0 2s n t a 2 2 1 e g d e g n i s i r k l c p b m o r f d l o h # r w 0s n t 9 5 1 e g d e g n i s i r k l c p b o t d i l a v s u t a t s l l u f r w 8 1s n t 0 6 1 e g d e g n i s i r k l c p b o t d i l a v s u t a t s e w f 6 2s n
12-166 electrical characteristics S5935 synchronous multiple wr# fifo timing figure 13. synchronous multiple wr# fifo timing bpclk select# adr[6:2] be[3:0]# dq[31:0] wr# t 113 t 117 t 121 t 122 t 123 t 123a 1 t 123a t 123 2 3 4 5 6 7 8 wrfull 3ns t 159 fwe 4ns t 123a t 160
12-167 electrical characteristics S5935 target S5935 pass-thru interface timings functional operation range (v cc =5.0v 5%, 0?c to 70?c, 50 pf load on outputs) notes: 1. this timing also applies to the use of be[3:0]# to control dq[31:0] drive. l o b m y sr e t e m a r a pn i mx a ms t i n us e t o n t a 0 1 e g d e g n i s i r k l c p b o t p u t e s # t c e l e s 3s n t a 1 1 e g d e g n i s i r k l c p b m o r f d l o h # t c e l e s 2s n t 2 1 ] 0 : 1 3 [ q d d i l a v o t # ] 0 : 3 [ e b , ] 2 : 6 [ r d a 6 1s n t 3 1 e g d e g n i s i r k l c p b o t p u t e s # ] 0 : 3 [ e b , ] 2 : 6 [ r d a 5s n t 4 1 e g d e g n i s i r k l c p b m o r f d l o h # ] 0 : 3 [ e b , ] 2 : 6 [ r d a 2s n t 7 1 n e v i r d ] 0 : 1 3 { q d o t w o l # d r 3 1s n1 t 4 2 e g d e g n i s i r k l c p b m o r f d i l a v s u t a t s u r h t - s s a p 5s n t 5 2 e g d e g n i s i r k l c p b m o r f d l o h s u t a t s u r h t - s s a p 0s n t 6 2 e g d e g n i s i r k l c p b o t p u t e s # y d r t p 5s n t 7 2 e g d e g n i s i r k l c p b m o r f d l o h # y d r t p 3s n t 8 2 y a l e d k l c p b o t k l c i c p 25 . 6s n t 9 2 e g d e g n i s i r k l c p b o t p u t e s # r w , # d r 5s n t 0 3 e g d e g n i s i r k l c p b m o r f d l o h # r w , # d r 2s n t 1 3 e g d e g n i s i r k l c p b o t p u t e s ] 0 : 1 3 [ q d 5s n t 2 3 e g d e g n i s i r k l c p b m o r f d l o h ] 0 : 1 3 [ q d 2s n t 3 3 e g d e g n i s i r k l c p b m o r f d i l a v ] 0 : 1 3 [ q d 5 1s n t 4 3 e g d e g n i s i r # d r m o r f t a o l f ] 0 : 1 3 [ q d 2 1s n
12-168 electrical characteristics S5935 figure 14. pass-thru data register read timing t 14 t 13 t 29 t 12 t 30 t 33 t 17 t 34 t 11a t 27 t 26 bpclk dq[31:0] rd# select# ptrdy# adr[6:2] be[3:0]# valid 2 valid data out 2 valid 1 valid data out 1 figure 15. pass-thru data register write timing t 14 t 13 t 32 t 31 t 29 t 30 t 11a t 27 t 26 t 10a bpclk dq[31:0] wr# select# ptrdy# adr[6:2] be[3:0]# valid 2 valid data in 2 valid 1 valid data in 1
12-169 electrical characteristics S5935 figure 16. pass-thru status indicator timing bpclk ptatn# ptwr ptburst# ptnum[1:0] ptbe[3:0]# valid valid t 24 t 25 target byte-wide nv memory interface timings functional operation range (v cc =5.0v 5%, 0?c to 70?c, 50 pf load on outputs) symbol t35 erd# cycle time 8t ns note 1 t36 erd# low time 6t ns note 1 t37 erd# high time 2t ns note 1 t38 ea[15:0] setup to erd# or ewr# low t ns note 1 t39 ea[15:0] hold from erd# or ewr# high t ns note 1 t40 eq[7:0] setup to erd# rising edge 10 ns note 1 t41 eq[7:0] hold from erd# rising edge 2 ns note 1 t42 ewr# cycle time ns note 1,2 t43 ewr# low time ns note 1 t44 ewr# high time 2t 6t ns note 1 t45 eq[7:0] setup to ewr# low -10 0 ns note 1 t46 eq[7:0] hold from ewr# high t ns note 1 parameter min max units notes notes: 1. t represents the clock period for the pci bus clock (30ns @ 33 mhz). 2. the write cycle time is controlled by both the pci bus clock and software operations to initiate the write operation of nv memory. this parameter is the result of several software operations to the bus master control/status register (mcsr).
12-170 electrical characteristics S5935 figure 17. nv memory read timing data valid eq[7:0] (input) ea[15:0] (output) erd# (output) address valid t 35 t 36 t 37 t 39 t 38 t 41 t 40 figure 18. nv memory write timing data valid eq[7:0] (output) ea[15:0] (output) ewr# (output) address valid t 42 t 43 t 44 t 39 t 46 t 45 t 38
12-171 electrical characteristics S5935 target interrupt timings functional operation range (v cc =5.0v 5%, 0?c to 70?c, 50 pf load on outputs) symbol t49 irq# low from bpclk rising edge 15 ns note 1 t50 irq# high from bpclk rising edge 15 ns note 1 parameter min max units notes figure 19. irq# interrupt output timing bpclk irq# t 50 t 49 functional operation range (v cc =5.0v 5%, 0?c to 70?c, 50 pf load on outputs) symbol t51 embclk low time 12 ns t52 emblk high time 12 ns t53 emb[7:0] setup to embclk rising edge 5ns t54 emb[7:0] hold from embclk rising edge 2ns parameter min max units notes embclk emb[7:0] t 51 t 52 t 54 t 53 valid figure 20. mailbox 4, byte 3 direct input timing notes: 1. this timing applies to interrupts generated and cleared from the pci interface.
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13-173 pinout and package information S5935 S5935 pinout and pin assignment - 160 pqfp 1 eq0 ad23 ad22 ad21 dq31 ad20 ad19 ad18 eq1 vss vcc ad17 dq30 ad16 c/be2# frame# eq2 irdy# trdy# devsel# eq3 stop# lock# perr# dq29 serr# par c/be1# eq4/fwc# vss vcc ad15 eq5/frc# ad14 ad13 ad12 dq28 ad11 ad10 ad9 ptbe3# ptbe2# ptbe1# dq20 ptbe0# ptrdy# ptatn# ea9 ptburst# vcc vss ea8 ptwr ptadr# rdempty dq21 rdfifo# wrfull wrfifo# ea7 dq0 dq1 dq2 ea6 dq3 dq4 dq5 dq22 dq6 vcc vss ea5 dq7 beo# dq8 dq23 dq9 dq10 dq11 ea4 S5935 (160 pqfp) dq13 dq12 dq14 dq24 dq15 select# wr# ea3 rd# vcc vss ea2 adr2 adr3 adr4 dq25 adr5 be1# be2# ea1 be3# mode inta# ea0 ad0 ad1 ad2 dq26 ad3 vcc vss eq7/amwen ad4 ad5 ad6 dq27 ad7 c/be0# ad8 eq6/amren ea10 ptnum1 ptnum0 irq# dq19 sysrst# ewr#/sda erd#/scl ea11 vss vcc adr6 dq18 nc snv nc ea12 rsvd rst# bpclk ea13 clk gnt# req# dq17 ad31 ad30 ad29 ea14/fwe vss vcc ad28 ea15/frf ad27 ad26 ad25 dq16 ad24 c/be3# idsel 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 ?
13-174 pinout and package information S5935 S5935 pinout and pin assignment - 208 tqfp 1 vdd vss vss eq0 ad23 ad22 ad21 dq31 ad20 ad19 ad18 n/c eq1 vss vss vdd vdd ad17 dq30 ad16 c/be2# frame# eq2 irdy# trdy# devsel# eq3 stop# lock# perr# dq29 serr# n/c par c/be1# eq4 vss vss vdd vdd vdd vdd vdd ptbe3# ptbe2# ptbe1# dq20 ptbe0# ptrdy# ptatn# ea9 ptburst# n/c vss vss vss ea8 ptwr ptaddr# n/c rdempty dq21 rdfifo# wrfull wrfifo# ea7 dq0 dq1 dq2 ea6 dq3 dq4 dq5 dq22 dq6 n/c vdd vss vss ea5 S5935 (208 tqfp) vss vdd vss vss ea2 adr2 adr3 n/c adr4 dq25 adr5 be1 be2 ea1 be3 mode inta# ea0 ad0 ad1 ad2 dq26 ad3 n/c vdd vss vss eq7 n/c ad4 ad5 ad6 dq27 ad7 c/be0# ad8 eq6 vss vss vdd ea11 vss vss vdd n/c adr6 dq18 nv n/c ea12 rsvd rst# bpclk ea13 clk gnt# req# dq17 ad31 ad30 n/c ad29 ea14 vss vss vdd n/c ad28 ea15 ad27 ad26 ad25 n/c dq16 ad24 c/be3# idsel vdd vdd vdd 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ad15 eq5 ad14 ad13 ad12 dq28 ad11 ad10 ad9 vdd vdd vdd 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 n/c dq7 be0 dq8 dq23 dq9 dq10 dq11 ea4 vss vss vdd 116 115 114 113 112 111 110 109 108 107 106 105 92 91 90 89 88 87 86 85 84 83 82 81 vdd vdd dq12 dq13 dq14 vss dq24 dq15 select# wr# ea3 rd# 104 103 102 101 100 99 98 97 96 95 94 93 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 169 170 171 172 173 174 175 176 177 178 179 180 vdd vss vss ea10 ptnum1 ptnum0 irq# dq19 stsrst# sda/ewr scl/erd n/c 157 158 159 160 161 162 163 164 165 166 167 168 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
13-175 pinout and package information S5935 table 1. S5935 numerical pin assignment - 160 pqfp pin# signal type 1 eq0 t/s 2 ad23 t/s 3 ad22 t/s 4 ad21 t/s 5 dq31 t/s 6 ad20 t/s 7 ad19 t/s 8 ad18 t/s 9 eq1 t/s 10 vss v 11 vcc v 12 ad17 t/s 13 dq30 t/s 14 ad16 t/s 15 c/be2# t/s 16 frame# t/s 17 eq2 t/s 18 irdy# t/s 19 trdy# t/s 20 devsel# t/s 21 eq3 t/s 22 stop# t/s 23 lock# in 24 perr# t/s 25 dq29 t/s 26 serr# o/d 27 par t/s 28 c/be1# t/s 29 eq4/fwc# t/s 30 vss v 31 vcc v 32 ad15 t/s pin# signal type 33 eq5/frc# t/s 34 ad14 t/s 35 ad13 t/s 36 ad12 t/s 37 dq28 t/s 38 ad11 t/s 39 ad10 t/s 40 ad9 t/s 41 eq6/amren t/s 42 ad8 t/s 43 c/be0# t/s 44 ad7 t/s 45 dq27 t/s 46 ad6 t/s 47 ad5 t/s 48 ad4 t/s 49 eq7/amwen t/s 50 vss v 51 vcc v 52 ad3 t/s 53 dq26 t/s 54 ad2 t/s 55 ad1 t/s 56 ad0 t/s 57 ea0 t/s 58 inta# o/d 59 mode in 60 be3# in 61 ea1 t/s 62 be2# in 63 be1# in 64 adr5 in pin# signal type 65 dq25 t/s 66 adr4 in 67 adr3 in 68 adr2 in 69 ea2 t/s 70 vss v 71 vcc v 72 rd# in 73 ea3 t/s 74 wr# in 75 select# in 76 dq15 t/s 77 dq24 t/s 78 dq14 t/s 79 dq13 t/s 80 dq12 t/s 81 ea4 t/s 82 dq11 t/s 83 dq10 t/s 84 dq9 t/s 85 dq23 t/s 86 dq8 t/s 87 be0# in 88 dq7 t/s 89 ea5 t/s 90 vss v 91 vcc v 92 dq6 t/s 93 dq22 t/s 94 dq5 t/s 95 dq4 t/s 96 dq3 t/s
13-176 pinout and package information S5935 pin# signal type 97 ea6 t/s 98 dq2 t/s 99 dq1 t/s 100 dq0 t/s 101 ea7 t/s 102 wrfifo# in 103 wrfull out 104 rdfifo# in 105 dq21 t/s 106 rdempty out 107 ptadr# in 108 ptwr out 109 ea8 t/s 110 vss v 111 vcc v 112 ptburst# out 113 ea9 out 114 ptatn# out 115 ptrdy# in 116 ptbe0# out 117 dq20 t/s 118 ptbe1# out 119 ptbe2# out 120 ptbe3# out 121 ea10 out 122 ptnum1 out 123 ptnum0 out 124 irq# out 125 dq19 t/s 126 sysrst# out 127 ewr#/sda t/s 128 erd#/scl out pin# signal type 129 ea11 out 130 vss v 131 vcc v 132 adr6 in 133 dq18 t/s 134 nc 135 snv in 136 nc 137 ea12 out 138 rsvd in 139 rst# in 140 bpclk out 141 ea13 out 142 clk in 143 gnt in 144 req# out 145 dq17 t/s 146 ad31 t/s 147 ad30 t/s 148 ad29 t/s 149 ea14/fwe t/s 150 vss v 151 vcc v 152 ad28 t/s 153 ea15/frf t/s 154 ad27 t/s 155 ad26 t/s 156 ad25 t/s 157 dq16 t/s 158 ad24 t/s 159 c/be3# t/s 160 idsel in table 1. S5935 numerical pin assignment - 160 pqfp (continued)
13-177 pinout and package information S5935 e see detail a e 1 b e d d 1 l a 2 c seating plane detail a a 1 a pqfp in millimeters lead# 160 symbol min max a --- 4.07 a1 0.25 --- a2 3.17 3.87 b 0.22 0.38 c 0.15 0.20 d1 27.90 28.10 e1 27.90 28.10 e 0.65 bsc d 31.65 32.15 e 31.65 32.15 l 0.65 0.95 package physical dimensions - 160 pqfp
13-178 pinout and package information S5935 table 2. S5935 numerical pin assignment - 208 tqfp pin# signal type 1 vdd v 2 vss v 3 vss v 4 eq0 t/s 5 ad23 t/s 6 ad22 t/s 7 ad21 t/s 8 dq31 t/s 9 ad20 t/s 10 ad19 t/s 11 ad18 t/s 12 n/c --- 13 eq1 t/s 14 vss v 15 vss v 16 vdd v 17 vdd v 18 ad17 t/s 19 dq30 t/s 20 ad16 t/s 21 c/be2# t/s 22 frame# t/s 23 eq2 t/s 24 irdy# t/s 25 trdy# t/s 26 devsel# t/s 27 eq3 t/s 28 stop# t/s 29 lock# i 30 perr# t/s 31 dq29 t/s 32 serr# o pin# signal type 33 n/c --- 34 par t/s 35 c/be1# t/s 36 eq4 t/s 37 vss v 38 vss v 39 vdd v 40 vdd v 41 ad15 t/s 42 eq5 t/s 43 ad14 t/s 44 ad13 t/s 45 ad12 t/s 46 dq28 t/s 47 ad11 t/s 48 ad10 t/s 49 ad9 t/s 50 vdd v 51 vdd v 52 vdd v 53 vdd v 54 vss v 55 vss v 56 eq6 t/s 57 ad8 t/s 58 c/be0# t/s 59 ad7 t/s 60 dq27 t/s 61 ad6 t/s 62 ad5 t/s 63 ad4 t/s 64 n/c --- pin# signal type 65 eq7 t/s 66 vss v 67 vss v 68 vdd v 69 n/c --- 70 ad3 t/s 71 dq26 t/s 72 ad2 t/s 73 ad1 t/s 74 ad0 t/s 75 ea0 t/s 76 inta# o 77 mode i 78 be3 i 79 ea1 t/s 80 be2 i 81 be1 i 82 adr5 i 83 dq25 t/s 84 adr4 i 85 n/c --- 86 adr3 i 87 adr2 i 88 ea2 t/s 89 vss v 90 vss v 91 vss v 92 vdd v 93 rd# i 94 ea3 t/s 95 wr# i 96 select# i
13-179 pinout and package information S5935 pin# signal type 97 dq15 t/s 98 dq24 t/s 99 vss v 100 dq14 t/s 101 dq13 t/s 102 dq12 t/s 103 vdd v 104 vdd v 105 vdd v 106 vss v 107 vss v 108 ea4 t/s 109 dq11 t/s 110 dq10 t/s 111 dq9 t/s 112 dq23 t/s 113 dq8 t/s 114 be0 i 115 dq7 t/s 116 n/c --- 117 ea5 t/s 118 vss v 119 vss v 120 vdd v 121 n/c --- 122 dq6 t/s 123 dq22 t/s 124 dq5 t/s 125 dq4 t/s 126 dq3 t/s 127 ea6 t/s 128 dq2 t/s pin# signal type 129 dq1 t/s 130 dq0 t/s 131 ea7 t/s 132 wrfifo# i 133 wrfull o 134 rdfifo# i 135 dq21 t/s 136 rdempty o 137 n/c --- 138 ptaddr# i 139 ptwr o 140 ea8 t/s 141 vss v 142 vss v 143 vss v 144 n/c --- 145 ptburst# o 146 ea9 t/s 147 ptatn# o 148 ptrdy# i 149 ptbe0# o 150 dq20 t/s 151 ptbe1# o 152 ptbe2# o 153 ptbe3# o 154 vdd v 155 vdd v 156 vdd v 157 vdd v 158 vss v 159 vss v 160 ea10 o table 2. S5935 numerical pin assignment - 208 tqfp (continued) pin# signal type 161 ptnum1 o 162 ptnum0 o 163 irq# o 164 dq19 t/s 165 sysrst# o 166 sda/ewr o 167 scl/erd o 168 n/c --- 169 ea11 o 170 vss v 171 vss v 172 vdd v 173 n/c --- 174 adr6 i 175 dq18 t/s 176 nv i 177 n/c --- 178 ea12 o 179 rsvd i 180 rst# i 181 bpclk t/s 182 ea13 o 183 clk i 184 gnt# i 185 req# o 186 dq17 t/s 187 ad31 t/s 188 ad30 t/s 189 n/c --- 190 ad29 t/s 191 ea14 o 192 vss v
13-180 pinout and package information S5935 pin# signal type 193 vss v 194 vdd v 195 n/c --- 196 ad28 t/s 197 ea15 o 198 ad27 t/s 199 ad26 t/s 200 ad25 t/s 201 n/c --- 202 dq16 t/s 203 ad24 t/s 204 c/be3# t/s 205 idsel i 206 vdd v 207 vdd v 208 vdd v table 2. S5935 numerical pin assignment - 208 tqfp (continued)
13-181 pinout and package information S5935 package physical dimensions - 208 tqfp
13-182 pinout and package information S5935 ordering information S5935 q f revision level package option q = 160-pin pqfp device number t = 208-pin tqfp

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