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any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircrafts control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. overview the LC3564CM and lc3564ct-55u/70u are 8192-word 8-bit asynchronous silicon gate cmos srams. these are full cmos type srams that adopt a six-transistor memory cell and feature fast access times, low operating power dissipation, and an ultralow standby current. these srams provide three control signal inputs: an oe input for high-speed memory access, and two chip enable lines, ce1 and ce2, for low power mode and device selection. these means that these srams area ideal for systems that require low power and battery backup, and that they support easy memory expansion. the ultralow standby current that is a feature of these srams allows them to be used with capacitor backup as well. since these srams support 3-v operation, they are also appropriate for use in portable battery operated systems. features ? supply voltage range: 2.7 to 5.5 v in 5-v operation mode: 5.0 v 10% in 3-v operation mode: 3.0 v 10% ? address access time (t aa ) in 5-v operation mode: LC3564CM, and ct-55u: 55 ns (max) LC3564CM, and ct-70u: 70 ns (max) in 3-v operation mode: LC3564CM, and ct-70u: 200 ns (max) ? ultralow standby current in 5-v operation mode: 1.0 a (ta 70c), 3.0 a (ta 85c) in 3-v operation mode: 0.8 a (ta 70c), 2.5 a (ta 85c) ? operating temperature range in 5-v operation mode: C40 to 85c in 3-v operation mode: C40 to 85c ? data retention supply voltage: 2.0 to 5.5 v ? all input and output levels: in 5-v operation mode: ttl compatible levels in 3-v operation mode: v cc C0.2 v/0.2 v ? three control inputs: oe, ce1, and ce2 ? shared input and output pins, three-state outputs ? no clock required ? packages 28-pin sop (450 mil) plastic package: LC3564CM 28-pin tsop (8 13.4 mm) plastic package: lc3564ct cmos ic 80502rm (ot) no. 6635-1/11 sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan 64k (8192-word 8-bit) sram with oe, ce1, and ce2 control pins LC3564CM, 3564ct-55u/70u ordering number : enn6635a
no. 6635- 2 /11 LC3564CM, ct-55u/70u p ac ka g e dimensions unit: mm 3187b-dip28d unit: mm 3221-tsop28a 0.15 18.0 14 15 28 1 (0.75) 1.27 0.4 8.4 11.8 1.0 (2.2) 0.1 2.5max sanyo: dip28d [LC3564CM] 13.4 11.8 22 28 1 7 8 21 0.05 0.5 (1.0) 8.0 0.2 0.125 1.2max (0.43) 0.55 sanyo: tsop28a [lc3564ct] pin assignments 1 nc 28 v cc 2 a12 27 we 3 a7 26 ce2 4 a6 25 a8 5 a5 24 a9 6 a4 23 a11 7 a3 22 oe 8 a2 21 a10 9 a1 20 ce1 10 a0 19 i/o8 11 i/o1 18 i/o7 12 i/o2 17 i/o6 13 i/o3 16 i/o5 14 gnd 15 i/o4 top view a13510 top view a13511 sop28 tsop28 oe 22 a10 21 a11 23 ce1 20 a9 24 i/o8 19 a8 25 i/o7 18 ce2 26 i/o6 17 we 27 i/o5 16 v cc 28 i/o4 15 nc 1 gnd 14 a12 2 i/o3 13 a7 3 i/o2 12 a6 4 i/o1 11 a5 5 a0 10 a4 6 a1 9 a3 7 a2 8
no. 6635- 3 /11 LC3564CM, ct-55u/70u block diagram a d d r e s s b u f f e r p o w d e c o d e r m e m o r y c e l l a r r a y o u t p u t b u f f e r i n p u t d a t a b u f f e r d a t a c o n t r o l c i r c u i t c o n t r o l c i r c u i t a 0 t o a 1 2 i / o 1 t o i / o 8 v c c g n d c e 1 c e 2 w e o e a 1 3 5 1 2 pin functions a0 to a12 address inputs we read/write control input oe output enable input ce1, ce2 chip enable inputs i/o1 to i/o8 data i/o v cc , gnd power supply and ground function table x : h or l mode ce1 ce2 oe we i/o supply current read cycle l h l h data output i cca write cycle l h x l data input i cca output disable l h h h high impedance i cca not selected h x x x high impedance i ccs x l x x high impedance i ccs
no. 6635- 4 /11 LC3564CM, ct-55u/70u parameter symbol conditions ratings unit maximum supply voltage v cc max 7.0 v input voltage v in C0.3 * to v cc + 0.3 v i/o voltage v i/o C0.3 to v cc + 0.3 v operating temperature topr C40 to +85 c storage temperature tstg C55 to +125 c specifications absolute maximum ratings at ta = 25 c note: for pulse widths less than 30 ns: C3.0 v note: these parameters are sampled, and are not measured for every unit. note: for pulse widths less than 30 ns: C3.0 v note * : reference values at v cc = 5 v, ta = 25 c [5-v operation] parameter symbol conditions ratings unit min typ max i/o pin capacitance c i/o v i/o = 0 v 6 10 pf input pin capacitance c in v in = 0 v 6 10 pf input and output capacitances at ta = 25 c, f = 1 mhz parameter symbol conditions ratings unit min typ max supply voltage v cc 4.5 5.0 5.5 v input voltage v ih 2.2 v cc + 0.3 v v il C0.3 * +0.8 v dc allowable operating ranges at ta = C40 to +85 c, v cc = 4.5 to 5.5 v parameter symbol conditions ratings unit min typ * max input leakage current i li v in = 0 to v cc C1.0 +1.0 a i/o leakage current i lo v ce1 = v ih or v ce2 = v il or v oe = v ih or C1.0 +1.0 a v we = v il , v i/o = 0 to v cc output high-level voltage v oh i oh = C1.0 ma 2.4 v output low-level voltage v ol i ol = 2.0 ma 0.4 v v ce1 0.2 v, v ce2 3 v cc C 0.2 v, ta 70 c 0.01 1.0 a i cca1 i i/o = 0 ma, v in 0.2 v or v cc C 0.2 v/0.2 v v in 3 v cc C 0.2 v ta 85 c 3.0 inputs min LC3564CM, ct-55u 45 i cca4 cycle LC3564CM, ct-70u 35 ma 1 s cycle 4 operating supply current i cca2 v ce1 = v il , v ce2 = v ih , i i/o = 0 ma, 7 ma v in = v ih or v il ttl inputs min LC3564CM, ct-55u 45 i cca3 cycle LC3564CM, ct-70u 40 ma 1 s cycle 7 standby mode supply v cc C 0.2 v/0.2 v v ce2 0.2 v or ta 70 c 0.01 1.0 a current inputs i ccs1 v ce1 3 v cc C 0.2 v v ce2 3 v cc C 0.2 v ta 85 c 3.0 ttl inputs i cc2 v ce2 = v il or v ce1 = v ih , v in = 0 to v cc 2.0 ma dc electrical characteristics at ta = C40 to +85 c, v cc = 4.5 to 5.5 v v ce1 0.2 v, v ce2 3 v cc C 0.2 v, i i/o = 0 ma, duty = 100% v ce1 = v il , v ce2 = v ih , i i/o = 0 ma, duty = 100%
ac electrical characteristics at ta = C40 to +85 c, v cc = 4.5 to 5.5 v no. 6635- 5 /11 LC3564CM, ct-55u/70u LC3564CM, ct parameter symbol -55u -70u unit min max min max read cycle time t rc 55 70 ns address access time t aa 55 70 ns ce1 access time t ca1 55 70 ns ce2 access time t ca2 55 70 ns oe access time t oa 30 35 ns output hold time t oh 10 10 ns ce1 output enable time t coe1 5 10 ns ce2 output enable time t coe2 5 10 ns oe output enable time t ooe 5 5 ns ce1 output disable time t cod1 20 30 ns ce2 output disable time t cod2 20 30 ns oe output disable time t ood 20 25 ns read cycle LC3564CM, ct parameter symbol -55u -70u unit min max min max write cycle time t wc 55 70 ns address setup time t as 0 0 ns write pulse width t wp 40 50 ns ce1 setup time t cw1 50 60 ns ce2 setup time t cw2 50 60 ns write recovery time t wr 0 0 ns ce1 write recovery time t wr1 0 0 ns ce2 write recovery time t wr2 0 0 ns data setup time t ds 25 35 ns data hold time t dh 0 0 ns ce1 data hold time t dh1 0 0 ns ce2 data hold time t dh2 0 0 ns we output enable time t woe 5 5 ns we output disable time t wod 30 30 ns write cycle parameter conditions [ac test conditions] input pulse voltage v ih = 2.4 v, v il = 0.6 v input rise and fall times 5 ns input and output timing level 1.5 v output load LC3564CM and ct-55u/70u: 30 pf + 1 ttl gate (including the jig capacitance.)
[3-v operation] no. 6635- 6 /11 LC3564CM, ct-55u/70u note * : reference values at v cc = 3 v, ta = 25 c parameter symbol conditions ratings unit min typ max supply voltage v cc 2.7 3.0 3.3 v input voltage v ih v cc C 0.2 v cc v v il 0 0.2 v dc allowable operating ranges at ta = C40 to +85 c, v cc = 2.7 to 3.3 v parameter symbol conditions ratings unit min typ * max input leakage current i li v in = 0 to v cc C1.0 +1.0 a i/o leakage current i lo v ce1 = v ih or v ce2 = v il or v oe = v ih or C1.0 +1.0 a v we = v il , v i/o = 0 to v cc output high-level voltage v oh i oh = C0.5 ma v cc C 0.2 v output low-level voltage v ol i ol = 1.0 ma 0.2 v v ce1 v il , v ce2 3 v ih , ta 70 c 0.01 0.8 a i cca1 i i/o = 0 ma, v in v il or v in 3 v ih ta 85 c 2.5 operation supply current v cc C 0.2 v/0.2 v min LC3564CM, ct-70u 20 ma inputs i cca4 cycle 1 s cycle 3 ma standby mode supply v cc C 0.2 v/0.2 v v ce2 0.2 v or ta 70 c 0.01 0.8 a current inputs i ccs1 v ce1 3 v ih v ce2 3 v ih ta 85 c 2.5 dc electrical characteristics at ta = C40 to +85 c, v cc = 2.7 to 3.3 v v ce1 v il , v ce2 3 v ih , i i/o = 0 ma, duty = 100%
no. 6635- 7 /11 LC3564CM, ct-55u/70u ac electrical characteristics at ta = C40 to +85 c, v cc = 2.7 to 3.3 v LC3564CM, ct-70u parameter symbol -10 unit min max read cycle time t rc 200 ns address access time t aa 200 ns ce1 access time t ca1 200 ns ce2 access time t ca2 200 ns oe access time t oa 100 ns output hold time t oh 20 ns ce1 output enable time t coe1 20 ns ce2 output enable time t coe2 20 ns oe output enable time t ooe 10 ns ce1 output disable time t cod1 60 ns ce2 output disable time t cod2 60 ns oe output disable time t ood 50 ns read cycle LC3564CM, ct-70u parameter symbol -70 unit min max write cycle time t wc 200 ns address setup time t as 0 ns write pulse width t wp 140 ns ce1 setup time t cw1 150 ns ce2 setup time t cw2 0 ns write recovery time t wr 0 ns ce1 write recovery time t wr1 0 ns ce2 write recovery time t wr2 130 ns data setup time t ds 0 ns data hold time t dh 0 ns ce1 data hold time t dh1 0 ns ce2 data hold time t dh2 10 ns we output enable time t woe ns we output disable time t wod 60 ns write cycle parameter conditions [ac test conditions] input pulse voltage v ih = v cc C 0.2 v, v il = 0.2 v input rise and fall times 10 ns input and output timing level 1.5 v output load LC3564CM, ct-70u : 30pf (including the jig capacitance.)
timing charts read cycle *1 write cycle (1): we write *6 no. 6635- 8 /11 LC3564CM, ct-55u/70u t rc t aa t ca2 t ca1 t oa t ooe t ood t cod1 t cod2 t oh t coe1 t coe2 a0 to a12 ce2 ce1 oe invalid data h or l * 5 d out1 to 8 output data valid a13513 t wc t as t wp * 3 t cw2 * 4 t cw1 * 4 t wod t wr t woe t dh t ds t oh invalid data h or l a0 to a12 we ce2 ce1 d in1 to 8 * 5 d out1 to 8 * 2 data in stable * 2 * 7 a13514
no. 6635- 9 /11 LC3564CM, ct-55u/70u write cycle (2): ce1 write *6 t wc t as t wp * 3 t cw2 * 4 t cw1 * 4 t wod t wr1 t dh1 t ds t coe1 a0 to a12 we ce2 ce1 d in1 to 8 * 5 d out1 to 8 data in stable a13515 invalid data h or l write cycle (3): ce2 write *6 notes: 1. hold we high during the read cycle. 2. applications must not apply reverse phase signals to the d out pins when those pins are in the output state. 3. the time twp is the period when ce1 and we are low and ce2 is high, and is defined as the time from the fall of we until either ce1 or we rises, or ce2 falls, whichever occurs first. 4. the times t cw1 and t cw2 are periods when ce1 and we are low and ce2 is high. they are defined as the times from the fall of ce1 or the rise of ce2 to the rise of ce1 and we, or the fall of ce2, whichever occurs first. 5. the d out pins will be in the high-impedance state if either oe is high, ce1 is high, ce2 is low, or we is low. 6. oe must be held either at v ih or v il during the write cycle. 7. the d out pins have the same phase as the write cycle write data. t wc t as t wp * 3 t cw2 * 4 t cw1 * 4 t wod t wr2 t dh2 t ds t coe2 a0 to a12 we ce2 ce1 d in1 to 8 * 5 d out1 to 8 data in stable a13516 invalid data h or l
no. 6635- 10 /11 LC3564CM, ct-55u/70u parameter symbol conditions ratings unit min typ max data retention supply voltage v dr v ce2 0.2 v or 2.0 5.5 a v ce1 3 v cc C 0.2 v, v ce2 3 v cc C 0.2 v v cc = 3v, v ce2 0.2 v, ta 70 c 0.8 a data retention supply current i ccdr or v ce1 3 v cc C 0.2 v, v ce2 3 v cc C 0.2 v ta 85 c 2.5 chip enable setup time t cdr 0 ns chip enable hold time t r t rc * ns data retention characteristics at ta = C40 to +85 c note * : t rc is the read cycle time. note * : in 5-v operation: 4.5 v in 3-v operation: 2.7 v data retention waveforms (1): ce1 control notes on circuit design when actually design a circuit using these devices, take the following points into consideration and design the circuit so that none of the maximum rating items are ever exceeded. ? variations in the supply voltage ? variations in the electrical characteristics of components such as semiconductor devices, resistors, and capacitors. ? ambient temperature ? variations in input and clock signals ? possible application of abnormal pulses also, these devices must be operated within the ranges stipulated in the allowable operating ranges. if cmos ic input pins are left open, intermediate potential input voltages may occur leading to incorrect operation due to through currents or other phenomenon. applications must handle unused input pins appropriately. t cdr data retention mode v ce1 3 v cc ?.2v t r v cc v ccl v ih v dr v ce1 gnd a13517 * t cdr data retention mode v ce2 0.2v t r v cc v ccl v ce2 v dr v il gnd a13518 * data retention waveforms (2): ce2 control
ps no. 6635- 11 /11 LC3564CM, ct-55u/70u this catalog provides information as of august, 2002. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customers products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customers products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the delivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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