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mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 1 description application main memory unit for pc, pc server, server, ws. features type name 133mhz MH28D72KLG-10 mh28d72klg-75 - utilizes industry standard 64m x 4 ddr synchronous drams in tsop package , industry standard registered buffer in tssop package , and industry standard pll in tssop package. - vdd=vddq=2.5v0.2v - double data rate architecture; two data transfers per clock cycle - bidirectional, data strobe (dqs) is transmitted/received with data - differential clock inputs (clk and /clk) - data referenced to both edges of dqs - /cas latency- 2.0/2.5 (programmable) - burst length- 2/4/8 (programmable) - auto precharge / all bank precharge controlled by a10 - 8192 refresh cycles /64ms - auto refresh and self refresh - row address a0-12 / column address a0-9,11 - sstl_2 interface - module 2bank configration - burst type - sequential/interleave(programmable) - commands entered on each positive clk edge max. frequency 100mhz 1pin 52pin 92pin 93pin 144pin 145pin 184pin the mh28d72klg is 134217728 - word x 72-bit double data rate(ddr) synchronous dram mounted module. this consists of 36 industry standard 64m x 4 ddr synchronous drams in tsop with sstl_2 interface which achieves very high speed data rate up to 133mhz. this socket-type memory module is suitable for main memory in computer systems and easy to interchange or add modules. clk access time [component level] 53pin + 0.75ns + 0.8ns
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 2 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vref 43 a1 84 127 2 dq0 44 85 128 3 vss 45 86 129 4 dq1 46 87 130 5 dqs0 47 88 131 6 dq2 48 89 132 7 vdd 49 90 133 8 dq3 50 91 134 9 nc 51 92 135 10 reset 52 94 136 11 vss 95 137 12 dq8 53 96 138 13 dq9 54 97 139 14 dqs1 55 98 140 15 vddq 56 99 141 16 nc 57 100 142 17 58 101 143 18 vss 59 102 144 19 dq10 60 103 145 20 dq11 61 104 146 21 cke0 62 105 147 22 vddq 63 106 148 23 dq16 64 107 149 24 dq17 65 108 150 25 dqs2 66 109 151 26 vss 67 110 152 27 a9 68 111 153 28 dq18 69 112 154 29 a7 70 113 155 30 vddq 71 114 156 31 dq19 72 115 157 32 a5 73 116 158 33 dq24 74 117 159 34 vss 75 118 160 35 dq25 76 119 161 36 dqs3 77 120 162 37 a4 78 121 163 38 vdd 79 122 164 39 dq26 80 123 165 40 dq27 81 124 166 41 a2 82 125 42 vss 83 pin no. pin name 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 cb0 cb1 vdd dqs8 a0 cb2 vss cb3 ba1 dq32 vddq dq33 dqs4 dq34 vss ba0 dq35 dq40 vddq /we dq41 /cas vss dqs5 dq42 dq43 vdd nc dq48 dq49 vss nc vddq dqs6 dq50 dq51 vss vddid dq56 dq57 vdd dqs7 dq58 dq59 vss nc sda scl vss dq4 dq5 vddq dqs9 dq6 dq7 vss nc nc nc vddq dq12 dq13 vdd dq14 dq15 cke1 vddq nc dq20 a12 vss dq21 a11 vdd dq22 a8 dq23 vss a6 dq28 dq29 vddq a3 dq30 vss dq31 cb4 cb5 vddq ck0 /ck0 vss a10 cb6 vddq cb7 vss dq36 dq37 vdd dq38 dq39 vss dq44 /ras dq45 vddq /s0 vss dq46 dq47 nc vddq dq52 dq53 vdd dq54 dq55 vddq nc dq60 dq61 vss dq62 dq63 vddq sa0 sa1 sa2 vddspd pin configuration nc key 93 126 key 167 168 nc: no connect nc dqs10 dqs11 dqs12 dqs17 dqs13 dqs14 nc dqs15 dqs16 /s1
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 3 /rs0 pll ck0 /ck0 pck0 -> sdrams d0-d35, registered buffer /pck0 -> sdrams d0-d35, registered buffer block diagram dqs0 /rs1 sa0 sa1 sa2 serial pd scl sda a0 a1 a2 wp vdd d0 to d35 vref vss d0 to d35 d0 to d35 v ddid vddq d0 to d35 v ddid: open -> vdd = vddq vss -> vdd = vddq dq0 dq1 dq2 dq3 dm dqs /s dm /s dqs dq8 dq9 dq10 dq11 dm dqs /s dm /s dqs dqs1 dq16 dq17 dq18 dq19 dm dqs /s dm /s dqs dqs2 dq24 dq25 dq26 dq27 dm dqs /s dm /s dqs dqs3 dq32 dq33 dq34 dq35 dm dqs /s dm /s dqs dqs4 dq40 dq41 dq42 dq43 dm dqs /s dm /s dqs dqs5 dq48 dq49 dq50 dq51 dm dqs /s dm /s dqs dqs6 dq56 dq57 dq58 dq59 dm dqs /s dm /s dqs dqs7 cb0 cb 1 cb 2 cb 3 dm dqs /s dm /s dqs dqs8 dqs9 dq4 dq5 dq6 dq7 dm dqs /s dm /s dqs dq12 dq13 dq14 dq15 dm dqs /s dm /s dqs dqs10 dq20 dq21 dq22 dq23 dm dqs /s dm /s dqs dqs11 dq28 dq29 dq30 dq31 dm dqs /s dm /s dqs dqs12 dq36 dq37 dq38 dq39 dm dqs /s dm /s dqs dqs13 dq44 dq45 dq46 dq47 dm dqs /s dm /s dqs dqs14 dq52 dq53 dq54 dq55 dm dqs /s dm /s dqs dqs15 dq60 dq61 dq62 dq63 dm dqs /s dm /s dqs dqs16 cb4 cb 5 cb 6 cb7 dm dqs /s dm /s dqs dqs17 vss d0 d1 d2 d3 d4 d5 d6 d7 d8 d18 d19 d20 d21 d22 d23 d024 d025 d026 d9 d10 d11 d12 d13 d14 d15 d16 d17 d27 d28 d29 d30 d31 d32 d33 d34 d35 /s0 ba0-ba1 a0-a12 /ras /cas cke0 /we /rs0 -> sdrams d0-d17 rba0-rba1 -> sdrams d0-d35 ra0-ra12 -> sdrams d0-d35 /rras -> sdrams d0-d35 /rcas -> sdrams d0-d35 /rcke0 -> sdrams d0-d17 /rwe -> sdrams d0-d35 /pck pck /reset /s1 /rs1 -> sdrams d18-d35 cke1 /rcke1 -> sdrams d18-d35 vddspd serial pd
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 4 pin function ck0,/ck0 input clock: ck0 and /ck0 are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck0 and negative edge of /ck0. output (read) data is referenced to the crossings of ck0 and /ck0 (both directions of crossing). cke0, cke1 input clock enable: cke0,1 controls sdram internal clock. when cke0 is low, the internal clock for the following cycle is ceased. cke0 is also used to select auto / self refresh. after self refresh mode is started, cke0 becomes asynchronous input. self refresh is maintained as long as cke0 is low. /s0, /s1 input physical bank select : when /s0,1 is high, any command means no operation. /ras, /cas, /we input combination of /ras, /cas, /we defines basic commands. a0-12 input a0-12 specify the row / column address in conjunction with ba0,1. the row address is specified by a0-12. the column address is specified by a0-9,11. a10 is also used to indicate precharge option. when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, all banks are precharged. ba0,1 input dq 0-64 cb 0-7 input / output dqs0-17 vdd, vddq power supply power supply. vdd and vddq are connected on the module. vddq, vssq power supply bank address: ba0,1 specifies one of four banks in sdram to which a command is applied. ba0,1 must be set with act, pre, read, write commands. data input/output: data bus data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. used to capture write data. symbol type description input / output vref input sstl_2 reference voltage. vddspd power supply power supply for spd reset input this signal is asynchronous and is driven low to the register in order to guarantee the register outputs are low. sda input / output this bidirectional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to vdd to act as a pullup. scl input this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from the scl bus time to vdd to act as a pullup. sa0-2 these signals are tied at the system planar to either vss or vdd to configure the serial spd eeprom address range. input vdd identification flag vddid power supply. vss and vssq are connected on the module.
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 5 basic functions the mh28d72klg provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. each command is defined by control signals of /ras, /cas and /we at clk rising edge. in addition to 3 signals, /cs ,cke and a10 are used as chip select, refresh option, and precharge option, respectively. to know the detailed definition of commands, please see the command truth table. /s0 chip select : l=select, h=deselect /ras command /cas command /we command cke0 refresh option @refresh command a10 precharge option @precharge or read/write command ck0 define basic commands activate (act) [/ras =l, /cas =/we =h] act command activates a row in an idle bank indicated by ba. read (read) [/ras =h, /cas =l, /we =h] read command starts burst read from the active bank indicated by ba. first output data appears after /cas latency. when a10 =h at this command, the bank is deactivated after the burst read (auto-precharge, reada ) write (write) [/ras =h, /cas =/we =l] write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write (auto-precharge, writea ). precharge (pre) [/ras =l, /cas =h, /we =l] pre command deactivates the active bank indicated by ba. this command also terminates burst read /write operation. when a10 =h at this command, all banks are deactivated (precharge all, prea ). auto-refresh (refa) [/ras =/cas =l, /we =cke0 =h] refa command starts auto-refresh cycle. refresh address including bank address are generated internally. after this command, the banks are precharged automatically. /ck0
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 6 command truth table h=high level, l=low level, v=valid, x=don't care, n=clk cycle number command mnemonic cke n-1 cke n /s /ras /cas /we ba0,1 a10 /ap a0-9, 11-12 deselect desel h x h x x x x x x no operation nop h x l h h h x x x row address entry & bank activate act h x l l h h v v v single bank precharge pre h x l l h l v l x precharge all banks prea h x l l h l h x column address entry & write write h x l h l l v l v column address entry & write with auto-precharge writea h x l h l l v h v column address entry & read read h x l h l h v l v column address entry & read with auto-precharge reada h x l h l h v h v auto-refresh refa h h l l l h x x x self-refresh entry refs h l l l l h x x x self-refresh exit refsx l h h x x x x x x l h l h h h x x x burst terminate term h x l h h l x x x mode register set mrs h x l l l l l l v x note 1 note: 1. applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for read bursts with autoprecharge enabled, and for write bursts. 2. ba0-ba1 select either the base or the extended mode register (ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selects extended mode register; other combinations of ba0-ba1 are reserved; a0-a11 provide the op-code to be written to the selected mode register. 2
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 7 function truth table current state /s /ras /cas /we address command action idle h x x x x desel nop l h h h x nop nop l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act bank active, latch ra l l h l ba, a10 pre / prea nop l l l h x refa auto-refresh l l l l op-code, mode-add mrs mode register set row active h x x x x desel nop l h h h x nop nop l h h l ba term nop l h l h ba, ca, a10 read / reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write / writea begin write, latch ca, determine auto-precharge l l h h ba, ra act bank active / illegal l l h l ba, a10 pre / prea precharge / precharge all l l l h x refa illegal l l l l op-code, mode-add mrs illegal read (auto- precharge disabled) h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin new read, determine auto-precharge l h l l ba, ca, a10 write writea l l h h ba, ra act bank active / illegal l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal notes 2 2 2 4 5 5 3 2 illegal
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 8 function truth table (continued) current state /s /ras /cas /we address command action write (auto- precharge disabled) h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin read, determine auto- precharge l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto- precharge l l h h ba, ra act bank active / illegal l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal read with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal l l h l ba, a10 pre / prea precharge/illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal write with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal l l h l ba, a10 pre / prea precharge/illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal notes 3 3 2 2 2 2 2
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 9 function truth table (continued) current state /s /ras /cas /we address command action pre - charging h x x x x desel nop (idle after trp) l h h h x nop nop (idle after trp) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea nop (idle after trp) l l l h x refa illegal l l l l op-code, mode-add mrs illegal row activating h x x x x desel nop (row active after trcd) l h h h x nop nop (row active after trcd) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal write re- covering h x x x x desel nop l h h h x nop nop l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal notes 2 2 2 4 2 2 2 2 2 2 2 2
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 10 function truth table (continued) current state /s /ras /cas /we address command action re- freshing h x x x x desel nop (idle after trc) l h h h x nop nop (idle after trc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal mode register setting h x x x x desel nop (idle after trsc) l h h h x nop nop (idle after trsc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal abbreviations: h=high level, l=low level, x=don't care ba=bank address, ra=row address, ca=column address, nop=no operation notes: 1. all entries assume that cke0 was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba. 5. illegal if any bank is not idle. illegal = device operation and/or data-integrity are not guaranteed. notes
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 11 current state cke n-1 cke n /s /ras /cas /we add action self- refresh h x x x x x x invalid l h h x x x x exit self-refresh (idle after trc) l h l h h h x exit self-refresh (idle after trc) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self-refresh) power down h x x x x x x invalid l h x x x x x exit power down to idle l l x x x x x nop (maintain self-refresh) all banks idle h h x x x x x refer to function truth table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state =power down any state other than listed above h h x x x x x refer to function truth table h l x x x x x begin clk suspend at next cycle l h x x x x x exit clk suspend at next cycle l l x x x x x maintain clk suspend function truth table for cke abbreviations: h=high level, l=low level, x=don't care notes: 1. cke0 low to high transition will re-enable ck0 and other inputs asynchronously . a minimum setup time must be satisfied before any command other than exit. 2. power-down and self-refresh can be entered only from the all banks idle state. 3. must be legal command. notes 3 3 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 12 simplified state diagram row active idle pre charge power down reada writea power on act refa refs refsx ckel ckeh mrs ckel ckeh write read writea writea reada read pre reada reada pre pre prea power applied mode register set self refresh auto refresh active power down automatic sequence command sequence write read pre charge all mrs burst stop term write read
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 13 power on sequence before starting normal operation, the following power on sequence is necessary to prevent a sdram from damaged or multifunctioning. 1. apply vdd and vddq before or the same time as vtt & vref 2. maintain stable condition for 200us after stable power and clk, apply nop or dsel 3. issue precharge command for all banks of the device 4 . issue emrs 5 . issue mrs 6. issue 2 or more auto refresh commands 7. maintain stable condition for 200 cycle after these sequence, the sdram is idle state and ready for normal operation. mode register burst length, burst type and /cas latency can be programmed by setting the mode register (mrs). the mode register stores these data until the next mrs command, which may be issued in idle state. after tmrd from a mrs command, the ddr dimm is ready for new command. r: reserved for future use bl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 burst length bt= 0 bt= 1 r 2 4 8 r r r r r 2 4 8 r r r r 0 1 burst type sequential interleaved a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba0 0 0 dr 0 ltmode bt bl 0 0 0 /s0 /ras /cas /we a11-a0 /ck0 v ck0 ba0 ba1 cl latency mode *1 (sdram level) /cas latency r r 2 r r 2.5 r 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 dll reset no yes r *1 in the module, 1latency should be added due to registered dimm. a12 0
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 14 extended mode register dll disable / enable mode can be programmed by setting the extended mode register (emrs). the extended mode register stores these data until the next emrs command, which may be issued in idle state. after tmrd from a emrs command, the ddr dimm is ready for new command. /s0 /ras /cas /we a11-a0 /ck0 v ck0 ba0 ba1 0 1 dll disable dll enable dll disable a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba0 0 0 0 0 dd 1 0 0 ds qfc 0 0 0 0 0 1 drive strength normal weak 0 1 qfc disable enable a12 0
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 15 /cas latency burst length cl= 2 bl= 4 burst length a2 a1 a0 initial address bl sequential interleaved column addressing 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 - 0 0 - 0 1 - 1 0 - 1 1 - - 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0 2 3 0 1 3 0 0 1 7 6 5 4 0 1 2 3 1 0 3 2 2 3 0 1 3 2 0 1 - - 1 1 2 1 0 3 4 5 6 3 2 1 0 1 0 1 0 8 4 2 command address dq y y read write dqs q0 q1 q2 q3 d0 d1 d2 d3 /clk clk ( componennt level )
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 16 absolute maximum ratings dc operating conditions (ta=0 ~ 70 c , unless otherwise noted) capacitance (ta=0 ~ 70 c , vdd = vddq = 2.5 0.2v, vss = vssq = 0v, unless otherwise noted) symbol parameter conditions ratings unit vdd supply voltage with respect to vss -0.5 ~ 3.7 v vddq supply voltage for output with respect to vssq -0.5 ~ 3.7 v vi input voltage with respect to vss -0.5 ~ vdd+0.5 v vo output voltage with respect to vssq -0.5 ~ vddq+0.5 v io output current 50 ma pd power dissipation ta = 25 c w topr operating temperature 0 ~ 70 tstg storage temperature -40 ~ 100 symbol parameter limits unit min. typ. max. vdd/vddq supply voltage 2.3 2.5 2.7 v vih(dc) high-level input voltage vref + 0.18 vddq+0.3 v vil(dc) low-level input voltage -0.3 vref - 0.18 v vref input reference voltage 1.15 1.35 v 1.25 vin(dc) input voltage level, ck0 and /ck0 -0.3 vddq + 0.3 v vid(dc) input differential voltage, ck0 and /ck0 0.36 vddq + 0.6 v vtt i/o termination voltage vref - 0.04 v vref + 0.04 notes 6 5 7 c c symbol ci(a) ci(c) ci(k) ci/o parameter input capacitance, address pin input capacitance, control pin input capacitance, ck0 pin input capacitance, i/o pin test condition limits(max.) unit f =1mhz 17 pf pf pf pf 17 8 20 2 0 notes 11 11 11 11
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 17 average supply current from vdd (ta=0 ~ 70 c , vdd = vddq = 2.5 0.2v, vss = vssq = 0v, output open, unless otherwise noted) ac operating conditions and characteristics (ta=0 ~ 70 c , vdd = vddq = 2.5 0.2v, vss = vssq = 0v, unless otherwise noted) 1394 908 983 4004 4259 3104 3269 3374 3629 1844 2009 1394 1469 1469 1214 1289 2744 2909 2520 2819 -10 -75 active power-down standby current: one bank active; power-down mode; cke v il (max); t ck = t ck min ma ma ma self refresh current: cke 0.2v auto refresh current: t rc = t rfc (min) operating current: burst = 2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; cl = 2.5; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle operating current: burst = 2; reads; continuous burst;one bank active; address and control inputs changing once per clock cycle; cl = 2.5; t ck = t ck min; iout = 0 ma active standby current: /cs > vih (min); cke > vih (min); one bank; active-precharge; t rc = t ras max; t ck = t ck min; dq,dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle idle standby current: /cs > vih (min); all banks idle; cke > vih (min); t ck = t ck min; address and other control inputs changing once per clock cycle idd2p precharge power-down standby current: all banks idle; power-down mode; cke vil (max); t ck = t ck min ma operating current: one bank; active-read-precharge; burst = 2; t rc = t rc min; cl = 2.5; t ck = t ck min; iout= 0 ma;address and control inputs changing once per clock cycle operating current: one bank; active-precharge; t rc = t rc min; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle parameter/test conditions idd4r idd3n ma ma ma ma ma ma idd6 idd5 idd4w idd3p idd2n idd1 idd0 notes unit limits(max) symbol symbol parameter/test conditions limits min. max. unit vih(ac) vil(ac) vid(ac) vix(ac) high-level input voltage (ac) low -level input voltage (ac) input differential voltage, clk and /clk input crossing point voltage, clk and /clk vref + 0.35 vref - 0.35 v v v v 0.7 0.5*v dd q-0.2 v dd q + 0.6 ioz i i off-state output current /q floating vo=0~v dd q input current / vin=0 ~ vddq a a -5 -10 5 10 0.5*v dd q+0.2 notes 7 8 9
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 18 ac timing requirements (component level) (ta=0 ~ 70 c , vdd = vddq = 2.5 0.2v, vss = vssq = 0v, unless otherwise noted) ns 15 10 15 10 cl=2 ns 15 8 15 7.5 cl=2.5 19 19 20 ns +0.6 +0.5 dqs-dq skew(for dqs and all dq signals) tdqsa ns min (tcl,tch) min (tcl,tc h) clk half period thp tck 0.55 0.45 0.55 0.45 clk low level width tcl clk cycle time tck 16 15 14 14 ac characteristics -10 -75 1.1 0.9 1.1 0.9 0.6 0.4 0.6 0.4 1.1 0.9 1.1 0.9 0.25 0.25 0.6 0.4 0.6 0.4 0 0 15 15 0.2 0.2 0.2 0.2 0.35 0.35 0.35 0.35 1.25 0.75 1.25 0.75 thp-1.0 thp-0.75 +0.6 +0.5 +0.8 -0.8 +0.75 -0.75 +0.8 -0.8 +0.75 -0.75 2 1.75 tck tck ns ns tck tck ns ns tck tck tck tck tck ns ns ns ns ns ns ns 0.6 0.5 0.6 0.5 tck 0.45 0.55 0.45 +0.8 -0.8 +0.75 -0.75 +0.8 -0.8 +0.75 -0.75 max. min. max. min. parameter 0.55 read preamble trpre read postamble trpst twpre write preamble twpst write postamble twpres write preamble setup time input hold time (address and control) tih tis input setup time (address and control) tmrd mode register set command cycle time tdsh dqs falling edge hold time from clk tdss dqs falling edge to clk setup time tdqsl dqs input low level width tdqsh dqs input high level width tdqss write command to first dqs latching transition tqh dq/dqs output hold time from dqs tdqsq dqs-dq skew(for dqs and associated dq signals) data-out-low impedance time from clk//clk tlz thz data-out-high impedance time from clk//clk tdipw dq and dm input pulse width (for each input) input hold time(dq,dm) input setup time (dq,dm) tds tdh tch clk high level width ns dq output valid data delay time from clk//clk tdqsck dq output valid data delay time from clk//clk ns tac notes unit symbol
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 19 18 17 7.8 7.8 1 1 1 1 200 200 80 75 1 1 15 15 15 15 20 20 20 20 80 75 70 65 120,000 50 120,000 45 u s tck tck tck ns tck ns ns ns ns ns average periodic refresh interval trefi exit power down to -read command txprd exit power down to command txpnr txsrd exit self ref. to -read command txsnr exit self ref. to non-read command twtr internal write to read command delay ns 35 35 auto precharge write recovery + precharge time tdal -10 -75 ac characteristics max. min. max. min. parameter twr write recovery time trrd act to act delay time row precharge time row to column delay trp trcd trfc auto ref. to active/auto ref. command period ns row cycle time(operation) trc row active time ns tras notes unit symbol output load condition (for component measurement) dq output timing measurement reference point v ref v ref dqs v out v ref 30pf 50ohm v tt =v ref zo=50 ohm 10cm ac timing requirements(continues) (ta=0 ~ 70 c , vdd = vddq = 2.5 0.2v, vss = vssq = 0v, unless otherwise noted)
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 20 notes 1. all voltages referenced to vss. 2. tests for ac timing, idd, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. ac timing and idd tests may use a vil to vih swing of up to 1.5v in the test environment, but input timing is still referenced to vref (or to the crossing point for ck//ck), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between vil(ac) and vih(ac). 4. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above (below) the dc input low (high) level. 5. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. peak-to-peak noise on vref may not exceed +/-2% of the dc value. 6. vtt is not applied directly to the device. vtt is a system supply for signal termination resistors, is expected to be set equal to vref, and must track variations in the dc level of vref. 7. vid is the magnitude of the difference between the input level on clk and the input level on /clk. 8. the value of vix is expected to equal 0.5*vddq of the transmitting device and must track variations in the dc level of the same. 9. enables on-chip refresh and address counters. 10. idd specification are tested after the device is properly initialized. 11. this parameter is sampled. vddq = +2.5v+/-0.2v, vdd = +2.5v+/-0.2v, f =100mhz, ta = 25 , vout(dc)= vddq/2, vout(peak to peak) = 25mv, dm inputs are grouped with i/o pins - reflecting the fact that they are matched in laoding (to faciliate trace matching at the board level). 12. the clk//clk input reference level (for signals other than clk//clk) is the point at which clk and /clk cross; the input reference level for signals other than clk//clk, is vref. 13. inputs are not recognized as valid until vref stabilized. exception: during the period before vref stabilizes, cke=< 0.3vddq is recognized as low. 14. t hz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz), or begins driving (lz). 15. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 16. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this clk edge. a valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from high-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on tdqss. 17. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 18. txprd should be 200 tclk in the condition of the unstable clk operation during the power down mode. 19. for command/address and clk & /clk slew rate >1.0v/ns. 20. min(tcl, tch)refers to the smaller of the actual clock low time and the actualclock high time as provided to the device. c o
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 21 /clk dqs tis tih vref clk valid data read operation tac tdqsck tcl tch tck tdqsq tdv trpre trpst dqs /clk clk tdqss tds tdh twpre write operation / tdqss=max. tdss twpres twpst dqs /clk clk tdqss tds tdh twpre write operation / tdqss=min. tdsh twpres twpst dq dq dq cmd & add. (component level) tdqsl tdqsh tdqsl tdqsh
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 22 a precharge command can be issued at bl/2(discrete) from a read command without data loss. precharge all bank activation and precharge all (bl=8, cl=2 (discrete level)) command a0-9,11-12 a10 ba0,1 dq act xa xa 00 read y 0 00 act xb xb 01 pre trrd trcd 1 act xb xb 01 tras trp trcmin 2 act command / trcmin dqs qa0 bl/2 operational description bank activate the ddr sdram has four independent banks. each bank is activated by the act command with the bank addresses (ba0,1). a row is indicated by the row address a12-0. the minimum activation interval between one bank and the other bank is trrd. maximum 2 act commands are allowed within trc,although the number of banks which are active concurrently is not limited. precharge the pre command deactivates the bank indicated by ba0,1. when multiple banks are active, the precharge all command (prea,pre+a10=h) is available to deactivate them at the same time. after trp from the precharge, an act command to the same bank can be issued. qa1 qa2 qa3 qa4 qa5 qa6 qa7 /clk clk module input and output timing.
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 23 read after trcd from the bank activation, a read command can be issued. 1st output data is available after the /cas latency from the read, followed by (bl-1) consecutive data when the burst length is bl. the start address is specified by a11,a9-a0, and the address sequence of burst data is defined by the burst type. a read command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous output data by interleaving the multiple banks. when a10 is high at a read command, the auto-precharge(reada) is performed. any command(read,write,pre,act) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at bl/2(discrete, in case of module, bl/2+1) after reada. the next act command can be issued after (bl/2+trp) from the previous reada. multi bank interleaving read (bl=8, cl=2(discrete level)) /clk command a0-9,11-12 a10 ba0,1 dq act xa xa 00 read y 0 00 read y 0 10 act xb xb 10 pre 0 00 trcd module /cas latency(discrete cl + 1) burst length dqs qa0 clk qa1 qa2 qa3 qa4 qa5 qa6 qa7 qb0 qb1 qb2 qb3 qb4 qb5 qb7 module input and output timing.
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 24 read with auto-precharge (bl=8, cl=2(discrete)) command a0-9,11-12 a10 ba0,1 dq act xa xa 00 read y 1 00 act xb xb 00 internal precharge start (bl/2+1 in case of module) trcd trp bl/2 + trp bl/2 dqs /clk clk qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 read auto-precharge timing (bl=8) command act read dq cl=2.5 bl/2 dq cl=2 qa0 /clk clk qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 qa1 qa2 qa3 qa4 qa5 qa6 qa7 module input and output timing. module input and output timing. discrete internal precharge start timing (in case of module, precharge start at bl/2+1) cl=3.5 cl=3 module
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 25 write after trcd from the bank activation, a write command can be issued. 1st input data is set from the write command with data strobe input, following (bl-1) data are written into ram, when the burst length is bl. the start address is specified by a11,a9-a0, and the address sequence of burst data is defined by the burst type. a write command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous input data by interleaving the multiple banks. from the last data to the pre command, the write recovery time (twrp) is required. when a10 is high at a write command, the auto-precharge(writea) is performed. any command(read,write,pre,act) to the same bank is inhibited till the internal precharge is complete. the next act command can be issued after tdal from the last input data cycle. write with auto-precharge (bl=8) command a0-9,11-12 a10 ba0,1 dq act xa 00 write 1 00 act xb 00 trcd da0 dqs /clk clk da1 da2 da3 da4 da5 da6 da7 tdal xa y xb multi bank interleaving write (bl=8) command a0-9,11-12 a10 ba0,1 dq act xa 00 write 00 write 0 0 10 act xb 10 0 10 trcd trcd pre xa 0 00 pre dqs /clk clk da0 da1 da2 da3 da4 da5 da6 da7 db0 db1 db2 db3 db4 db5 db6 db7 xa ya yb xb module input and output timing. module input and output timing.
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 26 burst interruption [read interrupted by read] burst read operation can be interrupted by new read of any bank. random column access is allowed. read to read interval is minimum 1clk. [read interrupted by precharge] burst read operation can be interrupted by precharge of the same bank. read to pre interval is minimum 1 clk. a pre command to output disable latency is equivalent to the /cas latency. as a result, read to pre interval determines valid data length to be output. the figure below shows examples of bl=8. read interrupted by precharge (bl=8) cl=2.5 command dqs command dq command dq q0 q1 q2 q3 q0 q1 read interrupted by read (bl=8, cl=2(discrete)) command a0-9,11 a10 ba0,1 dq yi read read read read yj yk yl 0 0 0 0 00 10 00 01 dqs qai0 qai1 qaj0 qaj1 qaj2 qaj3 qak0 qak1 qak2 qak3 qak4 qak5 qal0 qal1 qal2 qal3 qal4 qal5 qal6 qal7 /clk clk /clk clk dq q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dqs module input and output timing. module input and output timing. discrete cl=3.5 module
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 27 read interrupted by precharge (bl=8) cl=2.0 /clk clk command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dqs module input and output timing. discrete cl=3.0 module
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 28 [read interrupted by burst stop] burst read operation can be interrupted by a burst stop command(term). read to term interval is minimum 1 clk. a term command to output disable latency is equivalent to the /cas latency. as a result, read to term interval determines valid data length to be output. the figure below shows examples of bl=8. read interrupted by term (bl=8) cl=2.5 command dqs command dq command dq q0 q1 q2 q3 q0 q1 /clk clk dq q0 q1 q2 q3 q4 q5 term read read term read term dqs dqs cl=2.0 command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 term read read term read term dqs dqs module input and output timing. discrete cl=3.5 module discrete cl=3.0 module
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 29 [read interrupted by write with term] read interrupted by term (bl=8) cl=2.5 command dq q0 q1 q2 q3 /clk clk read term dqs write d 0 d 1 d 2 d 3 cl=2.0 command dq q0 q1 q2 q3 read term dqs write d 0 d 1 d 2 d 3 d 4 d 5 module input and output timing. discrete cl=3.5 module discrete cl=3.0 module
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 30 write interrupted by write (bl=8) command a0-9,11 a10 ba0,1 write yi 0 00 write yk 0 10 write yj 0 00 write yl 0 00 [write interrupted by write] burst write operation can be interrupted by write of any bank. random column access is allowed. write to write interval is minimum 1 clk. dq dai1 daj1 daj3 dak1 dak3 dak5 dal1 dqs dal2 dal3 dal5 dal6 dal7 dal4 dal0 dak4 dak2 dak0 dai0 daj0 daj2 /clk clk module input and output timing.
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 31 [initialize and mode register sets] command /clk clk emrs pre nop mrs pre ar ar mrs act code code xa code xa 1 0 xa a0-9,11,12 a10 code 1 ba0,1 dqs dq 1 0 0 0 0 code tmrd tmrd trp trfc trfc tmrd [auto refresh] single cycle of auto-refresh is initiated with a refa(/cs=/ras=/cas=l,/we=cke=h) command. the refresh address is generated internally. 8192 refa cycles within 64ms refresh 256mbits memory cells. the auto-refresh is performed on 4 banks concurrently. before performing an auto refresh, all banks must be in the idle state. auto-refresh to auto-refresh interval is minimum trfc . any command must not be supplied to the device before trfc from the refa command. auto-refresh /ras cke /cs /cas /we a0-12 ba0,1 nop or deselect trfc auto refresh on all banks auto refresh on all banks /clk clk code
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 32 [self refresh] self -refresh mode is entered by issuing a refs command (/cs=/ras=/cas=l,/we=h,cke=l). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self-refresh mode, cke is asynchronous and the only enable input, all other inputs including clk are disabled and ignored, so that power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable clk inputs, asserting desel or nop command and then asserting cke for longer than txsnr/txsrd. self-refresh /ras cke /cs /cas /we a0-12 ba0,1 txsnr self refresh exit /clk clk x y x y txsrd act read
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 33 [ asynchronous self refresh] asynchronous self -refresh mode is entered by cke=l within 2 tclk after issuing a refa command (/cs=/ras=/cas=l,/we=h). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self-refresh mode, cke is asynchronous and the only enable input, all other inputs including clk are disabled and ignored, so that power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable clk inputs, asserting desel or nop command and then asserting cke for longer than txsnr/txsrd. asynchronous self-refresh /ras cke /cs /cas /we a0-12 ba0,1 txsnr self refresh exit max 2 tclk /clk clk act
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 34 [power down] the purpose of clk suspend is power down. cke is synchronous input except during the self-refresh mode. a command at cycle is ignored. from cke=h to normal function, dll recovery time is not required in the condition of the stable clk operation during the power down mode. /clk clk power down by cke command pre cke command act cke standby power down active power down nop nop valid nop nop valid txpnr/ txprd
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 35 serial presence detect table i byte function described spd enrty data spd data(hex) 0 number of serial pd bytes written during production 128 80 1 total # bytes of spd memory device 256 bytes 08 2 fundamental memory type sdram ddr 07 3 # row addresses on this assembly 13 4 # column addresses on this assembly 11 5 # module banks on this assembly 2 bank 02 6 data width of this assembly... x72 48 7 ... data width continuation 0 00 8 voltage interface standard of this assembly sstl2.5v 04 9 sdram cycletime at max. supported cas latency (cl). cycle time for cl=2.5 10 sdram access from clock tac for cl=2.5 11 dimm configuration type (non-parity,parity,ecc) ecc 02 12 refresh rate/type 13 sdram width,primary dram x4 04 14 error checking sdram data width x4 04 15 miimum clock delay, random column access 01 16 burst lengths supported 2, 4, 8 0e 17 number of device banks 4bank 04 18 cas# latency 2.0, 2.5 0c 19 cs# latency 20 we latency 21 sdram module attributes registered with pll 26 22 sdram device attributes:general vdd + 0.2v 00 23 sdram cycle time(2nd highest cas latency) cycle time for cl=2 24 sdram access form clock(2nd highest cas latency) 8 0 tac for cl=2 25 sdram cycle time(3rd highest cas latency) 26 sdram access form clock(3rd highest cas latency) 27 minimum row precharge time (trp) 15 ns 50 28 minimum row active to row active delay (trrd) 20ns 3c 8.0 ns -10 10ns a0 75 -75 29 ras to cas delay minv (trcd) 20ns 2d 30 active to precharge min (tras) 32 7.5 ns +0.75 ns +0.8 ns -75 -10 -75 -10 -75 -10 -75 -10 45 ns 50 ns n/a +0.75 ns +0.8ns differential clock 0d 0b 75 80 75 80 00 00 00 50 7.8us/sr 8 2 0 1 02 01 1 clock 10ns a0 -75 -10 -75 -10 n/a 00 n/a n/a
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 36 serial presence detect table ii 31 density of each bank on module 512 mbyte 8 0 36-61 superset information (may be used in future) option 00 62 spd revision 63 checksum for bytes 0-62 check sum for -10 64-71 manufactures jedec id code per jep-108e mitsubishi 1cffffffffffffff 72 manufacturing location manufacture location xx 73-90 manufactures part number 91-92 revision code pcb revision rrrr 93-94 manufacturing date year/week code yyww 95-98 assembly serial number serial number ssssssss 99-127 reserved undefined 00 128-255 32 command and address signal input setup time 33 command and address signal input hold time 34 data signal input setup time 35 data signal input hold time 0 00 check sum for -75 mh64d72klg-75 mh64d72klg-10 4d4832384437324b4c472d37352020202020 4d4832384437324b4c472d31302020202020 -75 -10 -75 -10 -75 -10 -75 -10 0.9ns 1.1ns 0.9 ns 1.1ns 0.5 ns 0.6 ns 0.5 ns 0.6 ns open for customer use undefined 00 9 0 b 0 9 0 b 0 5 0 6 0 5 0 6 0 11 97
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 37 eeprom components a.c. and d.c. characteristics limits min. typ. max. v v 0 5.5 0 supply voltage supply voltage v cc v ss 2.2 v v -1 input high voltage input low voltage v ih v il symbol parameter units vccx0.3 vccx0.7 v output low voltage v ol 0.4 eeprom a.c.timing parameters (ta=0 to 70 c ) limits min. max. khz ns 200 100 4.7 scl clock frequency noise supression time constant at scl, sda inputs fscl ti us us 4. 7 scl low to sda data out valid time the bus must be free before a new transmission can start taa tbuf symbol parameter units 4.0 us start condition hold time thd:sta 4.0 us clock low time tlow 4.7 us clock high time thigh 0 us start condition setup time tsu:sta 250 us data in hold time thd:dat ns data in setup time tsu:dat us sda and scl rise time tr ns sda and scl fall time tf us stop condition setup time tsu:sto 4.0 ns data out hold time tdh 100 ms write cycle time twr twr is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/program cycle. 0 300 3.5 1 10 scl sda in t su:sta t hd:sta t f t low t high t r t hd:dat t su:dat t su:sto t buf sda out t aa t dh vcc+0.5
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 38 133.35 6.35 max 1.27+ 0.10 2 - 2.50
mitsubishi lsis mitsubishi electric mh28d72 k lg-75,-10 9,663,676,416 -bit (134,217,728-word by 72-bit) double data rate synchronous dram module mit-ds-0412-0.1 21 .mar.2001 preliminary spec. some contents are subject to change without notice. 39 keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1.these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. 2.mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3.all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor hom e page ( http://www.mitsubishichips.com ). 4.when using any or all of the information contained in these materials, including product data, diagrams, charts, programs and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6.the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. 7.if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8.please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.

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