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overview the lc74788, lc74788m, and LC74788JM are on- screen display controller cmos ics that display characters and patterns on the tv screen under microprocessor control. these ics support 12 18 dot characters and can display 12 lines by 24 characters of text. features ? display format: 24 characters by 12 rows (up to 288 characters) ? character format: 12 (horizontal) 18 (vertical) dots ? character sizes: three sizes each in the horizontal and vertical directions ? characters in font: 128 (128 characters, one spacing character, and one transparent spacing character) ? initial display positions: 64 horizontal positions and 64 vertical positions ? blinking: specifiable in character units ? blinking types: two periods supported: about 1.0 second and about 0.5 second ? blanking: over the whole font (12 18 dots) ? background color: 8 colors (internal synchronization mode): 2f sc and 4f sc ? line background color can be set for 3 lines line background color: 8 colors (internal synchronization mode): 2f sc and 4f sc ? external control input: 8-bit serial input format ? on-chip sync separator circuit ? video outputs - ntsc, pal, pal-n, pal-m, ntsc 4.43, and pal60 format composite video outputs ? package 24-pin plastic dip-24s (300 mil) 24-pin plastic mfp-24 (375 mil) 24-pin plastic mfp-24s (300 mil) package dimensions unit: mm 3067-dip24s unit: mm 3045b-mfp24 unit: mm 3112-mfp24s cmos ic 30698ha (ot) no. 5731-1/23 sanyo: dip24s [lc74788] sanyo: mfp24 [lc74788m] sanyo: mfp24s [LC74788JM] sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan on-screen display controller lc74788, 74788m, 74788jm ordering number : en5731a
pin assignment no. 5731- 2 /23 lc74788, 74788m, 74788jm pin functions pin no. pin function notes 1 v ss 1 ground ground connection (digital system ground) 2 xtal in these pins are used either to connect the crystal and capacitors used to form an external crystal oscillator crystal oscillator circuit to generate the internal synchronizing signals, or to input an external xtal out (mute input) clock signal (2fsc or 4fsc). as a mask option, the xtalout pin can be set to function as the 3 (mute) mute input pin. when this pin is set low, the video output is held at the pedestal level. (a pull- up resistor is built in and the input has hysteresis characteristics.) switches the mode between external clock input and crystal oscillator operation. a low level 4 ctrl1 crystal oscillator input switching selects crystal oscillator operation and a high level selects external clock input. as a mask (chablk) (chablk output) option, the ctrl1 input pin can be set to function as the chablk (character frame) output. this is a 3-value output. 5 hfton out background line output outputs the range signal specified by lna * , lnb * , and lnc * . outputs the crystal oscillator clock when rst is low. (this signal is not output after a reset command is executed.) 6 osc in lc oscillator connections for the inductor and capacitor that form the character output dot clock generation 7 osc out oscillator. outputs the state of the external synchronizing signal presence/absence judgment. outputs a 8 sync jdg external synchronizing signal high level when synchronizing signals are present. judgment output outputs the dot clock (lc oscillator) when rst is low. (this signal is not output on command resets.) 9 cs enable input serial data input circuit enable pin. serial data input is enabled when a low level is input. a pull-up resistor is built in. (this input has hysteresis characteristics.) 10 sclk clock input serial data input circuit clock input. a pull-up resistor is built in. (this input has hysteresis characteristics.) 11 sin data input serial data input. a pull-up resistor is built in. (this input has hysteresis characteristics.) 12 v dd 2 power supply composite video signal level adjustment power supply (analog system power supply) continued on next page. a08688 lc74788 lc74788m LC74788JM
no. 5731- 3 /23 lc74788, 74788m, 74788jm continued from preceding page. pin no. pin function notes 13 cv out video signal output composite video signal output 14 v ss 2 ground ground connection (analog system ground) 15 cv in video signal input composite video signal input 16 cv cr video signal input secam chrominance signal input 17 v dd 1 power supply power supply (+5 v: digital system power supply) video signal input to the internal sync separator circuit (used as either the horizontal 18 syn in sync separator circuit input synchronizing signal or the composite synchronizing signal input when the internal sync separator circuit is not used.) 19 sep c sync separator circuit bias internal sync separator circuit bias voltage monitor voltage 20 sep out composite synchronizing internal sync separator circuit composite synchronizing signal output. can be switched to signal output function as a signal (high, low, or st. pulse) output by the sel0 and mod0 setting. inputs the vertical synchronizing signal created by integrating the sep out pin output signal. 21 sep in vertical synchronizing signal input an integration circuit must be connected to the sep out pin. this pin must be tied to v dd 1 if unused. this pin can be switched to function as the frame signal input mode by setting sel1 high. this is valid when ctl3 is set high. this input has hysteresis characteristics. 22 cdlr background color phase background color phase adjustment. connect a resistor between this pin and ground. adjustment 23 rst reset input system reset input a pull-up resistor is built in and the input has hysteresis characteristics. 24 v dd 1 power supply (+5 v) power supply (+5 v: digital system power supply) note: both v dd 1 pins must be connected to the power supply.
no. 5731- 4 /23 lc74788, 74788m, 74788jm parameter symbol conditions ratings unit maximum supply voltage v dd max v dd 1 and v dd 2 v ss C0.3 to v ss +6.5 v maximum input voltage v in max all input pins v ss C0.3 to v dd +0.3 v maximum output voltage v out max hfton out , sync jdg , and sep out v ss C0.3 to v dd +0.3 v allowable power dissipation pd max ta = 25 c 350 mw operating temperature topr C30 to +70 c storage temperature tstg C40 to +125 c specifications absolute maximum ratings parameter symbol conditions ratings unit min typ max supply voltage v dd 1 v dd 1 4.5 5.0 5.5 v v dd 2 v dd 2 4.5 5.0 1.27v dd 1 v input high-level voltage v ih 1 rst, cs, sin, sclk, sep in , and mute 0.8v dd 1 v dd 1+0.3 v v ih 2 ctrl1 0.7v dd 1 v dd 1+0.3 v input low-level voltage v il 1 rst, cs, sin, sclk, sep in , and mute v ss C0.3 0.2v dd 1 v v il 2 ctrl1 v ss C0.3 0.3v dd 1 v pull-up resistance r pu rst, cs, sin, sclk, and mute 25 50 90 k applies to pins set up by options. v in 1 cv in : v dd 1 = 5 v 2.0 vp-p composite video signal input voltage v in 2 syn in : v dd 1 = 5 v 2.0 2.5 vp-p v in 3 cv cr : v dd 1 = 5 v 2.0 vp-p input voltage v in 4 xtal in (when used for external clock input) 0.10 5.0 vp-p f in = 2fsc or 4fsc ; v dd 1 = 5 v xtal in and xtal out oscillator pins (2fsc: ntsc) 7.159 mhz xtal in and xtal out oscillator pins (4fsc: ntsc) 14.318 mhz xtal in and xtal out oscillator pins (2fsc: pal) 8.867 mhz f osc 1 xtal in and xtal out oscillator pins (4fsc: pal) 17.734 mhz oscillator frequencies xtal in and xtal out oscillator pins (2fsc: pal-m) 7.151 mhz xtal in and xtal out oscillator pins (4fsc: pal-m) 14.302 mhz xtal in and xtal out oscillator pins (2fsc: pal-n) 7.164 mhz xtal in and xtal out oscillator pins (4fsc: pal-n) 14.328 mhz f osc 2 osc in and osc out oscillator pins (lc oscillator) 5 10 mhz allowable operating ranges note: applications must be especially cautious about noise when using the xtal in input pin in clock input mode.
no. 5731- 5 /23 lc74788, 74788m, 74788jm parameter symbol pin conditions ratings unit min typ max input off leakage current i leak1 cv in and cv cr 1 a output off leakage current i leak2 cv out 1 a output high-level voltage v oh1 hfton out , sync jdg , and sep out v dd 1 = 4.5 v, 3.5 v i oh = C1.0 ma output low-level voltage v ol 1 hfton out , sync jdg , and sep out v dd 1 = 4.5 v, 1.0 v i ol = C1.0 ma h 3.3 5.0 v three-value output voltage v o chablk v dd 1 = 5.0 v m 1.8 2.3 v l 0 0.8 v input current i ih rst, cs, sin, sclk, ctrl1, v in = v dd 1 1 a sep in , and mute i il ctrl1 and osc in v in = v ss 1 C1 a all outputs: open operating mode current drain i dd 1 v dd 1 xtal:7.159 mhz 15 ma lc:8 mhz i dd 2 v dd 2 v dd 2 = 5 v 20 ma (1) 0.70 0.82 0.94 sync level v sn (2) 0.89 1.01 1.13 v (3) 1.18 1.30 1.42 (1) 1.32 1.44 1.56 pedestal level v pd (2) 1.52 1.64 1.76 v (3) 1.81 1.93 2.05 (1) 0.98 1.10 1.22 color burst low level v cbl (2) 1.17 1.29 1.41 v (3) 1.46 1.58 1.70 (1) 1.63 1.75 1.87 color burst high level v cbh (2) 1.83 1.95 2.07 v (3) 2.11 2.23 2.35 (1) 1.17 1.29 1.41 background color low level (other than blue) v rsl 0 (2) 1.36 1.48 1.60 v (3) 1.65 1.77 1.89 (1) 2.33 2.45 2.57 background color high level (other than blue) v rsh 0 cv out (2) 2.52 2.64 2.76 v (1): when the sync level = 0.8 v v dd 1 = 5.0 v (3) 2.81 2.93 3.05 (2): when the sync level = 1.0 v v dd 2 = 5.0 v (1) 1.08 1.20 1.32 blue background 1 low level v rsl 1 (3): when the sync level = 1.3 v (2) 1.27 1.39 1.51 v (3) 1.56 1.68 1.80 (1) 1.49 1.61 1.83 blue background 2 low level v rsl 2 (2) 1.68 1.80 1.92 v (3) 1.97 2.09 2.21 (1) 1.97 2.09 2.21 blue background 1 and 2 high level v rsh 1, 2 (2) 2.17 2.29 2.41 v (3) 2.46 2.58 2.70 (1) 1.40 1.52 1.64 frame level 0 v bk 0 (2) 1.60 1.72 1.84 v (3) 1.89 2.01 2.13 (1) 1.97 2.09 2.21 frame level 1 v bk 1 (2) 2.17 2.29 2.41 v (3) 2.46 2.58 2.70 (1) 2.55 2.67 2.79 character level v cha (2) 2.75 2.87 2.99 v (3) 3.04 3.16 3.28 electrical characteristics at ta = C30 to +70 c. v dd 1 = 5 v unless otherwise specified. note: blue background 1 or 2 are option settings.
no. 5731- 6 /23 lc74788, 74788m, 74788jm parameter symbol conditions ratings unit min typ max minimum input pulse width t w(sclk) sclk 200 ns t w(cs) cs (the period when cs is high) 1 s data setup time t su(cs) cs 200 ns t su(sin) sin 200 ns data hold time t h(cs) cs 2 s t h(sin) sin 200 ns one word write time t word the time to write 8 bits of data 4.2 s t wt the ram data write time 1 s timing characteristics at ta = C30 to +70 c, v dd 1 = 5 0.5 v serial data input timing first byte second byte a08689
system block diagram no. 5731- 7 /23 lc74788, 74788m, 74788jm serial to parallel converter 8-bit latch + command decode horizontal character size register vertical character size register horizontal display position register vertical display position register blinking and reverse control register display control register ram write address counter display ram deco- der decoder font rom shift register character output control background control video output control blinking and reverse control circuit vertical dot counter horizontal dot counter vertical size counter horizontal size counter vertical display position detector horizontal display position detector line control counter character control counter synchroni- zation determination composite sync signal separation control sync separator character output dot clock generator sync signal generator timing generator a08690
display control commands display control commands have an 8-bit format and are transferred using the serial input function. commands consist of a command identification code in the first byte and command data in the following bytes. the following commands are supported. 1 command0: display memory (vram) write address setup command 2 command1: display character data write command 3 command2: vertical display start position and vertical character size setup command 4 command3: horizontal display start position and horizontal character size setup command 5 command4: display control setup command 6 command5: display control setup command 7 command6: synchronizing signal detection setup command 8 command7: display control setup command 9 command8: display control setup command 10 command9: display control setup command 11 command10: display control setup command once written, a first byte command identification code is stored until the next first byte is written. however, when the display character data write command (command1) is written, the lc74788/m/jm locks into the display character data write mode, and another first byte cannot be written. when the cs pin is set high, the lc74788/m/jm is set to the command0 (display memory write address setup mode) state. no. 5731- 8 /23 lc74788, 74788m, 74788jm display control command table first byte second byte command command identification code data data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 command0 1 0 0 0 v3 v2 v1 v0 0 0 0 h4 h3 h2 h1 h0 write address setup command1 1 0 0 1 0 0 0 at c7 c6 c5 c4 c3 c2 c1 c0 character write command2 1 0 1 0 vs vs vs vs 0 fs vp vp vp vp vp vp vertical character size and vertical 21 20 11 10 5 4 3 2 1 0 display start position command3 1 0 1 1 hs hs hs hs 0 lc hp hp hp hp hp hp horizontal character size and 21 20 11 10 5 4 3 2 1 0 horizontal display start position command4 1 1 0 0 tst ram osc sys 0 blk blk blk bk bk rv dsp display control mod ers stp rst 2 1 0 1 0 on command5 1 1 0 1 np np non int 0 np hlf bcl cb ph ph ph display control 1 0 2 int 2 1 0 command6 1 1 1 0 sel mod dis mut 0 rn rn rn sn sn sn sn synchronizing signal detection 0 0 lin 2 1 0 3 2 1 0 command7 1 1 1 1 0 0 sel ctl 0 cin cin vnp vsp msk msk egl display control 1 3 sel ctl sel sel ers sel command8 1 1 1 1 0 1 vsy hsy 0 lna lna lna lna lpa lpa lpa display control sel sel 3 2 1 0 2 1 0 command9 1 1 1 1 1 0 lnb mod 0 lnb lnb lnb lnb lpb lpb lpb display control sel 2 3 2 1 0 2 1 0 command10 1 1 1 1 1 1 lnc mod 0 lnc lnc lnc lnc lpc lpc lpc display control sel 3 3 2 1 0 2 1 0
command0 (display memory write address setup command) no. 5731- 9 /23 lc74788, 74788m, 74788jm ? first byte da register contents notes 0 to 7 state function 7 1 6 0 command 0 identification code 5 0 sets the display memory write address. 4 0 3 v3 0 1 2 v2 0 1 display memory line address (0 to b hexadecimal) 1 v1 0 1 0 v0 0 1 ? second byte da register contents notes 0 to 7 state function 7 1 second byte identification code 6 0 5 0 4 h4 0 1 3 h3 0 1 2 h2 0 display memory column address (0 to 17 hexadecimal) 1 1 h1 0 1 0 h0 0 1 note: all registers are set to 0 when the lc74788/m/jm is reset by the rst pin.
no. 5731- 10 /23 lc74788, 74788m, 74788jm command1 (display character data write setup command) ? first byte da register contents notes 0 to 7 state function 7 1 6 0 command 1 identification code. 5 0 sets up display character data write mode. 4 1 3 0 2 0 1 0 0 at 0 character attribute off 1 character attribute on when this command is input, the lc74788/m/jm locks in the display character data write mode until the cs pin goes high ? second byte da register contents notes 0 to 7 state function 7 c7 0 1 6 c6 0 1 5 c5 0 1 character code (00 to 7f hexadecimal) 4 c4 0 1 (fe (hex): spacing character) 3 c3 0 (ff (hex): transparent spacing character) 1 2 c2 0 1 1 c1 0 1 0 c0 0 1 note: all registers are set to 0 when the lc74788/m/jm is reset by the rst pin.
no. 5731- 11 /23 lc74788, 74788m, 74788jm command2: vertical display start position and vertical character size setup command ? first byte da register contents notes 0 to 7 state function 7 1 6 0 command 2 identification code 5 1 sets the vertical display start position and the vertical character size 4 0 3 vs21 0 1 second line vertical character size 2 vs20 0 1 1 vs11 0 1 first line vertical character size 0 vs10 0 1 vs20 0 1 vs21 0 1h/dot 2h/dot 1 3h/dot 1h/dot the vertical display start position is set by the 6 bits vp0 to vp5. the weight of bit 1 is 2h. ? second byte da register contents notes 0 to 7 state function 7 0 second byte identification bit 6 f s 0 crystal oscillator frequency: 2fsc 1 crystal oscillator frequency: 4fsc 5 vp5 0 if vs is the vertical display start position then: (msb) 1 vs = a + h (2 s 2 n vp n ) 4 vp4 0 h: the horizontal synchronization pulse period 1 a = 20 h (in 525-line systems) 3 vp3 0 = 25 h (in 625-line systems) 1 2 vp2 0 1 1 vp1 0 1 0 vp0 0 (lsb) 1 note: all registers are set to 0 when the lc74788/m/jm is reset by the rst pin. 5 n=0 vs10 0 1 vs11 0 1h/dot 2h/dot 1 3h/dot 1h/dot character display area
no. 5731- 12 /23 lc74788, 74788m, 74788jm command3 (horizontal display start position and horizontal size setup command) ? first byte da register contents notes 0 to 7 state function 7 1 6 0 command 3 identification code 5 1 sets the horizontal display start position and the horizontal character size. 4 1 3 hs21 0 1 second line horizontal character size 2 hs20 0 1 1 hs11 0 1 first line horizontal character size 0 hs10 0 1 hs20 0 1 hs21 0 1 tc/dot 2 tc/dot 1 3 tc/dot 1 tc/dot ? second byte da register contents notes 0 to 7 state function 7 0 second byte identification bit 6 lc 0 use the lc oscillator for the dot clock 1 use the crystal oscillator for the dot clock 5 hp5 0 if hs is the horizontal start position then: (msb) 1 hs =tc (2 s 2 n hp n ) 4 hp4 0 tc: period of the oscillator connected to oscin/oscout in operating 1 mode. 3 hp3 0 1 2 hp2 0 1 1 hp1 0 1 0 hp0 0 (lsb) 1 note: all registers are set to 0 when the lc74788/m/jm is reset by the rst pin. 5 n=0 hs10 0 1 hs11 0 1 tc/dot 2 tc/dot 1 3 tc/dot 1 tc/dot the horizontal display start position is set by the 6 bits hp0 to hp5. the weight of bit 1 is 2tc. selects the dot clock used for character display in the horizontal direction.
no. 5731- 13 /23 lc74788, 74788m, 74788jm command4 (display control setup command) ? first byte da register contents notes 0 to 7 state function 7 1 6 1 command 4 identification code. 5 0 display character data write setup. 4 0 3 tstmod 0 normal operating mode this bit must be set to 0. 1 test mode 2 ramers 0 1 erase display ram. (the ram data is set to ff hexadecimal.) 1 oscstp 0 do not stop the crystal and lc oscillators. 1 stop the crystal and lc oscillators. 0 sysrst 0 1 reset all registers and turn display off. ? second byte da register contents notes 0 to 7 state function 7 0 second byte identification bit 6 blk2 0 character display area specifies the size for complete fill in 1 video display area 5 blk1 0 1 changes the blanking size 4 blk0 0 1 3 bk1 0 blinking period: about 0.5 s switches the blinking period 1 blinking period: about 1.0 s 2 bk0 0 blinking off 1 blinking on 1 rv 0 reverse video off 1 reverse video on 0 dspon 0 character display off 1 character display on note: all registers are set to 0 when the lc74788/m/jm is reset by the rst pin. blinking in reverse video mode switches the display between normal character display and reverse video display. erasing ram takes about 500 s. (this operation must be executed in the dspoff state.) valid in external synchronization mode when character display is off. the registers are reset when the cs pin is low, and the reset state is cleared when cs is set high. blk0 0 1 blk1 0 blanking off character size 1 frame size complete fill in
no. 5731- 14 /23 lc74788, 74788m, 74788jm command5 (display control setup command) ? first byte da register contents notes 0 to 7 state function 7 1 6 1 command 5 identification code 5 0 display control setup 4 1 3 np1 0 1 2 np0 0 1 1 non 0 interlaced 1 noninterlaced 0 int 0 external synchronization 1 internal synchronization switches between the ntsc, pal, pal-n, pal-m, ntsc 4.43, and pal60 formats. switches between external and internal synchronization switches between interlaced and noninterlaced video. np2 np1 np0 format 0 0 0 ntsc 0 0 1 pal-m 0 1 0 pal 0 1 1 pal-n 1 0 0 ntsc4.43 1 0 1 pal60 ? second byte da register contents notes 0 to 7 state function 7 0 second byte identification bit 6 np2 0 set with np0 and np1. 1 5 hlfint 0 normal mode 1 half internal synchronization mode 4 bcl 0 background color on only valid in internal synchronization mode. 1 no background color (only the background level is set) 3 cb 0 color burst signal output. only valid when bcl is high. 1 color burst signal output stopped. 2 ph2 0 1 1 ph1 0 1 0 ph0 0 1 note: all registers are set to 0 when the lc74786/m/jm is reset by the rst pin. background color specification ph2 ph1 ph0 background color (phase) 0 0 0 cyan 0 0 1 yellow 0 1 0 red 0 1 1 blue 1 0 0 cyan blue 1 0 1 green 1 1 0 orange 1 1 1 magenta
da register contents notes 0 to 7 state function 7 1 6 1 command 6 identification code. 5 1 sets up synchronizing signal control. 4 0 3 sel0 0 1 2 mod0 0 1 1 dislin 0 12 lines switches the number of lines displayed 1 10 lines 0 mut 0 normal output cv out switching 1 cv in is cut and cv out is held at the pedestal level. sel0 mod sepout output 0 0 sync separator signal 0 1 low-level output 1 0 high-level output 1 1 st pulse signal no. 5731- 15 /23 lc74788, 74788m, 74788jm command6 (synchronizing signal detection setup command) ? first byte switches the sep out (pin 19) output ? second byte da register contents notes 0 to 7 state function 7 0 second byte identification bit 6 rn2 0 1 5 rn1 0 1 4 rn0 0 1 3 sn3 0 1 2 sn2 0 1 1 sn1 0 1 0 sn0 0 1 note: all registers are set to 0 when the lc74788/m/jm is reset by the rst pin. external synchronizing signal detection control. signal absent ? signal present transition detection sets the sampling period in which sync can be detected continuously in the horizontal synchronizing signal period (1h). external synchronizing signal detection control. signal present ? signal absent transition detection sets the sampling period in which sync cannot be detected continuously in the horizontal synchronizing signal period (1h). rn2 rn1 rn0 number of times hsync detected 0 0 0 0 times 0 0 1 4 times 0 1 0 8 times 1 0 0 16 times sn3 sn2 sn1 sn0 number of times hsync detected 0 0 0 0 not detected 0 0 0 1 32 times 0 0 1 0 64 times 0 1 0 0 128 times 1 0 0 0 256 times
no. 5731- 16 /23 lc74788, 74788m, 74788jm command7 (display control setup command) ? first byte da register contents notes 0 to 7 state function 7 1 6 0 command 7 identification code. 5 0 display control setup. 4 1 3 0 extended command 0 identification code 2 0 1 sel1 0 vertical synchronizing signal (external v separation) input switches the sep in (pin 20) input. 1 frame signal input only valid when ctl3 is high. 0 ctl3 0 use internal v separation switches v separation. 1 do not use internal v separation ? second byte da register contents notes 0 to 7 state function 7 0 second byte identification bit 6 cinsel 0 blanking area (the logical or of the character and frame signals) cv cr on signal switching 1 video signal display area 5 cinctl 0 cv cr : off cv cr on/off setting 1 cv cr : on 4 vnpsel 0 v falling edge detection switches the v acquisition polarity in external mode 1 v rising edge detection when internal v separation is used. 3 vspsel 0 vsep: about 8.9 s (for ntsc) switches the internal v separation period. 1 vsep: about 17.8 s (for ntsc) 2 mskers 0 mask valid clears the hsync and vsync masks. 1 mask invalid 1 msksel 0 3h (for ntsc) switches the vsync mask. 1 20h (for ntsc) 0 egl 0 frame level 0 only (v bk0 ) switches the frame level. note: all registers are set to 0 when the lc74786/m/jm is reset by the rst pin.
da register contents notes 0 to 7 state function 7 0 second byte identification bit 6 lna3 0 1 5 lna2 0 1 4 lna1 0 1 3 lna0 0 1 2 lpa2 0 1 1 lpa1 0 1 0 lpa0 0 1 no. 5731- 17 /23 lc74788, 74788m, 74788jm command8 (display control setup command) ? first byte da register contents notes 0 to 7 state function 7 1 6 1 command 8 identification code. 5 1 display control setup. 4 1 3 0 extended command 1 identification code 2 1 1 vsysel 0 negative polarity 1 positive polarity 0 hsysel 0 negative polarity 1 positive polarity sep in input polarity switching. only valid when ctl3 is high. syn in (only valid when the sync separator circuit is not used) and sep out input and output polarity switching specifies the line whose background is to be changed. (if the same line is specified to have different background colors with lna * , lnb * , and lnc * , then the setting specified by the last command issued will be valid. the previously specified registers (ln * and lp * ) will all be reset to 0.) specifies the background color ? second byte note: all registers are set to 0 when the lc74788/m/jm is reset by the rst pin. lna3 lna2 lna1 lna0 specified line 0 0 0 0 do not change the line background 0 0 0 1 line 1 0 0 1 0 line 2 0 0 1 1 line 3 0 1 0 0 line 4 0 1 0 1 line 5 0 1 1 0 line 6 0 1 1 1 line 7 1 0 0 0 line 8 1 0 0 1 line 9 1 0 1 0 line 10 1 0 1 1 line 11 1 1 line 12 lpa2 lpa1 lpa0 line background color (phase) 0 0 0 cyan 0 0 1 yellow 0 1 0 red 0 1 1 blue 1 0 0 cyan blue 1 0 1 green 1 1 0 orange 1 1 1 magenta
da register contents notes 0 to 7 state function 7 0 second byte identification bit 6 lnb3 0 1 5 lnb2 0 1 4 lnb1 0 1 3 lnb0 0 1 2 lpb2 0 1 1 lpb1 0 1 0 lpb0 0 1 no. 5731- 18 /23 lc74788, 74788m, 74788jm command9 (display control setup command) ? first byte da register contents notes 0 to 7 state function 7 1 6 1 command 9 identification code. 5 1 display control setup. 4 1 3 1 extended command 2 identification code 2 0 1 lnbsel 0 normal line background color operation 1 rv characters have the background color specified by ph * or the rv character background color is white. 0 mod2 0 the lnbsel: 1 setting specifications 1 rv characters have the background color specified by ph * , characters are white. switches the rv mode background color for the line specified by lnb * for characters specified for rv display. valid when lnbsel is high specifies the line whose background is to be changed. (if the same line is specified to have different background colors with lna * , lnb * , and lnc * , then the setting specified by the last command issued will be valid. the previously specified registers (ln * and lp * ) will all be reset to 0.) specifies the background color ? second byte note: all registers are set to 0 when the lc74788/m/jm is reset by the rst pin. lnb3 lnb2 lnb1 lnb0 specified line 0 0 0 0 do not change the line background 0 0 0 1 line 1 0 0 1 0 line 2 0 0 1 1 line 3 0 1 0 0 line 4 0 1 0 1 line 5 0 1 1 0 line 6 0 1 1 1 line 7 1 0 0 0 line 8 1 0 0 1 line 9 1 0 1 0 line 10 1 0 1 1 line 11 1 1 line 12 lpb2 lpb1 lpb0 line background color (phase) 0 0 0 cyan 0 0 1 yellow 0 1 0 red 0 1 1 blue 1 0 0 cyan blue 1 0 1 green 1 1 0 orange 1 1 1 magenta
da register contents notes 0 to 7 state function 7 0 second byte identification bit 6 lnc3 0 1 5 lnc2 0 1 4 lnc1 0 1 3 lnc0 0 1 2 lpc2 0 1 1 lpc1 0 1 0 lpc0 0 1 no. 5731- 19 /23 lc74788, 74788m, 74788jm command10 (display control setup command) ? first byte da register contents notes 0 to 7 state function 7 1 6 1 command 10 identification code. 5 1 display control setup. 4 1 3 1 extended command 3 identification code 2 1 1 lncsel 0 normal line background color operation 1 rv characters have the background color specified by ph * or the rv character background color is white. 0 mod3 0 the lncsel: 1 setting specifications 1 rv characters have the background color specified by ph * , characters are white. switches the rv mode background color for the line specified by lnc * for characters specified for rv display. valid when lncsel is high specifies the line whose background is to be changed. (if the same line is specified to have different background colors with lna * , lnb * , and lnc * , then the setting specified by the last command issued will be valid. the previously specified registers (ln * and lp * ) will all be reset to 0.) specifies the background color. ? second byte note: all registers are set to 0 when the lc74788/m/jm is reset by the rst pin. lnc3 lnc2 lnc1 lnc0 specified line 0 0 0 0 do not change the line background 0 0 0 1 line 1 0 0 1 0 line 2 0 0 1 1 line 3 0 1 0 0 line 4 0 1 0 1 line 5 0 1 1 0 line 6 0 1 1 1 line 7 1 0 0 0 line 8 1 0 0 1 line 9 1 0 1 0 line 10 1 0 1 1 line 11 1 1 line 12 lpc2 lpc1 lpc0 line background color (phase) 0 0 0 cyan 0 0 1 yellow 0 1 0 red 0 1 1 blue 1 0 0 cyan blue 1 0 1 green 1 1 0 orange 1 1 1 magenta
display screen structure the display consists of 12 lines of 24 characters. up to 288 characters can be displayed. the number of characters that can be displayed is reduced when enlarged characters are displayed. display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses. display screen structure (display memory addresses) no. 5731- 20 /23 lc74788, 74788m, 74788jm 24 characters 12 rows a08691
composite video signal output levels (internally generated levels) cv out output level waveform (v dd 2 = 5.0 v) no. 5731- 21 /23 lc74788, 74788m, 74788jm output level output voltage (1) [v] output voltage (2) [v] output voltage (3) [v] v cha : character 2.67 2.87 3.16 v rh 0 : background color (other than blue) high 2.45 2.64 2.93 v rsh 1, 2 : blue background color 1 and 2 high 2.09 2.29 2.58 v bk 1 : frame 1 2.09 2.29 2.58 v cbh : color burst high 1.75 1.95 2.23 v rsl 2 : blue background color 2 low 1.61 1.80 2.09 v bk 0 : frame 0 1.52 1.72 2.01 v pd : pedestal 1.44 1.64 1.93 v rsl 0 : background color (other than blue) low 1.29 1.48 1.77 v rsl 1 : blue background color 1 low 1.20 1.39 1.68 v cbl : color burst low 1.10 1.29 1.58 v sn : sync 0.82 1.01 1.30
sample application circuits (when the lc74788/m/jm is used in conjunction with a single-chip y/c circuit.) ? circuit using an external system clock input no. 5731- 22 /23 lc74788, 74788m, 74788jm ? circuit using a crystal oscillator micro- controller micro- controller a08693 a08694
ps no. 5731- 23 /23 lc74788, 74788m, 74788jm ? circuit using an external system clock input (when the pin 3 and 4 functions are modified by mask options) this catalog provides information as of march, 1998. specifications and information herein are subject to change without notice. n no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n anyone purchasing any products described or contained herein for an above-mentioned use shall: accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. note: when a sync tip level of 1.3 v dc (cv in input signal: sync tip = 1.3 v) is selected for the internal generated video signals by option settings, the electrolytic capacitor connected to syn in must be connected with the correct polarity. micro- controller a08695

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