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never stop thinking. microcontrollers data sheet, v 1.0, may 2003 C868 8-bit single-chip microcontroller
edition 2003-05 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2003. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
microcontrollers data sheet, v 1.0, may 2003 never stop thinking. C868 8-bit single-chip microcontroller
C868 revision history: 2003-05 v 1.0 previous version: - page subjects (major changes since last revision) current data updated description of i2c included we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
data sheet 5 v 1.0, 2003-05 C868 8-bit single-chip microcontroller c800 family C868 advance information ? c800 core : ?fully compatible to standard 8051 microcontroller ?superset of the 8051 architecture with 8 datapointers 40 mhz internal cpu clock ?external clock of 6.67 - 10.67 mhz at 50% duty cycle ? 300 ns instruction cycle time (@37.5 mhz cpu clock) 8 kbyte on-chip program rom for C868-1r and 8 kbyte on-chip program ram for C868-1s in-system programming support for programming the xram(C868-1r) or xram/ program ram(C868-1s) ?this feature is realized through 4kb boot rom 256 byte on-chip ram 256 byte on-chip xram (further features are on the next page) figure 1 C868 functional units 8-bit uart i/o xram 256 8 timer 2 watchdog timer port 1 5-bit i/o 8-bit port 3 cpu 8 datapointers 8-bit adc 16-bit capture/ ram 256 8 boot rom 4k x 8 compare unit timer 0 timer 1 analog/ rom/ram 8k 8 digital input 16-bit compare unit input 3-bit
C868 data sheet 6 v 1.0, 2003-05 one 8-bit and one 5 bits general purpose push-pull i/o ports ? enhanced sink current of 10 ma on port 1/3 (total max current of 43 ma @ 100 o c) three 16-bit timers/counters ? timer 0 / 1 (c501 compatible) ? timer 2 (up/down counter feature) ? timer 1 or 2 can be used for serial baudrate generator capture/compare unit for pwm signal generation ? 3-channel, 16-bit capture/compare unit ? 1-channel, 16-bit compare unit full duplex serial interface (uart) 5 channel 8-bit a/d converter ? start of conversion can be synchronized to capture/compare timer 12/13. 13 interrupt vectors with four priority levels programmable 16-bit watchdog timer brown out detection power saving modes ? slow-down mode ? idle mode (can be combined with slow-down mode) ? power-down mode with wake up capability through int0 or rxd pins. single power supply of 3.3v, internal voltage regulator for core voltage of 2.5v. p-dso-28-1, p-tssop-38-1 packages temperature ranges: saf-C868-1rr ba, saf-C868-1sr ba, saf-C868-1rg ba, saf-C868-1sg ba , saf-C868a-1rr ba, saf-C868a-1sr ba, saf-C868a-1rg ba, saf-C868a-1sg ba, saf-C868p-1sr ba, saf-C868p-1sg ba t a = ? 40 to 85 o c sak-C868-1rr ba, sak-C868-1sr ba, sak-C868-1rg ba, sak-C868-1sg ba , sak-C868a-1rr ba, sak-C868a-1sr ba, sak-C868a-1rg ba, sak-C868a-1sg ba, sak-C868p-1sr ba, sak-C868p-1sg ba t a = ? 40 to 125 o c
C868 data sheet 7 v 1.0, 2003-05 figure 2 logic symbol port 1 5-bit digital i/o port 3 8-bit digital i/o 5 adc channels 4 external interrupts reset ale/bsl ctrap txd C868 v ddp v ssp v aref v agnd v ddc v ssc rxd 3-bit digial input
C868 data sheet 8 v 1.0, 2003-05 figure 3 C868 pin configuration p-tssop-38 package (top view ) figure 4 C868 pin configuration p-dso-28 package (top view) 1 2 3 4 5 6 7 8 9 10 11 15 p3.6/cout60 p3.7/cc60 v agnd ale/bsl v ddc p1.4/rxd reset p3.0/cout63 an4 p1.1/exf2 v ssp v ddp p1.3/int3 an3 p3.4/cout61 p3.3/cc62 p3.2/cout62 p3.1/ctrap p3.5/cc61 16 12 13 14 v ssc C868 17 18 19 20 21 22 23 24 25 26 27 28 xtal2 xtal1 v aref p1.2 29 30 31 32 33 34 35 36 37 38 nc nc nc nc nc nc nc nc p1.0/txd p1.7/ccpos2/int2/an2 p1.6/ccpos1/t2ex/int1 /an1 p1.5/ccpos0/t2/int0 /an0 nc nc 1 2 3 5 6 7 8 9 ale/bsl p1.4/rxd reset p1.0/txd v ssp v ddp an3 p3.3/cc62 p3.2/cout62 C868 11 15 16 17 18 19 20 xtal1 xtal2 v agnd v aref v ddc v ssc p1.6/ccpos1/t2ex/int1 /an1 p1.5/ccpos0/t2/int0 /an0 12 13 14 10 4 22 24 25 23 28 21 26 27 p1.7/ccpos2/int2/an2 p3.0/cout63 p3.4/cout61 p3.1/ctrap an4 p3.6/cout60 p3.7/cc60 p1.1/exf2 p1.3/int3 p1.2 p3.5/cc61
C868 data sheet 9 v 1.0, 2003-05 table 1 pin definitions and functions symbol pin numbers i/o*) function p- dso- 28 p- tssop- 38 p1.0 ? p1.4 p1.5- p1.7 12-8 15-17 6,4-1 11-13 i/o i port 1 is a combination of 5 bits of push-pull bidirectional i/ o ports and 3 bits of input ports. as alternate digital functions, port 1 contains the interrupt 3, timer 2 overflow flag, receive data input and transmit data output of serial interface. the alternate functions are assigned to the pins of port 1 as follows: 12 11 10 9 8 6 4 3 2 1 p1.0/txd transmit data of serial interface p1.1/exf2 timer 2 overflow flag p1.2 p1.3/int3 interrupt 3 p1.4/rxd receive data of serial interface, use as wakeup source from powerdown if bit ws of pmcon0 is set. the input ports are also interrupt ports, input to the timer2, ccu6 modules and adc: 15 11 i p1.5/input to counter 2/external interrupt 0 input/ analog input channel 0 external interrupt input or hall input signal, counter 2 input or input channel 0 to the adc unit. use as wakeup source from powerdown if bit ws of pmcon0 is cleared. 16 12 i p1.6/timer 2 trigger/external interrupt 1 input/ analog input channel 1 external interrupt input or hall input signal, input channel 1 to the adc unit, trigger to timer 2. 17 13 i p1.7/external interrupt 2 input/ analog input channel 2 external interrupt input or hall input signal and input channel 2 to the adc unit. *)i=input o=output
C868 data sheet 10 v 1.0, 2003-05 p3.0 ? p3.7 2,3,23, 24,1, 22,5,6 2 3 23 24 1 22 5 6 32,33,25, 26,31,24, 36,37 32 33 25 26 31 24 36 37 i/o port 3 is an 8-bit push-pull bidirectional i/o port. this port also serves as alternate functions for the ccu6 functions. the functions are assigned to the pins of port 3 as follows : p3.0/cout63 16 bit compare channel output p3.1/ctrap ccu trap input p3.2/cout62 output of capture/compare ch 2 p3.3/cc62 input/output of capture/compare ch 2 p3.4/cout61 output of capture/compare ch 1 p3.5/cc61 input/output of capture/compare ch 1 p3.6/cout60 output of capture/compare ch 0 p3.7/cc60 input/output of capture/compare ch 0 v aref 19 15 ? reference voltage for the a/d converter. v agnd 18 14 ? reference ground for the a/d converter. an4 21 17 i analog input channel 4 is input channel 4 to the adc unit. an3 20 16 i analog input channel 3 is input channel 3 to the adc unit. reset 738 i reset a low level on this pin for two machine cycle while the oscillator is running resets the device. ale/bsl 4 34 i/o address latch enable/bootstrap mode a low level on this pin during reset allows the device to go into the bootstrap mode. after reset, this pin will output the address latch enable signal. the ale can be disabled by bit eale in sfr syscon0. v ssp 14 10 ? io ground (0v) v ddp 13 9 ? io power supply (+3.3v) *)i=input o=output table 1 pin definitions and functions symbol pin numbers i/o*) function p- dso- 28 p- tssop- 38
C868 data sheet 11 v 1.0, 2003-05 v ssc 25 27 ? core ground (0v) v ddc 26 28 o core internal reference (+2.5v) connect 2*68 - 470nf ceramic capacitor across this pin and core ground. nc ? 5,7,8,18, 19,20,21, 22,23,35 ? not connected xtal1 27 29 i xtal1 output of the inverting oscillator amplifier. xtal2 28 30 o xtal2 input to the inverting oscillator amplifier and input to the internal clock generation circuits. to drive the device from an external clock source, xtal2 should be driven, while xtal1 is left unconnected. *)i=input o=output table 1 pin definitions and functions symbol pin numbers i/o*) function p- dso- 28 p- tssop- 38
C868 data sheet 12 v 1.0, 2003-05 figure 5 block diagram of the C868 programmable watchdog timer port 3 5-bit port 1 osc cpu timer 0 timer 1 timer 2 uart reset C868 v ssc v ddc a/d converter 8-bit 8k x 8 rom/ 256 x 8 xram 256 x 8 ram capture/compare unit interrupt unit 4 external interrupts port 1 port 3 digital i/o i/o 8-bit digital ram boot/ self test rom 4k x 8 xtal2 xtal1 v aref v agnd v ddp v ssp 5-bit analog in pll 8 datapointers and 3-bit digital input
C868 data sheet 13 v 1.0, 2003-05 cpu the C868 is efficient both as a controller and as an arithmetic processor. it has extensive facilities for binary and bcd arithmetic and excels in its bit-handling capabilities. efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. with a 10.67 mhz external crystal (giving a 40mhz cpu clock), 58% of the instructions execute in 300 ns. psw program status word register [reset value: 00 h ] d7 h d6 h d5 h d4 h d3 h d2 h d1 h d0 h cy ac f0 rs1 rs0 ov f1 p rwh rwh rw rw rw rwh rw rwh field bits typ description p 0rwh parity flag set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. f1 1rw general purpose flag ov 2rwh overflow flag used by arithmetic instructions. rs0 rs1 3 4 rw register bank select control bits these bits are used to select one of the four register banks. f0 5rw general purpose flag ac 6rwh auxiliary carry flag used by instructions which execute bcd operations. cy 7rwh carry flag used by arithmetic instructions. table 2 : rs1 rs0 function 0 0 bank 0 selected, data address 00 h -07 h 0 1 bank 1 selected, data address 08 h -0f h 1 0 bank 2 selected, data address 10 h -17 h 1 1 bank 3 selected, data address 18 h -1f h
C868 data sheet 14 v 1.0, 2003-05 memory organization the C868 cpu manipulates operands in the following five address spaces: ? up to 8 kbyte of ram internal program memory : 8k rom for C868-1r : 8k ram for C868-1s ? 4 kbyte of internal self test and boot rom ? 256 bytes of internal data memory ? 256 bytes of internal xram data memory ? 128 byte special function register area figure 0-1 illustrates the memory address spaces of the C868. figure 0-1 C868 memory map 1fff h "code space" indirect direct addr. 7f h 00 h internal ram special function regs. 80 h ff h addr. internal ram "internal data space" ffff h ff00 h 0000 h "data space" internal self test internal internal xram and boot rom (4 kbyte)
C868 data sheet 15 v 1.0, 2003-05 the various chip modes supported are shown in figure 6 . figure 6 entry and exit of chip modes a valid hardware reset would, of course, override any of the above entry or exit procedures. table 0-1 hardware and software selection of chipmodes operating mode (chipmode) hardware selection software selection normal mode ale/bsl pin = high reset rising edge ale/bsl = don ? t care; setting bits bslen, swap = 0,0; execute unlocking sequence normal xram mode not possible setting bits bslen,swap = 0,1; execute unlocking sequence bootstrap xram mode not possible setting bits bslen,swap = 1,1; execute unlocking sequence bootstrap mode ale/bsl pin = low reset rising edge ale/bsl = don ? t care; setting bits bslen, swap = 1,0; execute unlocking sequence normal mode normal xram bootstrap mode hardware software bootstrap xram mode mode
C868 data sheet 16 v 1.0, 2003-05 table 3 normal memory configuration chip mode memory space memory boundary normal code space rom/ram: 0000 h to 1fff h internal data space xram: ff00 h to ffff h bootstrap code space boot rom: 0000 h to 0fff h internal data space xram: ff00 h to ffff h rom/ram: 0000 h to 1fff h normal xram code space xram: ff00 h to ffff h data space rom/ram: 0000 h to 1fff h bootstrap xram code space boot rom: 0000 h to 0fff h xram: ff00 h to ffff h data space rom/ram: 0000 h to 1fff h
C868 data sheet 17 v 1.0, 2003-05 bootstrap loader the C868, includes a bootstrap mode, which is activated by setting the ale/bsl pin at logic low with a pulldown and txd pin at logic high with a pullup at the rising edge of the reset . or it can be entered by software, that is by setting bslen bit and resetting swap bit in sfr syscon1 accompany by an unlock sequence. in the bootstrap mode, software routines of the bootstrap loader located in the boot rom will be executed. its purpose is to allow the easy and quick programming of the internal sram (0000 h to 1fff h ) or xram (ff00 h to ffff h ) via serial interface (uart) while the mcu is in-circuit. it also provides a way to program sram or xram through bootstrapping from an external spi or i2c eeprom. the first action of the bootstrap loader is to detect the presence of eeprom and its type, spi or i2c, and check the first byte of the serial eeprom. if the first byte is 0a5 h , the mcu would enter phase a to download from the eeprom. otherwise, it will enter phase b to establish a serial communication with the connected host. bootstrapping from the serial eeprom can also be done in phase b if it is invoked by the host. phase b consists of two functional parts that represent two phases: phase i: establish a serial connection and automatically synchronize to the transfer speed (baud rate) of the serial communication partner (host). phase ii: perform the serial communication with the host. the host controls the communication by sending special header information, which select one of the working modes. these modes are: the phases of the bootstrap loader are illustrated in figure 7 . table 4 serial communication modes of phase b modes description 0 transfer a customer program from the host to the sram (0000 h to 1fff h ) or xram (ff00 h -ffff h ). then return to the beginning of phase ii and wait for the next command from the host. 1 execute a customer program in the xram at start address ff00 h . 2 execute a customer program in the sram at start address 0000 h . 3 transfer a customer program from the spi eeprom to the sram (0000 h to 1fff h ) or xram (ff00 h -ffff h ). then return to the beginning of phase ii and wait for the next command from the host. 4 transfer a customer program from the i2c eeprom to the sram (0000 h to 1fff h ) or xram (ff00 h -ffff h ). then return to the beginning of phase ii and wait for the next command from the host. 5-9 reserved
C868 data sheet 18 v 1.0, 2003-05 figure 7 the phases of the bootstrap loader the serial communication is activated in phase b. using a full duplex serial cable (rs232), the mcu must be connected to the serial port of the host computer as shown in figure 8 . figure 8 bootstrap loader interface to the pc start byte=a5 h ? no yes phase a bootstrap from serial eeprom phase b init serial interface 0 and synchronize to the host baud rate receive header block from host select working mode activate mode 1 execute custom program in xram activate mode 2 execute custom program in sram activate mode 3 load program from spi serial eeprom to sram/xram activate mode 0 load custom code to sram/xram phase b, phase ii phase b, phase i read serial eeprom (first byte) activate mode 4 load program from i2c serial eeprom to sram/xram pc host computer C868 serial cable full duplex, rs232 serial interface (asynchronous, 8n1) serial interface, uart mode 1 (asynchronous, 8n1)
C868 data sheet 19 v 1.0, 2003-05 figure 9 eeprom connections for a) spi and b) i2c /cs sck si so /hold /wp vcc gn d 240r p1.3 p1.1 p1.2 6 5 2 7 3 8 4 1 a0 a1 a2 gn d vcc wp scl sda 6 5 2 7 3 8 4 1 p1.1 p1.2 3k3 vcc vcc b) i2c eeprom c onnection a) spi eeprom connection
C868 data sheet 20 v 1.0, 2003-05 reset and brownout the reset input is an active low input. an internal schmitt trigger is used at the input for noise rejection. the reset pin must be held low for at least tbd usec. but the cpu will only exit from reset condition after the pll lock had been detected. during reset at transition from low to high, C868 will go into normal mode if ale/bsl is high and bootstrap loading mode if ale/bsl is low. a pullup to v ddp or pulldown to ground is recommended for pin ale/bsl. txd should have a pullup to v ddp and should not be stimulated externally during reset, as a logic low at this pin will cause the chip to go into test mode if ale/bsl is low. figure 10 shows the possible reset circuits, note that the reset pin does not have an internal pullup resistance. figure 10 reset circuitries an on-chip analog circuit detects brownout, if the core voltage v ddc dips below the threshold voltage v threshold momentarily while reset pin is high. if this detection is active for tbd usec then the device will reset. when v ddc recovers by exceeding v threshold while reset is high, the reset is released once pll is locked for 4096 clocks. bit bo in the pmcon0 register is set when brownout detected if brownout detection was enabled, this bit is cleared by hardware reset reset and software. all ports are tristated during brownout. the v threshold has a nominal value of 1.47v, a minimum value of 1.1v and a maximum value of 1.8v. reset C868 ba a) reset C868 ba & reset C868 ba b) c) v ddp v ddp
C868 data sheet 21 v 1.0, 2003-05 clock system the C868 clock system consist of the on-chip oscillator, pll and multiplexer stage. the programmable slow down divider (sdd) divides the pll output clock frequency by a factor of 1...32 which is specified via cmcon.rel. the system clock is switched from the pll output to the output from the sdd when slowdown mode is selected. figure 11 block diagram of the clock generation on-chip osc clkin clkout f osc xtal1 xtal2 pll sdd mux system clock ( f sys ) f pll
C868 data sheet 22 v 1.0, 2003-05 the pll output frequency is determined by: [1] the range for the vco frequency is given by: 100 mhz f vco 160 mhz [2] the relationship between the input frequency and vco frequency is given by: [3] this gives the range for the input frequency which is given by: 6.67 mhz f osc 10.67 mhz [4] table 5 output frequencies f pll derived from various output factors k-factor f pll duty cycle [%] jitter selected factor kdiv f vco = 100 mhz f vco = 160 mhz 2 000 b 50 80 50 linear depending on f vco at f vco =100mhz: +/-300ps at f vco =160mhz: +/-250ps additional jitter for odd kdiv factors tbd. 4 010 b 25 40 50 5 1) 1) these odd factors should not be used (not tested because off the unsymmetrical duty cycle). 2) shaded combinations should not be used because they are above the maximum cpu frequency of 40mhz. 011 b 20 32 40 6 100 b 16.67 26.67 50 8 101 b 12.5 20 50 9 1) 110 b 11.11 17.78 44 10 111 b 10 16 50 16 001 b 6.25 10 50 f pll = f vco / k = f osc 15 k f vco =15 f osc
C868 data sheet 23 v 1.0, 2003-05 figure 12 shows the recommended oscillator circuitries for crystal and external clock operation. figure 12 recommended oscillator circuit in this application the on-chip oscillator is used as a crystal-controlled, positive- reactance oscillator (a more detailed schematic is given in figure 13 ). lt is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip. the crystal specifications and capacitances are non- critical. in this circuit tbd pf can be used as single capacitance at any frequency together with a good quality crystal. a ceramic resonator can be used in place of the crystal in cost-critical applications. if a ceramic resonator is used, the two capacitors normally have different values depending on the oscillator frequency. we recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors. c = 20 pf 10 pf for crystal operation 6.67-10.67 xtal2 xtal1 C868 (incl. straycapacitance) crystal oscillator mode driving from external source n.c. external oscillator signal xtal2 xtal1 mhz
C868 data sheet 24 v 1.0, 2003-05 figure 13 on-chip oscillator circuitry to drive the C868 with an external clock source, the external clock signal has to be applied to xtal2, as shown in figure 14 . xtal1 has to be left unconnected. a pullup resistor is suggested (to increase the noise margin), but is optional if v oh of the driving gate corresponds to the v ih2 specification of xtal2. figure 14 external clock source xtal2 xtal1 *) *) crystal or ceramic resonator C868 to internal timing circuitry c 1 c 2 v ddc n.c. external clock signal xtal1 xtal2 C868
C868 data sheet 25 v 1.0, 2003-05 0.1 special function registers all registers, except the program counter and the four general purpose register banks, reside in the special function register area. the special function register area consists of two portions: the standard special function register area and the mapped special function register area. for accessing the mapped special function area, bit rmap in special function register syscon0 must be set. all other special function registers are located in the standard special function register area which is accessed when rmap is cleared ( ? 0 ? ). as long as bit rmap is set, the mapped special function register area can be accessed. this bit is not cleared automatically by hardware. thus, when non-mapped/mapped registers are to be accessed, the bit rmap must be cleared/set respectively by software. the 109 special function registers (sfr) include pointers and registers that provide an interface between the cpu and the other on-chip peripherals. all available sfrs whose address bits 0-2 are 0 (e.g. 80 h , 88 h , 90 h , ..., f0 h , f8 h ) are bit- addressable. totally there are 128 directly addressable bits within the sfr area. all sfrs are listed in table 6 and table 7 .in table 6 they are organized in groups which refer to the functional blocks of the C868-1r, C868-1s. table 7 illustrates the contents (bits) of the sfrs syscon0 system control register 0 [reset value: xx10xxx1 b ] 76543210 -- eale rmap - - - xmap0 r r rw rw r r r rw the functions of the shaded bits are not described here field bits typ description rmap 4rw special function register map control rmap = 0 : the access to the non-mapped (standard) special function register area is enabled. rmap = 1 : the access to the mapped special function register area is enabled. - [7:2] r reserved; returns ? 0 ? if read; should be written with ? 0 ? ;
C868 data sheet 26 v 1.0, 2003-05 table 6 special function registers - functional blocks block symbol name add- ress contents after reset c800 core acc b dph dpl dpsel psw sp scon sbuf ien0 ien1 ien2 ip0 ip1 tcon tmod tl0 tl1 th0 th1 pcon accumulator b-register data pointer, high byte data pointer, low byte data pointer select register program status word register stack pointer serial channel control register serial data buffer interrupt enable register 0 interrupt enable register 1 interrupt enable register 2 interrupt priority register 0 interrupt priority register 1 timer 0/1 control register timer mode register timer 0, low byte timer 1, low byte timer 0, high byte timer 1, high byte power control register e0 h 1) f0 h 1) 83 h 82 h 84 h d0 h 1) 81 h 98 h 1) 99 h a8 h 1) a9 h aa h b8 h 1) ac h 88 h 1) 89 h 8a h 8b h 8c h 8d h 87 h 00 h 00 h 00 h 00 h 00 h 00 h 07 h 00 h 00 h 0x000000 b 2) xxxxx000 b 2) xx0000xx b 2) xx000000 b 2) xx000000 b 2) 00 h 00 h 00 h 00 h 00 h 00 h 0xxx0000 b 2) sys- tem pmcon0 cmcon exicon ircon0 ircon1 pmcon1 pmcon2 scuwdt version syscon0 syscon1 wake-up control register clock control register external interrupt control register external interrupt request register peripheral interrupt request register peripheral management ctrl register peripheral management status register scu/watchdog control register rom version register system control register 0 system control register 1 8e h 8f h 91 h 92 h 93 h e8 h 1) f8 h 1) c0 h 1) f9 h ad h af h xxx00000 b 2) 10011111 b xxxxxx00 b 2) xxxxxx00 b 2) xx0000x0 b 2) xxxxx000 b 2) xxxxx000 b 2) x0x00000 b 2) 00 h xx10xxx1 b 2) 00xxx0x0 b 2) 1) bit-addressable special function registers 2) ? x ? means that the value is undefined and the location is reserved 3) register is mapped by bit rmap in syscon0.4=1 4) register is mapped by bit rmap in syscon0.4=0
C868 data sheet 27 v 1.0, 2003-05 a/d- con- verter adcon0 adcon1 addath a/d converter control register 0 a/d converter control register 1 a/d converter data register d8 h 1) d9 h db h 00 h xx000000 b 2) 00 h ports p1 4) p1dir 3) p3 4) p3dir 3) p3alt p1alt port 1 register port 1 direction register port 3 register port 3 direction register port 3 alternate function register port 1 alternate function register 90 h 1) 90 h 1) b0 h 1) b0 h 1) b1 h b4 h ff h ff h ff h ff h 00 h xxx00x00 b 2) watch dog wdtcon wdtrel wdtl wdth watchdog timer control register watchdog timer reload register watchdog timer, low byte watchdog timer, high byte a2 h a3 h b2 h b3 h xxxxxx00 b 2) 00 h 00 h 00 h timer 2 t2con t2mod rc2h rc2l t2h t2l timer 2 control register timer 2 mode register timer 2 reload/capture, high byte timer 2 reload/capture, low byte timer 2, high byte timer 2, low byte c8 h 1) c9 h cb h ca h cd h cc h 00 h xxxxxxx0 b 2) 00 h 00 h 00 h 00 h 1) bit-addressable special function registers 2) ? x ? means that the value is undefined and the location is reserved 3) register is mapped by bit rmap in syscon0.4=1 4) register is mapped by bit rmap in syscon0.4=0 table 6 special function registers - functional blocks (cont ? d) block symbol name add- ress contents after reset
C868 data sheet 28 v 1.0, 2003-05 cap- ture/ com- pare unit t12l t12h t13l t13h t12prl t12prh t13prl t13prh cc60rl cc60rh cc61rl cc61rh cc62rl cc62rh cc63rl cc63rh t12dtcl t12dtch cmpstatl cmpstath cmpmodifl cmpmodifh tctr0l tctr0h tctr2l 3) tctr4l 4) tctr4h 4) isl ish piselh timer t12 counter register, low byte timer t12 counter register, high byte timer t13 counter register, low byte timer t13 counter register, high byte timer t12 period register, low byte timer t12 period register, high byte timer t13 period register, low byte timer t13 period register, high byte capture/compare ch 0 reg, low byte capture/compare ch 0 reg, high byte capture/compare ch 1 reg, low byte capture/compare ch 1 reg, high byte capture/compare ch 2 reg, low byte capture/compare ch 2 reg, high byte t13 compare register, low byte t13 compare register, high byte timer t12 dead time ctrl, low byte timer t12 dead time ctrl, high byte compare timer status, low byte compare timer status, high byte compare timer modification, low byte compare timer modification, high byte timer control register 0, low byte timer control register 0, high byte timer control register 2, low byte timer control register 4, low byte timer control register 4, high byte cap/com interrupt register, low byte cap/com interrupt register, high byte port input selector register, high byte ec h ed h ee h ef h de h df h d2 h d3 h c2 h c3 h c4 h c5 h c6 h c7 h d4 h d5 h e6 h e7 h f4 h f5 h ea h eb h e2 h e3 h f2 h f2 h f3 h e4 h e5 h bb h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 0 h 00 h 00 h 00 h 00 h 1) bit-addressable special function registers 2) ? x ? means that the value is undefined and the location is reserved 3) register is mapped by bit rmap in syscon0.4=1 4) register is mapped by bit rmap in syscon0.4=0 table 6 special function registers - functional blocks (cont ? d) block symbol name add- ress contents after reset
C868 data sheet 29 v 1.0, 2003-05 cap- ture/ com- pare unit issl 3) issh 3) isrl 4) isrh 4) inpl 3) inph 3) ienl 4) ienh 4) cc60srl cc60srh cc61srl cc61srh cc62srl cc62srh cc63srl cc63srh modctrl 3) modctrh 3) trpctrl trpctrh pslrl mcmoutl 3) mcmouth 3) mcmoutsl 4) mcmoutsh 4) mcmctrll 4) t12msell t12mselh cap/com int status set reg, low byte cap/com int status set reg, high byte cap/com int status reset reg, low byte cap/com int status reset reg,high byte cap/com int node ptr reg, low byte cap/com int node ptr reg, high byte cap/com interrupt register, low byte cap/com interrupt register, high byte cap/com channel 0 shadow, low byte cap/com channel 0 shadow, high byte cap/com channel 1 shadow, low byte cap/com channel 1 shadow, high byte cap/com channel 2 shadow, low byte cap/com channel 2 shadow, high byte t13 compare shadow reg, low byte t13 compare shadow reg, high byte modulation control register, low byte modulation control register, high byte trap control register, low byte trap control register, high byte passive state level register, low byte mcm output register, low byte mcm output register, high byte mcm output shadow register, low byte mcm output shadow register,high byte mcm control register, low byte t12 cap/com mode sel reg, low byte t12 cap/com mode sel reg, high byte bc h bd h bc h bd h be h bf h be h bf h fa h fb h fc h fd h fe h ff h b6 h b7 h d6 h d7 h ce h cf h a6 h dc h dd h dc h dd h d6 h f6 h f7 h 00 h 00 h 00 h 00 h 40 h 39 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 1) bit-addressable special function registers 2) ? x ? means that the value is undefined and the location is reserved 3) register is mapped by bit rmap in syscon0.4=1 4) register is mapped by bit rmap in syscon0.4=0 table 6 special function registers - functional blocks (cont ? d) block symbol name add- ress contents after reset
C868 data sheet 30 v 1.0, 2003-05 table 7 contents of the sfrs, sfrs in numeric order of their addresses addr reg- ister content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 81 h sp 07 h .7 .6 .5 .4 .3 .2 .1 .0 82 h dpl 00 h .7 .6 .5 .4 .3 .2 .1 .0 83 h dph 00 h .7 .6 .5 .4 .3 .2 .1 .0 84 h dpse l 00 h ????? d2 d1 d0 87 h pcon 0xx0 0000 b smod ?? sd gf1 gf0 pde idle 88 h tcon 00 h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 89 h tmod 00 h gate 1 c/nt1 m1(1) m0(1) gate 0 c/nt0 m1(0) m0(0) 8a h tl0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8b h tl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 8c h th0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8d h th1 00 h .7 .6 .5 .4 .3 .2 .1 .0 8e h pmco n0 xxx0 0000 b ??? ebo bo sdst at ws epwd 8f h cmco n 1001 1111 b kdiv2 kdiv1 kdiv0 rel4 rel3 rel2 rel1 rel0 90 h 2) p1 ff h .7 .6 .5 .4 .3 .2 .1 .0 90 h 3) p1dir ff h .7 .6 .5 .4 .3 .2 .1 .0 91 h exico n xxxx xx00 b ?????? esel3 esel2 92 h irco n0 xxxx xx00 b ?????? exint 3 exint 2 93 h irco n1 xx00 00x0 b ?? inp3 inp2 inp1 inp0 ? iadc 98 h scon 00 h sm0 sm1 sm2 ren tb8 rb8 ti ri 99 h sbuf 00 h .7 .6 .5 .4 .3 .2 .1 .0 1) x means that the value is undefined and the location is reserved 2) this register is mapped with rmap (syscon0.4)=0 3) this register is mapped with rmap (syscon0.4)=1 shaded registers are bit-addressable special function registers
C868 data sheet 31 v 1.0, 2003-05 a2 h wdtc on xxxx xx00 b ??????? wdti n a3 h wdtr el 00 h .7 .6 .5 .4 .3 .2 .1 .0 a6 h pslrl 00 h psl63 ? psl5 psl4 psl3 psl2 psl1 psl0 a8 h ien0 0x00 0000 b ea ? et2 es et1 ex1 et0 ex0 a9 h ien1 xxxx x000 b ????? ex3 ex2 eadc aa h ien2 xx00 00xx b ?? einp3 einp2 einp1 einp0 ?? ac h ip1 xx00 0000 b ?? .5 .4 .3 .2 .1 .0 ad h sysc on0 xx10 xxx1 b ?? eale rmap ??? xmap 0 af h sysc on1 00xx x0x0 b eswc swc _ _ _ bsle n _swap b0 h 2) p3 ff h .7 .6 .5 .4 .3 .2 .1 .0 b0 h 3) p3dir ff h .7 .6 .5 .4 .3 .2 .1 .0 b1 h p3alt 00 h cc60 cout 60 cc61 cout 61 cc62 cout 62 ctra p cout 63 b2 h wdtl 00 h .7 .6 .5 .4 .3 .2 .1 .0 b3 h wdth 00 h .7 .6 .5 .4 .3 .2 .1 .0 b4 h p1alt xxx0 0x00 b ___rxdint3_exf2txd b6 h cc63 srl 00 h .7 .6 .5 .4 .3 .2 .1 .0 b7 h cc63 srh 00 h .7 .6 .5 .4 .3 .2 .1 .0 1) x means that the value is undefined and the location is reserved 2) this register is mapped with rmap (syscon0.4)=0 3) this register is mapped with rmap (syscon0.4)=1 shaded registers are bit-addressable special function registers table 7 contents of the sfrs, sfrs in numeric order of their addresses addr reg- ister content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
C868 data sheet 32 v 1.0, 2003-05 b8 h ip0 xx00 0000 b ? ? .5 .4 .3 .2 .1 .0 bb h pisel h 00 h ?? ispos 2.1 ispos 2.0 ispos 1.1 ispos 1.0 ispos 0.1 ispos 0.0 bc h 3) issl 00 h st12p m st12o m scc62 f scc62 r scc61 f scc61 r scc60 f scc60 r bc h 2) isrl 00 h rt12p m rt12o m rcc6 2f rcc6 2r rcc6 1f rcc6 1r rcc6 0f rcc6 0r bd h 3) issh 00 h ? sidle swhe sche ? strp f st13p m st13c m bd h 2) isrh 00 h ? ridle rwhe rche ? rtrp f rt13p m rt13c m be h 2) ienl 00 h ent12 pm ent12 om encc 62f encc 62r encc 61f encc 61r encc 60f encc 60r be h 3) inpl 00 h inpch e.1 inpch e.0 inpcc 62.1 inpcc 62.0 inpcc 61.1 inpcc 61.0 inpcc 60.1 inpcc 60.0 bf h 2) ienh 00 h ? enidl e enwh e ench e ? entr pf ent13 pm ent13 cm bf h 3) inph 00 h ?? inpt1 3.1 inpt1 3.0 inpt1 2.1 inpt1 2.0 inper r.1 inper r.0 c0 h scuw dt 00 h ? pllr ? wdtr wdte oi wdtd is wdtr s wdtr e c2 h cc60 rl 00 h .7 .6 .5 .4 .3 .2 .1 .0 c3 h cc60 rh 00 h .7 .6 .5 .4 .3 .2 .1 .0 c4 h cc61 rl 00 h .7 .6 .5 .4 .3 .2 .1 .0 c5 h cc61 rh 00 h .7 .6 .5 .4 .3 .2 .1 .0 1) x means that the value is undefined and the location is reserved 2) this register is mapped with rmap (syscon0.4)=0 3) this register is mapped with rmap (syscon0.4)=1 shaded registers are bit-addressable special function registers table 7 contents of the sfrs, sfrs in numeric order of their addresses addr reg- ister content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
C868 data sheet 33 v 1.0, 2003-05 c6 h cc62 rl 00 h .7 .6 .5 .4 .3 .2 .1 .0 c7 h cc62 rh 00 h .7 .6 .5 .4 .3 .2 .1 .0 c8 h t2co n 00 h tf2 exf2 rclk tclk exen 2 tr2 c/t2 cp/ rl2 c9 h t2mo d xxxx xxx0 b ??????? dcen ca h rc2l 00 h .7 .6 .5 .4 .3 .2 .1 .0 cb h rc2h 00 h .7 .6 .5 .4 .3 .2 .1 .0 cc h tl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 cd h th2 00 h .7 .6 .5 .4 .3 .2 .1 .0 ce h trpc trl 00 h ????? trpm 2 trpm 1 trpm 0 cf h trpc trh 00 h trpp en trpe n13 trpe n5 trpe n4 trpe n3 trpe n2 trpe n1 trpe n0 d0 h psw 00 h cy ac f0 rs1 rs0 ov f1 p d2 h t13pr l 00 h .7 .6 .5 .4 .3 .2 .1 .0 d3 h t13pr h 00 h .7 .6 .5 .4 .3 .2 .1 .0 d4 h cc63 rl 00 h .7 .6 .5 .4 .3 .2 .1 .0 d5 h cc63 rh 00 h .7 .6 .5 .4 .3 .2 .1 .0 d6 h 2) mcmc trll 00 h ?? swsy n1 swsy n0 ? swse l2 swse l1 swse l0 d6 h 3) modc trl 00 h mcme n ? t12m oden 5 t12m oden 4 t12m oden 3 t12m oden 2 t12m oden 1 t12m oden 0 1) x means that the value is undefined and the location is reserved 2) this register is mapped with rmap (syscon0.4)=0 3) this register is mapped with rmap (syscon0.4)=1 shaded registers are bit-addressable special function registers table 7 contents of the sfrs, sfrs in numeric order of their addresses addr reg- ister content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
C868 data sheet 34 v 1.0, 2003-05 d7 h 3) modc trh 00 h ect13 o ? t13m oden 5 t13m oden 4 t13m oden 3 t13m oden 2 t13m oden 1 t13m oden 0 d8 h adco n0 00 h adst adbs y adm1 adm0 ccu- adex adch 2 adch 1 adch 0 d9 h adco n1 xx00 0000 b ?? adst c2 adst c1 adst c0 adct c2 adct c1 adct c0 db h adda th 00 h .7 .6 .5 .4 .3 .2 .1 .0 dc h 3) mcmo utl 00 h ? rmcmp 5 mcmp 4 mcmp 3 mcmp 2 mcmp 1 mcmp 0 dc h 2) mcmo utsl 00 h strm cm ? mcmp s5 mcmp s4 mcmp s3 mcmp s2 mcmp s1 mcmp s0 dd h 3) mcmo uth 00 h ?? curh 2 curh 1 curh 0 exph 2 exph 1 exph 0 dd h 2) mcmo utsh 00 h strh p ? curh s2 curh s1 curh s0 exph s2 exph s1 exph s0 de h t12pr l 00 h .7 .6 .5 .4 .3 .2 .1 .0 df h t12pr h 00 h .7 .6 .5 .4 .3 .2 .1 .0 e0 h acc 00 h .7 .6 .5 .4 .3 .2 .1 .0 e2 h tctr 0l 00 h ctm cdir ste12 t12r t12pr e t12cl k2 t12cl k1 t12cl k0 e3 h tctr 0h 10 h ?? ste13 t13r t13pr e t13cl k2 t13cl k1 t13cl k0 e4 h isl 00 h t12pm t12o m icc62 f icc62 r icc61 f icc61 r icc60 f icc60 r e5 h ish 00 h ? idle whe che trps trpf t13pm t13c m 1) x means that the value is undefined and the location is reserved 2) this register is mapped with rmap (syscon0.4)=0 3) this register is mapped with rmap (syscon0.4)=1 shaded registers are bit-addressable special function registers table 7 contents of the sfrs, sfrs in numeric order of their addresses addr reg- ister content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
C868 data sheet 35 v 1.0, 2003-05 e6 h t12dt cl 00 h ? dtm5 dtm4 dtm3 dtm2 dtm1 dtm0 e7 h t12dt ch 00 h ? dtr2 dtr1 dtr0 ? dte2 dte1 dte0 e8 h pmco n1 xxxx x000 b ? ? ? ? ? ccudi s t2dis adcdi s ea h cmpm odifl 00 h ? mcc6 3s ??? mcc6 2s mcc6 1s mcc6 0s eb h cmpm odifh 00 h ? mcc6 3r ??? mcc6 2r mcc6 1r mcc6 0r ec h t12l 00 h .7 .6 .5 .4 .3 .2 .1 .0 ed h t12h 00 h .7 .6 .5 .4 .3 .2 .1 .0 ee h t13l 00 h .7 .6 .5 .4 .3 .2 .1 .0 ef h t13h 00 h .7 .6 .5 .4 .3 .2 .1 .0 f0 h b 00 h .7 .6 .5 .4 .3 .2 .1 .0 f2 h 2) tctr 4l 00 h t12st d t12st r ?? dtre s t12re s t12rs t12rr f2 h 3) tctr 2l 00 h ? t13te d1 t13te d0 t13te c2 t13te c1 t13te c0 t13ss c t12ss c f3 h 2) tctr 4h 00 h t13st d t13st r ??? t13re s t13rs t13rr f4 h cmps tatl 00 h ? cc63s t ??? cc62s t cc61s t cc60s t f5 h cmps tath 00 h t13im cout 63ps cout 62ps cc62p s cout 61ps cc61p s cout 60ps cc60p s f6 h t12m sell 00 h msel 613 msel 612 msel 611 msel 610 msel 603 msel 602 msel 601 msel 600 f7 h t12m selh 00 h ???? msel 623 msel 622 msel 621 msel 620 1) x means that the value is undefined and the location is reserved 2) this register is mapped with rmap (syscon0.4)=0 3) this register is mapped with rmap (syscon0.4)=1 shaded registers are bit-addressable special function registers table 7 contents of the sfrs, sfrs in numeric order of their addresses addr reg- ister content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
C868 data sheet 36 v 1.0, 2003-05 f8 h pmco n2 xxxx x000 b ? ? ? ? ? ccus t t2st adcs t f9 h versi on 00 h prot ver6 ver5 ver4 ver3 ver2 ver1 ver0 fa h cc60 rl 00 h .7 .6 .5 .4 .3 .2 .1 .0 fb h cc60 rh 00 h .7 .6 .5 .4 .3 .2 .1 .0 fc h cc61 rl 00 h .7 .6 .5 .4 .3 .2 .1 .0 fd h cc61 rh 00 h .7 .6 .5 .4 .3 .2 .1 .0 fe h cc62 rl 00 h .7 .6 .5 .4 .3 .2 .1 .0 ff h cc62 rh 00 h .7 .6 .5 .4 .3 .2 .1 .0 1) x means that the value is undefined and the location is reserved 2) this register is mapped with rmap (syscon0.4)=0 3) this register is mapped with rmap (syscon0.4)=1 shaded registers are bit-addressable special function registers table 7 contents of the sfrs, sfrs in numeric order of their addresses addr reg- ister content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
C868 data sheet 37 v 1.0, 2003-05 ports the C868 has two kinds of ports. the first kind is push-pull ports instead of the traditional quasi-bidirectional ports. the ports belonging to this kind are lsb of port 1 which is a 5- bit i/o port and port 3 which is an eight-bit i/o port. when configured as inputs, these ports will be high impedance with schmitt trigger feature. port 3 is alternate for capture/ compare functions whereas, port 1 has alternate functions for some of the pins. the second kind is input ports which are shared by msb of port 1 which is a 3-bit input port, the interrupts, timer 2 inputs, capture/compare hall inputs and analog inputs.
C868 data sheet 38 v 1.0, 2003-05 timer 0 and 1 timer 0 and 1 can be used in four operating modes as listed in table 8 : the register is incremented every machine cycle. since the machine cycle consist of twelve oscillator periods, the count rate is 1/12th of the system frequency. external inputs int0 and int1 can be programmed to function as a gate to facilitate pulse width measurements. figure 15 illustrates the input clock logic. figure 15 timer 0 and 1 input clock logic table 8 timer 0 and 1 operating modes mode description tmod system clock m1 m0 0 8-bit timer with a divide-by-32 prescaler 0 0 f sys /(12*32) 1 16-bit timer 0 1 f sys /12 2 8-bit timer with 8-bit autoreload 1 0 3 timer 0 used as one 8-bit timer and one 8-bit timer timer 1 stops 11 c/t = 0 timer 0/1 tr0 control gate int0 f sys 12 =1 & 1 pin input clock
C868 data sheet 39 v 1.0, 2003-05 timer/counter 2 with compare/capture/capture timer 2 is a 16-bit timer/counter with an up/down count feature. it has three operating modes: 16-bit auto-reload mode (up or down counting) 16-bit capture mode baudrate generator note: denotes a falling edge table 9 timer/counter 2 operating modes mode t2con t2mod t2con t2ex remarks system clock rclk or tclk cp/ rl2 tr2 dcen exen inte- rnal t2 16-bit auto- reload 0010 0 xreload upon overflow f sys /12 max f sys /24 0 0 x 0 1 reload trigger (falling edge) 0011 x 0down counting 0011 x 1up counting 16-bit capture 011x 0 x16-bit timer/ counter (only up-counting) f sys /12 max f sys /24 011x 1 capture t2h,t2l-> rc2h,rc2l baudrate generator 1x1x 0 xno overflow interrupt request(tf2) f sys /2 - 1x1x 1 extra external interrupt ( ? timer 2 ? ) off x x 0 x x x timer 2 stops - -
C868 data sheet 40 v 1.0, 2003-05 serial interface (uart) the serial port is a full duplex port capable of simultaneous transmit and receive functions. it is also receive-buffered; it can commence reception of a second byte before a previously-received byte has been read from the receive register. the serial port can operate in 3 modes as illustrated in table 10 . for clarification, some terms regarding the difference between ? baudrate clock ? and ? baudrate ? should be mentioned. the serial interface requires a clock rate which is 16 times the baudrate for internal synchronization. therefore, the baudrate generators must provide a ? baudrate clock ? to the serial interface which divides it by 16, thereby resulting in the actual ? baudrate ? . table 10 uart operating modes mode scon description sm1 sm0 0 0 0 reserved 1 0 1 8-bit uart, variable baudrate 10 bits are transmitted (through txd) or received (rxd) 2 1 0 9-bit uart, fixed baudrate 11 bits are transmitted (through txd) or received (rxd) 3 1 1 9-bit uart, variable baudrate similar to mode 2, except for the variable baudrate.
C868 data sheet 41 v 1.0, 2003-05 the baudrates in mode 1 and 3 are determined by the timer overflow rate. these baudrates can be determined by timer 1 or by timer 2 or both (one for transmit, the other for receive. table 11 serial interface - baud rate dependencies serial interface operating modes active control bits baud rate calculation tclk/ rclk smod mode 1 (8-bit uart) mode 3 (9-bit uart) 0 x controlled by timer 1 overflow: (2 smod timer 1 overflow rate) / 32 1 x controlled by baud rate generator (2 smod timer 2 1) overflow rate) / 32 1) timer 2 functioning as baudrate generator mode 2 (9-bit uart) ? 0 f sys / 64 1 f sys / 32
C868 data sheet 42 v 1.0, 2003-05 capture/compare unit (ccu6) the ccu6 provides two independent timers (t12, t13), which can be used for pwm generation, especially for ac-motor control. additionally, special control modes for block commutation and multi-phase machines are supported. timer 12 features three capture/compare channels, each channel can be used either as capture or as compare channel. generation of a three-phase pwm supported (six outputs, individual signals for highside and lowside switches) 16 bit resolution, maximum count frequency = system clock dead-time control for each channel to avoid short-circuits in the power stage concurrent update of the required t12/13 registers center-aligned and edge-aligned pwm can be generated single-shot mode supported many interrupt request sources hysteresis-like control mode timer 13 features one independent compare channel with one output 16 bit resolution, maximum count frequency = system clock can be synchronized to t12 interrupt generation at period-match and compare-match single-shot mode supported additional features block commutation for brushless dc-drives implemented position detection via hall-sensor pattern automatic rotational speed measurement for block commutation integrated error handling fast emergency stop without cpu load via external signal (ctrap ) control modes for multi-channel ac-drives output levels can be selected and adapted to the power stage capture/compare unit can be powerdown in normal, idle and slow-down modes the timer t12 can work in capture and/or compare mode for its three channels. the modes can also be combined. the timer t13 can work in compare mode only. the multi- channel control unit generates output patterns which can be modulated by t12 and/or t13. the modulation sources can be selected and combined for the signal modulation.
C868 data sheet 43 v 1.0, 2003-05 switching examples figure 16 edge-aligned mode with duty cycles near 100% and near 0%. applicable to t13 as well. figure 17 centre-aligned mode with duty cycles near 100% and near 0%. t12 t12clk t12p t12p-1 0 1 t12p-2 t12p t12p-1 0 1 t12p-2 period-match active 0 0 < t12p-3 10 t12 shadow transfer active 0 t12p t12p 10 t12 shadow transfer compare state cdir cc6x ste12 passive zero-match compare-match = zero-match compare-match = period-match 0 1 2 1 2 passive active compare-match 10 2 1 10 t12 shadow transfer 0 1 2 1 2 active compare-match 10 0 1 10 t12 shadow transfer t12 compare state t12clk cdir cc6x ste12
C868 data sheet 44 v 1.0, 2003-05 dead-time generation the dead-time generation logic is built in a similar way for all three channels of t12. each of the three channels works independently with its own dead-time counter and the trigger and enable signals. figure 18 dead-time generation for centre and edge aligned modes capture mode in capture mode the bits cc6xst indicate the occurrence of the selected capture event according to the bit fields msel6x. a rising and/or a falling edge on the pins cc6x can be selected as capture event, that is used to transfer the contents of timer t12 to the cc6xr and cc6xsr registers. in order to work in capture mode, the capture pins have to be configured as inputs. t12 cc6xst dtcx_o cc6x (cc6xps=0) cc6xst cout6x (cc6xps=0) t12 centre-aligned edge-aligned
C868 data sheet 45 v 1.0, 2003-05 single shot mode in single shot mode, the timer t12 stops automatically at the end of the its counting period. figure 19 single shot mode of t12, t13 is edge-aligned mode only. hysteresis-like control mode the hysteresis-like control mode (msel6x = ? 1001 ? ) offers the possibility to switch off the pwm output if the input ccposx becomes ? 0 ? . this can be used as a simple motor control feature by using a comparator indicating e.g. over current. figure 20 hysteresis-like control mode t12p t12p-1 0 t12p-2 t12 t12r cc6xst t12 1 2 0 t12r if t12ssc = ? 1 ? cc6xst edge-aligned mode center-aligned mode period-match while counting up one-match while counting down if t12ssc = ? 1 ? t12 cc6x cout6x ccposx
C868 data sheet 46 v 1.0, 2003-05 synchronization of t13 to t12 the timer t13 can be synchronized on a t12 event. combined with the single shot mode, this feature can be used to generate a programmable delay after a t12 event. synchronization of t13 to t12 multi-channel mode the multi-channel mode offers a possibility to modulate all six t12-related output signals within one instruction. the bits in bit field mcmp are used to select the outputs that may become active. if the multi-channel mode is enabled (bit mcmen= ? 1 ? ), only those outputs may become active, which have a ? 1 ? at the corresponding bit position in bit field mcmp. this bit field has its own shadow bit field mcmps, which can be written by sw. the transfer of the new value in mcmps to the bit field mcmp can be triggered by and synchronized to t12 or t13 events. this structure permits the sw to write the new value, which is then taken into account by the hw at a well-defined moment and synchronized to a pwm period. this avoids unintended pulses due to unsynchronized modulation sources (t12, t13, sw). 0 1 2 t12 compare-match while counting up t13 t13r 0 1 2 3 4 5
C868 data sheet 47 v 1.0, 2003-05 trap handling the trap functionality permits the pwm outputs to react on the state of the input pin ctrap . this functionality can be used to switch off the power devices if the trap input becomes active (e.g. as emergency stop). figure 21 trap state synchronization (with trm2= ? 0 ? ) ctrap active t12 t13 sync. to t12 sync. to t13 no sync. trps trps trps trpf
C868 data sheet 48 v 1.0, 2003-05 modulation control the modulation control part combines the different modulation sources, six t12-related signals from the three compare channels, the t13-related signal and the multi-channel modulation signals. each modulation source can be individually enabled for each output line. furthermore, the trap functionality is taken into account to disable the modulation of the corresponding output line during the trap state (if enabled). figure 22 modulation control example for cc60 and cout60. t13 cc60 (mcmp0, no modulation) cout60 (mcmp1, no modulation) cout60 (t12, no modulation) cc60 (t12, no modulation) cc60 (mcmp0 modulated with t12) cout60 (mcmp1 modulated with t12) cc60 (mcmp0 modulated with t12 and 13) cout60 (mcmp1 modulated with t12 and t13)
C868 data sheet 49 v 1.0, 2003-05 hall sensor mode in brushless-dc motors the next multi-channel state values depend on the pattern of the hall inputs. there is a strong correlation between the hall pattern (curh) and the modulation pattern (mcmp). because of different machine types the modulation pattern for driving the motor can be different. therefore it is wishful to have a wide flexibility in defining the correlation between the hall pattern and the corresponding modulation pattern. the ccu6 offers this by having a register which contains the actual hall pattern (curhs), the next expected hall pattern (exphs) and its output pattern (mcmps). at every correct hall event (che, see figure hall event actions ) a new hall pattern with its corresponding output pattern can be loaded (from a predefined table) by software into the register mcmouts. loading this shadow register can also be done by a write action on mcmouts with bit strhp = ? 1 ? the sampling of the hall pattern (on ccposx) is done with the t12 clock. by using the dead-time counter dtc0 (mode msel6x= ? 1000 ? ) a hardware noise filter can be implemented to suppress spikes on the hall inputs due to high di/dt in rugged inverter environment. in case of a hall event the dtc0 is reloaded and starts counting. when the counter value of one is reached, the ccposx inputs are sampled (without noise and spikes) and are compared to the current hall pattern (curh) and to the expected hall pattern (exph). if the sampled pattern equals to the current pattern the edge on ccposx was due to a noise spike and no action will be triggered (implicit noise filter). if the sampled pattern equals to the next expected pattern the edge on ccposx was a correct hall event, the bit che is set which causes an interrupt and the resets t12 (for speed measurement, see description mode ? 1000 ? below). this correct hall event can be used as a transfer request event for register mcmouts. the transfer from mcmouts to mcmout transfers the new curh-pattern as well as the next exph-pattern. in case of the sampled hall inputs were neither the current nor the expected hall pattern, the bit whe (wrong hall event) is set which also can cause an interrupt and sets the idle mode clearing mcmp (modulation outputs are inactive). to restart from idle the transfer request of mcmouts have to be initiated by software (bit strhp and bitfields swsel/swsyn).
C868 data sheet 50 v 1.0, 2003-05 below is a table listing output (mcmp) for a bldc motor. block commutation control table mode ccpos0- ccpos2 inputs cc60 - cc62 outputs cout60 - cout62 outputs ccp os0 ccp os1 ccp os2 cc60 cc61 cc62 cout6 0 cout6 1 cout6 2 rotate left, 0 phase shift 1 0 1 inactive inactive active inactive active inactive 1 0 0 inactive inactive active active inactive inactive 1 1 0 inactive active inactive active inactive inactive 0 1 0 inactive active inactive inactive inactive active 0 1 1 active inactive inactive inactive inactive active 0 0 1 active inactive inactive inactive active inactive rotate right 1 1 0 active inactive inactive inactive active inactive 1 0 0 active inactive inactive inactive inactive active 1 0 1 inactive active inactive inactive inactive active 0 0 1 inactive active inactive active inactive inactive 0 1 1 inactive inactive active active inactive inactive 0 1 0 inactive inactive active inactive active inactive slow down x x x inactive inactive inactive active active active idle 1) 1) in case of the sampled hall inputs were neither the current nor the expected hall pattern, the bit whe (wrong hall event) is set which also can cause an interrupt and sets the idle mode clearing mcmp (modulation outputs are inactive). x x x inactive inactive inactive inactive inactive inactive
C868 data sheet 51 v 1.0, 2003-05 for brushless-dc motors there is a special mode (msel6x = ? 1000b ? ) which is triggered by a change of the hall-inputs (ccposx). this mode shows the capabilities of the ccu6. here t12 ? s channel 0 acts in capture function, channel 1 and 2 in compare function (without output modulation) and the multi-channel-block is used to trigger the output switching together with a possible modulation of t13. after the detection of a valid hall edge the t12 count value is captured to channel 0 (representing the actual motor speed) and resets the t12. when the timer reaches the compare value in channel 1, the next multi-channel state is switched by triggering the shadow transfer of bit field mcmp (if enabled in bit field swen). this trigger event can be combined with several conditions which are necessary to implement a noise filtering (correct hall event) and to synchronize the next multi-channel state to the modulation sources (avoiding spikes on the output lines). this compare function of channel 1 can be used as a phase delay for the position input to the output switching which is necessary if a sensorless back-emf technique is used instead of hall sensors. the compare value in channel 2 can be used as a time-out trigger (interrupt) indicating that the motors destination speed is far below the desired value which can be caused by a abnormal load change. in this mode the modulation of t12 has to be disabled (t12modenx = ? 0 ? ). figure 0-2 timer t12 brushless-dc mode (msel6x = 1000) capture event resets t12 ch0 gets captured value for act. speed ch1 compare for phase delay ch2 compare for timeout cc6x act. speed cc60 phase delay cc61 timeout cc62 cout6y 1 1 0 0 0 1 ccpos2 ccpos0 111 00 0 ccpos1 001 11 0
C868 data sheet 52 v 1.0, 2003-05 a/d converter the C868 includes a high performance / high speed 8-bit a/d-converter (adc) with 5 analog input channels. it operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. the a/d converter provides the following features: ? 5 multiplexed input channels, which can also be used as digital inputs ? 8-bit resolution with tue of +/- 2 lsb8. ? single or continuous conversion mode ? start of conversion by software and hardware ? interrupt request generation after each conversion ? using successive approximation conversion technique via a capacitor array ? powerdown in normal, idle and slow-down modes the adc supports two conversion modes - single and continuous conversions. for each mode, there are two ways in which conversion can be started - by software and by the t13pm signal from the ccu module. writing a ? 0 ? to bit ccu_adex select conversion control by adst. writing a ? 1 ? to bit field adst starts conversion on the channel that is specified by adch. in single conversion mode, bit field adm is cleared to ? 0 ? . this is the default mode selected after hardware reset. when a conversion is started, the channel specified is sampled. the busy flag adbsy is set and adst is cleared. when the conversion is completed, the interrupt request signal adcirq is asserted possitively for 2 clocks and the 8-bit result together with the number of the converted channel is transferred to the result register addath. in continuous conversion mode, bit field adm is set to ? 1 ? . in this mode, the adc repeatedly converts the channel specified by adch. bit adst is cleared at the beginning of the first conversion. the busy flag adbsy is asserted until the last conversion is completed. at the end of each conversion, the interrupt request signal adcirq will be activated. to stop conversion, adm has to be reset by software. if the channel number adch is changed while continuous conversion is in progress, the new channel specified will be sampled in the conversions that follow. a new request to start conversion will be allowed only after the completion of any conversion that is in progress. writing a ? 1 ? to bit ccu_adex select conversion control by t13pm trigger signal from the ccu module. note: caution must be taken when changing conversion start source. to change conversion source from software to hardware trigger, it is best to let remaining software conversion to complete before changing. to change conversion source from hardware trigger to software, it is best to change source first, let any
C868 data sheet 53 v 1.0, 2003-05 remaining hardware conversion to complete before beginning a software conversion. conversion and sample time control the conversion and sample times are programmed via the bit fields adctc and adstc respectively of the register adcon1. bit field adctc (conversion time control) selects the internal adc clock - adc_clk. bit field adstc (sample time control) selects the sample time. the total a/d conversion time is given by: t adcc = 2/f sys + t s + 8/adc_clk [5] the sample time t s is configured in periods of the selected internal adc clock. the table below lists the possible combinations. adctc clock divider (tvc) adc basic clock adc_clk adstc sample time t s (periods of adc_clk, stc) 000 (default) 32 f sys / 32 000 (default) 2 001 28 f sys / 28 001 4 010 24 f sys / 24 010 6 011 20 f sys / 20 011 8 100 16 f sys / 16 100 10 101 12 f sys / 12 101 12 110 8 f sys / 8 110 14 111 4 f sys / 4 111 16
C868 data sheet 54 v 1.0, 2003-05 interrupt system the C868 provides 13 interrupt vectors with four priority levels. nine interrupt requests are generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial channel, a/d converter, and the capture/compare unit with 4 interrupts) and four interrupts may be triggered externally. the wake-up from power-down mode interrupt has a special functionality which allows the software power-down mode to be terminated by a short negative pulse at pins ccpos0/t2/int0 /an0 or p1.4/rxd. the 13 interrupt sources are divided into six groups. each group can be programmed to one of the four interrupt priority levels. additionally, 4 of these interrupt sources are channeled from 7 capture/compare (ccu6) interrupt sources. figure 23 to figure 28 give a general overview of the interrupt sources and illustrate the request and control flags.
C868 data sheet 55 v 1.0, 2003-05 figure 23 capture/compare module interrupt structure encc60r icc60r isl.0 ienl.0 encc60f icc60f isl.1 ienl.1 encc61r icc61r isl.2 ienl.2 encc61f icc61f isl.3 ienl.3 encc62r icc62r isl.4 ienl.4 encc62f icc62f isl.5 ienl.5 p3.7/ cc0 p3.5/ cc1 1 p3.3/ cc2 1 1 ent12om isl.6 ienl.6 ent12pm isl.7 ienl.7 1 entrpf trpf ish.2 ienh.2 enwhe whe ish.5 ienh.5 1 t12 one match t12 period p3.1/ wrong hall event match t12pm t12om inpl.0 capcom interrupt node 0 capcom interrupt node 1 capcom interrupt node 2 capcom interrupt node 3 inpl.1 ent13cm t13cm ish.0 ienh.0 ent13pm t13pm ish.1 ienh.1 1 t13 compare match t13 period match enche che ish.4 ienh.4 correct hall event inpl.2 inpl.3 inpl.4 inpl.5 inph.0 inph.1 inph.4 inph.5 inph.2 inph.3 inpl.6 inpl.7 ctrap
C868 data sheet 56 v 1.0, 2003-05 figure 24 interrupt structure, overview part 1 0033 h 000b h 0003 h ien0.7 ip0.0 highest priority level ea ex0 ien0.0 eadc ien1.0 et0 ien0.1 tf0 tcon.5 timer 0 overflow bit addressable request flag is cleared by hardware a/d converter iadc ircon1.0 ie0 it0 tcon.0 tcon.1 ip1.1 ip0.1 lowest priority level p o l l i n g s e q u e n c ccpos2 / int2 / ex2 ien1.1 ex2 ircon0.0 esel2 exicon.0 003b h ip1.0 int0_ core_n (ccpos / t2 / int0 / an0) an2
C868 data sheet 57 v 1.0, 2003-05 figure 25 interrupt structure, overview part 2 ien0.7 highest priority level lowest priority level p o l l i n g s e q u e n c ea bit addressable request flag is cleared by hardware 0013 h 0043 h ex1 ien0.2 ccpos1 / ie1 it1 tcon.2 tcon.3 ex3 ien1.2 exint3 ircon0.1 esel3 exicon.1 int3 p1.3 / ip1.2 ip0.2 einp0 ien2.2 0083 h capture/compare interrupt node 0 t2ex / int1 / an1 inp0 ircon1.2
C868 data sheet 58 v 1.0, 2003-05 figure 26 interrupt structure, overview part 3 ien0.7 ip0.3 ea timer 1 overflow ip1.3 bit addressable request flag is cleared by hardware priority level lowest priority level p o l l i n g s e q u e n c highest 001b h et1 ien0.3 tf1 tcon.7 008b h capture/compare interrupt node 1 einp1 ien2.3 inp1 ircon1.3
C868 data sheet 59 v 1.0, 2003-05 figure 27 interrupt structure, overview part 4 priority level priority level p o l l i n g s e q u e n c highest ien0.7 ea ip0.4 ip1.4 0093 h 0023 h uart es ien0.4 1 ti ri scon.0 scon.1 capture/compare interrupt node 2 einp2 ien2.4 bit addressable request flag is cleared by hardware inp2 ircon1.4
C868 data sheet 60 v 1.0, 2003-05 figure 28 interrupt structure, overview part 5 ien0.7 priority level priority level p o l l i n g s e q u e n c ea bit addressable request flag is cleared by hardware ip1.5 ip0.5 002b h et2 ien0.5 timer 2 overflow tf2 ircon0.6 highest einp3 ien2.5 009b h capture/compare interrupt node 3 inp3 ircon1.5
C868 data sheet 61 v 1.0, 2003-05 table 12 interrupt source and vectors interrupt source interrupt vector address(core connections) interrupt request flags external interrupt 0 0003 h (ex0) ie0 timer 0 overflow 000b h (et0) tf0 external interrupt 1 0013 h (ex1) ie1 timer 1 overflow 001b h (et1) tf1 serial channel 0023 h (es) ri / ti timer 2 overflow 002b h (ex5) tf2 a/d converter 0033 h (ex6) iadc external interrupt 2 003b h (ex7) iex2 external interrupt 3 0043 h (ex8) iex3 004b h (ex9) 0053 h (ex10) 005b h (ex11) 0063 h (ex12) 006b h (ex13) capcom interrupt node 0 0083 h (ex14) inp0 1) 1) capture/compare has 10 interrupt sources channeled to the 4 interrupt nodes inp0..3. the 3 capture/compare ports has 3 pairs of interrupt request flags, icc60r, icc60f, icc61r, icc61f, icc62r, icc62f. the other flags are t12om, t12pm, t13cm, t13pm, trpf, whe, che. capcom interrupt node 1 008b h (ex15) inp1 1) capcom interrupt node 2 0093 h (ex16) inp2 1) capcom interrupt node3 009b h (ex17) inp3 1) 00a3 h (ex18) 00ab h (ex19) 00d3 h (ex20) 00db h (ex21) 00e3 h (ex22) wake-up from power-down mode 007b h ?
C868 data sheet 62 v 1.0, 2003-05 lf two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. lf requests of the same priority level are received simultaneously, an internal polling sequence determines which request is to be serviced first. thus, within each priority level there is a second priority structure determined by the polling sequence. this is illustrated in table 13 . within a column, the topmost interrupt is serviced first, then the second and the third, when available. the interrupt groups are serviced from left to right of the table. a low- priority interrupt can itself be interrupted by a higher-priority interrupt, but not by another interrupt of the same or a lower priority. an interrupt of the highest priority level cannot be interrupted by another interrupt source. table 13 interrupt source structure interrupt group priority bits of interrupt group interrupt source priority high priority low priority priority 0 ip0.0 exint0 iadc high low 1 ip0.1 tf0 exint2 2 ip0.2 exint1 exint3 inp0 1) 1) capture/compare has 10 interrupt sources channeled to the 4 interrupt nodes inp0..3. the 3 capture/ compare ports has 3 pairs of interrupt request flags, icc60r, icc60f, icc61r, icc61f, icc62r, icc62f. the other flags are t12om, t12pm, t13cm, t13pm, trpf, whe, che. 3 ip0.3 tf1 inp1 1) 4 ip0.4 ri + ti inp2 1) 5 ip0.5 tf2 inp3 1)
C868 data sheet 63 v 1.0, 2003-05 fail save mechanisms the C868 offers enhanced fail save mechanisms, which allow an automatic recovery from software upset or hardware failure : a programmable watchdog timer (wdt), with variable time-out period from 12.8 s to 819.2 s at f sys = 40 mhz . programmable watchdog timer to protect the system against software failure, the user ? s program has to clear this watchdog within a previously programmed time period. lf the software fails to do this periodical refresh of the watchdog timer, an internal reset will be initiated. the software can be designed so that the watchdog times out if the program does not work properly. lt also times out if a software error is based on hardware-related problems. the watchdog timer in the C868 is a 16-bit timer, which is incremented by a count rate of f sys /2 upto f sys /128. the machine clock of the C868 is divided by a prescaler, a divide- by-two or a divide-by-128 prescaler. the upper 8 bits of the watchdog timer can be preset to a user-programmable value via a watchdog service access in order to vary the watchdog expire time. the lower 8 bits are reset on each service access. figure 29 shows the block diagram of the watchdog timer unit. figure 29 block diagram of the programmable watchdog timer after a reset, the watchdog timer is automatically enabled. if it is disabled, it cannot be enabled again during active mode of the device. if the software fails to clear the watchdog timer an internal reset will be initiated. the reset cause (external reset or reset caused by the watchdog) can be examined by software (status flag wdtr in scuwdt is set). a refresh of the watchdog timer is done by setting bits wdtre and wdtrs (in wdt high byte wdtrst wdtrel diswdt wdtin mux 1:2 wdt low byte wdt control clear 1:128 f sys
C868 data sheet 64 v 1.0, 2003-05 sfr scuwdt) consecutively. this double instruction sequence has been implemented to increase system security. it must be noted, however, that the watchdog timer is halted during the idle mode and power-down mode of the processor (see section "power saving modes"). it is not possible to use the idle mode in combination with the watchdog timer function. therefore, even the watchdog timer cannot reset the device when one of the power saving modes has been entered accidentally. the time period for an overflow of the watchdog timer is programmable in two ways : ? the input frequency to the watchdog timer can be selected via bit wdtin in register wdtcon to be either f sys /2 or f sys /128. ? the reload value wdtrel for the high byte of wdt can be programmed in register wdtcon. the period p wdt between servicing the watchdog timer and the next overflow can therefore be determined by the following formula: [0.1] table 14 lists the possible ranges for the watchdog time which can be achieved using a certain module clock. some numbers are rounded to 3 significant digits. for safety reasons, the user is advised to rewrite wdtcon each time before the watchdog timer is serviced. table 14 watchdog time ranges reload value in wdtrel prescaler for f sys 2 (wdtin = ? 0 ? ) 128 (wdtin = ? 1 ? ) 40 mhz 20 mhz 16 mhz 40 mhz 20 mhz 16 mhz ff h 12.8 s 25.6 s 32.0 s 819.2 s 1.64 ms 2.05 ms 7f h 1.65 ms 3.3 ms 4.13 ms 105.7 ms 211.3 ms 264 ms 00 h 3.28 ms 6.55 ms 8.19 ms 209.7 ms 419.4 ms 524 ms p wdt = f sys 2 (1 +wdtin*6) * (2 16 - wdtrel * 2 8 )
C868 data sheet 65 v 1.0, 2003-05 power saving modes the C868 provides two basic power saving modes, the idle mode and the power down mode. additionally, a slow down mode is available. this power saving mode reduces the internal clock rate in normal operating mode and it can also be used for further power reduction in idle mode. idle mode in the idle mode, the oscillator of the C868 continues to run, but the cpu is gated off from the clock signal. however, the interrupt system, the serial port, the a/d converter, the capture/compare unit, and all timers are further provided with the clock. the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. slow down mode in some applications, where power consumption and dissipation are critical, the controller might run for a certain time at reduced speed (for example, if the controller is waiting for an input signal). since in cmos devices, there is an almost linear dependence of the operating frequency and the power supply current, so, a reduction of the operating frequency results in reduced power consumption. software power down mode in the software power down mode, the on-chip oscillator which operates with the xtal pins and the pll are all stopped. therefore, all functions of the microcontroller are stopped and only the contents of the on-chip ram, xram and the sfr's are maintained. the port pins, which are controlled by their port latches, output the values that are held by their sfr's. the port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power down mode. ale is held at logic low level or high impedance if disabled. in the power down mode of operation, v ddp can be reduced to minimize power consumption. it must be ensured, however, that v ddp is not reduced before the power down mode is invoked, and that v ddp is restored to its normal operating level before the power down mode is terminated.
C868 data sheet 66 v 1.0, 2003-05 table 15 power saving modes overview mode entering leaving by remarks idle mode orl pcon,#01 h occurance of any enabled interrupt cpu clock is stopped; cpu maintains its data; peripheral units are active (if enabled) and provided with clock hardware reset slow down mode in normal mode: orl pcon,#10 h anl pcon,#0ef h or hardware reset internal clock rate is reduced to a configurable factor of 1 / 2 to 1 / 32 of the system clock rate with idle mode: orl pcon,#11 h occurance of any enabled interrupt to exit idle mode and the instruction anl pcon,#0ef h to terminate slow down mode cpu clock is stopped; cpu maintains all its data; peripheral units are active (if enabled) and provided with a configurable factor of 1 / 2 to 1 / 32 of the system clock rate hardware reset software power down mode with external wake-up capability from power down enabled orl pmcon0,#01 h (to wake-up via pin int0 ) or orl pmcon0,#03 h (to wake-up via pin rxd) orl pcon,#02 h hardware reset oscillator is stopped; contents of on-chip ram and sfr ? s are maintained when int0 or rxd goes low for at least 10 s (latch phase). but it is desired that the corresponding pin must be held at high level during the power down mode entry and up to the wake-up. with external wake-up capability from power down disabled orl pcon,#02 h hardware reset
C868 data sheet 67 v 1.0, 2003-05 device specifications absolute maximum ratings note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maximum rating overload conditions ( v in > v ddp or v in < v ssp , v in2 > v ddc or v in2 < v ssc ) the voltage on v ddp pin with respect to ground ( v ssp ) must not exceed the values defined by the absolute maximum ratings. absolute maximum rating parameters parameter symbol limit values unit notes min. max. ambient temperature under bias t a -40 125 c storage temperature t stg -65 150 c- voltage on v ddp pins with respect to ground ( v ssp ) v ddp -0.3 4.6 v - voltage on any pin except int/ analog and xtal with respect to ground ( v ssp ) v in0 -0.5 4.6 v - voltage on any int/analog pin with respect to ground ( v ssp ) v in1 -0.5 4.6 v - voltage on xtal pins with respect to ground ( v ssc ) v in2 -0.5 4.6 v - input current on any pin during overload condition ov -10 10 ma - 1) 1) proper operation is not guaranteed if overload conditions occur on functional pins like xtal2 etc. absolute sum of all input currents during overload condition | ov |- 43 ma- power dissipation p diss -tbdw-
C868 data sheet 68 v 1.0, 2003-05 operating conditions the following operating conditions must not be exceeded in order to ensure correct operation of the C868. all parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. operating condition parameters parameter symbol limit values unit notes min. max. digital supply voltage v ddp 3.0 3.6 v active mode, f sysmax = 40 mhz tbd 3.6 v powerdown mode 1) 1) oscillator or external clock disabled. digital ground voltages v ssc, v ssp 0v- ambient temperature t a -40 85 c saf-C868... -40 125 c sak-C868... analog reference voltage v aref 3.0v v ddp + 0.1 v- analog ground voltage v agnd v ssp - 0.1 v ssp + 0.1 v- analog input voltage v ain v agnd v aref v- external clock f osc 6.67 10.67 mhz - input current on any pin during overload condition except int/ analog and xtal ov0 -5 5 ma - 2)3) 2) overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. v ov > v ddp +0.5v or v ov < v ssp -0.5v). the absolute sum of input currents on all port pins may not exceed 20ma. the suply voltages v ddp and v ssp must remain within the specified limits. 3) not 100% tested, but guaranteed by design characterization. int/analog pin ov1 -2 5 ma - 3)4) xtal pin ov2 -5 5 ma - 3)5) absolute sum of all input currents during overload condition ? ov -|20|ma- 3) notes:
C868 data sheet 69 v 1.0, 2003-05 4) overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. v ov > tbd or v ov < v ssc -0.5v). the absolute sum of input currents on all port pins may not exceed 20ma. the suply voltages v ddp and v ssp must remain within the specified limits. 5) overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. v ov > v ddc +0.5v or v ov < v ssc -0.5v). the absolute sum of input currents on all port pins may not exceed 20ma. the suply voltages v ddp and v ssp must remain within the specified limits.
C868 data sheet 70 v 1.0, 2003-05 dc characteristics (operating conditions apply) parameter symbol limit values unit test condition min. max. input low voltages all except xtal2, int/analog i nt/analog xtal2 v il0 v il1 v il2 -0.5 -0.5 -0.5 0.3v ddp 0.3v ddc 0.1v ddc v v v ? 1) 1) interrupt/analog pins are input only and has cmos characteristics whereas the other i/o pins have ttl characteristics. input high voltages all except xtal2, int/analog int/analog xtal2 v ih0 v ih1 v ih2 0.7v ddp 0.7v ddc 0.7v ddc v ddp +0.5 v ddp +0.5 v ddc +0.5 v v v ? output low voltage v ol ? 0.45 v saf-C868... i ol =10ma ? 0.55 v sak-C868... i ol =10ma output high voltage v oh 2.4 ? vi oh =10ma input leakage current (all except int/analog) i li0 ? 0. 5ua0.4 C868 data sheet 71 v 1.0, 2003-05 power supply current parameter symbol limit values unit test condition typ. 1) 1) the typical i ddp values are periodically measured at t a = + 25 c but not 100% tested. max. 2) 2) the maximum i ddp values are measured under worst case conditions ( t a = ? 40 c and v ddp =3.6v). active mode C868-1s 40 mhz 3) 3) system clock, set by using external clock of 10.67mhz and setting kdiv in cmcon to 010 (factor of 4) i ddp 13.1 15.6 ma 4) 4) i ddp (active mode) is measured with: xtal2 driven with t r , t f =5ns, v il1 ,v il2 = v ssp +0.5v, v ih1 ,v ih2 = v ddp ? 0.5 v; xtal1 = n.c.; reset = v ddp ; all other pins are disconnected. ?i ddp would be slightly higher if the crystal oscillator is used (approx. 1 ma). C868-1r 40 mhz 3) i ddp 13.5 15.5 ma idle mode C868-1s 40 mhz 3) i ddp 7.8 9.6 ma 5) C868-1r 40 mhz 3) i ddp 7.9 9.1 ma active mode with slow-down enabled C868-1s 40 mhz 3) i ddp 3.5 4.4 ma 6) C868-1r 40 mhz 3) i ddp 3.6 4.1 ma idle mode with slow- down enabled C868-1s 40 mhz 3) i ddp 3.4 4.2 ma 7) C868-1r 40 mhz 3) i ddp 3.6 4.1 ma power- down mode C868-1s i pdp 240 300 ua saf-C868... 8) 240 400 ua sak-C868... 8) C868-1r i pdp 240 300 ua saf-C868... 8) 240 400 ua sak-C868... 8) note:
C868 data sheet 72 v 1.0, 2003-05 5) i ddp (idle mode) is measured with all output pins disconnected and with all peripheral disabled: xtal2 driven with t r , t f =5ns, v il1 ,v il2 = v ssp +0.5v, v ih1 ,v ih2 = v ddp ? 0.5 v; xtal1 = n.c.; reset = v ddp ; all other pins are disconnected. 6) i ddp (active mode with slow down mode) is measured with all output pins disconnected: xtal2 driven with t r , t f =5ns, v il1 ,v il2 = v ssp +0.5v, v ih1 ,v ih2 = v ddp ? 0.5 v; xtal1 = n.c.; reset = v ddp ; all other pins are disconnected; the microcontroller is put into slow-down mode by software with the slow-down clock set to 1/32 of system clock. 7) i ddp (idle mode with slow down mode) is measured with all output pins disconnected and with all peripheral disabled: xtal2 driven with t r , t f =5ns, v il1 ,v il2 = v ssp +0.5v, v ih1 ,v ih2 = v ddp ? 0.5 v; xtal1 = n.c.; reset = v ddp ; all other pins are disconnected; the microcontroller is put into slow-down mode by software with the slow-down clock set to 1/32 of system clock. 8) i pdc and i pdp (power-down mode) are measured under the following conditions: reset = v ddp ; xtal2 = v ssc ; xtal1 = n.c.; v agnd = v ssp ; v aref = v ddp ; rxd/int0 = v ddp ; all other pins are set to input and connected to gnd; ale output disabled and connected to gnd.
C868 data sheet 73 v 1.0, 2003-05 power supply current calculation formulae parameter symbol formula 1) 1) f sys is in mhz and results in ma. active mode C868-1s i ddp typ 0.25* f sys + 3.1 0.26 * f sys + 5.2 i ddp max C868-1r i ddp typ 0.27* f sys + 2.7 0.29 * f sys + 3.9 i ddp max idle mode C868-1s i ddp typ 0.13* f sys + 2.6 0.13 * f sys + 4.0 i ddp max C868-1r i ddp typ 0.13* f sys + 3.7 0.15 * f sys + 3.1 i ddp max active mode with slow-down enabled C868-1s i ddp typ 0.01 * f sys + 3.1 0.02 * f sys + 3.6 i ddp max C868-1r i ddp typ 0.01 * f sys + 3.2 0.01 * f sys + 3.7 i ddp max idle mode with slow- down enabled C868-1s i ddp typ 0.01* f sys + 3.0 0.01 * f sys + 3.8 i ddp max C868-1r i ddp typ 0.02* f sys + 2.8 0.02 * f sys + 3.3 i ddp max
C868 data sheet 74 v 1.0, 2003-05 a/d converter characteristics (operating condition parameters) parameter symbol limits unit test condition min max analog input voltage v ain v agnd v aref v 1) 1) v ain may exceed v agnd or v aref up to the maximum ratings. however, the conversion result in these cases will be 00 h or ff h , respectively. sample time t s 64* t sys 52* t sys 48* t sys 40* t sys 32* t sys 24* t sys 16* t sys 8* t sys 512* t sys 448* t sys 384* t sys 320* t sys 256* t sys 192* t sys 128* t sys 64* t sys ns prescaler/32 prescaler/28 prescaler/24 prescaler/20 prescaler/16 prescaler/12 prescaler/8 prescaler/4 conversion cycle time t adcc 322* t sys 282* t sys 242* t sys 202* t sys 162* t sys 122* t sys 82* t sys 42* t sys 770* t sys 674* t sys 578* t sys 482* t sys 386* t sys 290* t sys 194* t sys 98* t sys ns prescaler/32 prescaler/28 prescaler/24 prescaler/20 prescaler/16 prescaler/12 prescaler/8 prescaler/4 total unadjusted error t ue ? 2 3 lsb v agnd v ain v aref 2) v agnd v ain v aref 3) 2) t ue (max.) is tested at ? 20 t a 125 c; v ddp = 3.3 v; v aref = v ddp v and v ssp = v agnd . it is guaranteed by design characterization for all other voltages within the defined voltage range. 3) t ue (max.) is tested at ? 40 t a < ? 20 c; v ddp 3.3 v; v aref = v ddp and v ssp = v agnd . it is guaranteed by design characterization for all other voltages within the defined voltage range. adc input resistance r ain ? 1.5 k ? 4)5) adc input capacitance c ain ? 10 pf 5) adc reference pin capacitance c aref ? 40 pf 5) note:
C868 data sheet 75 v 1.0, 2003-05 4) during the sample time the input capacitance c ain must be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach their final voltage level within t s . after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. 5) not 100% tested, but guaranteed by design characterization.
C868 data sheet 76 v 1.0, 2003-05 clock calculation table for adc tvc 1) 32 stc 2) 246810121416 t adc 3) t adcc 322 386 450 514 578 642 706 770 t sys t s 64 128 192 256 320 384 448 512 t sys tvc 1) 28 stc 2) 246810121416 t adc 3) t adcc 282 338 394 450 506 562 618 674 t sys t s 56 112 168 224 280 336 392 448 t sys tvc 1) 24 stc 2) 246810121416 t adc 3) t adcc 242 290 338 386 434 482 530 578 t sys t s 48 96 144 192 240 288 336 384 t sys tvc 1) 20 stc 2) 246810121416 t adc 3) t adcc 202 242 282 322 362 402 442 482 t sys t s 40 80 120 160 200 240 280 320 t sys tvc 1) 16 stc 2) 246810121416 t adc 3) t adcc 162 194 226 258 290 322 354 386 t sys t s 32 64 96 128 160 192 224 256 t sys tvc 1) 12 stc 2) 246810121416 t adc 3) t adcc 122 146 170 194 218 242 266 290 t sys t s 24 48 72 96 120 144 168 192 t sys
C868 data sheet 77 v 1.0, 2003-05 tvc 1) 8 stc 2) 246810121416 t adc 3) t adcc 82 98 114 130 146 162 178 194 t sys t s 16 32 48 64 80 96 112 128 t sys tvc 1) 4 stc 2) 246810121416 t adc 3) t adcc 42 50 58 66 74 82 90 98 t sys t s 8 16243240485664 t sys 1) tvc is the clock divider specified by bit fields adctc. 2) stc is the sample time control specified by bit fields adstc. 3) t adc is t sys * tvc
C868 data sheet 78 v 1.0, 2003-05 ac characteristics (operating condition apply) external clock drive characteristics parameter symbol limit values unit variable ext clock 6.67 to 10.67 mhz min max oscillating period t osc 93.75 150 ns high time t 1 46.875 75 ns low time t 2 46.875 75 ns rise time t r -10ns fall time t f -10ns ale characteristics parameter symbol limit values unit system freq = 6.25mhz to 40mhz duty cycle 0.5 min max ale pulse width t awd 50 320 ns ale period t acy 150 960 ns
C868 data sheet 79 v 1.0, 2003-05 figure 30 external clock drive on xtal2 figure 31 ale characteristic mct04105 t 1 t r t f t 2 t osc 0.7 v dd 0.2 v dd - 0.1 c c t awd t acy
C868 data sheet 80 v 1.0, 2003-05 package outlines figure 32 dso-28-1 package outlines 0.35 x 45? -0.2 index marking 1 -0.4 18.1 14 1) 28 0.35 1.27 +0.15 2) 0.2 28x 0.2 15 2.65 max. 0.1 2.45 -0.1 -0.2 7.6 1) 10.3 ?.3 0.23 +0.09 max. 8? +0.8 0.4 does not include dambar protrusion of 0.05 max. per side does not include plastic or metal protrusion of 0.15 max. per side 2) 1) plastic package, p-dso-28-1 for saf-C868-1rg ba, saf-C868-1sg ba saf-C868a-1rg ba, saf-C868a-1sg ba and saf-C868p-1sg ba, sak-C868-1rg ba, sak-C868-1sg ba, sak-C868a-1rg ba, sak-C868a-1sg ba and sak-C868p-1sg ba.
C868 data sheet 81 v 1.0, 2003-05 figure 33 tssop-38-1 package outlines does not include plastic or metal protrusion of 0.25 max. per side does not include dambar protrusion of 0.08 max. per side does not include plastic or metal protrusion of 0.15 max. per side index marking a a 9.7 1 38 0.1 1) 19 0.08 20 m 38x c 0.2 -0.03 +0.07 0.5 2) -0.2 0.05 0.1 c +0.05 1 1.2 max. 0.1 1) 2) 3) -0.035 +0.075 0.1 4.4 3) b ...8 ? 0 ? 0.125 38x 6.4 0.15 0.6 0.2 b plastic package, p-tssop-38-1 for saf-C868-1rr ba, saf-C868-1sr ba, saf-C868a-1rr ba, saf-C868a-1sr ba, saf-C868p-1sr ba, sak-C868-1rr ba, sak-C868-1sr ba, sak-C868a-1rr ba, sak-C868a-1sr ba, and sak-C868p-1sr ba.
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