regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
mitsubishi 8-bit single-chip microcomputer 740 family / 38000 series 38C3 group users manual
keep safety first in your circuit designs ! l mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials l these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. l mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. l all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. l mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. l if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. l please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.
rev. rev. no. date 1.0 first edition 990412 revision description list 38C3 group user?s manual (1/1) revision description
preface this users manual describes mitsubishis cmos 8- bit microcomputers 38C3 group. after reading this manual, the user should have a through knowledge of the functions and features of the 38C3 group, and should be able to fully utilize the product. the manual starts with specifications and ends with application examples. for details of software, refer to the 740 family software manual. for details of development support tools, refer to the development support tools for microcomputers data book.
before using this users manual this users manual consists of the following three chapters. refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. organization l chapter 1 hardware this chapter describes features of the microcomputer and operation of each peripheral function. l chapter 2 application this chapter describes usage and application examples of peripheral functions, based mainly on setting examples of relevant registers. l chapter 3 appendix this chapter includes a list of registers, and necessary information for systems development using the microcomputer, the mask rom confirmation (for mask rom version), rom programming confirmation, and the mark specifications which are to be submitted when ordering. 2. structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows: 2: bit attributesthe attributes of control register bits are classified into 3 bytes : read-only, write-only and read and write. in the figure, these attributes are represented as follows : : bit in which nothing is arranged name functions at reset rw b 0 1 2 3 4 0 0 0 0 0 5 5 5 6 7 0 b0 b1 b2 b3 b4 b5 b6 b7 contents immediately after reset release bit attributes (note 1) 0 0 : single-chip mode 0 1 : 1 0 : 1 1 : processor mode bits stack page selection bit nothing arranged for these bits. these are write disabled bits. when these bits are read out, the contents are ?. fix this bit to ?. main clock division ratio selection bits not available b1 b0 0 : 0 page 1 : 1 page 0 0 : f = x in /2 (high-speed mode) 0 1 : f = x in /8 (middle-speed mode) 1 0 : f = x in /8 (middle-speed mode) 1 1 : f = x in (double-speed mode) : bit that is not used for control of the corresponding function 0 notes 1: contents immediately after reset release 0??at reset release 1??at reset release undefinedundefined or reset release contents determined by option at reset release [ rread read enabled 5 read disabled wwrite write enabled 5 write disabled (note 2) cpu mode register (cpum) [address : 3b 16 ] bits 1 b7 b6 0
1 38C3 group users manual table of contents table of contents chapter 1 hardware description ............................................................................................................................... . 1-2 features ............................................................................................................................... ..... 1-2 application ............................................................................................................................... . 1-2 pin configuration .................................................................................................................. 1-2 functional block .................................................................................................................. 1-3 pin description ........................................................................................................................ 1-4 part numbering ....................................................................................................................... 1-6 group expansion .................................................................................................................... 1-7 memory type ............................................................................................................................ 1-7 memory size ............................................................................................................................. 1- 7 package ............................................................................................................................... ...... 1-7 functional description ...................................................................................................... 1-8 central processing unit (cpu) .............................................................................................. 1-8 memory ............................................................................................................................... ..... 1-12 i/o ports ............................................................................................................................... ... 1-14 interrupts ............................................................................................................................... .. 1-19 timers ............................................................................................................................... ....... 1-23 serial i/o ............................................................................................................................... .. 1-28 a-d converter ......................................................................................................................... 1-30 lcd drive control circuit ....................................................................................................... 1-31 f clock output function ....................................................................................................... 1-37 rom correction function (mask rom version only) ........................................................ 1-38 reset circuit ........................................................................................................................... 1-39 clock generating circuit ....................................................................................................... 1-41 notes on programming ..................................................................................................... 1-44 notes on use .......................................................................................................................... 1-44 data required for mask orders ................................................................................ 1-45 data required for rom writing orders ................................................................. 1-45 rom programming method .............................................................................................. 1-45 functional description supplement ......................................................................... 1-46 chapter 2 application 2.1 i/o port ............................................................................................................................... ...... 2-2 2.1.1 memory map ................................................................................................................... 2-2 2.1.2 relevant registers .......................................................................................................... 2-3 2.1.3 terminate unused pins .................................................................................................. 2-7 2.1.4 notes on i/o port ........................................................................................................... 2-8 2.1.5 termination of unused pins .......................................................................................... 2-9 2.2 timer ............................................................................................................................... ........ 2-10 2.2.1 memory map ................................................................................................................. 2-10 2.2.2 relevant registers ........................................................................................................ 2-11 2.2.3 timer application examples ........................................................................................ 2-19 2.2.4 notes on timer a (pwm mode and igbt output mode) ...................................... 2-31 2.3 serial i/o ............................................................................................................................... . 2-33 2.3.1 memory map ................................................................................................................. 2-33 2.3.2 relevant registers ........................................................................................................ 2-33 2.3.3 serial i/o connection examples ................................................................................. 2-36
2 38C3 group users manual table of contents 2.3.4 serial i/os modes ....................................................................................................... 2-38 2.3.5 serial i/o application examples ................................................................................. 2-38 2.3.6 notes on serial i/o ...................................................................................................... 2-51 2.4 lcd controller ...................................................................................................................... 2-52 2.4.1 memory map ................................................................................................................. 2-52 2.4.2 relevant registers ........................................................................................................ 2-53 2.4.3 lcd controller application examples ......................................................................... 2-54 2.4.4 notes on lcd controller ............................................................................................. 2-58 2.5 a-d converter ....................................................................................................................... 2-59 2.5.1 memory map ................................................................................................................. 2-59 2.5.2 relevant registers ........................................................................................................ 2-59 2.5.3 a-d converter application examples .......................................................................... 2-62 2.5.4 notes on a-d converter .............................................................................................. 2-64 2.6 rom correct function ......................................................................................................... 2-65 2.6.1 memory map ................................................................................................................. 2-65 2.6.2 relevant registers ........................................................................................................ 2-66 2.6.3 rom correct function application examples ............................................................. 2-67 2.7 reset circuit ......................................................................................................................... 2-69 2.7.1 connection example of reset ic ................................................................................ 2-69 2.7.2 notes on reset circuit .................................................................................................. 2-70 2.8 clock generating circuit .................................................................................................... 2-71 2.8.1 relevant register .......................................................................................................... 2-71 2.8.2 clock generating circuit application examples ......................................................... 2-72 chapter 3 appendix 3.1 electrical characteristics ..................................................................................................... 3-2 3.1.1 absolute maximum ratings ............................................................................................ 3-2 3.1.2 recommended operating conditions ............................................................................ 3-2 3.1.3 electrical characteristics ................................................................................................ 3-5 3.1.4 a-d converter characteristics ....................................................................................... 3-7 3.1.5 timing requirements and switching characteristics ................................................... 3-8 3.1.6 absolute maximum ratings (m version) ..................................................................... 3-10 3.1.7 recommended operating conditions (m version) ..................................................... 3-10 3.1.8 electrical characteristics (m version) ......................................................................... 3-14 3.1.9 a-d converter characteristics (m version) ................................................................ 3-16 3.1.10 timing requirements and switching characteristics (m version) .......................... 3-17 3.2 standard characteristics .................................................................................................... 3-20 3.2.1 power source current standard characteristics ........................................................ 3-20 3.2.2 port standard characteristics ...................................................................................... 3-21 3.3 notes on use ........................................................................................................................ 3-26 3.3.1 notes on interrupts ...................................................................................................... 3-26 3.3.2 notes on timer a (pwm mode and igbt output mode) ...................................... 3-27 3.3.3 notes on serial i/o ...................................................................................................... 3-29 3.3.4 notes on lcd controller ............................................................................................. 3-29 3.3.5 notes on a-d converter .............................................................................................. 3-30 3.3.6 notes on reset circuit .................................................................................................. 3-30 3.4 countermeasures against noise ...................................................................................... 3-31 3.4.1 shortest wiring length .................................................................................................. 3-31 3.4.2 connection of bypass capacitor across v ss line and v cc line ............................... 3-33 3.4.3 wiring to analog input pins ........................................................................................ 3-34 3.4.4 oscillator concerns ....................................................................................................... 3-34 3.4.5 setup for i/o ports ....................................................................................................... 3-36
3 38C3 group users manual table of contents 3.4.6 providing of watchdog timer function by software .................................................. 3-37 3.5 control registers .................................................................................................................. 3-38 3.6 mask rom confirmation form ........................................................................................... 3-58 3.7 rom programming confirmation form ............................................................................ 3-62 3.8 mark specification form ..................................................................................................... 3-66 3.9 package outline ................................................................................................................... 3-67 3.10 machine instructions ........................................................................................................ 3-68 3.11 list of instruction code ................................................................................................... 3-79 3.12 sfr memory map .............................................................................................................. 3-80 3.13 pin configuration ............................................................................................................... 3-81
4 38C3 group users manual list of figures list of figures chapter 1 hardware fig. 1 m38C34m6axxxfp pin configuration .............................................................................. 1-2 fig. 2 functional block diagram ................................................................................................... 1-3 fig. 3 part numbering .................................................................................................................... 1-6 fig. 4 memory expansion plan ..................................................................................................... 1-7 fig. 5 740 family cpu register structure ................................................................................... 1-8 fig. 6 register push and pop at interrupt generation and subroutine call ........................... 1-9 fig. 7 structure of cpu mode register ..................................................................................... 1-11 fig. 8 memory map diagram ...................................................................................................... 1-12 fig. 9 memory map of special function register (sfr) .......................................................... 1-13 fig. 10 structure of pull register a and pull register b ................................................... 1-14 fig. 11 structure of port p8 output selection register ............................................................ 1-14 fig. 12 port block diagram (1) ................................................................................................... 1-16 fig. 13 port block diagram (2) ................................................................................................... 1-17 fig. 14 port block diagram (3) ................................................................................................... 1-18 fig. 15 interrupt control ............................................................................................................... 1-21 fig. 16 structure of interrupt-related registers ......................................................................... 1-21 fig. 17 connection example when using key input interrupt and port p8 block diagram 1-22 fig. 18 structure of timer related register ................................................................................ 1-23 fig. 19 block diagram of timer .................................................................................................. 1-24 fig. 20 timing chart of timer 6 pwm 1 mode ........................................................................... 1-25 fig. 21 block diagram of timer a .............................................................................................. 1-26 fig. 22 structure of timer a related registers .......................................................................... 1-26 fig. 23 timing chart of timer a pwm, igbt output modes .................................................. 1-27 fig. 24 block diagram of serial i/o ........................................................................................... 1-28 fig. 25 structure of serial i/o control register ......................................................................... 1-29 fig. 26 serial i/o timing (for lsb first) .................................................................................... 1-29 fig. 27 structure of a-d control register .................................................................................. 1-30 fig. 28 black diagram of a-d converter ................................................................................... 1-30 fig. 29 structure of lcd related registers ............................................................................... 1-31 fig. 30 block diagram of lcd controller/driver ....................................................................... 1-32 fig. 31 example of circuit at each bias .................................................................................... 1-33 fig. 32 lcd display ram map .................................................................................................. 1-34 fig. 33 lcd drive waveform (1/2 bias) .................................................................................... 1-35 fig. 34 lcd drive waveform (1/3 bias) .................................................................................... 1-36 fig. 35 structure of f output control register .......................................................................... 1-37 fig. 36 structure of rom correct address register ................................................................. 1-38 fig. 37 structure of rom correct data .................................................................................... 1-38 fig. 38 structure of rom correct enable register 1 ............................................................... 1-38 fig. 39 reset circuit example .................................................................................................... 1-39 fig. 40 reset sequence .............................................................................................................. 1-39 fig. 41 internal status at reset .................................................................................................. 1-40 fig. 42 ceramic resonator circuit .............................................................................................. 1-41 fig. 43 external clock input circuit ............................................................................................ 1-41 fig. 44 clock generating circuit block diagram ....................................................................... 1-42 fig. 45 state transitions of system clock ................................................................................. 1-43 fig. 46 programming and testing of one time prom version ............................................ 1-45 fig. 47 timing chart after interrupt occurs ............................................................................... 1-47
5 38C3 group users manual list of figures fig. 48 time up to execution of interrupt processing routine ............................................... 1-47 fig. 49 a-d conversion equivalent circuit ................................................................................. 1-49 fig. 50 a-d conversion timing chart .......................................................................................... 1-49 chapter 2 application fig. 2.1.1 memory map of i/o port relevant registers .............................................................. 2-2 fig. 2.1.2 structure of port pi (i = 0, 1, 2, 3, 4, 5, 6, 8) ........................................................ 2-3 fig. 2.1.3 structure of port p7 ..................................................................................................... 2-3 fig. 2.1.4 structure of port p0 direction register and port p1 direction register ................. 2-4 fig. 2.1.5 structure of port pi direction register (i = 2, 4, 5, 6, 8) ....................................... 2-4 fig. 2.1.6 structure of port p7 direction register ...................................................................... 2-5 fig. 2.1.7 structure of pull register a ...................................................................................... 2-5 fig. 2.1.8 structure of pull register b ...................................................................................... 2-6 fig. 2.1.9 structure of port p8 output selection register ......................................................... 2-6 fig. 2.2.1 memory map of registers relevant to timers .......................................................... 2-10 fig. 2.2.2 structure of timer i (i=1, 3, 4, 5, 6) ....................................................................... 2-11 fig. 2.2.3 structure of timer 2 .................................................................................................. 2-11 fig. 2.2.4 structure of timer 6 pwm register ......................................................................... 2-12 fig. 2.2.5 structure of timer 12 mode register ....................................................................... 2-12 fig. 2.2.6 structure of timer 34 mode register ....................................................................... 2-13 fig. 2.2.7 structure of timer 56 mode register ....................................................................... 2-13 fig. 2.2.8 structure of timer a register (low-order, high-order) ........................................... 2-14 fig. 2.2.9 structure of compare register (low-order, high-order) .......................................... 2-14 fig. 2.2.10 structure of timer a mode register ...................................................................... 2-15 fig. 2.2.11 structure of timer a control register .................................................................... 2-15 fig. 2.2.12 structure of interrupt request register 1 ............................................................... 2-16 fig. 2.2.13 structure of interrupt request register 2 ............................................................... 2-17 fig. 2.2.14 structure of interrupt control register 1 ................................................................ 2-18 fig. 2.2.15 structure of interrupt control register 2 ................................................................ 2-18 fig. 2.2.16 timers connection and setting of division ratios ................................................. 2-20 fig. 2.2.17 relevant registers setting ....................................................................................... 2-21 fig. 2.2.18 control procedure ..................................................................................................... 2-22 fig. 2.2.19 peripheral circuit example ....................................................................................... 2-23 fig. 2.2.20 timers connection and setting of division ratios ................................................. 2-23 fig. 2.2.21 relevant registers setting ....................................................................................... 2-24 fig. 2.2.22 control procedure ..................................................................................................... 2-24 fig. 2.2.23 judgment method of valid/invalid of input pulses ............................................... 2-25 fig. 2.2.24 relevant registers setting ....................................................................................... 2-26 fig. 2.2.25 control procedure ..................................................................................................... 2-27 fig. 2.2.26 timers connection and setting of division ratios ................................................. 2-28 fig. 2.2.27 relevant registers setting ....................................................................................... 2-29 fig. 2.2.28 control procedure ..................................................................................................... 2-30 fig. 2.2.29 pwm output and igbt output (1) ......................................................................... 2-31 fig. 2.2.30 pwm output and igbt output (2) ......................................................................... 2-31 fig. 2.2.31 pwm output and igbt output (3) ......................................................................... 2-32 fig. 2.3.1 memory map of registers relevant to serial i/o .................................................... 2-33 fig. 2.3.2 structure of serial i/o control register 1 ................................................................ 2-33 fig. 2.3.3 structure of serial i/o control register 2 ................................................................ 2-34 fig. 2.3.4 structure of interrupt request register 1 ................................................................. 2-34 fig. 2.3.5 structure of interrupt control register 1 .................................................................. 2-35 fig. 2.3.6 serial i/o connection examples (1) ......................................................................... 2-36 fig. 2.3.7 serial i/o connection examples (2) ......................................................................... 2-37
6 38C3 group users manual list of figures fig. 2.3.8 serial i/os modes ..................................................................................................... 2-38 fig. 2.3.9 connection diagram ................................................................................................... 2-38 fig. 2.3.10 timing chart .............................................................................................................. 2-39 fig. 2.3.11 registers setting relevant to transmission side ................................................... 2-40 fig. 2.3.12 registers setting relevant to reception side ......................................................... 2-41 fig. 2.3.13 control procedure of transmission side ................................................................ 2-41 fig. 2.3.14 control procedure of reception side ...................................................................... 2-42 fig. 2.3.15 connection diagram ................................................................................................. 2-43 fig. 2.3.16 timing chart .............................................................................................................. 2-43 fig. 2.3.17 relevant registers setting ....................................................................................... 2-44 fig. 2.3.18 setting of transmission data ................................................................................... 2-44 fig. 2.3.19 control procedure ..................................................................................................... 2-45 fig. 2.3.20 connection diagram ................................................................................................. 2-46 fig. 2.3.21 timing chart .............................................................................................................. 2-47 fig. 2.3.22 relevant registers setting in master unit .............................................................. 2-48 fig. 2.3.23 relevant registers setting in slave unit ................................................................ 2-48 fig. 2.3.24 control procedure of master unit ........................................................................... 2-49 fig. 2.3.25 control procedure of slave unit ............................................................................. 2-50 fig. 2.4.1 memory map of registers relevant to lcd controller ............................................ 2-52 fig. 2.4.2 structure of segment output enable register ......................................................... 2-53 fig. 2.4.3 structure of lcd mode register ............................................................................... 2-53 fig. 2.4.4 lcd panel ................................................................................................................... 2-54 fig. 2.4.5 segment allocation example ..................................................................................... 2-54 fig. 2.4.6 lcd display ram map .............................................................................................. 2-55 fig. 2.4.7 lcd display ram setting .......................................................................................... 2-55 fig. 2.4.8 relevant registers setting ......................................................................................... 2-56 fig. 2.4.9 control procedure ....................................................................................................... 2-57 fig. 2.5.1 memory map of a-d converter relevant registers ................................................. 2-59 fig. 2.5.2 structure of a-d control register .............................................................................. 2-59 fig. 2.5.3 structure of a-d conversion register (low-order) ................................................... 2-60 fig. 2.5.4 structure of a-d conversion register (high-order) ................................................. 2-60 fig. 2.5.5 structure of interrupt request register 2 ................................................................. 2-61 fig. 2.5.6 structure of interrupt control register 2 .................................................................. 2-61 fig. 2.5.7 connection diagram ................................................................................................... 2-62 fig. 2.5.8 setting of relevant registers ..................................................................................... 2-62 fig. 2.5.9 control procedure ....................................................................................................... 2-63 fig. 2.6.1 memory map of rom correct function relevant registers .................................... 2-65 fig. 2.6.2 structure of rom correct enable register 1 ........................................................... 2-66 fig. 2.6.3 connection diagram ................................................................................................... 2-67 fig. 2.6.4 setting of relevant registers ..................................................................................... 2-67 fig. 2.6.5 control procedure ....................................................................................................... 2-68 fig. 2.7.1 example of power-on reset circuit ........................................................................... 2-69 fig. 2.7.2 ram backup system example .................................................................................. 2-69 fig. 2.8.1 structure of cpu mode register .............................................................................. 2-71 fig. 2.8.2 connection diagram ................................................................................................... 2-72 fig. 2.8.3 status transition diagram during power failure ...................................................... 2-73 fig. 2.8.4 setting of relevant registers ..................................................................................... 2-74 fig. 2.8.5 control procedure ....................................................................................................... 2-75 fig. 2.8.6 structure of clock counter ......................................................................................... 2-76 fig. 2.8.7 initial setting of relevant registers ........................................................................... 2-77 fig. 2.8.8 setting of relevant registers after detecting power failure ................................... 2-78 fig. 2.8.9 control procedure ....................................................................................................... 2-79
7 38C3 group users manual list of figures chapter 3 appendix fig. 3.1.1 circuit for measuring output switching characteristics .......................................... 3-18 fig. 3.1.2 timing chart ................................................................................................................ 3-19 fig. 3.2.1 power source current standard characteristics ...................................................... 3-20 fig. 3.2.2 power source current standard characteristics (in wait mode) ........................... 3-20 fig. 3.2.3 cmos output port (p0, p1, p2, p3) p-channel side characteristics (25 c) .... 3-21 fig. 3.2.4 cmos output port (p0, p1, p2, p3) p-channel side characteristics (90 c) .... 3-21 fig. 3.2.5 cmos output port (p0, p1, p2, p3) p-channel side characteristics (25 c) .... 3-22 fig. 3.2.6 cmos output port (p0, p1, p2, p3) n-channel side characteristics (90 c) ... 3-22 fig. 3.2.7 cmos output port (p4, p5 0 , p5 2 Cp5 7 , p6, p7 0 , p7 1 , p8) p-channel side characteristics (25 c) .......................................................................................................................... 3-23 fig. 3.2.8 cmos output port (p4, p5 0 , p5 2 Cp5 7 , p6, p7 0 , p7 1 , p8) p-channel side characteristics (90 c) .......................................................................................................................... 3-23 fig. 3.2.9 cmos output port (p4, p5 2 Cp5 7 , p6, p7 0 , p7 1 ) n-channel side characteristics (25 c) ............................................................................................................................... ......................... 3-24 fig. 3.2.10 cmos output port (p4, p5 2 Cp5 7 , p6, p7 0 , p7 1 ) n-channel side characteristics (90 c) ....................................................................................................................... 3-24 fig. 3.2.11 cmos output port (p5 0 , p8) n-channel side characteristics (25 c) ............... 3-25 fig. 3.2.12 cmos output port (p5 0 , p8) n-channel side characteristics (90 c) ............... 3-25 fig. 3.3.1 sequence of switch detection edge ......................................................................... 3-26 fig. 3.3.2 sequence of check of interrupt request bit ............................................................ 3-26 fig. 3.3.3 structure of interrupt control register 2 .................................................................. 3-27 fig. 3.3.4 pwm output and igbt output (1) ............................................................................ 3-27 fig. 3.3.5 pwm output and igbt output (2) ............................................................................ 3-28 fig. 3.3.6 pwm output and igbt output (3) ............................................................................ 3-28 fig. 3.4.1 selection of packages ............................................................................................... 3-31 fig. 3.4.2 wiring for the reset pin ......................................................................................... 3-31 fig. 3.4.3 wiring for clock i/o pins ........................................................................................... 3-32 fig. 3.4.4 wiring for the v pp pin of the one time prom and the eprom version ......... 3-33 fig. 3.4.5 bypass capacitor across the v ss line and the v cc line ........................................ 3-33 fig. 3.4.6 analog signal line and a resistor and a capacitor ................................................ 3-34 fig. 3.4.7 wiring for a large current signal line ...................................................................... 3-34 fig. 3.4.8 wiring of signal lines where potential levels change frequently ......................... 3-35 fig. 3.4.9 v ss pattern on the underside of an oscillator ........................................................ 3-35 fig. 3.4.10 setup for i/o ports ................................................................................................... 3-36 fig. 3.4.11 watchdog timer by software ................................................................................... 3-37 fig. 3.5.1 structure of port pi .................................................................................................... 3-38 fig. 3.5.2 structure of port p0 direction register and port p1 direction register ............... 3-38 fig. 3.5.3 structure of port pi direction register ..................................................................... 3-39 fig. 3.5.4 structure of port p7 ................................................................................................... 3-39 fig. 3.5.5 structure of port p7 direction register .................................................................... 3-40 fig. 3.5.6 structure of pull register a .................................................................................... 3-40 fig. 3.5.7 structure of pull register b .................................................................................... 3-41 fig. 3.5.8 structure of port p8 output selection register ....................................................... 3-42 fig. 3.5.9 structure of serial i/o control register 1 ................................................................ 3-43 fig. 3.5.10 structure of serial i/o control register 2 .............................................................. 3-44 fig. 3.5.11 structure of serial i/o register ............................................................................... 3-44 fig. 3.5.12 structure of timer i ................................................................................................. 3-45 fig. 3.5.13 structure of timer 2 ................................................................................................ 3-45 fig. 3.5.14 structure of timer 6 pwm register ....................................................................... 3-46 fig. 3.5.15 structure of timer 12 mode register ..................................................................... 3-46
8 38C3 group users manual list of figures fig. 3.5.16 structure of timer 34 mode register ..................................................................... 3-47 fig. 3.5.17 structure of timer 56 mode register ..................................................................... 3-47 fig. 3.5.18 structure of f output control register .................................................................... 3-48 fig. 3.5.19 structure of timer a register (low-order, high-order) ......................................... 3-48 fig. 3.5.20 structure of compare register (low-order, high-order) ........................................ 3-49 fig. 3.5.21 structure of timer a mode register ...................................................................... 3-49 fig. 3.5.22 structure of timer a control register .................................................................... 3-50 fig. 3.5.23 structure of a-d control register ............................................................................ 3-50 fig. 3.5.24 structure of a-d conversion register (low-order) ................................................. 3-51 fig. 3.5.25 structure of a-d conversion register (high-order) ............................................... 3-51 fig. 3.5.26 structure of segment output enable register ....................................................... 3-52 fig. 3.5.27 structure of lcd mode register ............................................................................. 3-52 fig. 3.5.28 structure of interrupt edge selection register ...................................................... 3-53 fig. 3.5.29 structure of cpu mode register ............................................................................ 3-53 fig. 3.5.30 structure of interrupt reqeust register 1 ............................................................... 3-54 fig. 3.5.31 structure of interrupt request register 2 ............................................................... 3-55 fig. 3.5.32 structure of interrupt control register 1 ................................................................ 3-56 fig. 3.5.33 structure of interrupt control register 2 ................................................................ 3-56 fig. 3.5.34 structure of rom correct enable register 1 ......................................................... 3-57
9 38C3 group users manual list of tables list of tables chapter 1 hardware table 1 pin description (1) ........................................................................................................... 1-4 table 2 pin description (2) ........................................................................................................... 1-5 table 3 support products ............................................................................................................. 1-7 table 4 push and pop instructions of accumulator or processor status register ................. 1-9 table 5 set and clear instructions of each bit of processor status register ....................... 1-10 table 6 list of i/o port function (1) .......................................................................................... 1-14 table 7 list of i/o port function (2) .......................................................................................... 1-15 table 8 interrupt vector addresses and priority ...................................................................... 1-20 table 9 function of p4 6 /s clk1 and p4 0 /s clk2 ............................................................................................................................... ...... 1-28 table 10 maximum number of display pixels at each duty ratio .......................................... 1-31 table 11 bias control and applied voltage to v l1 Cv l3 .......................................................................................................... 1-33 table 12 duty ratio control and common pins used ............................................................... 1-33 table 13 programming adapter .................................................................................................. 1-45 table 14 interrupt sources, vector addresses and interrupt priority ..................................... 1-46 table 15 relative formula for a reference voltage v ref of a-d converter and v ref ..................... 1-48 table 16 change of a-d conversion register during a-d conversion .................................. 1-48 chapter 2 application table 2.1.1 termination of unused pins ..................................................................................... 2-7 chapter 3 appendix table 3.1.1 absolute maximum ratings ....................................................................................... 3-2 table 3.1.2 recommended operating conditions ....................................................................... 3-2 table 3.1.3 recommended operating conditions ....................................................................... 3-3 table 3.1.4 recommended operating conditions ....................................................................... 3-4 table 3.1.5 electrical characteristics ........................................................................................... 3-5 table 3.1.6 electrical characteristics ........................................................................................... 3-6 table 3.1.7 a-d converter characteristics .................................................................................. 3-7 table 3.1.8 timing requirements 1 .............................................................................................. 3-8 table 3.1.9 timing requirements 2 .............................................................................................. 3-8 table 3.1.10 switching characteristics 1 .................................................................................... 3-9 table 3.1.11 switching characteristics 2 .................................................................................... 3-9 table 3.1.12 absolute maximum ratings (m version) ............................................................. 3-10 table 3.1.13 recommended operating conditions (m version) ............................................. 3-10 table 3.1.14 recommended operating conditions (m version) ............................................. 3-11 table 3.1.15 recommended operating conditions (m version) ............................................. 3-11 table 3.1.16 recommended operating conditions (m version) ............................................. 3-12 table 3.1.17 recommended operating conditions (m version) ............................................. 3-13 table 3.1.18 electrical characteristics (m version) .................................................................. 3-14 table 3.1.19 electrical characteristics (m version) .................................................................. 3-15 table 3.1.20 a-d converter characteristics (m version) ......................................................... 3-16 table 3.1.21 timing requirements 1 (m version) .................................................................... 3-17 table 3.1.22 timing requirements 2 (m version) .................................................................... 3-17 table 3.1.23 switching characteristics 1 (m version) ............................................................. 3-18 table 3.1.24 switching characteristics 2 (m version) ............................................................. 3-18
chapter 1 chapter 1 hardware description features application pin configuration functional block pin description part numbering group expansion functional description notes on programming notes on use data required for mask orders data required for rom writing orders rom programming method functional description supplement
38C3 group users manual hardware 1-2 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 p6 7 /an 7 av ss v ref p6 0 /an 0 p6 1 /an 1 p6 2 /an 2 p6 3 /an 3 v cc v ss x out p7 0 /xc in p7 1 /xc out x in reset vl 1 com 3 com 2 com 1 com 0 vl 3 vl 2 p4 0 /s clk2 p4 2 /t3 out p4 3 / f p4 4 /s in p4 5 /s out p4 6 /s clk1 p4 7 /s rdy p4 1 /t1 out p8 0 p8 1 p8 2 p8 3 p8 4 p8 5 p8 6 p8 7 p3 0 /seg 24 p3 3 /seg 27 p3 4 /seg 28 p3 5 /seg 29 p3 6 /seg 30 p3 7 /seg 31 p3 1 /seg 25 p3 2 /seg 26 m38C34m6axxxfp p5 1 p5 2 /pwm 1 p5 5 /int 0 p5 6 /int 1 p5 7 /int 2 p1 0 /seg 16 p1 1 /seg 17 p1 2 /seg 18 p1 3 /seg 19 p1 4 /seg 20 p1 5 /seg 21 p1 6 /seg 22 p1 7 /seg 23 p0 0 /seg 8 p0 1 /seg 9 p0 2 /seg 10 p0 3 /seg 11 p0 4 /seg 12 p0 5 /seg 13 p0 6 /seg 14 p0 7 /seg 15 p2 7 /seg 7 p2 6 /seg 6 p2 5 /seg 5 p2 4 /seg 4 p2 3 /seg 3 p2 2 /seg 2 p2 1 /seg 1 p2 0 /seg 0 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p5 3 /cntr 0 p5 4 /cntr 1 p5 0 /ta out pin configuration (top view) package type : 80p6n-a 80-pin plastic-molded qfp description the 38C3 group is the 8-bit microcomputer based on the 740 family core technology. the 38C3 group has a lcd drive control circuit, a 10-channel a-d converter, and a serial i/o as additional functions. the various microcomputers in the 38C3 group include variations of internal memory size and packaging. for details, refer to the section on part numbering. for details on availability of microcomputers in the 38C3 group, refer to the section on group expansion. features l basic machine-language instructions ....................................... 71 l the minimum instruction execution time ............................. 0.5 m s (at 8mhz oscillation frequency) l memory size rom .................................................................. 4 k to 48 k bytes ram ................................................................. 192 to 1024 bytes l programmable input/output ports ............................................. 57 l software pull-up/pull-down resistors ..................................................... (ports p0Cp8 except port p5 1 ) l interrupts ................................................... 16 sources, 16 vectors (includes key input interrupt) l timers ............................................................ 8-bit 5 6, 16-bit 5 1 l a-d converter ................................................. 10-bit 5 8 channels l serial i/o ....................................... 8-bit 5 1 (clock-synchronized) l lcd drive control circuit bias ............................................................................ 1/1, 1/2, 1/3 duty .................................................................... 1/1, 1/2, 1/3, 1/4 common output .......................................................................... 4 segment output ........................................................................ 32 l 2 clock generating circuit (connect to external ceramic resonator or quartz-crystal oscillator) l power source voltage in high-speed mode .................................................... 4.0 to 5.5 v in middle-speed mode ................................................ 2.5 to 5.5 v (m version is 2.2 ] to 5.5 v) in low-speed mode ..................................................... 2.5 to 5.5 v (m version is 2.2 ] to 5.5 v) l power dissipation in high-speed mode ........................................................... 32 mw (at 8 mhz oscillation frequency) in low-speed mode .............................................................. 45 m w (at 32 khz oscillation frequency, at 3 v power source voltage) l operating temperature range ................................... C 20 to 85c ] mask rom version only application camera, household appliances, consumer electronics, etc. fig. 1 m38C34m6axxxfp pin configuration description/features/application/pin configuration
38C3 group users manual hardware 1-3 functional block diagram fig. 2 functional block diagram key-on wake-up int 0 ?nt 2 cntr 0 ,cntr 1 t1 out, t3 out f data bus c p u a x y s pc h pc l ps reset v cc v ss reset input ( 5 v ) ( 0 v ) r o m r a m lcd display ram (16 bytes) 10 16 13 i/o port p5 p4(8) i/o port p4 i/o port p2 p2(8) i/o port p1 p1(8) p6(8) output port p3 i/o port p6 p5(8) i/o port p7 p7(2) 28 27 26 32 31 30 29 i/o port p0 p0(8) 49 50 51 52 53 54 55 56 41 42 43 44 45 46 47 48 57 58 59 60 61 62 63 64 67 68 69 70 71 72 65 66 12 11 1 2 75 76 77 78 79 80 73 74 456789 17 3 clock generating circuit main clock input x in main clock output x out x cout sub- clock output x cin sub- clock input si/o(8) v ref av ss ( 0 v ) a-d converter(10) timer 1(8) timer 2(8) lcd drive control circuit v l1 v l2 v l3 com 0 com 1 com 2 com 3 f x cin x cout 14 15 timer 3(8) timer 4(8) timer 5(8) timer 6(8) p3(8) 33 34 35 36 37 38 39 40 r o m corrective circuit rom corrective ram (8 bytes) i/o port p8 p8(8) 18 19 20 21 22 23 24 25 pwm 0, pwm 1 timer a(16) ] ] this is valid only in mask rom version. functional block
38C3 group users manual hardware 1-4 ? apply voltage of 2.5 ] v to 5.5 v to v cc , and 0 v to v ss . ? reference voltage input pin for a-d converter. ? gnd input pin for a-d converter. ? connect to v ss . ? reset input pin for active l. ? input and output pins for the main clock generating circuit. ? feedback resistor is built in between x in pin and x out pin. ? connect a ceramic resonator or a quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ? if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ? input 0 v l1 v l2 v l3 v cc voltage. ? input 0 C v l3 voltage to lcd. ? lcd common output pins. ? com 1 , com 2 , and com 3 are not used at 1/1 duty ratio. ? com 2 and com 3 are not used at 1/2 duty ratio. ? com 3 is not used at 1/3 duty ratio. ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each port to be individually programmed as either input or output. ? pull-down control is enabled. ? 8-bit output port. ? cmos state output. ? pull-down control is enabled. ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? lcd segment pins ? serial i/o function pin ? timer output pin ? timer output pin ? f output pin ? serial i/o function pins pin v cc , v ss v ref av ss reset x in x out v l1 C v l3 com 0 C com 3 p0 0 /seg 8 C p0 7 /seg 15 p1 0 /seg 16 C p1 7 /seg 23 p2 0 /seg 0 C p2 7 /seg 7 p3 0 /seg 24 C p3 7 /seg 31 p4 0 /s clk2 p4 1 /t 1out p4 2 /t 3out p4 3 / f p4 4 /s in , p4 5 /s out , p4 6 /s clk1, p4 7 /s rdy name power source analog reference voltage analog power source reset input clock input clock output lcd power source common output i/o port p0 i/o port p1 i/o port p2 output port p3 i/o port p4 function except a port function pin description table 1 pin description (1) function pin description ] mask rom version of m version is 2.2 v to 5.5 v.
38C3 group users manual hardware 1-5 ? 1-bit input pin. ? cmos compatible input level. ? 7-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? 2-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? 8-bit i/o port. ? ttl input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. pin p5 1 p5 0 /ta out p5 2 /pwm 1 p5 3 /cntr 0 , p5 4 /cntr 1 p5 5 /int 0 , p5 6 /int 1 , p5 7 /int 2 p6 0 /an 0 C p6 7 /an 7 p7 0 /x cin, p7 1 /x cout p8 0 C p8 7 table 2 pin description (2) name input port p5 i/o port p5 i/o port p6 i/o port p7 i/o port p8 function except a port function ? timer a output pin ? pwm 1 output (timer output) pin ? external count i/o pins ? external interrupt input pins ? a-d conversion input pins ? sub-clock generating circuit i/o pins ? key input (key-on wake-up) interrupt input pins function pin description
38C3 group users manual hardware 1-6 m38C3 4 m 6 a xxx fp product rom/prom size 1 2 3 4 5 6 7 8 : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used. memory type m e : mask rom version : eprom or one time prom version ram size 0 1 2 3 4 5 6 7 : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes package type fp fs rom number omitted in one time prom version shipped in blank and eprom version. a : standard (note) m : m version : 80p6n-a package : 80d0 package 9 a b c : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes note : difference between standard and m version ?standard : ?m version : port p5 0 /ta out pin remains set to the input mode until the direction register is set to the output mode during reset and after reset. port p5 0 /ta out pin remains set to the output mode (??output) until the direction register is set to the input mode during reset and after reset. part numbering fig. 3 part numbering part numbering
38C3 group users manual hardware 1-7 rom size (bytes) 32k 28k 24k 20k 16k 12k 8k 4k 256 384 512 640 768 896 1024 192 ram size (bytes) 36k 40k 44k 48k under development m38C34m6a/m6m m38C37eca/ecm planning m38C33m4 products under development or planning : the development schedule and specification may be revised without notice. planning products may be stopped the development. m38C34m8 group expansion mitsubishi plans to expand the 38C3 group as follows. memory type support for mask rom, one time prom, and eprom versions memory size rom/prom size ................................................ 16 k to 48 k bytes ram size ............................................................. 512 to 1024 bytes memory expansion plan fig. 4 memory expansion plan currently supported products are listed below. as of december 1998 package 80p6n-a 80d0 80p6n-a 80d0 product name m38C34m6axxxfp m38C37ecaxxxfp m38C37ecafp m38C37ecafs m38C34m6mxxxfp m38C37ecmxxxfp m38C37ecmfp m38C37ecmfs (p) rom size (bytes) rom size for user in ( ) 24576 (24446) 49152 (49022) 24576 (24446) 49152 (49022) ram size (bytes) 640 1024 640 1024 table 3 support products mask rom version one time prom version one time prom version (blank) eprom version mask rom version one time prom version one time prom version (blank) eprom version remarks packages 80p6n-a ..................................... 0.8 mm-pitch plastic molded qfp 80d0 ........................ 0.8 mm-pitch ceramic lcc (eprom version) group expansion
38C3 group users manual hardware 1-8 functional description central processing unit (cpu) the 38C3 group uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine instruc- tions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the con- tents of the stack pointer. the high-order 8 bits of the stack address are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1, the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and pop- ping them from the stack are shown in figure 6. store registers other than those described in figure 6 with program when the user needs them during interrupts or subroutine calls. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit regis- ters pc h and pc l . it is used to indicate the address of the next in- struction to be executed. fig. 5 740 family cpu register structure functional description a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
38C3 group users manual hardware 1-9 table 4 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 6 register push and pop at interrupt generation and subroutine call functional description n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 e x e c u t e j s r o n - g o i n g r o u t i n e m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) e x e c u t e r t s ( p c l )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) s u b r o u t i n e p o p re t u r n a d d r e s s f r o m s t a c k p u s h r e t u r n a d d r e s s o n s t a c k m ( s )( p s ) e x e c u t e r t i ( p s )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 i n t e r r u p t s e r v i c e r o u t i n e p o p c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) ( s ) ( s ) 1 ( p c l )m ( s ) ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) p o p r e t u r n a d d r e s s f r o m s t a c k i f l a g i s s e t f r o m 0 t o 1 f e t c h t h e j u m p v e c t o r p u s h r e t u r n a d d r e s s o n s t a c k p u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k i n t e r r u p t r e q u e s t ( n o t e ) i n t e r r u p t d i s a b l e f l a g i s 0
38C3 group users manual hardware 1-10 [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch operations can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. ?bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. ?bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0, and cleared if the result is anything other than 0. ?bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1. ?bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0; decimal arithmetic is executed when it is 1. decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. ?bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0. when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1. ?bit 5: index x mode flag (t) when the t flag is 0, arithmetic operations are performed between accumulator and memory. when the t flag is 1, direct arithmetic operations and direct data transfers are enabled between memory locations. ?bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. ?bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 5 set and clear instructions of each bit of processor status register set instruction clear instruction c flag z flag i flag d flag b flag t flag v flag n flag sec clc _ _ sei cli sed cld _ _ set clt clv _ _ _ functional description
38C3 group users manual hardware 1-11 [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit and the internal system clock selection bit etc. the cpu mode register is allocated at address 003b 16 . fig. 7 structure of cpu mode register functional description not available processor mode bits b1 b0 0 0 : single-chip mode 0 1 : 1 0 : 1 1 : stack page selection bit 0 : ram in the zero page is used as stack area 1 : ram in page 1 is used as stack area not used (returns ??when read) (do not write ??to this bit.) port x c switch bit 0 : i/o port 1 : x cin , x cout main clock ( x in ? out ) stop bit 0 : operating 1 : stopped main clock division ratio selection bit 0 : f(x in )/2 (high-speed mode) 1 : f(x in )/8 (middle-speed mode) internal system clock selection bit 0 : x in -x out selected (middle-/high-speed mode) 1 : x cin -x cout selected (low-speed mode) cpu mode register (cpum (cm) : address 003b 16 ) b7 b0
38C3 group users manual hardware 1-12 memory special function register (sfr) area the special function register area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page access to this area with only 2 bytes is possible in the zero page addressing mode. special page access to this area with only 2 bytes is possible in the special page addressing mode. fig. 8 memory map diagram functional description 192 256 384 512 640 768 896 1024 00ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 ram area ram size (bytes) address xxxx 16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 f000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 f080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 rom area rom size (bytes) address yyyy 16 address zzzz 16 0058 16 0000 16 0040 16 0440 16 ff00 16 ffdc 16 fffe 16 ffff 16 xxxx 16 yyyy 16 zzzz 16 ram rom 0050 16 reserved area sfr area 1 not used interrupt vector area reserved rom area (128 bytes) zero page special page lcd display ram area reserved rom area rom corrective ram area 0100 16 (note 1) sfr area 2 (note 1) 0f00 16 0fff 16 note 1 : this is valid only in mask rom version.
38C3 group users manual hardware 1-13 fig. 9 memory map of special function register (sfr) functional description rom correct high-order address register 1 (note) rom correct high-order address register 2 (note) rom correct high-order address register 3 (note) rom correct high-order address register 4 (note) port p8 output selection register (p8sel) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) serial i/o control register 1 (siocon1) serial i/o control register 2 (siocon2) serial i/o register (sio) interrupt control register 2 (icon2) timer 6 pwm register (t6pwm) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) timer 1 (t1) timer 3 (t3) timer 5 (t5) timer 6 (t6) timer 2 (t2) timer 4 (t4) pull register a (pulla) pull register b (pullb) timer 12 mode register (t12m) timer 34 mode register (t34m) timer 56 mode register (t56m) segment output enable register (seg) lcd mode register (lm) a-d control register (adcon) a-d conversion register (low) (adl) port p8 (p8) port p8 direction register (p8d) f output control register (ckout) timer a register (low) (tal) timer a register (high) (tah) compare register (low) (conal) compare register (high) (conah) timer a mode register (tam) timer a control register (tacon) a-d conversion register (high) (adh) 0f0a 16 0f0b 16 0f0c 16 0f0d 16 0f0e 16 0f0f 16 0f10 16 0f11 16 rom correct enable register 1 (note) rom correct low-order address register 1 (note) rom correct high-order address register 5 (note) rom correct low-order address register 5 (note) rom correct high-order address register 6 (note) rom correct low-order address register 6 (note) rom correct high-order address register 7 (note) rom correct low-order address register 7 (note) rom correct high-order address register 8 (note) rom correct low-order address register 8 (note) 0f01 16 0f02 16 0f03 16 0f07 16 0f08 16 0f09 16 0f04 16 0f05 16 0f06 16 rom correct low-order address register 2 (note) rom correct low-order address register 3 (note) rom correct low-order address register 4 (note) note: this register is valid only in mask rom version.
38C3 group users manual hardware 1-14 i/o ports [direction registers (ports p2, p4, p5 0 , p5 2 Cp5 7 , and p6Cp8)] the i/o ports p2, p4, p5 0 , p5 2 Cp5 7 , and p6Cp8 have direction reg- isters which determine the input/output direction of each individual pin. each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin becomes an output pin. if data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are float- ing. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. [direction registers (ports p0 and p1)] ports p0 and p1 have direction registers which determine the input/ output direction of each individual port. each port in a direction register corresponds to one port, each port can be set to be input or output. when 0 is written to the bit 0 of a direction register, that port be- comes an input port. when 1 is written to that port, that port be- comes an output port. bits 1 to 7 of ports p0 and p1 direction regis- ters are not used. pull-up/pull-down control by setting the pull register a (address 0016 16 ) or the pull register b (address 0017 16 ), ports except for ports p3 and p5 1 can control either pull-down or pull-up (pins that are shared with the segment output pins for lcd are pull-down; all other pins are pull-up) with a program. however, the contents of pull register a and pull register b do not affect ports programmed as the output ports. port p8 output selection ports p8 0 to p8 7 can be switched to n-channel open-drain output by setting 1 to the port p8 output selection register. fig. 10 structure of pull register a and pull register b pin p0 0 /seg 8 C p0 7 /seg 15 p1 0 /seg 16 C p1 7 /seg 23 p2 0 /seg 0 C p2 7 /seg 7 p3 0 /seg 24 C p3 7 /seg 31 name port p0 port p1 port p2 port p3 input/output input/output, port unit input/output, port unit input/output, individual bits output, individual bits i/o format cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input cmos 3-state output cmos 3-state output non-port function lcd segment output lcd segment output lcd segment output lcd segment output related sfrs pull register a segment output enable reg- ister pull register a segment output enable reg- ister pull register a segment output enable reg- ister segment output enable reg- ister ref. no. (1) (2) table 6 list of i/o port function (1) fig. 11 structure of port p8 output selection register functional description p0 0 ?0 7 pull-down p1 0 ?1 7 pull-down p2 0 ?2 7 pull-down not used p7 0 , p7 1 pull-up p8 0 ?8 7 pull-up pull register a (pulla : address 0016 16 ) b7 b0 p4 0 ?4 3 pull-up p4 4 ?4 7 pull-up p5 0 , p5 2 , p5 3 pull-up p5 4 ?5 7 pull-up p6 0 ?6 3 pull-up p6 4 ?6 7 pull-up not used (return ??when read) 0 : disable 1 : enable pull register b (pullb : address 0017 16 ) b7 b0 note: the contents of pull register a and pull register b do not affect ports programmed as the output ports. not used (return ??when read) 0 : cmos output (in output mode) 1 : n-channel open-drain output (in output mode) port p8 output selection register (p8sel : address 0018 16 ) b7 b0
38C3 group users manual hardware 1-15 pin p4 0 /s clk2 p4 1 /t 1out p4 2 /t 3out p4 3 / f p4 4 /s in p4 5 /s out p4 6 /s clk1 p4 7 /s rdy p5 0 /ta out p5 1 p5 2 /pwm 1 p5 3 /cntr 0 p5 4 /cntr 1 p5 5 /int 0 p5 6 /int 1 p5 7 /int 2 p6 0 /an 0 C p6 7 /an 7 p7 0 /x cin p7 1 /x cout p8 0 C p8 7 com 0 C com 3 name port p4 port p5 port p6 port p7 port p8 common input/output input/output, individual bits input/output, individual bits input input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits output i/o format cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output lcd common output non-port function serial i/o function i/o timer output timer output f clock output serial i/o function i/o timer a output pwm output external count i/o external interrupt in- put a-d converter input sub-clock generating circuit i/o key input (key-on wake-up) interrupt in- put related sfrs serial i/o control registers 1, 2 pull register b timer 12 mode register pull register b timer 34 mode register pull register b f output control register pull register b serial i/o control registers 1, 2 pull register b timer a mode register timer a control register pull register b timer 56 mode register pull register b interrupt edge selection reg- ister pull register b interrupt edge selection reg- ister pull register b a-d control register pull register b cpu mode register pull register a interrupt control register 2 pull register a lcd mode register ref. no. (3) (4) (4) (5) (6) (7) (8) (9) (10) (11) (4) (12) (12) (13) (14) (15) (17) (16) table 7 list of i/o port function (2) notes 1: make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from v cc to v ss through the input-stage gate. 2: for details of how to use double function ports as function i/o ports, refer to the applicable sections. functional description
38C3 group users manual hardware 1-16 fig. 12 port block diagram (1) functional description (6)port p4 4 serial i/o input (1)ports p0, p1, p2 segment output enable bit pull-down control segment output enable bit direction register data bus port latch v l2 /v l3 v l1 /v ss (5)port p4 3 f f output control bit (2)port p3 segment output enable bit pull-down control segment output enable bit data bus port latch v l2 /v l3 v l1 /v ss (4)ports p4 1 , p4 2 , p5 2 timer 1 output selection bit timer 3 output selection bit timer 6 output selection bit direction register pull-up control timer 1 output timer 3 output timer 6 output (3)port p4 0 data bus serial i/o clock output serial i/o mode selection bit port latch direction register pull-up control p-channel output disable bit (note) note : port p0, p1 direction registers are only bit 0. data bus port latch port latch direction register data bus pull-up control data bus port latch direction register pull-up control
38C3 group users manual hardware 1-17 fig. 13 port block diagram (2) functional description (7)port p4 5 data bus serial i/o port selection bit serial i/o output p-channel output disable bit port latch direction register pull-up control (9)port p4 7 data bus serial i/o ready output port latch s rdy output enable bit direction register pull-up control (8)port p4 6 serial i/o clock output serial i/o clock input serial i/o mode selection bit port latch direction register pull-up control p-channel output disable bit (10)port p5 0 data bus port latch direction register pull-up control timer a output enable bit timer a output (12)ports p5 3 ?5 7 int 0 ?nt 2 interrupt input data bus direction register port latch pull-up control (11)port p5 1 data bus (note) note: the initial value of m version becomes ??(output). data bus cntr 0 ,cntr 1 interrupt input
38C3 group users manual hardware 1-18 fig. 14 port block diagram (3) functional description (14)port p7 0 direction register data bus port latch port selection ?pull-up control oscillator port p7 0 (15)port p7 1 direction register data bus port xc switch bit port latch port selection ?pull-up control sub-clock generating circuit input (16)com 0 ?om 3 v l3 v l2 v l1 the gate input signal of each transistor is controlled by the lcd duty ratio and the bias value. (13)port p6 analog input pin selection bit a-d conversion input data bus port latch direction register pull-up control (17)port p8 key input (key-on wake-up) interrupt input data bus direction register port latch pull-up control p-channel output disable bit port xc switch bit port xc switch bit
38C3 group users manual hardware 1-19 interrupts interrupts occur by sixteen sources: six external, nine internal, and one software. interrupt control each interrupt except the brk instruction interrupt have both an in- terrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. an interrupt occurs if the corresponding inter- rupt request and enable bits are 1 and the interrupt disable flag is 0. interrupt enable bits can be set or cleared by software. interrupt re- quest bits can be cleared by software, but cannot be set by software. the brk instruction interrupt and reset cannot be disabled with any flag or bit. the i flag disables all interrupts except the brk instruction interrupt and reset. if several interrupts requests occurs at the same time the interrupt with highest priority is accepted first. interrupt operation by acceptance of an interrupt, the following operations are automati- cally performed: 1. the processing being executed is stopped. 2. the contents of the program counter and processor status reg- ister are automatically pushed onto the stack. 3. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. the interrupt jump destination address is read from the vector table into the program counter. n notes on interrupts when the active edge of an external interrupt (int 0 C int 2 , cntr 0 or cntr 1 ) is set or an vector interrupt source where several interrupt source is assigned to the same vector address is switched, the cor- responding interrupt request bit may also be set. therefore, take fol- lowing sequence: (1) disable the interrupt. (2) change the active edge in interrupt edge selection register. (3) clear the set interrupt request bit to 0. (4) enable the interrupt. functional description
38C3 group users manual hardware 1-20 interrupt source reset (note 2) int 0 int 1 int 2 serial i/o timer a timer 1 timer 2 timer 3 timer 4 timer 5 timer 6 cntr 0 cntr 1 key input (key- on wake-up) a-d conversion brk instruction priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 vector addresses (note 1) high fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 interrupt request generating conditions at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at detection of either rising or falling edge of int 2 input at completion of serial i/o data transmit/re- ceive at timer a underflow at timer 1 underflow at timer 2 underflow at timer 3 underflow at timer 4 underflow at timer 5 underflow at timer 6 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at falling of port p8 (at input) input logical level and at completion of a-d conversion at brk instruction execution remarks non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o is selected stp release timer underflow external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (falling valid) valid when a-d conversion interrupt is selected non-maskable software interrupt low fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. table 8 interrupt vector addresses and priority functional description
38C3 group users manual hardware 1-21 fig. 15 interrupt control fig. 16 structure of interrupt-related registers functional description interrupt request bit interrupt enable bit interrupt disable flag (i) brk instruction reset interrupt request b7 b0 interrupt edge selection register int 0 interrupt edge selection bit int 1 interrupt edge selection bit int 2 interrupt edge selection bit not used (return ??when read) cntr 0 active edge switch bit cntr 1 active edge switch bit (intedge : address 003a 16 ) interrupt request register 1 int 0 interrupt request bit int 1 interrupt request bit int 2 interrupt request bit serial i/o interrupt request bit timer a interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit timer 3 interrupt request bit interrupt control register 1 int 0 interrupt enable bit int 1 interrupt enable bit int 2 interrupt enable bit serial i/o interrupt enable bit timer a interrupt enable bit timer 1 interrupt enable bit timer 2 interrupt enable bit timer 3 interrupt enable bit 0 : no interrupt request issued 1 : interrupt request issued (ireq1 : address 003c 16 ) (icon1 : address 003e 16 ) interrupt request register 2 timer 4 interrupt request bit timer 5 interrupt request bit timer 6 interrupt request bit cntr 0 interrupt request bit cntr 1 interrupt request bit key input interrupt request bit ad conversion interrupt request bit not used (returns ??when read) (ireq2 : address 003d 16 ) interrupt control register 2 timer 4 interrupt enable bit timer 5 interrupt enable bit timer 6 interrupt enable bit cntr 0 interrupt enable bit cntr 1 interrupt enable bit key input interrupt enable bit ad conversion interrupt enable bit not used (returns ??when read) (do not write ??to this bit) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 ) 0 : falling edge active 1 : rising edge active b7 b0 b7 b0 b7 b0 b7 b0 0 : falling edge active, rising edge count 1 : rising edge active, falling edge count
38C3 group users manual hardware 1-22 key input interrupt (key-on wake-up) a key input interrupt request is generated by applying l level to any pin of port p8 that have been set to input mode. in other words, it is generated when and of input level goes from 1 to 0. an example of using a key input interrupt is shown in figure 17, where an inter- rupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports p8 0 Cp8 3 . fig. 17 connection example when using key input interrupt and port p8 block diagram functional description ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] port p8 0 latch port p8 0 direction register = ? port p8 1 latch port p8 1 direction register = ? port p8 2 latch port p8 2 direction register = ? port p8 3 latch port p8 3 direction register = ? port p8 4 latch port p8 4 direction register = ? port p8 5 latch port p8 5 direction register = ? port p8 6 latch port p8 6 direction register = ? port p8 7 latch port p8 7 direction register = ? p8 0 input p8 1 input p8 2 input p8 3 input p8 4 output p8 5 output p8 6 output p8 7 output pull register a bit 5 = ? port p8 input reading circuit port pxx ??level output ] p-channel transistor for pull-up ] ] cmos output buffer key input interrupt request
38C3 group users manual hardware 1-23 timers 8-bit timer the 38C3 group has six built-in timers : timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. each timer has the 8-bit timer latch. all timers are down-counters. when the timer reaches 00 16 , an underflow occurs with the next count pulse. then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. when a timer underflows, the interrupt request bit corresponding to that timer is set to 1. the count can be stopped by setting the stop bit of each timer to 1. the system clock f can be set to either the high-speed mode or low- speed mode with the cpu mode register. at the same time, timer internal count source is switched to either f(x in ) or f(x cin ). l timer 1, timer 2 the count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. a rectangular waveform of timer 1 under- flow signal divided by 2 is output from the p4 1 /t1 out pin. the wave- form polarity changes each time timer 1 overflows. the active edge of the external clock cntr 0 can be switched with the bit 6 of the interrupt edge selection register. at reset or when executing the stp instruction, all bits of the timer 12 mode register are cleared to 0, timer 1 is set to ff 16 , and timer 2 is set to 01 16 . l timer 3, timer 4 the count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. a rectangular waveform of timer 3 under- flow signal divided by 2 is output from the p4 2 /t3 out pin. the wave- form polarity changes each time timer 3 overflows. the active edge of the external clock cntr 1 can be switched with the bit 7 of the interrupt edge selection register. l timer 5, timer 6 the count sources of timer 5 and timer 6 can be selected by setting the timer 56 mode register. a rectangular waveform of timer 6 under- flow signal divided by 2 can be output from the p5 2 /pwm 1 pin. l timer 6 pwm 1 mode timer 6 can output a rectangular waveform with h duty cycle n/ (n+m) from the p5 2 /pwm 1 pin by setting the timer 56 mode register (refer to figure 20). the n is the value set in timer 6 latch (address 0025 16 ) and m is the value in the timer 6 pwm register (address 0027 16 ). if n is 0, the pwm output is l, if m is 0, the pwm output is h (n = 0 is prior than m = 0). in the pwm mode, interrupts occur at the rising edge of the pwm output. fig. 18 structure of timer related register functional description timer 12 mode register (t12m: address 0028 16 ) timer 1 count stop bit 0 : count operation 1 : count stop timer 2 count stop bit 0 : count operation 1 : count stop timer 1 count source selection bits 00 : f(x in )/16 or f(x cin )/16 01 : f(x cin ) 10 : f(x in )/32 or f(x cin )/32 11 : f(x in )/128 or f(x cin )/128 timer 2 count source selection bits 00 : underflow of timer 1 01 : f(x cin ) 10 : external count input cntr 0 11 : not available timer 1 output selection bit (p4 1 ) 0 : i/o port 1 : timer 1 output not used (returns ??when read) (do not write ??to this bit.) timer 34 mode register (t34m: address 0029 16 ) timer 3 count stop bit 0 : count operation 1 : count stop timer 4 count stop bit 0 : count operation 1 : count stop timer 3 count source selection bits 00 : f(x in )/16 or f(x cin )/16 01 : underflow of timer 2 10 : f(x in )/32 or f(x cin )/32 11 : f(x in )/128 or f(x cin )/128 timer 4 count source selection bits 00 : f(x in )/16 or f(x cin )/16 01 : underflow of timer 3 10 : external count input cntr 1 11 : not available timer 3 output selection bit (p4 2 ) 0 : i/o port 1 : timer 3 output not used (returns ??when read) (do not write ??to this bit.) timer 56 mode register (t56m: address 002a 16 ) timer 5 count stop bit 0 : count operation 1 : count stop timer 6 count stop bit 0 : count operation 1 : count stop timer 5 count source selection bit 0 : f(x in )/16 or f(x cin )/16 1 : underflow of timer 4 timer 6 operation mode selection bit 0 : timer mode 1 : pwm mode timer 6 count source selection bits 00 : f(x in )/16 or f(x cin )/16 01 : underflow of timer 5 10 : underflow of timer 4 11 : not available timer 6 (pwm) output selection bit (p5 2 ) 0 : i/o port 1 : timer 6 output not used (returns ??when read) (do not write ??to this bit.) b7 b0 b7 b0 b7 b0
38C3 group users manual hardware 1-24 fig. 19 block diagram of timer functional description x in p4 2 /t3 out 1/2 x cin ? ? ?1 ?0 ?1 ?0 ?1 ?0 ?0 ? ? ?1 ?0 ?0 ?0 ?1 p4 1 /t1 out 1/2 p5 3 /cntr 0 ?0 1/2 pwm p5 2 /pwm 1 ? ? p5 4 /cntr 1 1/2 ?1 ?1 ?0 ?0 internal system clock selection bit timer 1 count source selection bit timer 1 interrupt request data bus timer 1 latch (8) timer 1 (8) ff 16 timer 1 count stop bit reset stp instruction p4 1 latch timer 1 output selection bit p4 1 direction register timer 2 count source selection bit timer 2 latch (8) timer 2 (8) timer 2 count stop bit 01 16 timer 3 count source selection bit timer 3 latch (8) timer 3 (8) timer 3 count stop bit timer 2 interrupt request timer 3 interrupt request p4 2 latch rising/falling active edge switch timer 3 output selection bit p4 2 direction register timer 4 count source selection bit timer 4 latch (8) timer 4 (8) timer 4 count stop bit rising/falling active edge switch timer 4 interrupt request timer 5 count source selection bit timer 5 latch (8) timer 5 (8) timer 5 count stop bit timer 5 interrupt request p5 2 latch timer 6 output selection bit p5 2 direction register timer 6 count source selection bit timer 6 latch (8) timer 6 (8) timer 6 count stop bit timer 6 pwm register (8) timer 6 operation mode selection bit timer 6 interrupt request 1/16 1/128 1/32 cntr 1 interrupt request cntr 0 interrupt request
38C3 group users manual hardware 1-25 fig. 20 timing chart of timer 6 pwm 1 mode 16-bit timer timer a is a 16-bit timer that can be selected in one of four modes by the timer a mode register and the timer a control register. l timer a the timer a operates as down-count. when the timer contents reach 0000 16 , an underflow occurs at the next count pulse and the timer latch contents are reloaded. after that, the timer continues count- down. when the timer underflows, the interrupt request bit correspond- ing to the timer a is set to 1. (1) timer mode the count source can be selected by setting the timer a mode regis- ter. (2) pulse output mode pulses of which polarity is inverted each time the timer underflows are output from the ta out pin. except for that, this mode operates just as in the timer mode. when using this mode, set port p5 0 sharing the ta out pin to output mode. (3) igbt output mode after dummy output from the ta out pin, count starts with the int 0 pin input as a trigger. when the trigger is detected or the timer a underflows, h is output from the the ta out pin. when the count value corresponds with the compare register value, the ta out output becomes l. when the int 0 signal becomes h, the ta out output is forced to become l. after noise is cleared by noise filters, judging continuous 4-time same levels with sampling clocks to be signals, the int 0 signal can use 4 types of delay time by a delay circuit. when using this mode, set port p5 5 sharing the int 0 pin to input mode and set port p5 0 sharing the ta out pin to output mode. it is possible to force the timer a output to be l using pins int 1 and int 2 by the timer a control register. (4) pwm mode igbt dummy output, an external trigger with the int 0 pin and output control with pins int 1 and int 2 are not used. except for those, this mode operates just as in the igbt output mode. the period of pwm waveform is specified by the timer a set value. the h term is specified by the compare register set value. when using this mode, set port p5 0 sharing the ta out pin to output mode. functional description t s timer 6 count source n 5 ts m 5 ts (n+m) 5 ts note: pwm waveform (duty : n/(n+m) and period : (n+m) 5 ts) is output. n: setting value of timer 6 m: setting value of timer 6 pwm register ts: period of timer 6 count source timer 6 interrupt request timer 6 interrupt request timer 6 pwm mode
38C3 group users manual hardware 1-26 fig. 21 block diagram of timer a fig. 22 structure of timer a related registers functional description timer a underflow interrupt request timer a (high-order) (8) timer a (low-order) (8) timer a (high-order) latch (8) timer a (low-order) latch (8) timer a operating mode bits timer a write control bit data bus x in 1/1 1/2 1/4 timer a count source selection bits 1/8 output selection bit p5 0 latch timer a output active edge switch bit p5 0 /ta out p5 0 direction register s ? ? q q d compare register (high-order) (8) compare register (low-order) (8) 1/2 1/4 divider noise filter sampling clock selection bit int 0 0 m s delay circuit external trigger delay time selection bits 4/f(x in ) timer a output control bit 1 timer a output control bit 2 ? ? ? ? ?0 r timer a start signal int 1 int 2 00 01 10 11 internal trigger start ?0? ?1? ?1 ?0 match ?0? ?1? ?1 timer a operating mode bits timer a output active edge switch bit s ? ? q q t s pulse output mode igbt output mode pwm mode 8/f(x in ) 16/f(x in ) note: the initial value of m version becomes ??(output). (note) noise filter (4-time same levels judgement) divider b7 b0 timer a control register (tacon : address 0031 16 ) noise filter sampling clock selection bit 0 : f(x in )/2 1 : f(x in )/4 external trigger delay time selection bits 0 0 : no delay 0 1 : ( 4/f(x in )) m s 1 0 : ( 8/f(x in )) m s 1 1 : (16/f(x in )) m s timer a output control bit 1 (p5 6 ) 0 : not used 1 : int1 interrupt used timer a output control bit 2 (p5 7 ) 0 : not used 1 : int2 interrupt used not used (returns 0 when read) b7 b0 timer a mode register (tam : address 0030 16 ) timer a operating mode bits 00 : timer mode 01 : pulse output mode 10 : igbt output mode 11 : pwm mode timer a write control bit 0 : write data to both timer latch and timer 1 : write data to timer latch onl y timer a count source selection bits 0 0 : f(x in ) 0 1 : f(x in )/2 1 0 : f(x in )/4 1 1 : f(x in )/8 timer a output active edge switch bit 0 : output starts with l level 1 : output starts with h level timer a count stop bit 0 : count operating 1 : count stop timer a output selection bit (p5 0 ) 0 : i/o port 1 : timer a output
38C3 group users manual hardware 1-27 fig. 23 timing chart of timer a pwm, igbt output modes n notes on timer a (1) write order to timer a ? in the timer and pulse output modes, write to the timer a register (low-order) first and to the timer a register (high-order) next. do not write to only one side. ? in the igbt and pwm modes, write to the registers as follows: the compare register (high- and low-order) the timer a register (low-order) the timer a register (high-order). it is possible to use whichever order to write to the compare register (high- and low-order). however, write both the compare register and the timer a register at the same time. (2) read order to timer a ? in all modes, read to the timer a register (high-order) first and to the timer a register (low-order) next. read order to the compare regis- ter is not specified. ? if reading to the timer a register during write operation or writing to it during read operation, normal operation will not be performed. (3) write to timer a ? when writing a value to the timer a address to write to the latch only, the value is set into the reload latch and the timer is updated at the next underflow. normally, when writing a value to the timer a address, the value is set into the timer and the timer latch at the same time, because they are written at the same time. when writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, an ex- pected value may be set in the high-order counter. ? do not switch the timer count source during timer count operation. stop the timer count before switching it. additionally, when perform- ing write to the latch and the timer at the same time, the timer count value may change large. (4) set of timer a mode register set the write control bit to 1 (write to the latch only) when setting the igbt and pwm modes. output waveform simultaneously reflects the contents of both regis- ters at the next underflow after writing to the timer a register (high- order). (5) output control function of timer a when using the output control function (int 1 and int 2 ) in the igbt mode, set the levels of int 1 and int 2 to h in the falling edge active or to l in the rising edge active before switching to the igbt mode. functional description t s timer a count source timer a pwm mode igbt output mode (n-m+1) 5 ts m 5 ts (n+1) 5 ts note: pwm waveform (duty : (n-m+1)/(n+1) and period : (n+1) 5 ts) is output. n : setting value of timer a m : setting value of compare register ts : period of timer a count source
38C3 group users manual hardware 1-28 serial i/o the 38C3 group has a built-in 8-bit clock synchronous serial i/o. the i/o pins of serial i/o also operate as i/o port p4, and their function is selected by the serial i/o control register 1 (address 0019 16 ). fig. 24 block diagram of serial i/o functional description data bus x cin x in serial i/o interrupt request p4 6 latch p4 5 latch serial i/o port selection bit p4 7 latch serial i/o counter (3) serial i/o shift register (8) synchronous circuit internal system clock selection bit serial i/o port selection bit ? ? s clk s rdy output selection bit external clock synchronous clock selection bit divider 1/8 1/16 1/32 1/64 1/128 1/256 internal synchronous clock selection bits p4 6 /s clk1 p4 5 /s out p4 4 /s in s rdy p4 7 /s rdy p4 0 latch serial i/o port selection bit p4 0 /s clk2 ? ? ? ? ? ? ? ? ? ? [serial i/o control registers 1, 2 (siocon1, siocon2)] 0019 16 , 001a 16 each of the serial i/o control registers 1, 2 contains 8 bits that select various control parameters of serial i/o. l operation in serial i/o mode either an internal clock or an external clock can be selected as the synchronous clock for serial i/o transfer. a dedicated divider is built- in as the internal clock, giving a choice of six clocks. when internal clock is selected, serial i/o starts to transfer by a write signal to the serial i/o register (address 001b 16 ). after 8 bits have been transferred, the s out pin goes to high impedance. when external clock is selected, the clock must be controlled exter- nally because the contents of the serial i/o register continue to shift while the transfer clock is input. in this case, the s out pin does not go to high impedance at the completion of data transfer. the interrupt request bit is set at the end of the transfer of 8 bits, regardless of whether the internal or external clock is selected. when selecting internal clock and setting 1 to siocon2 0 , the p4 0 pin can be also used as synchronous clock output pin sclk 2 . at this time, the sclk 1 pin can be used as i/o port. table 9 function of p4 6 /s clk1 and p4 0 /s clk2 siocon1 6 1 siocon1 3 1 siocon2 0 0 1 p4 6 /sclk 1 sclk 1 p4 6 p4 0 /sclk 2 p4 0 sclk 2 siocon1 3 : serial i/o port selection bit siocon1 6 : synchronous clock selection bit siocon2 0 : synchronous clock output pin selection bit
38C3 group users manual hardware 1-29 fig. 25 structure of serial i/o control register fig. 26 serial i/o timing (for lsb first) functional description serial i/o control register 1 (siocon1 : address 0019 16 ) internal synchronous clock selection bits b2 b1 b0 0 0 0 : f(x in )/8 or f(x cin )/8 0 0 1 : f(x in )/16 or f(x cin )/16 0 1 0 : f(x in )32 or f(x cin )/32 0 1 1 : f(x in )/64 or f(x cin )/64 1 1 0 : f(x in )/128 or f(x cin )/128 1 1 1 : f(x in )/256 or f(x cin )/256 serial i/o port selection bit (p4 0 , p4 5 , p4 6 ) 0 : i/o port 1 : s out , s clk1 , s clk2 signal pin s rdy output selection bit (p4 7 ) 0 : i/o port 1 : s rdy signal pin transfer direction selection bit 0 : lsb first 1 : msb first synchronous clock selection bit 0 : external clock 1 : internal clock p-channel output disable bit (p4 0 , p4 5 , p4 6 ) 0 : cmos output (in output mode) 1 : n-channel open-drain (in output mode) b7 b0 serial i/o control register 2 (siocon2: address 001a 16 ) synchronous clock output pin selection bit 0 : s clk1 1 : s clk2 not used (returns ??when read) b7 b0 interrupt request bit set synchronous clock transfer clock serial i/o register write signal serial i/o output s out serial i/o input s in receive enable signal s rdy d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 note: when internal clock is selected, the s out pin goes to high impedance after transfer ends. (note)
38C3 group users manual hardware 1-30 a-d converter the 38C3 group has a 10-bit a-d converter. the a-d converter per- forms successive approximation conversion. [a-d conversion register (ad)] 0033 16 , 0034 16 one of these registers is a high-order register, and the other is a low- order register. the high-order 8 bits of a conversion result is stored in the a-d conversion register (high-order) (address 0034 16 ), and the low-order 2 bits of the same result are stored in bit 7 and bit 6 of the a-d conversion register (low-order) (address 0033 16 ). during a-d conversion, do not read these registers. [a-d control register (adcon)] 0032 16 this register controls a-d converter. bits 2 to 0 are analog input pin selection bits. bit 4 is an ad conversion completion bit and 0 during a-d conversion. this bit is set to 1 upon completion of a-d conver- sion. a-d conversion is started by setting 0 in this bit. [comparison voltage generator] the comparison voltage generator divides the voltage between av ss and v ref , and outputs the divided voltages. [channel selector] the channel selector selects one of the input ports p6 7 /an 7 Cp6 0 / an 0 and inputs it to the comparator. [comparator and control circuit] the comparator and control circuit compares an analog input volt- age with the comparison voltage and stores the result in the a-d conversion register. when an a-d conversion is completed, the con- trol circuit sets the ad conversion completion bit and the ad conver- sion interrupt request bit to 1. fig. 28 block diagram of a-d converter note that the comparator is constructed linked to a capacitor, so set f(x in ) to at least 500 khz during a-d conversion. use a cpu system clock dividing the main clock x in as the internal system clock. fig. 27 structure of a-d control register functional description ad conversion result stored bits a-d conversion register (high-order) (adh: address 0034 16 ) b7 b0 analog input pin selection bits 000: p6 0 /an 0 001: p6 1 /an 1 010: p6 2 /an 2 011: p6 3 /an 3 100: p6 4 /an 4 101: p6 5 /an 5 110: p6 6 /an 6 111: p6 7 /an 7 a-d control register (adcon: address 0032 16 ) ad conversion completion bit 0: conversion in progress 1: conversion completed not used (returns ??when read) b7 b0 not used (returns ??when read) ad conversion result stored bits a-d conversion register (low-order) (adl: address 0033 16 ) b7 b0 not used (returns ??when read) data bus av ss a-d interrupt request b7 b0 3 p6 0 /an 0 p6 1 /an 1 p6 2 /an 2 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 p6 7 /an 7 a-d control register channel selector comparator a-d control circuit a-d conversion register (h) a-d conversion register (l) (address 0034 16 ) (address 0033 16 ) resistor ladder v ref
38C3 group users manual hardware 1-31 lcd drive control circuit the 38C3 group has the built-in liquid crystal display (lcd) drive control circuit consisting of the following. ? lcd display ram ? segment output enable register ? lcd mode register ? selector ? timing controller ? common driver ? segment driver ? bias control circuit a maximum of 32 segment output pins and 4 common output pins can be used. up to 128 pixels can be controlled for a lcd display. when the lcd enable bit is set to 1 after data is set in the lcd mode register, the fig. 29 structure of lcd related registers segment output enable register, and the lcd display ram, the lcd drive control circuit starts reading the display data automatically, per- forms the bias control and the duty ratio control, and displays the data on the lcd panel. table 10 maximum number of display pixels at each duty ratio duty ratio 1 2 3 4 maximum number of display pixels 32 dots or 8 segment lcd 4 digits 64 dots or 8 segment lcd 8 digits 96 dots or 8 segment lcd 12 digits 128 dots or 8 segment lcd 16 digits functional description segment output enable bit 0 0 : i/o ports p2 0 ?2 3 1 : segment output seg 0 ?eg 3 segment output enable bit 1 0 : i/o ports p2 4 ?2 7 1 : segment output seg 4 ?eg 7 segment output enable bit 2 0 : i/o ports p0 0 ?0 3 1 : segment output seg 8 ?eg 11 segment output enable bit 3 0 : i/o ports p0 4 ?0 7 1 : segment output seg 12 ?eg 15 segment output enable bit 4 0 : i/o ports p1 0 ?1 3 1 : segment output seg 16 ?eg 19 segment output enable bit 5 0 : i/o ports p1 4 ?1 7 1 : segment output seg 20 ?eg 23 segment output enable bit 6 0 : output ports p3 0 ?3 3 1 : segment output seg 24 ?eg 27 segment output enable bit 7 0 : output ports p3 4 ?3 7 1 : segment output seg 28 ?eg 31 segment output enable register (seg : address 0038 16 ) b7 b0 lcd mode register (lm : address 0039 16 ) duty ratio selection bits 0 0 : 1 (use com 0 ) 0 1 : 2 (use com 0 ,com 1 ) 1 0 : 3 (use com 0 ?om 2 ) 1 1 : 4 (use com 0 ?om 3 ) bias control bit 0 : 1/3 bias 1 : 1/2 bias lcd enable bit 0 : lcd off 1 : lcd on not used (returns ??when read) (do not write ??to this bit.) lcd circuit divider division ratio selection bits 0 0 : clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input lcdck count source selection bit (note) 0 : f(x cin )/32 1 : f(x in )/8192 (f(x cin )/8192 in low-speed mode) note : lcdck is a clock for a lcd timing controller. b7 b0
38C3 group users manual hardware 1-32 fig. 30 block diagram of lcd controller/driver functional description data bus timing controller lcd divider f(x cin )/32 f(x in )/8192 (f(x cin )/8192 in low-speed mode) common driver bias control com 0 com 1 com 2 com 3 v ss v l1 v l2 v l3 p2 3 /seg 3 p2 2 /seg 2 p2 1 /seg 1 p2 0 /seg 0 address 0040 16 address 0041 16 ? ? lcdck lcdck count source selection bit lcd circuit divider division ratio selection bits bias control bit lcd enable bit duty ratio selection bits 2 2 selector selector selector selector selector selector lcd display ram address 004f 16 p3 6 /seg 30 p0 4 /seg 12 p3 7 /seg 31 segment driver segment driver segment driver segment driver segment driver segment driver common driver common driver common driver
38C3 group users manual hardware 1-33 duty ratio 1 2 3 4 voltage value v l3 =v lcd v l2 =2/3 v lcd v l1 =1/3 v lcd v l3 =v lcd v l2 =v l1 =1/2 v lcd v l3 =v lcd v l2 =v l1 =v ss bias control and applied voltage to lcd power input pins to the lcd power input pins (v l1 Cv l3 ), apply the voltage value shown in table 11 according to the bias value. select a bias value by the bias control bit (bit 2 of the lcd mode register). common pin and duty ratio control the common pins (com 0 Ccom 3 ) to be used are determined by duty ratio. select duty ratio by the duty ratio selection bits (bits 0 and 1 of the lcd mode register). when selecting 1-duty ratio, 1/1 bias can be used. fig. 31 example of circuit at each bias table 11 bias control and applied voltage to v l1 Cv l3 bias value 1/3 bias 1/2 bias 1/1 bias (1-duty ratio) note 1: v lcd is the maximum value of supplied voltage for the lcd panel. table 12 duty ratio control and common pins used notes 1: com 1 , com 2 , and com 3 are open. 2: com 2 and com 3 are open. 3: com 3 is open. common pins used com 0 (note 1) com 0 , com 1 (note 2) com 0 Ccom 2 (note 3) com 0 Ccom 3 bit 1 0 0 1 1 bit 0 0 1 0 1 duty ratio selection bit functional description r4 r5 r4 = r5 contrast control 1/2 bias v l3 contrast control r1 r2 r3 r1 = r2 = r3 1/3 bias r6 contrast control 1/1 bias v l1 v l2 v l3 v l1 v l2 v l3 v l1 v l2
38C3 group users manual hardware 1-34 lcd display ram address 0040 16 to 004f 16 is the designated ram for the lcd dis- play. when 1 are written to these addresses, the corresponding seg- ments of the lcd display panel are turned on. lcd drive timing the lcdck timing frequency (lcd drive timing) is generated inter- nally and the frame frequency can be determined with the following equation; (frequency of count source for lcdck) (divider division ratio for lcd) f(lcdck)= f(lcdck) duty ratio frame frequency= fig. 32 lcd display ram map functional description bit address 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 seg 13 seg 15 seg 17 seg 19 seg 21 seg 23 seg 25 seg 27 seg 29 seg 31 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 seg 1 seg 3 seg 5 seg 7 seg 9 seg 11 76543210 seg 12 seg 14 seg 16 seg 18 seg 20 seg 22 seg 24 seg 26 seg 28 seg 30 seg 0 seg 2 seg 4 seg 6 seg 8 seg 10 com 3 com 0 com 2 com 1 com 0 com 3 com 2 com 1
38C3 group users manual hardware 1-35 fig. 33 lcd drive waveform (1/2 bias) functional description internal signal lcdck timing 1/4 duty voltage level v l3 v l2 =v l1 v ss v l3 v ss com 0 com 1 com 2 com 3 seg 0 off on off on com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 1/3 duty v l3 v l2 =v l1 v ss v l3 v ss off on on off on off 1/2 duty com 0 com 1 com 2 seg 0 com 0 com 1 seg 0 v l3 v l2 =v l1 v ss v l3 v ss off on off on off on off on com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 1 com 0 com 1 com 0 com 1 com 0 1/1 duty (1/1 bias) com 0 seg 0 v l3 v l2 =v l1 =v ss v l3 v ss on off
38C3 group users manual hardware 1-36 fig. 34 lcd drive waveform (1/3 bias) functional description internal signal lcdck timing 1/4 duty voltage level v l3 v ss com 0 com 1 com 2 com 3 seg 0 off on off on com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 1/3 duty off on on off on off 1/2 duty com 0 com 1 com 2 seg 0 com 0 com 1 seg 0 off on off on off on off on v l3 v l2 v ss v l1 v l3 v l2 v ss v l1 v l3 v ss v l3 v l2 v ss v l1 v l3 v ss com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 1 com 0 com 1 com 0 com 1 com 0
38C3 group users manual hardware 1-37 f clock output function the internal system clock f can be output from port p4 3 by setting the f output control register. set 1 to bit 3 of the port p4 direction register when outputting f clock. fig. 35 structure of f output control register functional description f output control bit 0 : port function 1 : f clock output f output control register (ckout : address 002b 16 ) b7 b0 not used (return ??when read)
38C3 group users manual hardware 1-38 rom correction function (mask rom version only) the 38C3 group has the rom correction function correcting data at the arbitrary addresses in the rom area. [rom correct address register] 0f02 16 C 0f11 16 this is the register to store the address performing rom correction. there are two types of registers to correct up to 8 addresses: one is the register to store the high-order address and the other is to store the low-order address. [rom correct enable register 1 (rc1)] 0f01 16 this is the register to enable the rom correction function. when set- ting the bit corresponding to the rom correction address to 1, the rom correction function is enabled. it becomes invalid to the addresses of which corresponding bit is 0. all bits are 0 at the initial state. [rom correct data] this is the register to store a correct data for the address specified by the rom correct address register. n notes on rom correction function 1. to use the rom correction function, transfer data to each rom correct data register in the initial setting. 2. do not specify the same addresses in the rom correct address register. fig. 36 structure of rom correct address register fig. 37 structure of rom correct data fig. 38 structure of rom correct enable register 1 functional description 0f02 16 0f03 16 0f04 16 0f05 16 0f06 16 0f07 16 0f08 16 0f09 16 0f0a 16 0f0b 16 0f0c 16 0f0d 16 0f0e 16 0f0f 16 0f10 16 0f11 16 rom correct high-order address register 1 rom correct low-order address register 1 rom correct high-order address register 2 rom correct low-order address register 2 rom correct high-order address register 3 rom correct low-order address register 3 rom correct high-order address register 4 rom correct low-order address register 4 rom correct high-order address register 5 rom correct low-order address register 5 rom correct high-order address register 6 rom correct low-order address register 6 rom correct high-order address register 7 rom correct low-order address register 7 rom correct high-order address register 8 rom correct low-order address register 8 rom correct data 1 rom correct data 2 rom correct data 3 rom correct data 4 rom correct data 5 rom correct data 6 rom correct data 7 rom correct data 8 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 rom correct enable register 1(address 0f01 16 ) rc1 b7 b0 rom correct address 1 enable bit 0 : disabled 1 : enabled rom correct address 2 enable bit 0 : disabled 1 : enabled rom correct address 3 enable bit 0 : disabled 1 : enabled rom correct address 4 enable bit 0 : disabled 1 : enabled rom correct address 5 enable bit 0 : disabled 1 : enabled rom correct address 6 enable bit 0 : disabled 1 : enabled rom correct address 7 enable bit 0 : disabled 1 : enabled rom correct address 8 enable bit 0 : disabled 1 : enabled
38C3 group users manual hardware 1-39 reset circuit ______ to reset the microcomputer, reset pin should be held at an l level ______ for 2 m s or more. then the reset pin is returned to an h level (the power source voltage should be between 2.5 v and 5.5 v (m version: 2.2 ] v to 5.5 v), and the oscillation should be stable), reset is re- leased. after the reset is completed, the program starts from the ad- dress contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.5 v for v cc of 2.5 v (m version: less than 0.44 v for vcc of 2.2 ] v) when switching to the high-speed mode, a power source voltage must be between 4.0 v and 5.5 v. fig. 40 reset sequence fig. 39 reset circuit example functional description (note) 0.2v cc 0v 0v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage ; vcc=2.5 v (m version is 2.2 v.) reset internal reset address data sync f x in fffc fffd ad h, ad l ad l ???? x in : about 8000 cycles note reset address from vector table 1: the frequency relation of f(x in ) and f( f ) is f(x in ) = 8 ?f( f ). 2: the question marks (?) indicate an undefined state that depends on the previous state. ad h
38C3 group users manual hardware 1-40 fig. 41 internal status at reset functional description 00 16 00 16 ff 16 ff 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0031 16 x: not fixed since the initial values for other than above mentioned registers and ram contents are indefinite at reset, they must be set. in the m version, bit 0 of the port p5 direction register becomes ?. address register contents address register contents 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 ff 16 ff 16 00 16 00 16 0000 16 0001 16 0002 16 0004 16 0005 16 0006 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0016 16 0017 16 0018 16 0019 16 001a 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0028 16 timer 4 port p0 port p0 direction register port p1 port p2 port p2 direction register port p3 port p4 port p4 direction register port p5 port p5 direction register port p6 port p6 direction register port p7 port p7 direction register port p8 port p8 direction register port p8 output selection register serial i/o control register 1 serial i/o control register 2 timer 1 timer 2 timer 3 timer 5 timer 6 timer 12 mode register (1) (2) (3) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) 00 16 0029 16 timer 34 mode register (30) (32) (33) (34) (35) (36) (37) (38) timer 56 mode register f output control register timer a register (low-order) timer a register (high-order) compare register (low-order) compare register (high-order) timer a mode register timer a control register 10 16 00 16 00 16 00 16 00 16 0032 16 0038 16 003b 16 003c 16 003d 16 003e 16 003f 16 (39) (40) (43) (44) (45) (46) (47) a-d control register segment output enable register cpu mode register interrupt request register 1 interrupt request register 2 interrupt control register 1 interrupt control register 2 00 16 00 16 00 16 00 16 pull register a pull register b (31) fffc 16 contents (ps) (pc h ) (pc l ) (65) (66) program counter processor status register fffd 16 contents 1 5 0030 16 00 16 00 16 0f 16 00 16 00 16 00 16 00 16 ff 16 01 16 ff 16 010010 0 0 00 16 5 5 5 55 5 00 16 0003 16 port p1 direction register (4) 003a 16 (41) (42) lcd mode register interrupt edge selection register 00 16 00 16 0039 16 00 16 ff 16 ff 16 0f01 16 0f02 16 0f03 16 0f04 16 (48) (49) (50) (51) rom correct enable register 1 rom correct high-order address register 1 rom correct low-order address register 1 rom correct high-order address register 2 ff 16 ff 16 0f05 16 0f06 16 0f07 16 (52) (53) (54) rom correct low-order address register 2 ff 16 ff 16 rom correct high-order address register 3 rom correct low-order address register 3 ff 16 ff 16 0f08 16 0f09 16 0f0a 16 (55) (56) (57) rom correct high-order address register 4 rom correct low-order address register 4 rom correct high-order address register 5 ff 16 ff 16 0f0b 16 0f0c 16 0f0d 16 (58) (59) (60) rom correct low-order address register 5 ff 16 ff 16 rom correct high-order address register 6 rom correct low-order address register 6 ff 16 ff 16 0f0e 16 0f0f 16 0f10 16 (61) (62) (63) rom correct high-order address register 7 rom correct low-order address register 7 rom correct high-order address register 8 ff 16 ff 16 0f11 16 (64) rom correct low-order address register 8
38C3 group users manual hardware 1-41 clock generating circuit the 38C3 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturer's recommended values. no external re- sistor is needed between x in and x out since a feedback resistor exists on-chip. however, an external feedback resistor is needed be- tween x cin and x cout . immediately after power on, only the x in oscillation circuit starts os- cillating, and x cin and x cout pins function as i/o ports. frequency control (1) middle-speed mode the internal system clock is the frequency of x in divided by 8. after reset, this mode is selected. (2) high-speed mode the internal system clock is the frequency of x in divided by 2. (3) low-speed mode the internal system clock is the frequency of x cin divided by 2. n notes on clock generating circuit if you switch the mode between middle/high-speed and low-speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. when switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(x in ) > 3f(x cin ). oscillation control (1) stop mode if the stp instruction is executed, the internal system clock stops at an h level, and x in and x cin oscillators stop. timer 1 is set to ff 16 and timer 2 is set to 01 16 . either x in divided by 16 or x cin divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. the bits of the timer 12 mode register are cleared to 0. set the interrupt enable bits of the timer 1 and timer 2 to disabled (0) before execut- ing the stp instruction. oscillator restarts when an external interrupt is received, but the internal system clock is not supplied to the cpu until timer 2 underflows. this allows time for the clock circuit oscilla- tion to stabilize. (2) wait mode if the wit instruction is executed, the internal system clock stops at an h level. the states of x in and x cin are the same as the state before executing the wit instruction. the internal system clock re- starts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. fig. 42 ceramic resonator circuit fig. 43 external clock input circuit functional description x cin x cout x in x out c in c out c cin c cout rf rd x in x out external oscillation circuit v cc v ss open x cin x cout c cin c cout rf rd
38C3 group users manual hardware 1-42 fig. 44 clock generating circuit block diagram functional description wit instruction stp instruction timing f (internal system clock) s r q stp instruction s r q main clock stop bit s r q timer 2 timer 1 1/2 1/4 x in x out interrupt request reset port x c switch bit ? ? low-speed mode middle-/high-speed mode internal system clock selection bit (note) middle-speed mode high-speed mode or low-speed mode note : when using the low-speed mode, set the port x c switch bit to ??. main clock division ratio selection bit ? ? interrupt disable flag i 1/2 x cout x cin ? ?
38C3 group users manual hardware 1-43 fig. 45 state transitions of system clock functional description cm 4 : port xc switch bit 0: i/o port function 1: x cin -x cout oscillating function cm 5 : main clock (x in - x out ) stop bit 0: oscillating 1: stopped cm 6 : main clock division ratio selection bit 0: f(x in )/2(high-speed mode) 1: f(x in )/8 (middle-speed mode) cm 7 : internal system clock selection bit 0: x in ? out selected (middle-/high-speed mode) 1: x cin ? cout selected (low-speed mode) reset cm 4 cm 7 cm 4 cm 5 cm 6 cm 6 cpu mode register (cpum : address 003b 16 ) b7 b4 cm 7 cm 5 cm 6 cm 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cm 4 ? ? cm 4 ? ? ? ? cm 5 ? ? ? ? cm 5 ? ? ? ? ? ? cm 6 cm 6 cm 6 cm 6 cm 7 =0(8 mhz selected) cm 6 =1(middle-speed) cm 5 =0(8 mhz oscillating) cm 4 =0(32 khz stopped) 1: switch the mode by the allows shown between the mode blocks. (do not switch between the mode directly without an allow.) 2: the all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait m ode is ended. 3: timer,lcd operate in the wait mode. 4: when the stop mode is ended, a delay of approximately 1 ms occurs by connecting timer 1 and timer 2 in middle-/high-speed mode . 5: when the stop mode is ended, a delay of approximately 0.25 s occurs in low-speed mode. 6: wait until oscillation stabilizes after oscillating the main clock x in before the switching from the low-speed mode to middle/high-speed mode. 7: the example assumes that 8 mhz is being applied to the x in pin and 32 khz to the x cin pin. f indicates the internal system clock. middle-speed mode (f( f )=1 mhz) middle-speed mode ((f( f )=1 mhz) cm 7 =0(8 mhz selected) cm 6 =0(high-speed) cm 5 =0(8 mhz oscillating) cm 4 =0(32 khz stopped) high-speed mode (f( f ) =4 mhz) cm 7 =0(8 mhz selected) cm 6 =0(high-speed) cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) high-speed mode (f( f ) =4 mhz) cm 7 =1(32 khz selected) cm 6 =0(high-speed) cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) low-speed mode (f( f ) =16 khz) cm 7 =1(32 khz selected) cm 6 =0(high-speed) cm 5 =1(8 mhz stopped) cm 4 =1(32 khz oscillating) cm 7 =0(8 mhz selected) cm 6 =1(middle-speed) cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) cm 7 =1(32 khz selected) cm 6 =1(middle-speed) cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) low-speed mode ((f( f )=16 khz) cm 7 =1(32 khz selected) cm 6 =1(middle-speed) cm 5 =1(8 mhz stopped) cm 4 =1(32 khz oscillating) low-speed mode (f( f ) =16 khz) low-speed mode ((f( f )=16 khz) notes
38C3 group users manual hardware 1-44 notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. after a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immediately after they have been written. after writing to an interrupt request reg- ister, execute at least one instruction before performing a bbc or bbs instruction. decimal calculations ? to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction before executing a sec, clc, or cld instruction. ? in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions ? the index x mode (t) and the decimal mode (d) flags do not affect the mul and div instruction. ? the execution of these instructions does not change the contents of the processor status register. ports the contents of the port direction registers cannot be read. the fol- lowing cannot be used: ? the data transfer instruction (lda, etc.) ? the operation instruction when the index x mode flag (t) is 1 ? the addressing mode which uses the value of a direction register as an index ? the bit-test instruction (bbc or bbs, etc.) to a direction register ? the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direction registers. serial i/o ? using an external clock when using an external clock, input h to the external clock input pin and clear the serial i/o interrupt request bit before executing serial i/o transfer and serial i/o automatic transfer. ? using an internal clock when using an internal clock, set the synchronous clock to the in- ternal clock, then clear the serial i/o interrupt request bit before executing a serial i/o transfer and serial i/o automatic transfer. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) is at least on 500 khz during an a-d conversion. do not execute the stp or wit instruction during an a-d conversion. instruction execution time the instruction execution time is obtained by multiplying the frequency of the internal system clock by the number of cycles needed to ex- ecute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal system clock is the same half of the x in frequency in high-speed mode. at stp instruction release at the stp instruction release, all bits of the timer 12 mode register are cleared. notes on use notes on built-in eprom version the p5 1 pin of the one time prom version or the eprom version functions as the power source input pin of the internal eprom. therefore, this pin is set at low input impedance, thereby being af- fected easily by noise. to prevent a malfunction due to noise, insert a resistor (approx. 5 k w ) in series with the p5 1 pin. notes on programming/notes on use
38C3 group users manual hardware 1-45 name of programming adapter pca4738f-80a pca4738l-80a data required for mask orders the following are necessary when ordering a mask rom production: 1. mask rom order confirmation form 2. mark specification form 3. data to be written to rom, in eprom form (three identical copies) data required for rom writing orders the following are necessary when ordering a rom writing: 1. rom writing confirmation form 2. mark specification form 3. data to be written to rom, in eprom form (three identical copies) rom programming method the built-in prom of the blank one time prom version and built-in eprom version can be read or programmed with a general-purpose prom programmer using a special programming adapter. fig. 46 programming and testing of one time prom version table 13 programming adapter package 80p6n-a 80d0 the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 46 is recommended to verify programming. data required for mask orders and rom writing orders/rom programming method programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer functional check in target device the screening temperature is far higher than the storage temperature. never expose to 150 c exceeding 100 hours. caution :
1-46 38C3 group users manual hardware functional description supplement interrupt 38C3 group permits interrupts on the basis of 16 sources. it is vector interrupts with a fixed priority system. accordingly, when two or more interrupt requests occur during the same sampling, the table 14 interrupt sources, vector addresses and interrupt priority functional description supplement higher-priority interrupt is accepted first. this priority is determined by hardware, but various priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. for interrupt sources, vector addresses and interrupt priority, refer to table 14. interrupt source reset (note 2) int 0 int 1 int 2 serial i/o timer a timer 1 timer 2 timer 3 timer 4 timer 5 timer 6 cntr 0 cntr 1 key input (key- on wake-up) a-d conversion brk instruction priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 vector addresses (note 1) high fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 interrupt request generating conditions at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at detection of either rising or falling edge of int 2 input at completion of serial i/o data transmit/re- ceive at timer a underflow at timer 1 underflow at timer 2 underflow at timer 3 underflow at timer 4 underflow at timer 5 underflow at timer 6 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at falling of port p8 (at input) input logical level and at completion of a-d conversion at brk instruction execution remarks non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o is selected stp release timer underflow external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (falling valid) valid when a-d conversion interrupt is selected non-maskable software interrupt low fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority.
1-47 38C3 group users manual hardware functional description supplement timing after interrupt the interrupt processing routine begins with the machine cycle fol- lowing the completion of the instruction that is currently in execution. figure 47 shows a timing chart after an interrupt occurs, and figure 48 shows the time up to execution of the interrupt processing routine. fig. 47 timing chart after interrupt occurs fig. 48 time up to execution of interrupt processing routine p c h p c l p sa l a h s , s p ss - 2 , s p s s - 1 , s p s p c b l b h a l , a h a d d r e s s b u s d a t a b u s n o t u s e d : c p u o p e r a t i o n c o d e f e t c h c y c l e ( t h i s i s a n i n t e r n a l s i g n a l w h i c h c a n n o t b e o b s e r v e d f r o m t h e e x t e r n a l u n i t . ) : v e c t o r a d d r e s s o f e a c h i n t e r r u p t : j u m p d e s t i n a t i o n a d d r e s s o f e a c h i n t e r r u p t : 0 0 1 6 o r 0 1 1 6 s y n c b l , b h a l , a h s p s w r r d s y n c f 7 t o 2 3 c y c l e s ( 4 m h z , 1 . 7 5 m s t o 5 . 7 5 m s ) i n t e r r u p t r e q u e s t o c c u r s m a i n r o u t i n e i n t e r r u p t p r o c e s s i n g r o u t i n e 2 c y c l e s5 c y c l e s w a i t i n g t i m e f o r p i p e l i n e p o s t - p r o c e s s i n g p u s h o n t o s t a c k v e c t o r f e t c h i n t e r r u p t o p e r a t i o n s t a r t s 0 t o 1 6 c y c l e s
1-48 38C3 group users manual hardware functional description supplement a-d converter a-d conversion is started by setting ad conversion completion bit to 0. during a-d conversion, internal operations are performed as fol- lows. 1. after the start of a-d conversion, a-d conversion register goes to 00 16 . 2. the highest-order bit of a-d conversion register is set to 1, and the comparison voltage vref is input to the comparator. then, v ref is compared with analog input voltage v in . 3. as a result of comparison, when v ref < v in , the highest-order bit of a-d conversion register becomes 1. when v ref > v in , the high- est-order bit becomes 0. by repeating the above operations up to the lowest-order bit of the a-d conversion register, an analog value converts into a digital value. a-d conversion completes at 61 clock cycles (15.25 m s at f(x in ) = 8 mhz) after it is started, and the result of the conversion is stored into the a-d conversion register. concurrently with the completion of a-d conversion, a-d conversion interrupt request occurs, so that the ad conversion interrupt request bit is set to 1. table 15 relative formula for a reference voltage v ref of a-d converter and v ref v ref 1024 ] 1C ] 10: a result of the first comparison to the tenth comparison table 16 change of a-d conversion register during a-d conversion at start of conversion first comparison second comparison third comparison after completion of tenth comparison 0 a result of a-d conversion ] 1 change of a-d conversion register 0 value of comparison voltage (v ref ) v ref 2 v ref 2 v ref 4 v ref 2 v ref 4 v ref 8 when n = 0 v ref = 0 when n = 1 to 1023 v ref = 5 n n: value of a-d converter (decimal numeral) v ref 2 v ref 4 v ref 1024 ? ? ? ? 0 0 000 0 000 1 0 0 00 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ] 1 ] 2 00 0 0 00 0 1 ] 1 ] 2 ] 3 ] 4 ] 5 ] 6 ] 7 ] 8 ] 9 ] 10 ~ ~ ~ ~
1-49 38C3 group users manual hardware functional description supplement figures 49 shows the a-d conversion equivalent circuit, and figure 50 shows the a-d conversion timing chart. fig. 49 a-d conversion equivalent circuit fig. 50 a-d conversion timing chart v s s v c c v s s v c c a n 0 a n 1 a n 2 a n 3 a n 4 a n 5 a n 6 a n 7 v r e f a v s s v r e f v i n a b o u t 2 k w c b 1 b 2b 0 a - d c o n t r o l r e g i s t e r b u i l t - i n d - a c o n v e r t e r r e f e r e n c e c l o c k a - d c o n v e r s i o n r e g i s t e r ( h i g h - o r d e r ) a d c o n v e r s i o n i n t e r r u p t r e q u e s t c h o p p e r a m p l i f i e r s a m p l i n g c l o c k a - d c o n v e r s i o n r e g i s t e r ( l o w - o r d e r ) w r i t e s i g n a l f o r a - d c o n t r o l r e g i s t e r a d c o n v e r s i o n c o m p l e t i o n b i t s a m p l i n g c l o c k f 6 1 c y c l e s
1-50 38C3 group users manual hardware functional description supplement memorandum
chapter 2 chapter 2 application 2.1 i/o port 2.2 timer 2.3 serial i/o 2.4 lcd controller 2.5 a-d converter 2.6 rom correct function 2.7 reset circuit 2.8 clock generating circuit
2-2 38C3 group users manual application 2.1 i/o port 2.1 i/o port this paragraph describes the setting method of i/o port relevant registers, notes etc. 2.1.1 memory map fig. 2.1.1 memory map of i/o port relevant registers pull register a (pulla) pull register b (pullb) port p7 (p7) port p6 direction register (p6d) port p6 (p6) 0016 16 0017 16 000e 16 000d 16 port p7 direction register (p7d) 000f 16 port p8 (p8) 0010 16 port p8 direction register (p8d) 0011 16 000c 16 port p8 output selection register (p8sel) 0018 16 port p5 direction register (p5d) port p5 (p5) port p4 direction register (p4d) 000b 16 000a 16 0009 16 port p4 (p4) 0008 16 0007 16 port p3 (p3) port p2 direction register (p2d) port p2 (p2) 0006 16 0005 16 0004 16 0003 16 port p1 (p1) port p0 direction register (p0d) port p1 direction register (p1d) port p0 (p0) 0002 16 0001 16 0000 16 address
2-3 application 2.1 i/o port 38C3 group users manual 2.1.2 relevant registers fig. 2.1.2 structure of port pi (i = 0, 1, 2, 3, 4, 5, 6, 8) fig. 2.1.3 structure of port p7 port pi b7 b6 b5 b4 b3 b2 b1 b0 port pi (i = 0, 1, 2, 3, 4, 5, 6, 8) (pi: addresses 00 16 , 02 16 , 04 16 , 06 16 , 08 16 , 0a 16 , 0c 16 , 10 16 ) b 0 0 port pi 0 l in output mode write port latch read port latch l in input mode write port latch read value of pin port pi 1 port pi 2 port pi 3 port pi 4 port pi 5 port pi 6 port pi 7 functions name at reset r w 1 0 2 0 3 0 4 0 5 0 6 0 7 0 port p7 b7 b6 b5 b4 b3 b2 b1 b0 port p7 (p7: address 0e 16 ) b 0 0 port p7 0 l in output mode write port latch read port latch l in input mode write port latch read value of pin port p7 1 functions name at reset r w 1 0 2 0 3 0 4 0 5 0 6 0 7 0 55 55 55 55 55 55 nothing is arranged for these bits. when these bits are read out, the contents are undefined.
2-4 38C3 group users manual application 2.1 i/o port fig. 2.1.5 structure of port pi direction register (i = 2, 4, 5, 6, 8) fig. 2.1.4 structure of port p0 direction register and port p1 direction register port p0 direction register, port p1 direction register b7 b6 b5 b4 b3 b2 b1 b0 port p0 direction register (p0d: address 01 16 ) port p1 direction register (p1d: address 03 16 ) b 0 name 0 functions at reset r w 0 0 0 0 0 ports p0/p1 direction register 0 0 55 55 0 55 55 55 55 5 5 5 nothing is arranged for these bits. when these bits are read out, the contents are undefined. 2 3 4 5 6 7 1 0 : all bits of ports p0/p1 input mode 1 : all bits of ports p0/p1 output mode note: ports p0 and p1 are switched to input and output by each port. when b0 of corresponding port direction register is set to ?? all 8 bits of port become input port. when b0 of corresponding port direction register is set to ?? all 8 bits of port become output port. nothing is arranged for b1 to b7 of port p0 and port p1 direction registers. these are write disabled bits. port pi direction register b7 b6 b5 b4 b3 b2 b1 b0 port pi direction register (i = 2, 4, 5, 6, 8) (pid: addresses 05 16 , 09 16 , 0b 16 , 0d 16 , 11 16 ) 0 : port pi 0 input mode 1 : port pi 0 output mode b 0 1 2 3 4 5 6 7 name 0 functions at reset r w 0 0 : port pi 2 input mode 1 : port pi 2 output mode 0 0 : port pi 3 input mode 1 : port pi 3 output mode 0 0 : port pi 4 input mode 1 : port pi 4 output mode 0 0 : port pi 5 input mode 1 : port pi 5 output mode 0 0 : port pi 6 input mode 1 : port pi 6 output mode 0 0 : port pi 7 input mode 1 : port pi 7 output mode 0 port pi direction register note: bit 1 of the port p5 direction register (address 0b 16 ) does not have direction register function, because p5 1 is an input port. when writing to bit 1 of the port p5 direction register, write ??to the bit. 0 : port pi 1 input mode 1 : port pi 1 output mode (note)
2-5 application 2.1 i/o port 38C3 group users manual fig. 2.1.7 structure of pull register a fig. 2.1.6 structure of port p7 direction register port p7 direction register b7 b6 b5 b4 b3 b2 b1 b0 port p7 direction register (p7d: address 0f 16 ) 0 : port p7 0 input mode 1 : port p7 0 output mode b 0 1 2 3 4 5 name 0 functions at reset r w 0 : port p7 1 input mode 1 : port p7 1 output mode 0 0 0 0 0 port p7 direction register 6 0 7 0 55 55 55 55 55 5 5 5 5 nothing is arranged for these bits. when these bits are read out, the contents are undefined. b7 b6 b5 b4 b3 b2 b1 b0 pull register a (pulla: address 16 16 ) 0: no pull-down control 1: pull-down control b 0 1 2 3 4 7 name functions at reset r w 0: no pull-down control 1: pull-down control 0: no pull-down control 1: pull-down control 0 0 1 1 1 1 port p0 0 ?0 7 pull-down control port p1 0 ?1 7 pull-down control port p2 0 ?2 7 pull-down control port p7 0 , p7 1 pull-up control port p8 0 ?8 7 pull-up control nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? 0 0 5 6 0: no pull-up control 1: pull-up control 0: no pull-up control 1: pull-up control note: the pin which is set to output port is cut off from pull-up control. pull register a
2-6 38C3 group users manual application 2.1 i/o port fig. 2.1.8 structure of pull register b fig. 2.1.9 structure of port p8 output selection register pull register b b7 b6 b5 b4 b3 b2 b1 b0 pull register b (pullb: address 17 16 ) 0: no pull-up control 1: pull-up control b 0 1 2 3 4 7 name functions at reset r w 0: no pull-up control 1: pull-up control 0: no pull-up control 1: pull-up control 0 0 0 0 0 0 port p4 0 ?4 3 pull-up control port p4 4 ?4 7 pull-up control port p6 0 ?6 3 pull-up control port p5 4 ?5 7 pull-up control port p5 0 , p5 2 , p5 3 pull-up control port p6 4 ?6 7 pull-up control nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? 0 0 5 6 0: no pull-up control 1: pull-up control 0: no pull-up control 1: pull-up control note: the pin which is set to output port is cut off from pull-up control. 0: no pull-up control 1: pull-up control port p8 output selection register b7 b6 b5 b4 b3 b2 b1 b0 port p8 output selection register (p8sel: address 18 16 ) b 0 name functions at reset r w 0 port p8 output selection register 0 0 0 0 0 0 0 1 2 3 4 7 5 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) 6
2-7 application 2.1 i/o port 38C3 group users manual 2.1.3 terminate unused pins table 2.1.1 termination of unused pins pins p3 p0, p1, p2, p4, p5 0 , p5 2 Cp5 7 , p6, p7, p8 p5 1 vl 1 Cvl 3 com 0 Ccom 3 v ref x out av ss termination open at h output state. ? set to the input mode and connect each to v cc or v ss through a resistor of 1 k w to 10 k w . ? set to the output mode and open at l or h output state. connect to v cc or v ss through a resistor of 1 k w to 10 k w . connect to vss (gnd). open open open (only when using external clock) connect to v ss (gnd).
2-8 38C3 group user s manual applica tion 2.1 i/o port 2.1.4 notes on i/o port (1) notes in standby state in standby state ] 1 for low-power dissipation, do not make input levels of an input port and an i/o port undefined . pull-up (connect the port to v cc ) or pull-down (connect the port to v ss ) these ports through a resistor. when determining a resistance value, note the following points: external circuit variation of output levels during the ordinary operation when using built-in pull-up resistor, note on varied current values: when setting as an input port : fix its input level when setting as an output port : prevent current from flowing out to external l r eason the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an i/o port are undefined . this may cause power source current. ] 1 standby state: stop mode by executing stp instruction wait mode by executing wit instruction (2) modifying port latch of i/o port with bit managing instruction when the port latch of an i/o port is modified with the bit managing instruction ] 2 , the value of the unspecified bit may be changed. l reason the bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. accordingly, when these instructions are executed on a bit of the port latch of an i/o port, the following is executed to all bits of the port latch. as for bit which is set for input port: the pin state is read in the cpu, and is written to this bit after bit managing. as for bit which is set for output port: the bit value is read in the cpu, and is written to this bit after bit managing. note the following: even when a port which is set as an output port is changed for an input port, its port latch holds the output data. as for a bit of which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. ] 2 bit managing instructions: seb and clb instructions (3) pull-up/pull-down control when each port which has built-in pull-up/pull-down resistor (p0, p1, p2, p4, p5 0 , p5 2 p5 7 , p6, p7, p8) is set to output port, pull-up/pull-down control of corresponding port become invalid. (pull-up/pull- down cannot be set.) l reason pull-up control is valid only when each direction register is set to the input mode.
2-9 application 2.1 i/o port 38C3 group users manual 2.1.5 termination of unused pins (1) terminate unused pins output ports : open input ports : connect each pin to v cc or v ss through each resistor of 1 k w to 10 k w . as for pins whose potential affects to operation modes such as pin int or others, select the v cc pin or the v ss pin according to their operation mode. a i/o ports : ? set the i/o ports for the input mode and connect them to v cc or v ss through each resistor of 1 k w to 10 k w . ports that permit the selecting of a built-in pull-up resistor can also use this resistor. set the i/o ports for the output mode and open them at l or h. ? when opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. thus, the potential at these pins is undefined and the power source current may increase in the input mode. with regard to an effects on the system, thoroughly perform system evaluation on the user side. ? since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) termination remarks input ports and i/o ports : do not open in the input mode. l reason ? the power source current may increase depending on the first-stage circuit. ? an effect due to noise may be easily produced as compared with proper termination and a shown on the above. i/o ports : when setting for the input mode, do not connect to v cc or v ss directly. l reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and v cc (or v ss ). a i/o ports : when setting for the input mode, do not connect multiple ports in a lump to v cc or v ss through a resistor. l reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. ? at the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins.
2-10 38C3 group users manual application 2.2 timer 2.2 timer this paragraph explains the registers setting method and the notes relevant to the timers. 2.2.1 memory map fig. 2.2.1 memory map of registers relevant to timers 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 5 1 6 0 0 2 7 1 6 0 0 2 8 1 6 0 0 2 c 1 6 t i m e r 1 ( t 1 ) t i m e r 4 ( t 4 ) t i m e r 6 ( t 6 ) t i m e r 6 p w m r e g i s t e r ( t 6 p w m ) t i m e r 1 2 m o d e r e g i s t e r ( t 1 2 m ) t i m e r a r e g i s t e r ( l o w - o r d e r ) ( t a l ) 0 0 3 e 1 6 0 0 3 f 1 6 i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) 0 0 2 0 1 6 0 0 2 1 1 6 t i m e r 2 ( t 2 ) t i m e r 3 ( t 3 ) 0 0 2 4 1 6 t i m e r 5 ( t 5 ) t i m e r 3 4 m o d e r e g i s t e r ( t 3 4 m ) 0 0 2 9 1 6 t i m e r 5 6 m o d e r e g i s t e r ( t 5 6 m ) 0 0 2 a 1 6 0 0 2 d 1 6 t i m e r a r e g i s t e r ( h i g h - o r d e r ) ( t a h ) 0 0 2 e 1 6 c o m p a r e r e g i s t e r ( l o w - o r d e r ) ( c o n a l ) 0 0 2 f 1 6 c o m p a r e r e g i s t e r ( h i g h - o r d e r ) ( c o n a h ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) 0 0 3 d 1 6 0 0 3 c 1 6 t i m e r a m o d e r e g i s t e r ( t a m ) t i m e r a c o n t r o l r e g i s t e r ( t a c o n ) 0 0 3 1 1 6 0 0 3 0 1 6
38C3 group users manual application 2-11 2.2 timer fig. 2.2.3 structure of timer 2 fig. 2.2.2 structure of timer i (i=1, 3, 4, 5, 6) 2.2.2 relevant registers (1) 8-bit timer timer i b7 b6 b5 b4 b3 b2 b1 b0 timer i (i = 1, 3, 4, 5, 6) (ti: addresses 20 16 , 22 16 , 23 16 , 24 16 , 25 16 ) b 0 1 at reset r w 1 2 3 4 5 6 7 functions ?set timer i count value. ?the value set in this register is written to both the timer i and the timer i latch at one time. ?when the timer i is read out, the count value of the timer i is read out. 1 1 1 1 1 1 1 timer 2 b7 b6 b5 b4 b3 b2 b1 b0 timer 2 (t2: address 21 16 ) b 0 1 at reset r w 1 2 3 4 5 6 7 functions ?set timer 2 count value. ?the value set in this register is written to both the timer 2 and the timer 2 latch at one time. ?when the timer 2 is read out, the count value of the timer 2 is read out. 0 0 0 0 0 0 0
2-12 38C3 group users manual application 2.2 timer fig. 2.2.4 structure of timer 6 pwm register fig. 2.2.5 structure of timer 12 mode register timer 6 pwm register b7 b6 b5 b4 b3 b2 b1 b0 timer 6 pwm register (t6pwm: address 27 16 ) b 0 1 2 3 4 5 6 7 undefined functions at reset r w undefined undefined undefined undefined undefined undefined undefined ?in timer 6 pwm 1 mode ??level width of pwm rectangular waveform is set. ?duty of pwm rectangular waveform: n/(n + m) period: (n + m) ts n = timer 6 set value m = timer 6 pwm register set value ts = timer 6 count source period at n = 0, all pwm output ?? at m = 0, all pwm output ?? (however, n = 0 has priority.) ?selection of timer 6 pwm 1 mode set ??to the timer 6 operation mode selection bit. timer 12 mode register b7 b6 b5 b4 b3 b2 b1 b0 timer 12 mode register (t12m: address 28 16 ) 0: count operation 1: count stop b 0 1 2 3 4 5 6 7 name 0 functions at reset r w 0: count operation 1: count stop 0 0 0: f(x in )/16 or f(x cin )/16 0 1: f(x cin ) 1 0: f(x in )/32 or f(x cin )/32 1 1: f(x in )/128 or f(x cin )/128 0 0 0 0: i/o port 1: timer 1 output 0 0 0 timer 1 count stop bit timer 2 count stop bit timer 2 count source selection bits timer 1 output selection bit (p4 1 ) timer 1 count source selection bits nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? b3 b2 b5 b4 0 0: timer 1 underflow 0 1: f(x cin ) 1 0: external count input cntr 0 1 1: not available
38C3 group users manual application 2-13 2.2 timer fig. 2.2.6 structure of timer 34 mode register fig. 2.2.7 structure of timer 56 mode register timer 34 mode register b7 b6 b5 b4 b3 b2 b1 b0 timer 34 mode register (t34m: address 29 16 ) 0: count operation 1: count stop b 0 1 2 3 4 5 6 7 name 0 functions at reset r w 0: count operation 1: count stop 0 0 0: f(x in )/16 or f(x cin )/16 0 1: timer 2 underflow 1 0: f(x in )/32 or f(x cin )/32 1 1: f(x in )/128 or f(x cin )/128 0 0 0 0: i/o port 1: timer 3 output 0 0 timer 3 count stop bit timer 4 count stop bit timer 4 count source selection bits timer 3 output selection bit (p4 2 ) timer 3 count source selection bits nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? b3 b2 b5 b4 0 0: f(x in )/16 or f(x cin )/16 0 1: timer 3 underflow 1 0: external count input cntr 1 1 1: not available timer 56 mode register b7 b6 b5 b4 b3 b2 b1 b0 timer 56 mode register (t56m: address 2a 16 ) 0: count operation 1: count stop b 0 1 2 3 4 5 6 7 name 0 functions at reset r w 0: count operation 1: count stop 0 0: f(x in )/16 or f(x cin )/16 1: timer 4 underflow 0: timer mode 1: pwm mode 0 0 0 0: i/o port 1: timer 6 output 0 0 0 timer 5 count stop bit timer 6 count stop bit timer 6 count source selection bits timer 6 (pwm) output selection bit (p5 2 ) timer 5 count source selection bit timer 6 operation mode selection bit nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? b5 b4 0 0: f(x in )/16 or f(x cin )/16 0 1: timer 5 underflow 1 0: timer 4 underflow 1 1: not available
2-14 38C3 group users manual application 2.2 timer fig. 2.2.8 structure of timer a register (low-order, high-order) (2) 16-bit timer timer a register (low-order, high-order) b7 b6 b5 b4 b3 b2 b1 b0 timer a register (low-order, high-order) (tal, tah: addresses 2c 16 , 2d 16 ) b 0 1 2 3 4 5 6 7 1 functions at reset r w 1 1 1 1 1 1 1 ?set timer a count value. ?when the timer a write control bit of the timer a mode register is ?? the value is written to timer a and the latch at one time. when the timer a write control bit of the timer a mode register is ?? the value is written only to the latch. ?the timer a count value is read out by reading this register. notes 1: when reading and writing, perform them to both the high- order and low-order bytes. 2: read both registers in order of tah and tal following. 3: write both registers in order of tal and tah following. 4: do not read both registers during a write, and do not write to both registers during a read. fig. 2.2.9 structure of compare register (low-order, high-order) compare register (low-order, high-order) b7 b6 b5 b4 b3 b2 b1 b0 compare register (low-order, high-order) (conal, conah: addresses 2e 16 , 2f 16 ) b 0 1 2 3 4 5 6 7 0 functions at reset r w 0 0 0 0 0 0 0 ?set compare register value. note: write registers in order of conah, conal, tal, and tah following.
38C3 group users manual application 2-15 2.2 timer fig. 2.2.10 structure of timer a mode register fig. 2.2.11 structure of timer a control register timer a mode register b7 b6 b5 b4 b3 b2 b1 b0 timer a mode register (tam: address 30 16 ) b 0 4 name 0 functions at reset r w timer a operating mode bits timer a write control bit 0 0: timer mode 0 1: pulse output mode 1 0: igbt output mode 1 1: pwm mode 0 0: f(x in ) 0 1: f(x in )/2 1 0: f(x in )/4 1 1: f(x in )/8 0 0 0: write data to both timer latch and timer 1: write data to timer latch 1 timer a count source selection bits 3 0 0 0 0 0 timer a output active edge switch bit timer a count stop bit 0: output starts with ??level 1: output starts with ??level 0: count operating 1: count stop timer a output selection bit (p5 0 ) 0: i/o port 1: timer a output 5 6 7 b1b0 2 b4b3 timer a control register b7 b6 b5 b4 b3 b2 b1 b0 timer a control register (tacon: address 31 16 ) b 0 4 name 0 functions at reset r w noise filter sampling clock selection bit external trigger delay time selection bits 0: f(x in )/2 1: f(x in )/4 0: not used 1: int1 interrupt used 0 0: no delay 0 1: (4/f(x in )) m s 1 0: (8/f(x in )) m s 1 1: (16/f(x in )) m s 0 0 1 timer a output control bit 1 (p5 6 ) 0: not used 1: int2 interrupt used timer a output control bit 2 (p5 7 ) 3 0 0 0 5 6 7 2 b2b1 0 0 nothing is arranged for these bits. these are write disabled bits. when these bits are read out, the contents are ??
2-16 38C3 group users manual application 2.2 timer fig. 2.2.12 structure of interrupt request register 1 (3) 8-bit timer, 16-bit timer interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 1 (ireq1 : address 3c 16 ) b 0 1 2 3 4 5 6 7 name 0 functions at reset r w 0 0 0 0 0 0 int 0 interrupt request bit int 1 interrupt request bit serial i/o interrupt request bit timer a interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit int 2 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued timer 3 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued 0 ] ] ] ] ] ] ] ] ] : ??can be set by software, but ??cannot be set.
38C3 group users manual application 2-17 2.2 timer fig. 2.2.13 structure of interrupt request register 2 interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 interrupt request register 2 (ireq2 : address 3d 16 ) b 0 1 2 3 4 5 6 7 name 0 functions at reset r w 0 0 0 0 0 0 timer 4 interrupt request bit timer 5 interrupt request bit cntr 0 interrupt request bit cntr1 interrupt request bit key input interrupt request bit ad conversion interrupt request bit timer 6 interrupt request bit 0 ] ] ] ] ] ] ] nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? ] : ??can be set by software, but ??cannot be set. 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued
2-18 38C3 group users manual application 2.2 timer fig. 2.2.14 structure of interrupt control register 1 fig. 2.2.15 structure of interrupt control register 2 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 1 (icon1 : address 3e 16 ) b 0 1 2 3 4 5 6 7 name 0 functions at reset r w 0 0 0 0 int 0 interrupt enable bit int 1 interrupt enable bit serial i/o interrupt enable bit timer a interrupt enable bit timer 1 interrupt enable bit timer 2 interrupt enable bit int 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled timer 3 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 0 0 interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 interrupt control register 2 (icon2 : address 3f 16 ) b 0 1 2 4 name 0 functions at reset r w 0 0 0 0 timer 5 interrupt enable bit cntr 0 interrupt enable bit cntr 1 interrupt enable bit timer 6 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 5 0 key input interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 6 7 0 ad conversion interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 timer 4 interrupt enable bit nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are ?? 3
38C3 group users manual application 2-19 2.2 timer 2.2.3 timer application examples (1) basic functions and uses [function 1] control of event interval (timer 1 to timer 6, timer a: timer mode) when a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs. |
