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1 ? semiconductor MSM54V24632A description the MSM54V24632A is a synchronous graphics random access memory without graphics oriented functions; block write, write per bit, single write and burst stop. it is organized as 128k words 32 bits 2 banks. this device can operate up to 125mhz by using synchronous interface. features ? 131,072-words 32 bits 2 banks memory ? single 3.3 v 0.3 v power supply ? lvttl compatible inputs and outputs ? all input signals are latched at rising edge of system clock ? auto precharge and controlled precharge ? internal pipelined operation: column address can be changed every clock cycle ? dual internal banks controlled by a9 (bank address: ba) ? independent byte operation via dqm0 to dqm3 ? simplified function (no block write, write per bit, single write and burst stop) ? programmable burst sequence (sequential / interleave) ? programmable burst length (1, 2, 4, 8 and full page) ? programmable cas latency (1, 2 and 3) ? power down operation and clock suspend operation ? auto refresh and self refresh capability ? 1,024 refresh cycle / 16 ms ? package : 100-pin plastic qfp (qfp100-p-1420-0.65-bk4) (product : MSM54V24632A-xxgs-bk4) xx indicates speed rank. product family ? semiconductor 11 feb. 1998 MSM54V24632A 131,072-word 32-bit 2-bank sgram without graphics functions preliminary family MSM54V24632A-10 MSM54V24632A-12 clock frequency mhz (max.) 100 83 MSM54V24632A-8 125 100-pin plastic qfp (14 20 mm) package
3 MSM54V24632A ? semiconductor pin configuration (top view) 100pin plastic qfp dq29 81 vss(q) 82 dq30 83 dq31 84 vss 85 nc 86 nc 87 nc 88 nc 89 nc 90 nc 91 nc 92 nc 93 nc 94 nc 95 vcc 96 dq0 97 dq1 98 vss(q) 99 dq2 80 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 dq3 vcc(q) dq4 dq5 vss(q) dq6 dq7 vcc(q) dq16 dq17 vss(q) dq18 dq19 vcc(q) vcc vss dq20 dq21 vss(q) dq22 dq23 vcc(q) dqm0 dqm2 we cas ras cs a9 nc 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 a7 a6 a5 a4 vss nc nc nc nc nc nc nc nc nc nc vcc a3 a2 a1 a0 dq28 1 79 vcc(q) 78 dq27 77 dq26 76 vss(q) 75 dq25 74 dq24 73 vcc(q) 72 dq15 71 dq14 70 vss(q) 69 dq13 68 dq12 67 vcc(q) 66 vss 65 vcc 64 dq11 63 dq10 62 vss(q) 61 dq9 60 dq8 59 vcc(q) 58 nc 57 dqm3 56 dqm1 55 clk 54 cke 53 nc 52 nc 51 a8 100 note: the same power supply voltage must be provided to every v cc pin and v cc (q)pin. the same gnd voltage level must be provided to every v ss pin and v ss (q) pin. pin name function system clock clock enable address row address strobe column address strobe write enable data input/output mask data input/output power supply (3.3 v) ground (0 v) data output power supply (3.3 v) data output ground (0 v) clk cke a0 - a8 ras cas we dqm0~dqm3 dqi v cc v ss v cc (q) v ss (q) chip select cs bank select address a9 no connection nc pin name function
3 ? semiconductor MSM54V24632A pin description clk fetches all inputs at the "h" edge. cke masks system clock to deactivate the subsequent clk operation. if cke is deactivated, system clock will be masked that the subsequent clk operation is deactivated. cke should be asserted at least one cycle prior to a new command. row & column multiplexed. row address: ra0 C ra8 column address: ca0 C ca7 ras cas we functionality depends on the combination. for details, see the function truth table. dqm0 ~dqm3 masks the read data of two clocks later when dqm0~dqm3 is set "h" at the "h" edge of the clock signal. masks the write data of the same clock when dqm0~dqm3 is set "h" at the "h" edge of the clock signal. address dqi data inputs/outputs are multiplexed on the same pin. cs disables or enables device operation by asserting or deactivating all inputs except clk, cke, dqm0, dqm1, dqm2 and dqm3. selects bank to be activated during row address latch time and selects bank for precharge and read/ write during column address latch time. a9= "l" : bank a, a9= "h" : bank b a9
5 MSM54V24632A ? semiconductor block diagram timing register progra- ming register latency & burst controller cke clk cs ras cas we internal col. address counter column address buffers internal row address counter row address buffers a0-a9 8 9 row decoders word drivers 4mb memory cells 9 8 column decoders sense amplifier 32 read data register output buffers input data register input buffers 16 dq0-dq31 i/o controller 32 dqm0 bank controller a9 row decoders word drivers 4mb memory cells sense amplifier column decoders 32 32 dqm1 dqm2 dqm3
5 ? semiconductor MSM54V24632A electrical characteristics absolute maximum ratings (voltages referenced to v ss ) parameter unit symbol voltage on any pin relative to v ss rating v in , v out C0.5 to 4.6 v v cc supply voltage v cc , v cc q C0.5 to 4.6 v storage temperature t stg C55 to 150 c power dissipation p d *1 w short circuit current i os 50 ma operating temperature t opr 0 to 70 c *: ta = 25 c (voltages referenced to v ss = 0 v) parameter unit symbol power supply voltage v cc , v cc q input high voltage v ih input low voltage v il min. 3.0 2.0 C0.3 v v v typ. 3.3 max. 3.6 v cc + 0.2 0.8 recommended operating conditions capacitance (v cc = 3.3 v 0.3 v, ta = 25c, f = 1 mhz) parameter unit symbol input capacitance (clk, cke, cs , ras , cas , we , dqm0~dqm3) input/output capacitance (dq0 - dq31) c in2 c out pf pf input capacitance (a0 - a9) c in1 pf 5 5 7 typ. max.
7 MSM54V24632A ? semiconductor dc characteristics parameter condition version unit note cke others bank C8 C10 C12 symbol output high voltage output low voltage input leakage current 2.4 C 10 v v m a i oh = C2 ma i ol = 2 ma v oh v ol i li 0.4 10 2.4 C 10 0.4 10 2.4 C 10 0.4 10 output leakage current C 10 m a i lo 10 C 10 10 C 10 10 min. max. min. max. min. max. average power supply current (operating) ma 1, 2 cke 3 v ih t cc = min t rc = min no burst one bank active i cc 1 180 160 140 ma 1, 2 cke 3 v ih t cc = min t rc = min t rrd = min no burst both banks active i cc 1d 240 200 180 power supply current (stand by) ma 3 cke 3 v ih t cc = min both banks precharge i cc 2 80 70 60 average power supply current (clock suspension) ma 3 cke v il t cc = min both banks active i cc 3s 35 30 25 power supply current (burst) ma 1, 2 cke 3 v ih t cc = min both banks active i cc 4 210 180 160 power supply current (auto-refresh) ma 2 cke 3 v ih t cc = min t rc = min one bank active i cc 5 170 150 130 average power supply current (self-refresh) ma cke v il t cc = min both banks precharge i cc 6 2 2 2 average power supply current (power down) ma cke v il t cc = min both banks precharge i cc 7 2 2 2 average power supply current (active stand by) ma 3 cke 3 v ih t cc = min one bank active i cc 3 95 80 70 notes: 1. measured with outputs open. 2. address and data can be changed once or not be changed during one cycle. 3. address and data can be changed once or not be changed during two cycles.
7 ? semiconductor MSM54V24632A mode set address keys a8 a7 tm a6 a5 a4 cl a3 bt a2 a1 a0 bt = 0 bt = 1 operation code cas latency burst type burst length 00 mode setting 000 reserved 0 sequential 000 1 1 0 1 001 1 1 interleave 001 2 2 10 reserved 010 2 010 4 4 011 3 011 8 8 100 reserved 100 reserved reserved 101 reserved 101 reserved reserved 110 reserved 110 reserved reserved 111 reserved 111 full page reserved reserved 11 reserved note: a9 should stay "l" during mode set cycle. power on sequence 1. with inputs in nop state, turn on the power supply and start the system clock. 2. after the v cc voltage has reached the specified level, pause for 200 m s or more with the input kept in nop state. 3. issue the precharge all bank command. 4. apply an auto-refresh eight or more times. 5. enter the mode register setting command.
9 MSM54V24632A ? semiconductor ac characteristics 1 parameter MSM54V24632A-8 MSM54V24632A-10 MSM54V24632A-12 clock cycles time access time from clock clock "h" pulse time clock "l" pulse time input setup time input hold time output low impedance time form clock output high impedance time form clock output hold from clock ras cycle time ras precharge time ras active time write recovery time write command input time form output refresh time power-down exit set-up time ras to cas delay time cl = 3 cl = 2 cl = 1 cl = 3 cl = 2 cl = 1 symbol t cc t ac t ch t cl t si t hi t rc t rp t ras t wr t ref t pde t rcd t olz t ohz min. 8 12 24 2.5 2.5 2.5 1 72 24 48 16 8 24 3 max. 7 10 22 10 5 16 6 min. 10 15 30 3 3 3 1 90 30 60 20 10 30 3 max. 9 13 27 10 5 16 8 min. 12 18 36 4 4 3 1.5 106 36 72 24 12 36 3 max. 10 15 32 10 5 16 10 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns note 3, 4 3, 4 3, 4 t owd 16 20 24 ns ras to ras bank active delay time t rrd 16 20 24 ns input level transition time t t 151515ns t oh 3 3 3 ns 3 note 1, 2
9 ? semiconductor MSM54V24632A ac characteristics 2 parameter MSM54V24632A-8 MSM54V24632A-10 MSM54V24632A-12 symbol unit note cas to cas delay time (min.) l ccd cycle clock disable time from cke l cke cycle data output high impedance time from dqm l doz cycle data input mask time from dqm l dod cycle data input time from write command l dwd cycle data output high impedance time from precharge command l roh active command input time from mode register set command input (min.) l mrd cycle note 1, 2 t ck ns cl 2 31 2 31 2 31 12 824 15 10 30 18 12 36 1 11 1 11 1 11 1 11 1 11 1 11 2 22 2 22 2 22 0 00 0 00 0 00 0 00 0 00 0 00 2 21 2 21 2 21 cycle 3 33 3 33 3 33
11 MSM54V24632A ? semiconductor notes : 1. ac measurements assume t t = 1 ns. 2. the reference level for timing of input signals is 1.4 v. 3. output load. output z = 50 w 30 pf 50 w 1.4 v 4. an access time is measured at 1.4 v. 5. if t t is longer than 1ns, the reference level for timing of input signals is v ih and v il .
11 ? semiconductor MSM54V24632A timing waveform read & write cycle (same bank) @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we dqm0 ~dqm3 ra ca0 qa0 t oh t rc cs t rp t rcd a9 a8 rb cb0 qa1 qa2 qa3 db0 db1 db2 db3 t ohz row active read command precharge command row active write command precharge command ra rb t wr t ac
13 MSM54V24632A ? semiconductor single bit read-write-read cycle (same page) @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we dqm0 ~dqm3 ra ca qa cs a9 a8 cb cc db qc row active read command read command write command precharge command t ch t cc t cl t hi t si t hi t si t hi t si l ccd t hi t si bs bs bs bs t si t hi bs ra t hi t si t ac t olz t ohz t hi t si t oh high t owd
13 ? semiconductor MSM54V24632A a9 0 1 active, read or write bank a bank b a8 0 operation after the end of burst, bank a holds the active status. a9 0 0 0 after the end of burst, bank b holds the active status. 1 1 after the end of burst, bank a is precharged automatically. after the end of burst, bank b is precharged automatically. 1 1 a8 0 0 1 a9 0 1 x operation bank a is precharged. bank b is precharged. both banks a and b are precharged. * notes: 1. when cs is set "high" at a clock transition from "low" to "high", all inputs except cke and dqm0, dqm1, dqm2, dqm3 are invalid. 2. when issuing an active, read or write command, the bank is selected by a9. 3. the auto precharge function is enabled or disabled by the a8 input when the read or write command is issued. 4. when issuing a precharge command, the bank to be precharged is selected by the a8 and a9 inputs. 5. the input data and the write command are latched by the same clock (write latency = 0). 6. the output is forced to high impedance by (1 clk + t ohz ) after dqmi entry.
15 MSM54V24632A ? semiconductor page read & write cycle (same bank) @ cas latency = 2, burst length = 4 * notes: 1. to write data before a burst read ends, dqmi should be asserted three cycles prior to the write command, to avoid bus contention. 2. to assert row precharge before a burst write ends, wait t wr after the last write data input. input data during the precharge input cycle will be masked internally. clk 012345678910111213141516171819 cke ras cas addr dq we dqm0 ~dqm3 ca0 cb0 cs a9 a8 cc0 cd0 qa0 read command write command precharge command t wr bank a active qa1 qb0 qb1 dc0 dc1 dd0 read command write command high l ccd *note2 *note1
15 ? semiconductor MSM54V24632A clk 012345678910111213141516171819 cke ras cas addr we dq dqm0 ~dqm3 ra cs a9 a8 rb ca qa0 row active (a-bank) row active (b-bank) a-bank precharge start b bank write with auto precharge cb cas latency = 1 dqm0 ~dqm3 dq cas latency = 2 dq dqm0 ~dqm3 cas latency = 3 qa1 qa2 qa3 db0 db1 db2 db3 qa0 qa1 qa2 qa3 db0 db1 db2 db3 qa0 qa1 qa2 qa3 db0 db1 db2 db3 a bank read with auto precharge b bank precharge start point high t rrd a-bank precharge start a-bank precharge start t wr ra rb read & write cycle with auto precharge @ burst length = 4
17 MSM54V24632A ? semiconductor bank interleave random row read cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we dqm0 ~dqm3 raa caa cs a9 a8 qaa0 row active (a-bank) row active (a-bank) read command (b-bank) precharge command (b-bank) t rc raa t rrd rbb cbb rac cac rbb rac qaa1 qaa2 qaa3 qbb1 qbb2 qbb3 qbb4 qac0 qac1 qac2 read command (a-bank) row active (b-bank) precharge command (a-bank) read command (a-bank) high qac3
17 ? semiconductor MSM54V24632A bank interleave random row write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we dqm0 ~dqm3 raa caa cs a9 a8 daa0 row active (a-bank) precharge command (a-bank) raa rbb cbb rac ca daa1 daa2 daa3 dbb0 dbb1 dbb2 dbb3 dac0 dac1 write command (a-bank) row active (b-bank) rac rbb write command (b-bank) precharge command (a-bank) row active (a-bank) precharge command (b-bank) write command (a-bank) high
19 MSM54V24632A ? semiconductor bank interleave page read cycle @ cas latency = 2, burst length = 4 *note: 1. cs is ignored when ras , cas and we are high at the same cycle. clk 012345678910111213141516171819 cke ras cas addr dq we dqm0 ~dqm3 raa caa cs a9 a8 qaa0 row active (a-bank) read command (a-bank) raa rbb cbb cac cbd qaa1 qaa2 qaa3 qbb0 qbb1 qbb2 qbb3 qae0 qae1 read command (a-bank) row active (b-bank) raa read command (b-bank) read command (a-bank) read command (b-bank) cae qac0 qac1 qbd0 qbd1 precharge command (a-bank) high l roh *note1
19 ? semiconductor MSM54V24632A bank interleave page write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we dqm0 ~dqm3 raa caa cs a9 a8 daa0 row active (a-bank) precharge command (both bank) raa rbb cbb cac cbd daa1 daa2 daa3 dbb0 dbb1 dbb2 dbb3 dac0 dac1 write command (a-bank) row active (b-bank) rab write command (b-bank) write command (a-bank) write command (b-bank) dbd0 high
21 MSM54V24632A ? semiconductor bank interleave random row read/write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we dqm0 ~dqm3 raa caa cs a9 a8 qaa0 row active (a-bank) raa rbb cbb rac qaa1 qaa2 qaa3 read command (a-bank) row active (b-bank) precharge command (a-bank) cac rac rbb dbb0 dbb1 dbb2 dbb3 qac0 qac1 qac2 qac3 write command (b-bank) row active (a-bank) read command (a-bank) high
21 ? semiconductor MSM54V24632A bank interleave page read/write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we dqm0 ~dqm3 caa0 qac3 cs cbb0 cac0 a9 a8 high read command (a-bank) write command (b-bank) read command (a-bank) dbb3 qaa3 qaa2 qaa1 qaa0 dbb2 dbb1 dbb0 qac2 qac1 qac0
23 MSM54V24632A ? semiconductor clock suspension & dqm operation cycle @ cas latency = 2, burst length = 4 *notes: 1. when cke is deactivated, the next clock cycle will be ignored. 2. when dqms are asserted, the read data after two clock cycles will be masked. 3. when dqms are asserted, the write data in the same clock cycle will be masked. 4. when dqm0 is set high, the input/output data of dq0 - dq7 will be masked. when dqm2 is set high, the input/output data of dq8 - dq15 will be masked. when dqm3 is set high, the input/output data of dq16 - dq23 will be masked. when dqm4 is set high, the input/output data of dq24 - dq31 will be masked. clock suspension clk 012345678910111213141516171819 cke ras cas addr dq0 - 7 we dqm1 ra cs ca cb a9 a8 row active qb1 qb0 read command read command read dqm write command clock suspension write dqm read dqm cc t ohz dc2 dc0 qa1 qa0 qa2 t ohz write dqm *note1 ? *note1 *note4 qb1 qb0 dc1 dc0 qa2 dq8 - 15 dqm0 *note4 qa0 qa3 *note2 *note3 ? read dqm ra
23 ? semiconductor MSM54V24632A read interruption by precharge command @ burst length = 8 *notes: 1. when cas latency = 1, and if row precharge is esserted before a burst read ends, then the read data will not output after the next clock cycle of precharge command. 2. if row precharge is asserted before burst read ends when cas latency = 2 or 3, then the read data will not output after the second clock cycle of the precharge command. we clk 012345678910111213141516171819 cke ras cas addr dq dqm0 ~dqm3 cs ca a9 a8 high row active read command precharge command qa3 qa2 qa1 qa0 dq dqm0 ~dqm3 dqm0 ~dqm3 cas latency = 1 dq cas latency = 3 cas latency = 2 qa4 qa3 qa2 qa1 qa0 qa4 qa3 qa2 qa1 qa0 qa4 ra qa5 qa5 *note1 *note2 *note2 ra
25 MSM54V24632A ? semiconductor power down mode @ cas latency = 2, burst length = 4 *notes: 1. when both banks are in precharge state, and if cke is set low, then the MSM54V24632A enters power- down mode and maintains the mode while cke is low. 2. to release the circuit from power-down mode, set cke high for longer than t pde , and the inputs will be set within the same cycle. clock suspention exit clk 012345678910111213141516171819 cke ras cas addr dq we dqm0 ~dqm3 cs a9 a8 qa2 qa1 qa0 t si t pde t si t si ra ca row active power-down entry power-down exit clock suspention entry read command precharge command *note1 *note2 t ref (min.) ra
25 ? semiconductor MSM54V24632A self refresh cycle clk 012 cke ras cas addr dq we dqm0 ~dqm3 cs a9 a8 t si t rc min. t pde hi - z hi - z self refresh entry self refresh exit row active ra ra bs
27 MSM54V24632A ? semiconductor mode register set cycle clk 012345 012345678910 cke ras cas addr dq we dqm0 ~dqm3 cs key ra mrs high high hi - z hi - z new command auto refresh t rc 6 11 12 l mrd auto refresh auto refresh cycle
27 ? semiconductor MSM54V24632A function truth table (table 1) (1/2) current state 1 cs ras cas we ba addr hxxxx x lhhhx x lhhlba x lhlxba ca l l h h ba ra l l h l ba a8 lllhx x llll op code hxxxx x lhhxx x lhlhba ca, a8 l h l l ba ca, a8 l l h h ba ra l l h l ba a8 lllxx x hxxxx x lhhhx x lhhlba x lhlhba ca, a8 l h l l ba ca, a8 l l h h ba ra l l h l ba a8 lllxx x hxxxx x lhhhx x lhhlba x lhlhba ca, a8 l h l l ba ca, a8 l l h h ba ra l l h l ba a8 hxxxx x lhhhx x lhhlba x lhlhba ca, a8 lhllx x l l h x ba ra, a8 lllxx x idle row active read write read with auto precharge hxxxx x lhhhx x lhhlba x lhlhba ca, a8 lhllx x l l h x ba ra, a8 lllxx x write with auto precharge action nop nop illegal 2 illegal 2 row active nop 4 auto-refresh or self-refresh 5 mode register write nop nop read write illegal 2 precharge illegal nop (continue row active after burst ends) nop (continue row active after burst ends) reserved term burst, start new burst read term burst, start new burst write illegal 2 term burst, execute row precharge illegal nop (continue row active after burst ends) nop (continue row active after burst ends) reserved (term burst) --> row active term burst, start new burst read term burst, start new burst write illegal 2 term burst, executo row precharge illegal nop (continue burst to end and enter row precharge) nop (continue burst to end and enter row precharge) illegal 2 illegal 2 illegal illegal 2 illegal nop (continue burst to end and enter row precharge) nop (continue burst to end and enter row precharge) illegal 2 illegal 2 illegal illegal 2 lllxx x illegal
29 MSM54V24632A ? semiconductor function truth table (table 1) (2/2) notes: 1. all inputs will be enabled when cke is set high for at least 1 cycle prior to the inputs. 2. illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. satisfy the timing of t ccd and t wr to prevent bus contention. 4. nop to bank precharging or in idle state. precharges activated bank by ba or a8. 5. illegal if any bank is not idle. current state 1 cs ras cas we ba addr hxxxx x lhhhx x lhhlba x lhlxba ca l l h h ba ra l l h l ba a8 lllxx x hxxxx x lhhhx x lhhlba x lhlxba ca l l h h ba ra l l h l ba a8 lllxx x hxxxx x lhhhx x lhhlba x lhlxba ca l l h h ba ra l l h l ba a8 lllxx x hxxxx x lhhxx x lhlxx x llhxx x lllxx x hxxxx x lhhhx x lhhlx x lhlxx x llxxx x precharge write recovery row active refresh mode register access action nop --> idle after t rp nop --> idle after t rp illegal 2 illegal 2 illegal 2 nop 4 illegal nop nop illegal 2 illegal 2 illegal 2 illegal 2 illegal nop --> row active after t rcd nop --> row active after t rcd illegal 2 illegal 2 illegal 2 illegal 2 illegal nop --> idle after t rc nop --> idle after t rc illegal illegal illegal nop nop illegal illegal illegal abbreviations ra = row address ba = bank address nop = no operation command ca = column address ap = auto precharge
29 ? semiconductor MSM54V24632A current state (n) cken-1 cs ras cas we addr h xxxx x l hxxx x l lhhh x llhhlx l lhlx x lllxxx l xxxx x h xxxx x l hxxx x l lhhh x llhhlx l lhlx x lllxxx l xxxx x h xxxx x h hxxx x h lhhh x hlhhlx h lhlx x h llhl x h lllh x h xxxx x h xxxx x l xxxx x l xxxx x self refresh 6 power down 6 all banks idle 7 any state other action invalid exit self refresh --> abi exit self refresh --> abi illegal illegal illegal nop (maintain self refresh) invalid exit power down --> abi exit power down --> abi illegal illegal illegal 7 nop (continue power down mode) refer to table 1 enter power down enter power down illegal illegal illegal enter self refresh refer to operations in table 1 begin clock suspend next cycle enaole clock of next cycle continue clock suspension cken x h h h h h l x h h h h h l h l l l l l l h l h l (abi) than listed above h llll x illegal l l xxxx x nop l function truth table for cke (table 2) notes: 6. if a minimam set-up time t pde is satisfied when cke transitions from "l" to "h", cke operates asynchronously so that a command can be input in the same internal clock cycle. 7. power-down and self refresh can be entered only when all the banks are in an idle state.

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