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dm4m32sj 4mb x 32 enhanced dram sim m product specification ?1996 enhanced memory systems inc., 1850 ramtron drive, colorado springs, co 80921 telephone (800) 545-dram; fax (719) 488-9095; http://www.csn.net/ramtron/enhanced 38-2110-002 the information contained herein is subject to change without notice. enhanced reserves the right to change or discontinue this product without notice. features n integrated 2,048 x 32 sram cache row register allows 12ns access random reads within the page n interleaved sram cache for 8ns burst reads n 30ns dram array for fast random access to any page n ultra-fast integrated 8kbyte-wide dram to cache bus for 454-gbyte/sec cache fill bandwidth n on-chip write posting and fast page mode operation allows 12ns writes and burst writes n on-board address and control buffering n low power self refresh mode option description the enhanced memory systems 16mb edram simm module provides a single memory module solution for the main memory or local memory of fast pcs, workstations, servers, and other high performance systems. due to its fast 12ns cache row register, the edram memory module supports zero-wait-state burst read operations at up to 66mhz bus rates in a non-interleave configuration and >100mhz bus rates with a two-way interleave configuration. on-chip write posting and fast page mode operation supports 12ns write and burst write operations. on a cache miss, the fast dram array reloads the entire 8kbyte cache over an 8kbyte-wide bus in 18ns for an effective bandwidth of 454 gbytes/sec. this means very low latency and fewer wait states on a cache miss than a non- integrated cache/dram solution. the jedec compatible simm configuration allows a single memory controller to be designed to support either jedec slow drams or high speed edrams to provide a simple upgrade path to higher system performance. architecture the dm4m32sj achieves 4mb x 32 density by mounting 32 4m x 1 edrams, packaged in 28-pin plastic soj packages on both sides of the multi- layer substrate. four buffers have been added to reduce the loading on the address and control lines. the buffers have balanced output current levels and current limiting resistors. these offer low ground bounce, minimal undershoot, and controlled fall times. the edram memory module architecture is very similar to a standard 16mb dram module with the addition of an integrated cache and on-chip control which allows it to operate much like a page mode or static column dram. the edram's sram cache is integrated into the dram array as tightly coupled row registers. memory reads always occur from the cache row register. when the on-chip comparator detects a page hit, only the sram is accessed and data is available in 12ns from column address. when a page read miss is detected, the entire new dram row is updated into the cache and data is available at the output all within a single 30ns access. subsequent reads within the page (burst reads, local instructions, or data) will continue at 12ns cycle time. since reads occur from the sram cache, dram precharge can occur simultaneously without degrading performance. the on-chip refresh counter with independent refresh bus allows the edram to be refreshed during cache reads. memory writes are internally posted in 12ns and directed to the dram array. during a write hit, the on-chip address comparator activates a parallel write path to the sram cache to maintain coherency. the edram delivers 12ns cycle page mode memory writes. memory writes do not affect the contents of the cache row register except during a cache hit. by integrating the sram cache as row registers in the dram array and keeping the on-chip control simple, the edram is able to provide superior performance over standard slow drams. cal a 0-10 w/r f v v sense amps & column write select column decoder row add latch cc ss pd pd16m 2048 x 32 cache (row register) memory array 16mbyte g s we dq 0-31 column add latch 11-bit comp last row read add latch i/o control and data latches refresh counter row decoder row add and refresh control 0-3 re 0,2 a 0-10 a 0-9 c 1-36 dm4m32sj functional diagram enhanced memory systems inc.
1-106 function /s low power standby h /re w/r /f a 0-10 comment h x x x low power self refresh option h x h x internal refresh x x l x read miss l l h row 1 lrr dram row to cache write hit l h h row = lrr write to dram and cache, reads enabled write miss l h h row 1 lrr write to dram, cache not updated, reads disabled cache reads enabled standby current standby current, internal refresh clock read hit l l h /cal h l x h h h h /we h unallowed mode h l x h x unallowed mode (except -l option) x x h x x h h x row = lrr no dram reference, data in cache h = high; l = low; x = don? care; = high-to-low transition; lrr = last row read edram basic operating modes functional description the edram is designed to provide optimum memory performance with high speed microprocessors. as a result, it is possible to perform simultaneous operations to the dram and sram cache sections of the edram. this feature allows the edram to hide precharge and refresh operation during sram cache reads and maximize sram cache hit rate by maintaining valid cache contents during write operations even if data is written to another memory page. these new functions, in conjunction with the faster basic dram and cache speeds of the edram, minimize processor wait states. edram basic operating modes the edram operating modes are specified in the table below . hit and miss t er minology in this datasheet, ?it?and ?iss?always refer to a hit or miss to the page of data contained in the sram cache row register . this is always equal to the contents of the last row that was read from (as modified by any write hit data). w riting to a new page does not cause the cache to be modified. dram read hit if a dram read request is initiated by clocking /re with w/r low and /f and /cal high, the edram will compare the new row address to the last row read address latch (lrr; an 11-bit latch loaded on each /re active read cycle). if the row address matches the lrr, the requested data is already in the sram cache and no dram memory reference is initiated. the data specified by the column address is available at the output pins at the greater of times t ac or t gqv . since no dram activity is initiated, /re can be brought high after time t re1 , and a shorter precharge time, t rp1 , is required. it is possible to access additional sram cache locations by providing new column addresses to the multiplex address inputs. new data is available at the output at time t ac after each column address change in static column mode. during read cycles, it is possible to operate in either static column mode with /cal=high or page mode with /cal clocked to latch the column address. in page mode, data valid time is determined by either t ac or t cqv . dram read miss if a dram read request is initiated by clocking /re with w/r low and /f and /cal high, the edram will compare the new row address to the lrr address latch (an 11-bit latch loaded on each /re active read cycle). if the row address does not match the lrr, the requested data is not in sram cache and a new row must be fetched from the dram. the edram will load the new row data into the sram cache and update the lrr latch. the data at the specified column address is available at the output pins at the greater of times t rac , t ac , and t gqv . it is possible to bring /re high after time t re since the new row data is safely latched into sram cache. this allows the edram to precharge the dram array while data is accessed from sram cache. it is possible to access additional sram cache locations by providing new column addresses to the multiplex address inputs. new data is available at the output at time t ac after each column address change in static column mode. during read cycles, it is possible to operate in either static column mode with /cal=high or page mode with /cal clocked to latch the column address. in page mode, data valid time is determined by either t ac or t cqv . dram w rite hit if a dram write request is initiated by clocking /re while w/r and /f are high, the edram will compare the new row address to the lrr address latch (an 11-bit address latch loaded on each /re active read). if the row address matches, the edram will write data to both the dram array and selected sram cache simultaneously to maintain coherency . the write address and data are posted to the dram as soon as the column address is latched by bringing /cal low and the write data is latched by bringing /we low (both /cal and /we must be high when initiating the write cycle with the falling edge of /re). the write address and data can be latched very quickly after the fall of /re (t rah + t asc for the column address and t ds for the data). during a write burst sequence, the second write data can be posted at time t rsw after /re. subsequent writes within a page can occur with write cycle time t pc . with /g enabled and /we disabled, it is possible to perform cache read operations while the /re is activated in write hit mode. this allows read-modify- write, write-verify , or random read-write sequences within the page with 12ns cycle times (the first read cannot complete until after time t rac2 ). at the end of a write sequence (after /cal and /we are brought high and t re is satisfied), /re can be brought high to
precharge the memory . it is possible to perform cache reads concurrently with precharge. during write sequences, a write operation is not performed unless both /cal and /we are low . as a result, the /cal input can be used as a byte write select in multi- chip systems. if /cal is not clocked on a write sequence, the memory will perform a /re only refresh to the selected row and data will remain unmodified. dram w rite miss if a dram write request is initiated by clocking /re while w/r and /f are high, the edram will compare the new row address to the lrr address latch (an 11-bit latch loaded on each /re active read cycle). if the row address does not match, the edram will write data to the dram array only and contents of the current cache is not modified. the write address and data are posted to the dram as soon as the column address is latched by bringing /cal low and the write data is latched by bringing /we low (both /cal and /we must be high when initiating the write cycle with the falling edge of /re). the write address and data can be latched very quickly after the fall of /re (t rah + t asc for the column address and t ds for the data). during a write burst sequence, the second write data can be posted at time t rsw after /re. subsequent writes within a page can occur with write cycle time t pc . during a write miss sequence, cache reads are inhibited and the output buffers are disabled (independently of /g) until time t wrr after /re goes high. at the end of a write sequence (after /cal and /we are brought high and t re is satisfied), /re can be brought high to precharge the memory . it is possible to perform cache reads concurrently with the precharge. during write sequences, a write operation is not performed unless both /cal and /we are low . as a result, /cal can be used as a byte write select in multi-chip systems. if /cal is not clocked on a write sequence, the memory will perform a /re only refresh to the selected row and data will remain unmodified. /re inactive operation it is possible to read data from the sram cache without clocking /re. this option is desirable when the external control logic is capable of fast hit/miss comparison. in this case, the controller can avoid the time required to perform row/column multiplexing on hit cycles. this capability also allows the edram to perform cache read operations during precharge and refresh cycles to minimize wait states. it is only necessary to select /s and /g and provide the appropriate column address to read data as shown in the table below . the row address of the sram cache accessed without clocking /re will be specified by the lrr address latch loaded during the last /re active read cycle. t o perform a cache read in static column mode, /cal is held high, and the cache contents at the specified column address will be valid at time t ac after address is stable. t o perform a cache read in page mode, /cal is clocked to latch the column address. the cache data is valid at time t ac after the column address is setup to /cal. on-chip sram interleave the dm4m32 has an on-chip interleave of its sram cache which allows 8ns random accesses (t ac1 ) for up to three data words (burst reads) following an initial read access (hit or miss). the sram cache is integrated into the dram arrays in a 512 x 128 organization. it is converted into a 2k x 32 page organization by using an on-chip address multiplexer to select one of four 32-bit words to the output pins dq 0-31 (as shown below). the specific word selected to the output is determined by column addresses a o and a 1 . system operation is consistent with the standard ?unctional description?and timing diagrams shown in this specification. see the note in the read timing diagrams and ?witching characteristics?chart for the faster access and data hold times. inter nal refr esh if /f is active (low) on the assertion of /re, an internal refresh cycle is executed. this cycle refreshes the row address supplied by an internal refresh counter . this counter is incremented at the end of the cycle in preparation for the next /f refresh cycle. at least 1,024 /f cycles must be executed every 64ms. /f refresh cycles can be hidden because cache memory can be read under column address control throughout the entire /f cycle. /f cycles are the only active cycles during which /s can be disabled. /cal befor e /re refr esh (?cas befor e /ras? /cal before /re refresh, a special case of internal refresh, is discussed in the ?educed pin count operation?section below . /re only refr esh operation although /f refresh using the internal refresh counter is the recommended method of edram refresh, it is possible to perform an /re only refresh using an externally supplied row address. /re refresh is performed by executing a write cycle (w/r and /f are high) where /cal is not clocked. this is necessary so that the current cache contents and lrr are not modified by the refresh operation. all combinations of addresses a 0 , a 2 - a 10 must be sequenced every 64ms refresh period. a 1 does not need to be cycled. read refresh cycles are not allowed because a dram refresh cycle does not occur when a read refresh address matches the lrr address latch. 1-107 function /s /g /cal a 0-10 cache read (static column) l h column address cache read (page mode) l column address h = high; l = low; x = don? care; = transitioning l l dm4m32 datapath ar chitectur e 65,538 bits 128 bits 32 bits q row address a 0-10 column address a 2-10 column address a 0, a 1 32 4m dram arrays 32 2k sram caches 4 to 1 output selector
1-108 low power self refr esh when the low power , self-refresh option is specified when ordering the edram, the edram enters this mode when /re is clocked while /s, w/r, /f , and /we are high; and /cal is low . in this mode, the power is turned off to all i/o pins except /re to minimize chip power and an on-board refresh clock is enabled to perform self-refresh cycles using the on-board refresh counter . the edram remains in this low power mode until /re is brought high again to terminate the mode. the edram /re input must remain high for t rp2 following exit from self-refresh mode to allow any on-going internal refresh to terminate prior to the next memory operation. low power mode the edram enters its low power mode when /s is high. in this mode, the internal dram circuitry is powered down to reduce standby current to 34ma. initialization cycles a minimum of 10 initialization (start-up) cycles are required before normal operation is guaranteed. a combination of eight /f refresh cycles and two read cycles to different row addresses are necessary to complete initialization. /re must be high for 300ns prior to initialization. unallowed mode read, write, or /re only refresh operations must not be initiated to unselected memory banks by clocking /re when /s is high. reduced pin count operation it is possible to simplify the interface to the 16 mbyte simm to reduce the number of control lines. /reo and /re2 could be tied together externally to provide a single row enable. w/r and /g can be tied together if reads are not performed during write hit cycles. this external wiring simplifies the interface without any performance impact. pin descriptions /re 0, 2 ?row enable these inputs are used to initiate dram read and write operations and latch a row address as well as the states of w/r and /f . it is not necessary to clock /re 0, 1 to read data from the edram sram row registers. on read operations, /re 0, 1 can be brought high as soon as data is loaded into cache to allow early precharge. /reo controls bytes 1 and 2. /re2 controls bytes 3 and 4. /cal 0 -3 ?column addr ess latch these inputs are used to latch the column address and in combination with /we to trigger write operations. when /cal is high, the column address latch is transparent. when /cal is low , the column address is closed and the output of the latch contains the address present while /cal was high. /cal can be toggled when /re is low or high. however , /cal must be high during the high-to- low transition of /re except for /f refresh cycles. /cal 0-3 controls bytes 1-4 respectively . w/r ?w rite/read this input along with /f specifies the type of dram operation initiated on the low going edge of /re. when /f is high, w/r specifies either a write (logic high) or read operation (logic low). /f ?refr esh this input will initiate a dram refresh operation using the internal refresh counter as an address source when it is low on the low going edge of /re. /we ?w rite enable this input controls the latching of write data on the input data pins. a write operation is initiated when both /cal and /we are low . /g ?output enable this input controls the gating of read data to the output data pins during read operations. /s ?chip select this input is used to power up the i/o and clock circuitry . when /s is high, the edram remains in its low power mode. /s must remain active throughout any read or write operation. with the exception of /f refresh cycles, /re 0,2 should never be clocked when /s is inactive. dq 0 -31 ?data input/output these bidirectional pins are used to read and write data to the edram. pd ?pr esence detect this signal is grounded to indicate the presence of simm module in the socket. pd16m ?16m pr esence detect this signal is grounded to indicate the presence of a 16m simm. a 4 or 8 mb simm has this pin open. a 0-10 ?multiplex addr ess these inputs are used to specify the row and column addresses of the edram data. the 11-bit row address is latched on the falling edge of /re. the 11-bit column address can be specified at any other time to select read data from the sram cache or to specify the write column address during write cycles. a 0,1 are used to select one of four interleaved data words during read operations. v cc power supply these inputs are connected to the +5 volt power supply . v ss gr ound these inputs are connected to the power supply ground connection.
1-109 pin no. function 1 gnd organization ground 2 3 4 byte 1 i/o 2 5 6 byte 1 i/o 3 7 8 byte 1 i/o 4 9 10 +5 volts 11 +5 volts 12 address 13 14 15 16 17 18 address 19 20 21 22 23 24 25 byte 3 i/o 7 26 byte 1 i/o 8 27 byte 3 i/o 8 28 address 29 gnd ground 30 +5 volts 31 address 32 address 33 nc not connected 34 35 36 a 9 row enable (bytes 3, 4) 37 38 39 gnd 40 byte 1 column address latch 41 byte 3 column address latch 42 byte 4 column address latch 43 byte 2 column address latch 44 row enable (bytes 1, 2) 45 not connected 46 ground 47 48 write enable 49 byte 2 i/o 1 50 byte 4 i/o 1 51 byte 2 i/o 2 52 byte 4 i/o 2 53 byte 2 i/o 3 54 byte 4 i/o 3 55 56 byte 4 i/o 4 57 byte 2 i/o 5 58 byte 4 i/o 5 59 +5 volts 60 byte 4 i/o 6 61 byte 2 i/o 6 62 byte 4 i/o 7 63 byte 2 i/o 7 64 byte 4 i/o 8 65 byte 2 i/o 8 66 +5 volts 67 68 69 s 70 pd signal gnd signal gnd 71 gnd 72 g ground we gnd f output enable refresh mode control chip select presence detect ground pin no. function organization byte 1 i/o 5 byte 3 i/o 5 byte 1 i/o 6 byte 1 i/o 7 byte 3 i/o 6 ground byte 2 i/o 4 ground byte 1 i/o 1 byte 3 i/o 1 byte 3 i/o 2 byte 3 i/o 3 byte 3 i/o 4 v cc v cc a 0 address a 1 address a 2 a 3 address address a 4 address a 5 address v cc ground ground v cc a 6 a 7 a 8 v cc a 10 v cc dq 0 dq 18 dq 1 dq 19 dq 2 dq 20 dq 3 dq 21 dq 4 dq 22 dq 5 dq 23 dq 6 dq 24 dq 7 dq 25 re 2 gnd gnd dq 16 dq 34 dq 15 dq 33 dq 14 dq 32 dq 31 dq 13 dq 30 dq 12 dq 29 dq 11 dq 28 dq 10 dq 27 dq 9 pd16m re 0 cal 1 cal 3 cal 2 cal 0 gnd +5 volts w/r mode control w/r nc pinout
1-110 edge connecter edge connecter a9 2 a0b1 3 a0b2 5 a0b3 32 19 a10 6 a1b1 8 a1b2 9 a1b3 14 a2 11 a2b1 12 a2b2 13 a2b3 15 a3 14 a3b1 16 a3b2 17 a3b3 16 a4 19 a4b1 20 a4b2 22 a4b3 17 a5 2 a5b1 3 a5b2 5 a5b3 18 a6 6 a6b1 8 a6b2 9 a6b3 28 a7 11 a7b1 12 a7b2 13 a7b3 31 a8 14 a8b1 16 a8b2 17 a8b3 12 a0 19 a9b1 20 a9b2 22 a9b3 23 a9b4 13 a1 2 a10b1 3 a10b2 5 a10b3 6 a10b4 48 w/r 8 w/rb1 u33a2 u33a3 u33a4 u15a1 u15a2 u15a3 u14a4 u15a4 u15a4 u15a4 u14a1 u14a1 u32a3 u32a2 u32a2 u32a3 u32a1 u32a2 u32a2 u32a1 u14a4 u14a3 u33a1 u14a2 u14a2 u14a3 u32a4 u15a4 9 w/rb2 11 w/rb3 12 w/rb4 47 /we 13 /web1 14 /web2 16 /web3 17 /web4 68 /f 19 /fb1 20 /fb2 22 /fb3 23 /fb4 69 /s 2 /sb1 3 /sb2 5 /sb3 6 /sb4 44 /re0 34 /re2 8 /re0b1 9 /re0b2 11 /re0b3 12 /re0b4 40 /cal0 /cal0b 13 /re2b1 14 /re2b2 16 /re2b3 17 /re2b4 43 /cal1 /cal1b 41 /cal2 /cal2b 42 /cal3 /cal3b 67 /g /gb 26 30 29 27 26 19 20 22 23 23 41 29 30 27 26 47 46 44 43 38 37 36 35 33 32 30 29 27 47 46 44 43 41 40 38 37 36 35 33 32 47 46 44 43 41 40 40 37 35 36 33 32 30 29 26 47 46 44 43 41 40 38 37 36 33 32 35 27 38 note: address and control buffers add minimum of 1.7ns to maximum of 4.5ns to each signal path. u14, 15, 32, 33 pins 1, 4, 10, 21, 24, 25, 28, 34, 39, 45, 48 - gnd. u14, 15, 32, 33, pins 7, 18, 31, 42, - vcc buf fer diagram
1-111 dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 w/r /we /f /s /g d q /cal /cal /cal /cal /cal /cal /cal /cal vcc vcc vcc vss vss vss 7 14 22 8 21 28 16 16 16 16 16 16 16 16 1 2 12 3 4 5 9 10 11 13 15 17 20 18 19 23 a0b1 a1b1 a2b1 a3b1 a4b1 a5b1 a6b1 a7b1 a8b1 a9b1 a10b1 /re0b1 /re0b2 w/rb1 /web1 /fb1 /sb1 /gb /cal0b vcc vcc vcc vcc vcc vcc vss vss vss vss vss pd +5v 10 11 30 37 59 66 1 29 vss 35 vss 36 vss 38 39 71 72 70 pd16m 46 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 26 24 22 20 8 6 4 2 j1 edge connecter +5v /re /re /re /re /re /re /re c1 c2 c3 c4 c5 c6 c7 c8 c9 /re 6 6 6 6 6 6 6 6 dq0 d q dq1 d q dq2 d q dq3 d q dq4 d q dq5 d q dq6 d q dq7 26 27 26 27 26 27 26 27 26 27 26 27 26 27 26 27 u1 u2 u3 u4 u5 u6 u7 u8 inter connect diagram ?byte 1
1-112 dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 w/r /we /f /s /g d q /cal1 /cal1 /cal1 /cal1 /cal1 /cal1 /cal1 /cal1 vcc vcc vcc vss vss vss 7 14 22 8 21 28 16 16 16 16 16 16 16 16 1 2 12 3 4 5 9 10 11 13 15 17 20 18 19 23 a0b1 a1b1 a2b1 a3b1 a4b1 a5b1 a6b1 a7b1 a8b1 a0 a1 a2 a3 a4 a5 a6 a7 a8 1 2 12 3 4 5 9 10 11 a0b2 a1b2 a2b2 a3b2 a4b2 a5b2 a6b2 a7b2 a8b2 a9b2 a10b2 w/rb2 /web2 /fb2 /sb2 /gb dq16 dq15 dq14 dq13 dq12 dq11 dq10 dq9 65 63 61 57 55 53 51 49 j1 edge connecter +5v /re /re /re /re /re /re /re c10 c11 c12 c13 c14 c15 c16 c17 c18 /re 6 6 6 6 6 6 6 6 dq9 d q d q d q dq12 d q dq13 d q dq14 d q dq15 d q dq16 26 27 26 27 26 27 26 27 26 27 26 27 26 27 26 27 dq10 dq11 vcc vcc vcc vcc vcc vcc vss vss vss vss vss pd +5v 10 11 30 37 59 66 1 29 vss 35 vss 36 vss 38 39 71 72 70 pd16m 46 /re0b3 /re0b4 /cal1b u9 u10 u11 u25 u26 u27 u28 u29 inter connect diagram ?byte 2
1-113 dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 w/r /we /f /s /g d q /cal2 /cal2 /cal2 /cal2 /cal2 /cal2 /cal2 /cal2 vcc vcc vcc vss vss vss 7 14 22 8 21 28 16 16 16 16 16 16 16 16 1 2 12 3 4 5 9 10 11 13 15 17 20 18 19 23 a0b2 a1b2 a2b2 a3b2 a4b2 a5b2 a6b2 a7b2 a8b2 a9b3 a10b3 w/rb3 /web3 /fb3 /sb3 /gb dq25 dq24 dq23 dq22 dq21 dq20 dq19 dq18 25 24 23 21 9 7 5 3 j1 edge connecter +5v /re /re /re /re /re /re /re c19 c20 c21 c22 c23 c24 c25 c26 c27 /re 6 6 6 6 6 6 6 6 dq18 d q dq19 d q dq20 d q dq21 d q d q d q dq24 d q dq25 26 27 26 27 26 27 26 27 26 27 26 27 26 27 a1 a2 a3 a4 a5 a6 a7 a8 1 2 12 3 4 5 9 10 11 a0b3 a1b3 a2b3 a3b3 a4b3 a5b3 a6b3 a7b3 a8b3 26 27 dq23 dq22 vcc vcc vcc vcc vcc vcc vss vss vss vss vss pd +5v 10 11 30 37 59 66 1 29 vss 35 vss 36 vss 38 39 71 72 70 pd16m 46 /re2b1 /re2b2 /cal2b u19 u20 u21 u22 u23 u24 u34 u16 inter connect diagram ?byte 3
1-114 dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram u35 u17 u36 u18 u30 u12 u31 u13 dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram dm2200j 4mb x 1 edram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 w/r /we /f /s /g d q /cal3 /cal3 /cal3 /cal3 /cal3 /cal3 /cal3 /cal3 vcc vcc vcc vss vss vss 7 14 22 8 21 28 16 16 16 16 16 16 16 16 1 2 12 3 4 5 9 10 11 13 15 17 20 18 19 23 a0b3 a1b3 a2b3 a3b3 a4b3 a5b3 a6b3 a7b3 a8b3 a9b4 a10b4 w/rb4 /web4 /fb4 /sb4 /gb dq34 dq33 dq32 dq31 dq30 dq29 dq28 dq27 64 62 60 58 56 54 52 50 j1 edge connecter +5v /re /re /re /re /re /re /re c28 c29 c30 c31 c32 c33 c34 c35 c36 /re 6 6 6 6 6 6 6 6 dq27 d q dq28 d q dq29 d q dq30 d q dq31 d q dq32 d q dq33 d q dq34 26 27 26 27 26 27 26 27 26 27 26 27 26 27 26 27 vcc vcc vcc vcc vcc vcc vss vss vss vss vss pd +5v 10 11 30 37 59 66 1 29 vss 35 vss 36 vss 38 39 71 72 70 pd16m 46 /re2b3 /re2b4 /cal3b inter connect diagram ?byte 4
1-115 r = 828 1 5ns v gnd 5.0v w output c = 50pf l r = 295 2 load circuit input waveforms w 5ns il v il v ih v ih ambient operating temperature (t ) description ratings in output voltage (v ) power supply voltage (v ) storage temperature (t ) static discharge voltage (per mil-std-883 method 3015) short circuit o/p current (i ) cc out a s out - 1 ~ 7v - 1 ~ 7v input voltage (v ) - 1 ~ 7v 0 ~ 70? -55 ~ 150? class 1 50ma* description max pins input capacitance input capacitance 39pf 29pf a 0-10 0-3 dq 0-31 /g, /cal input/output capacitance 18pf /re , /re , w/r, /we, /f, /s 0 2 input capacitance 19pf symbol parameters min max test conditions v cc supply voltage 4.75v 5.25v all voltages referenced to v ss v v i i v ih il i(l) o(l) oh v ol ov v 6.5v, all other pins not under test = 0v in ov v , ov v 5.5v out i = - 5ma out i = 4.2ma 6.5v 0.8v 40? 0.4v 20? 2.4v -1.0v 40? 20? 2.4v input high voltage input low voltage input leakage current output leakage current output high level output low level in out symbol operating current -15 max test condition i cc1 random read /re, /cal, /g and addresses cycling: t = t minimum c all control inputs stable v - 0.2v, outputs driven cc cc 0-10 ss /re, /cal, /we and addresses cycling: t = t minimum c /cal, /we and addresses cycling: t = t minimum 4960ma 3840ma 36ma 4640ma fast page mode read static column read standby random write fast page mode write pc 7520ma i cc2 i cc3 i cc4 i cc5 i cc6 6400ma 33mhz typ 2400ma 2080ma 36ma 1920ma 3840ma 4640ma c notes 2, 3 2, 4 2, 4 2, 3 2, 4 /cal, /g and addresses cycling: t = t minimum pc pc /g and addresses cycling: t = t minimum sc sc c pc 3 < 3 (1) ?3mhz typ?refers to worst case i cc expected in a system operating with a 33mhz memory bus. in this typical example , page mode and random reads refers to page burst hits and misses. writes are two clock cycle random and page mode writes. see power applications note for further details. this parameter is not 100% tested or gua ranteed. -12 max 7520ma 4960ma 3840ma 36ma /s, /f, w/r, /we and a at v - 0.2v, /re and /cal at v + 0.2v, i/o option 6.4ma self-refresh (-l option) i cc7 6.4ma 6.4ma 1280ma 1280ma 6400ma 4640ma see ?stimating edram operating power?application note average typical operating current i cct 1280ma 1 (1) (2) i cc is dependent on cycle rates and is measured with cmos levels and the outputs op en. (3) i cc is measured with a maximum of one address change while /re = v il . (4) i cc is measured with a maximum of one address change while /cal = v ih . ac t est load and w avefor ms electrical characteristics absolute maximum ratings (beyond which permanent damage could result) capacitance
1-116 switching characteristics v cc = 5v + 5%, t a = 0 - 70 o c, c l = 50pf note: these parameters do not include address and control buffer delays. see page 1-110 for derating factor . symbol description t ac (1) t asc t asr t c t c1 t cae t cah t ch t cqv t crp t cwl t dh t ds t gqv (1) t gqx (2,3) column address access time for addresses a 2-10 column address setup time row enable cycle time row enable cycle time, cache hit (row=lrr), read cycle only row address setup time column address latch active time column address hold time column address latch high time (latch transparent) column address latch high to data valid column address latch inactive to data invalid for addresses a 0-8 column address latch setup time to row enable /we low to /cal inactive data input hold time data input setup time output enable access time output enable to output drive time 5 5 55 20 5 5 5 5 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min max units 12 5 0 15 0 5 t aqx column address change to output data invalid for addresses a 0-8 ns 5 t ach column address valid to /cal inactive (write cycle) ns 12 t ca address cycle time (cache hits) ns 12 5 5 5 65 25 5 5 5 5 0 5 min max 15 6 0 17 0 5 5 15 15 5 -12 -15 t cqx t nrs t pc t rac (1) t rac1 (1) t rah output turn-off delay from output disabled (/g - ) /cal, /g, and /we setup time for /re-only refresh column address latch cycle time row address hold time row enable access time, on a cache miss t nrh /cal, /g, and /we hold time for /re-only refresh t msu /f and w/r mode select setup time t mh /f and w/r mode select hold time ns 0 5 0 5 ns 0 0 ns 5 5 ns 0 0 ns 5 5 ns 12 15 ns 30 35 ns 1.5 t gqz (4,5) t rac2 (1,6) row enable access time for a cache write hit ns 30 35 1 t chr /cal inactive lead time to /re inactive (write cycles only) -2 ns -2 t chw column address latch high to write enable low (multiple writes) 0 ns 0 t ac1 (1) column address access time for addresses a 0 and a 1 ns 8 8 t aqx1 column address change to output data invalid for addresses a 9 and a 10 ns 1 1 column address latch inactive to data invalid for addresses a 9 and a 10 1 ns 1 t cqx1 row enable access time, on a cache hit (limit becomes t ac ) 15 17 ns
1-117 switching characteristics (continued) v cc = 5v + 5%, t a = 0 - 70 o c, c l = 50pf note: these parameters do not include address and control buffer delays. see page 1-110 for derating factor . symbol description t rgx t rp (7) t rp1 t rrh t rsh t output enable don't care from row enable (write, cache miss), o/p hi z row precharge time row precharge time, cache hit (row=lrr) read cycle read hold time from row enable (write only) last write address latch to end of write row enable to column address latch low for second write 9 20 8 0 ns ns ns ns ns ns min max units 35 25 t rqx1 row enable high to output turn-on after write miss ns 12 15 10 0 t rp2 row precharge time, self-refresh mode 100 ns 100 min max 10 40 -12 -15 12 15 rsw ns t sc column address cycle time ns 12 15 t shr select hold from row enable ns 0 0 t sqv (1) chip select access time ns 12 15 t sqx (2,3) output turn-on from select low ns 12 15 0 0 output turn-off from chip select ns 8 10 0 0 t ssr select setup time to row enable ns 5 5 t t transition time (rise and fall) ns 10 10 1 1 t wc write enable cycle time ns 12 15 t wch column address latch low to write enable inactive time ns 5 5 t wi write enable inactive time ns 5 5 t wp t wrp write enable active time write enable setup time to row enable write to read recovery (cache miss) 16 ns ns ns 5 data turn-off from write enable low ns t wqx (2,5) data output turn-on from write enable high ns 0 t wqv (1) data valid from write enable high ns 18 5 0 12 5 5 15 12 15 0 0 12 15 t re1 t ref row enable active time, cache hit (row=lrr) read cycle refresh period ms 64 64 8 10 ns t whr write enable hold after /re ns 0 0 t sqz (4,5) t wqz (3,4) t re row enable active time ns 30 100000 35 100000 t rwl last write enable to end of write ns 12 15 t wrr (1) v out timing reference point at 1.5v (2) parameter defines time when output is enabled (sourcing or sinking current) and is not referenced to v oh or v ol (3) minimum specification is referenced from v ih and maximum specification is referenced from v il on input control signal (4) parameter defines time when output achieves open-circuit condition and is no t referenced to v oh or v ol (5) minimum specification is referenced from v il and maximum specification is referenced from v ih on input control signal (6) access parameter applies when /cal has not been asserted prior to t rac2 (7) for back-to-back /f refreshes, t rp = 40ns. for non-consecutive /f refreshes, t rp = 25ns and 32ns respectively.
/re 0, 2 /f w/r a 0-10 /cal 0-3 /g /s column 1 t sc t sc data 1 open t gqz t gqx t gqv t sqv t sqx t sqz dq 0-31 don? care or indeterminate /we column 2 column 3 column 4 data 2 data 3 data 4 ac t t aqx t aqx ac t t aqx ac t ac t t sc notes: 1. data accessed during /re inactive read is from the row address specified during the last /re active read cycle. if column address 2, 3, or 4 modifies only address pin a 0 or a 1 , then t ac becomes t ac1 for data 2, 3, and 4, and t aqx becomes t aqx1 for data 1, 2, and 3. 2. 1-118 /re inactive cache read hit (static column mode)
/re 0, 2 /f w/r a 0-10 /cal 0-3 /g /s t cah column 1 column 2 t asc t cah t ch t cae t pc t cqv t ac t cqx data 1 open data 2 t gqz t gqx t gqv t ac t sqz t sqv t sqx row t asc dq 0-31 /we don? care or indeterminate notes: 1. 2. data accessed during /re inactive read is from the row address specified during the last /re active read cycle. if column address 2 modifies only address pin a 0 or a 1 , then t ac becomes t ac1 for data 2 and t cqx becomes t cqx1 for data 1. 1-119 /re inactive cache read hit (page mode)
/re 0, 2 t c1 row open /f w/r a 0-10 /cal 0-3 /g /s t re1 t msu t mh t rp1 t asr t rah column 1 t crp t rac1 data 1 t gqz t gqx t gqv t ssr t sqz t shr t mh t msu dq 0-31 don? care or indeterminate /we column 2 column 3 column 4 data 2 data 3 data 4 ac t t aqx t aqx ac t t aqx ac t ac t notes: 1. if column address 2, 3, or 4 modifies only address pin a 0 or a 1 , then t ac becomes t ac1 for data 2, 3, and 4, and t aqx becomes t aqx1 for data 1, 2, and 3. t sc t sc t sc /re active cache read hit (static column mode) 1-120
/re 0, 2 t c1 row /f w/r a 0-10 /cal 0-3 /g /s t re1 t msu t mh t rp1 t asr t rah t cah column 1 column 2 t crp t asc t cah t ch t cae t pc t cqv t ac t rac1 t cqx data 1 open data 2 t gqz t gqx t gqv t ac t ssr t sqz t shr t mh t msu row t asc dq 0-31 /we don? care or indeterminate notes: 1. if column address 2 modifies only address pin a 0 or a 1 , then t ac becomes t ac1 for data 2 and t cqx becomes t cqx1 for data 1. 1-121 /re active cache read hit (page mode)
w/r t c column 1 t re t rp t msu t msu t asr t mh t mh t rah t crp t aqx t ac t ac t rac t aqx row column 2 row open data 1 data 2 t gqx t gqv t gqz t ssr t sqz t shr dq 0-31 /re /f a 0-10 /cal 0-3 /g /s /we t sc don? care or indeterminate notes: 1. if column address 2 modifies only address pin a 0 or a 1 , then t ac becomes t ac1 for data 2, and t aqx becomes t aqx1 for data 1. 0, 2 1-122 /re active cache read miss (static column mode)
/re 0, 2 t c1 row /f w/r a 0-10 /cal 0-3 /g /s t re1 t msu t mh t rp1 t asr t rah t cah column 1 column 2 t crp t asc t cah t ch t cae t pc t cqv t ac t rac1 t cqx data 1 open data 2 t gqz t gqx t gqv t ac t ssr t sqz t shr t mh t msu row t asc dq 0-31 /we don? care or indeterminate notes: 1. if column address 2 modifies only address pin a 0 or a 1 , then t ac becomes t ac1 for data 2 and t cqx becomes t cqx1 for data 1. 1-123 /re active cache read miss (page mode)
w/r t re column 1 t msu t msu t asr t mh t mh t rah t rsw column 2 row column n t crp t cah t asc t cwl t cae t cwl t rsh t cae t wrp t wp t rrh t wch t wch t pc t wp t rwl t dh t dh t ds t ds t ac t wrr t gqx t rqx1 t gqv t ssr 10 a - a 0 data 1 data 2 t ach t ach t ch t whr t wi t wc cache (column n) open dq 0-31 /re 0, 2 /f /cal 0-3 /g /s /we t chw t rp t chr a 0-10 t cah don? care or indeterminate notes: 1. /g becomes a don? care after t rgx during a write miss. t mh 1-124 burst w rite (hit or miss) followed by /re inactive cache reads
1-125 /re 0, 2 /f w/r a 0-10 /cal 0-3 /we /g t re /s column 1 t msu t msu t asr t mh t mh t rah column 2 row column 3 t wrp t cqx t gqx t ssr dq 0-31 read data t whr t c t rp notes: 1. if column address 2 modifies only address pin a 0 or a 1 , then t aqx becomes t aqx1 . t crp t cae t ach t asc t rsh t wch t rrh t cqv t wp t cwl read data t rac2 t ac t aqx t ds t rwl t wqv t gqv t gqz t dh t gqz t gqv t wqx write data t chr don? care or indeterminate t cah t ac page read/w rite during w rite hit cycle (can include read-modify-w rite)
1-126 /re 0, 2 /f t re t msu t mh don? care or indeterminate notes: 1. 2. during /f refresh cycles, the status of w/r, /we, a 0-10 , /cal, /s, and /g is a don? care. /re inactive cache reads may be performed in parallel with /f refresh cycles. t rp t c w/r, /f t re t rp t asr t rah row t nrs t nrh t ssr t shr t msu t mh /re 0, 2 a 0-10 0-3 /cal , /we, /g /s don? care or indeterminate notes: 1. all binary combinations of a 0 , a 2-10 must be refreshed every 64ms interval. a 1 does not have to be cycled, but must remain valid during row address setup and hold times. 2. /re refresh is write cycle with no /cal active cycle. /f refr esh cycle /re-only refr esh
1-127 /f, w/r, /we, /s t rp2 t msu t mh t msu t mh /re don? care or indeterminate notes: 1. edram self refreshes as long as /re remains low. (low power self refresh part on ly). 2. when using the low power self refresh mode the following operations must be perf ormed: if row addresses are being refreshed in an evenly distributed manner over the refresh interval using /f refresh cycles, then at least one /f refresh cycle must be performed immediately after exit from the low power self refesh mode. if row addresses are being refreshed in any other manner (/f burst or /re distri buted or burst), then all rows must be refreshed immediately befor entry to and immediately after exit from the low power self refresh. a 0-10 0,2 /cal low power self-refr esh mode option
1-128 dm4m32sj -12l dynamic memory memory depth (megabits) i/o width (including parity) packaging system j = 300 mil, plastic soj memory module configuration s = simm 32 = 32 bits 4m access time from cache in nanoseconds 12ns 15ns no designator = 0 to 70 o c (commercial) l= 0 to 70 o c, low power self refresh option lower power, self refresh option par t numbering system 4.595 (116.70) 3.984 (101.19) 0.080 (2.03) 0.050 (1.27) 1.750 (44.45) 2.125 (53.98) 3.750 (95.25) 0.250 (6.35) 0.041 (1.04) 0.062 (1.57) rad. 0.250 (6.35) 0.062 (1.57) rad. 0.250 (6.35) 0.400 (10.16) 1.40 (35.56) 0.125 (3.18) 0.100 (2.54) 1 72 u1-13, u16-31, u34-36 u14-15, u32-33 c1-13, c16-31, c34-36 enhanced dm2200j-xx, 4m x 1 edrams, 300 mil soj idt 74 fct 162244ct pa 16-bit buffer/line driver or equivalent 0.22? chip capacitor 4.7? chip capacitor amp 822030-3 or equivalent inches (mm) double side mounting c 0.185 (4.70) c c c c c c c c c c c c c 0.350 (8.89) 0.050 (1.27) 0.225 (5.71) 0.125 (3.17) c c c c c14-15, c32-33 socket mechanical data dm4m32sj 72 pin simm module configuration the information contained herein is subject to change without notice. enhanced memory systems inc. assumes no responsibility fo r the use of any circuitry other than circuitry embodied in an enhanced product, nor does it convey or imply any license under patent or other rights.

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