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asahi kasei [AK4115] ms0573-e-00 2006/12 - 1 - general description the AK4115 is a 24-bit stereo digital audio transceiver that supports sampling rates up to 216khz. the channel status bit decoder supports both consumer and professional modes and can automatically detect non-pcm bit streams such as dolby digital or mpeg. the AK4115 supports a wide array of features a couple of them being; differential cable driver and receiver support, and an internal pll that can support clock sources such as bi-phase and ?word clock?. control of AK4115 is achieved though a p or pin-strapping (parallel mode) and it is packaged in a space- saving 64pin-lqfp. * dolby digital is a trademark of dolby laboratories. features ? aes3, iec60958, s/pdif, eiaj cp1201 compatible ? very low jitter analog pll ? synchronous / asynchronous mode ? include two x?tal oscillators ? clock source: pll or external clock - reference clock for pll: ? biphase signal: 22khz to 216khz ? external clock (elrck pin): 22khz to 216khz ? 8-channel receiver input - one channel supports differential input ? 2-channel transmission output (through output or dit) - one channel supports differential output (rs422 line output buffer) ? auxiliary digital input ? de-emphasis for 32khz, 44.1khz and 48khz ? detection functions - non-pcm bit stream detection - dts-cd bit stream detection - sampling frequency detection: (22.05khz, 24khz, 32khz, 44.1khz, 48khz, 64khz, 88.2khz, 96khz, 176.4khz and 192khz) - unlock & parity error detection - dat start id detection ? up to 24bit audio data format ? audio interface: master or slave mode ? 192-bit channel status buffer ? burst preamble bit pc and pd buffer for non-pcm bit stream ? q-subcode buffer for cd bit stream ? serial p interface: 4-wire or i 2 c (max. 400khz) ? two master clock outputs: 64fs/128fs/256fs/512fs ? operating voltage: 2.7 to 3.6v with 5v logic tolerance ? package: 64pin lqfp ? ta: -20 to 85 c AK4115 high feature 192khz 24bit digital audio interface transceive r
asahi kasei [AK4115] ms0573-e-00 2006/12 - 2 - input selector clock recovery clock generator daif decoder a c-3/mpeg detect dem p i/f a udio i/f for rx/tx x'tal oscillator pdn int0 p/sn= ?l? lrck bick sdto daux mcko2 xto1 xti1 r avdd avs s cdti cdto cclk csn ovdd ovss mcko1 iic rx1 rx2 rx3 rx4 rx5 rx6 rx7 dit tx0 error & detect status int1 q-subcode buffer txp1 vout 8 to 3 vin rxn0 rxp0 txn1 channel buffer status x'tal oscillator xto2 clock selector vcom psel acks xti2 filt tvdd tvss ebick audio i/f for tx elrck dvdd dvss emclk elrck xtl1 xtl0 b, c, u a sync figure 1. AK4115 block diagram in serial mode
asahi kasei [AK4115] ms0573-e-00 2006/12 - 3 - in p ut selector clock recovery clock generator daif decoder a c-3/mpeg detect dem a udio i/f for rx/tx x'tal oscillator pdn int0 p/sn= ?h? lrck bick sdto daux mcko2 xto1 xti1 r avdd av ss cm1 cm0 ocks1 ocks0 ovdd ovss mcko1 ips1 rx1 rx2 rx3 ips0 dif0 dif1 dit tx0 error & detect status int1 txp1 b,c,u,vout 4 to 2 vin rxn0 rxp0 txn1 x'tal oscillator xto2 clock selector vcom psel a cks xti2 filt tvdd tvss elrck dvdd dvss xtl1 xtl0 xsel ebick emck figure 2. AK4115 block diagram in parallel mode
asahi kasei [AK4115] ms0573-e-00 2006/12 - 4 - ? ordering guide AK4115vq -20 ~ +85 c 64pin lqfp (0.5mm pitch) AK4115 evaluation board for AK4115 ? pin layout dif0/rx5 ips0/rx4 1 test 64 2 dif1/rx6 3 pdn 4 xsel/rx7 5 dvdd 6 vin 7 daux 8 dvss 9 mcko1 10 mcko2 a vdd 63 rx3 62 61 60 avdd 59 rx1 58 a vss 57 rxp0 56 rxn0 55 a cks 54 ebick 17 b 18 c 19 u 20 vout 21 22 tx0 23 txp1 24 txn1 25 tvss 26 xti1 27 48 47 46 45 44 43 42 41 40 39 38 filt xtl1 xtl0 psel ips1/iic bvss dvss dvdd ocks0/csn/cad0 ocks1/cclk/scl cm1/cdti/sda top view tvdd a vss rx2 p/sn 5 3 xto1 28 11 ovdd 12 37 cm0/cdto/cad1 ovss 13 bick 14 sdto 15 lrck 16 xti2 29 xto2 30 ovdd 31 ovss 32 av dd 52 vcom 51 r 50 a vss 49 36 35 34 int1 int0 elrck 33 emck
asahi kasei [AK4115] ms0573-e-00 2006/12 - 5 - pin/function no. pin name i/o function dif0 i audio data interface format #0 pin in parallel mode 1 rx5 i receiver channel #5 pin in serial mode (internal biased pin) 2 test i test pin this pin must be connected to avss. dif1 i audio data interface format #1 pin in parallel mode 3 rx6 i receiver channel #6 pin in serial mode (internal biased pin) 4 pdn i power-down mode pin when ?l?, the AK4115 is powered-down and reset. xsel i x?tal oscillator selection pin in parallel mode ?l?: x?tal #1 is powered-up. ?h?: x?tal #2 is powered-up. xsel pin and xsel bit are ored. 5 rx7 i receiver channel #7 pin in serial mode (internal biased pin) 6 dvdd - digital power supply pin, 3.3v 7 vin i v-bit input pin for transmitter output 8 daux i auxiliary audio data input pin 9 dvss - digital ground pin 10 mcko1 o master clock output #1 pin 11 mcko2 o master clock output #2 pin 12 ovdd - digital power supply pin, 3.3v 13 ovss - digital ground pin 14 bick i/o audio serial data clock pin 15 sdto o audio serial data output pin 16 lrck i/o channel clock pin 17 b i/o block-start input/output pin 18 c i/o c-bit input/output pin 19 u i/o u-bit input/output pin 20 vout o v-bit output pin for receiver 21 tvdd - input tolerance & tx output buffer power supply pin, 3.3v or 5v 22 tx0 o transmit channel (through data) output #0 pin 23 txp1 o transmit channel positive output #1 pin 24 txn1 o transmit channel negative output #1 pin 25 tvss - input & tx output buffer ground pin 26 xti1 i x?tal #1 input pin 27 xto1 o x?tal #1 output pin 28 xti2 i x?tal #2 input pin 29 xto2 o x?tal #2 output pin 30 ovdd - digital power supply pin, 3.3v 31 ovss - digital ground pin 32 ebick i/o external serial data clock pin 33 emck i external master clock input pin 34 elrck i/o external channel clock pin 35 int0 o interrupt #0 pin 36 int1 o interrupt #1 pin note 1. do not allow digital input pins except internal biased pins to float.
asahi kasei [AK4115] ms0573-e-00 2006/12 - 6 - pin/function (continued) no. pin name i/o function cm0 i master clock operation mode #0 pin in parallel mode cdto o control data output pin in serial mode, iic pin = ?l?. 37 cad1 i chip address #1 pin in serial mode, iic pin = ?h?. cm1 i master clock operation mode #1 pin in parallel mode cdti i control data input pin in serial mode, iic pin = ?l?. 38 sda i/o control data pin in serial mode, iic pin = ?h?. an external pull-up resistor is required. ocks1 i output clock select #1 pin in parallel mode cclk i control data clock pin in serial mode, iic pin = ?l? 39 scl i control data clock pin in serial mode, iic pin = ?h? an external pull-up resistor is required. ocks0 i output clock select #0 pin in parallel mode csn i chip select pin in serial mode, iic pin = ?l?. 40 cad0 i chip address #0 pin in serial mode, iic pin = ?h?. 41 dvdd - digital power supply pin, 3.3v 42 dvss - digital ground pin 43 bvss - substrate ground pin ips1 i input channel select #1 pin in parallel mode 44 iic i iic select pin in serial mode ?l?: 4-wire serial, ?h?: i 2 c 45 psel i pll source select pin ?l?: s/pdif input, ?h?: elrck input clock psel pin and psel bit are ored in serial mode. 46 xtl0 i x?tal frequency select #0 pin 47 xtl1 i x?tal frequency select #1 pin 48 filt o pll loop filter pin 49 avss - analog ground pin 50 r o external resistor pin 10k ? 1% resistor should be connected to avss externally. 51 vcom o common voltage output pin 4.7f capacitor should be connected to avss externally. 52 avdd - analog power supply pin, 3.3v 53 p/sn i parallel/serial select pin ?l?: serial mode, ?h?: parallel mode 54 acks i master clock frequency auto setting mode pin. ?l?: disable, ?h?: enable acks pin and acks bit are ored in serial mode. 55 rxn0 i receiver channel #0 negative input pin (internal biased pin) in serial mode, this channel is selected as default channel. 56 rxp0 i receiver channel #0 positive input pin (internal biased pin) in serial mode, this channel is selected as default channel. 57 avss - analog ground pin 58 rx1 i receiver channel #1 pin (internal biased pin) 59 avdd - analog power supply pin, 3.3v 60 rx2 i receiver channel #2 pin (internal biased pin) 61 avss - analog ground pin 62 rx3 i receiver channel #3 pin (internal biased pin) 63 avdd - analog power supply pin, 3.3v ips0 i input channel select #0 pin in parallel mode 64 rx4 i receiver channel #4 pin in serial mode (internal biased pin) note 1. do not allow digital input pins except internal biased pins to float.
asahi kasei [AK4115] ms0573-e-00 2006/12 - 7 - ? handling of unused pin the unused i/o pin should be processed appropriately as below. 1. serial mode (p/sn pin = ?l?) classification pin name setting analog input rxp0, rxn0, rx7-1 these pins should be open. test this pin should be connected to avss. analog output filt this pin should be open. digital input vin, daux, xti1, xti2, emck these pin should be connected to dvss. digital output mcko1, mcko2, vout, tx0, txp1, txn1, xto1, xto2, int0, int1, cdto these pins should be open. digital input/output b, u, c these pins should be open when bcu_ic bit is ?1?. these pins should be dvss when bcu_io bit is ?0?. ebick, elrck these pins should be open in master mode. these pins should be connected to dvss in slave mode. 2. parallel mode (p/sn pin = ?h?) classification pin name setting analog input rxp0, rxn0, rx3-1 these pins should be open. test this pin should be connected to avss. analog output filt this pin should be open. digital input vin, daux, xti1, xti2, emck, ebick, elrck these pin should be connected to dvss. digital output mcko1, mcko2, vout, tx0, txp1, txn1, xto1, xto2, int0, int1, cdto, b, u, c these pins should be open.
asahi kasei [AK4115] ms0573-e-00 2006/12 - 8 - absolute maximum ratings (avss, ovss, dvss, tvss, bvss=0v; note 2) parameter symbol min max units power supplies: analog digital logic output buffer input tolerance and tx buffer avdd dvdd ovdd tvdd -0.3 -0.3 -0.3 -0.3 4.6 4.6 4.6 6.0 v v v v | bvss ? avss | (note 3) ? gnd1 - 0.3 v | bvss ? ovss | (note 3) ? gnd2 - 0.3 v | bvss ? dvss | (note 3) ? gnd3 - 0.3 v | bvss ? tvss | (note 3) ? gnd4 - 0.3 v input current (any pins except supplies) iin - 10 ma input voltage (note 4) vin -0.3 ?tvdd+0.3? or 6.0 v ambient temperature (power applied) ta -20 85 c storage temperature tstg -65 150 c note 2. all voltages with respect to ground. note 3. avss, ovss, dvss, bvss and tvss must be connected to the same ground plane. note 4. all input pins. the maximum value is low value either ?tvdd+0.3v? or ?6.0v?. pull-up resistor at sda and scl pins should be connected to (tvdd+0.3)v or less voltage. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, ovss, dvss, tvss, bvss=0v; note 2) parameter symbol min typ max units power supplies: (note 5) analog digital logic output buffer input tolerance and tx buffer avdd dvdd ovdd tvdd 2.7 2.7 2.7 dvdd 3.3 3.3 3.3 5.0 3.6 3.6 3.6 5.5 v v v v difference avdd ? dvdd avdd ? ovdd ovdd ? dvdd -0.3 -0.3 -0.3 0 0 0 0.3 0.3 0.3 v v v note 2. all voltages with respect to ground. note 5. the power up sequence among avdd, dvdd, ovdd and tvdd is not critical. *akm assumes no responsib ility for the usage beyond the conditions in this data sheet.
asahi kasei [AK4115] ms0573-e-00 2006/12 - 9 - s/pdif receiver characteristics (ta=25 c; avdd, ovdd, dvdd=2.7~3.6v;tvdd=2.7~5.5v) parameter symbol min typ max units input resistance zin - 10 - k ? input voltage vth 200 - - mvpp input sample frequency fs 22 - 216 khz time deviation jitter rx input (psel = ?0?) elrck input (psel = ?1?) - - 100 300 - - ps rms ps rms cycle - to - cycle jitter rx input (psel = ?0?) elrck input (psel = ?1?) - - 70 70 - - ps rms ps rms dc characteristics (ta=25 c; avdd, ovdd, dvdd=2.7~3.6v;tvdd=2.7~5.5v; unless otherwise specified) parameter symbol min typ max units power supply current normal operation: pdn pin = ?h? (note 6) avdd+dvdd+ovdd: tvdd: - - 28 30 42 45 ma ma power down: pdn pin = ?l? (note 7) avdd+dvdd+ovdd+tvdd: - 10 100 a high-level input voltage low-level input voltage input level at ac coupling (only elrck pin) vih vil vac 70%dvdd dvss-0.3 0.5 - - - tvdd 30%dvdd tvdd v v vpp except for tx0, txn1 and txp1 pins high-level output voltage (iout=-400 a) low-level output voltage (except sda pin: iout=400 a) ( sda pin: iout= 3ma) voh vol vol ovdd-0.4 - - - - - - 0.4 0.4 v v v tx0 output level output level (note 8) vtxo0 0.4 0.5 0.6 v txn1 and txp1 pins professional mode (tvdd= 4.5 ~ 5.5v) output impedance (rp + rn + r1) (note 9) rtxpn 88 110 132 ? consumer mode (tvdd = 2.7 ~ 5.5v) output level (note 10) vtxo1 0.4 0.5 0.6 v input leakage current iin - - 10 a note 6. avdd, ovdd, dvdd = 3.3v, tvdd=5.0v, c l =20pf, fs=216khz, x'tal=24.576mhz, clock operation mode 2, ocks1=1, ocks0=1, tx0 output circuit: figure 23, tx1 output circuit: figure 25. avdd=10ma (typ), ovdd+dvdd=18ma (typ) note 7. rx inputs are open and all digital input pins are held tvdd or dvss. note 8. by using figure 23 or figure 24. note 9. rp: output impedance of txp1, rn: output impedance of txn1, r1 = 75 ? . by using figure 25. note 10. by using figure 26
asahi kasei [AK4115] ms0573-e-00 2006/12 - 10 - switching characteristics (ta=25 c; avdd, ovdd, dvdd=2.7~3.6v, tvdd=2.7~5.5v; c l =20pf) parameter symbol min typ max units master clock timing crystal resonator frequency fxtal 11.2896 - 24.576 mhz external clock frequency duty feclk declk 11.2896 40 - 50 27.648 60 mhz % mcko1 output frequency duty fmck1 dmck1 2.816 40 - 50 27.648 60 mhz % mcko2 output frequency duty fmck2 dmck2 1.408 40 - 50 27.648 60 mhz % pll clock recover frequency (rx7-0) fpll 22 - 216 khz lrck frequency duty cycle (at slave mode) duty cycle (at master mode) fs dlck dlck 22 45 - - - 50 216 55 - khz % % audio interface timing 1 slave mode bick period bick pulse width low pulse width high lrck edge to bick ? ? (note 11) bick ? ? to lrck edge (note 11) lrck to sdto (msb) (3.0v dvdd,ovdd 3.6v) bick ? ? to sdto (3.0v dvdd,ovdd 3.6v) lrck to sdto (msb) (2.7v dvdd,ovdd < 3.0v) bick ? ? to sdto (2.7 v dvdd,ovdd < 3.0v) daux hold time daux setup time tbck tbckl tbckh tlrb tblr tlrm tbsd tlrm tbsd tdxh tdxs 72 27 27 15 15 - - - - 15 15 - - - - - - - - - - - - - - - - 20 20 25 25 - - ns ns ns ns ns ns ns ns ns ns ns master mode bick frequency bick duty bick ? ? to lrck bick ? ? to sdto daux hold time fbck dbck tmblr tbsd tdxh - - -15 - 15 64fs 50 - - - - - 15 15 - hz % ns ns ns daux setup time tdxs 15 - - ns master clock timing 2 emck frequency duty feclk2 declk2 2.816 40 - 50 27.648 60 mhz % elrck pll lock range frequency duty fepll fs dlck 22 22 40 - - 50 216 216 60 khz khz % audio interface timing 2 slave mode ebick period ebick pulse width low pulse width high elrck edge to bick ? ? (note 12) ebick ? ? to elrck edge (note 12) daux hold time daux setup time tebck tebckl tebckh telrb teblr tedxh tedxs 72 27 27 15 15 15 15 - - - - - - - - - - - - - - ns ns ns ns ns ns ns master mode ebick frequency ebick duty ebick ? ? to elrck daux hold time febck debck temblr tedxh - - -15 15 64fs 50 - - - - 15 - hz % ns ns daux setup time tedxs 15 - - ns note 11. bick rising edge must not occur at the same time as lrck edge. note 12. ebick rising edge must not occur at the same time as elrck edge.
asahi kasei [AK4115] ms0573-e-00 2006/12 - 11 - switching characteristics (continued) (ta=25 c; avdd, ovdd, dvdd=2.7~3.6v, tvdd=2.7~5.5v; c l =20pf) parameter symbol min typ max units control interface timing (4-wire serial mode) cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? cdto delay csn ? ? to cdto hi-z tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tdcd tccz 200 80 80 50 50 150 50 50 - - - - - - - - - - - - - - - - - - - - 45 70 ns ns ns ns ns ns ns ns ns ns control interface timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling (note 13) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition capacitive load on bus pulse width of spike noise suppressed by input filter fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto cb tsp - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 - 0 - - - - - - - - - - - - - 400 - - - - - - - 0.3 0.3 - 400 50 khz s s s s s s s s s s pf ns reset timing pdn pulse width tpw 150 - - ns note 13. data must be held for sufficient time to bridge the 300ns transition time of scl. note 14. i 2 c is a registered tradmark of philips semiconductors.
asahi kasei [AK4115] ms0573-e-00 2006/12 - 12 - ? timing diagram 1/feclk teclkl vih teclkh xti vil declk = teclkh x feclk x 100 = teclkl x feclk x 100 1/fmck1 50%ovdd mcko1 tmckl1 tmckh1 dmck1 = tmckh1 x fmck1 x 100 = tmckl1 x fmck1 x 100 1/fmck2 50%ovdd mcko2 tmckl2 tmckh2 dmck2 = tmckh2 x fmck2 x 100 = tmckl2 x fmck2 x 100 1/fs lrck vih vil tlrl tlrh dlck = tlrh x fs x 100 = tlrl x fs x 100 1/feclk2 teclkl2 vih teclkh2 emck vil declk2 = teclkh2 x feclk2 x 100 = teclkl2 x feclk2 x 100 1/fs elrck vih vil telrl telrh delck = telrh x fs x 100 = telrl x fs x 100 figure 3. clock timing
asahi kasei [AK4115] ms0573-e-00 2006/12 - 13 - tlrb lrck bick sdto tbsd tblr tbckl tbckh tlrm 50%ovdd daux tdxs tdxh vih vil vih vil vih vil tbck figure 4. serial interface timing 1 (slave mode) lrck bick sdto tbsd tmblr 50%ovdd 50%ovdd 50%ovdd daux tdxh tdxs vih vil figure 5. serial interface timing 1 (master mode) telrb elrck ebick teblr tebckl tebckh daux tedxs tedxh vih vil vih vil vih vil tebck figure 6. serial interface timing 2 (slave mode)
asahi kasei [AK4115] ms0573-e-00 2006/12 - 14 - elrck ebick temblr 50%ovdd 50%ovdd daux tedxh tedxs vih vil figure 7. serial interface timing 2 (master mode) tcckl csn cclk tcds cdti tcdh tcss c0 tcckh cdto hi-z c1 vih vil vih vil vih vil tcck 0 0 figure 8. write/read command input timing in 4-wire serial mode tcsw csn cclk cdti d2 d0 tcsh cdto hi-z d1 d3 vih vil vih vil vih vil figure 9. write data input timing in 4-wire serial mode
asahi kasei [AK4115] ms0573-e-00 2006/12 - 15 - csn cclk tdcd cdto d7 d6 cdti a1 a0 d5 hi-z 50%ovdd vih vil vih vil vih vil figure 10. read data output timing 1 in 4-wire serial mode csn cclk tccz cdto d2 d1 cdti d0 d3 tcsw tcsh 50%ovdd vih vil vih vil vih vil figure 11. read data input timing 2 in 4-wire serial mode thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 12. i 2 c bus mode timing tpw pdn vil figure 13. power down & reset timing
asahi kasei [AK4115] ms0573-e-00 2006/12 - 16 - operation overview ? non-pcm (dolby digital, mpeg, etc) and dts-cd bitstream detection the AK4115 has a non-pcm bitstream auto-detection function, when the 32-bit mode non-pcm preamble based on dolby ?dolby digital data stream in iec 60958 interface? is detected, the npcm bit sets to ?1?. the 96-bit sync code consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xf872 and 0x4e1f. detection of this pattern will set the npcm bit to ?1?. once the npcm bit is set to ?1?, it will remain ?1? until 4096 frames pass through the chip without an additional sync pattern being detected. when those preambles are detected, the burst preambles pc (burst information: figure 51) and pd (length code: figure 52) that follow those sync codes are stored to registers. the AK4115 has also a dts-cd bitstream auto-detection function. when the AK4115 detects dts-cd bitstream, the dtscd bit sets to ?1?. if the next sync code does not occur within 4096frames, the dtscd bit sets to ?0? until no-pcm bitstream is detected again. the ored value of npcm and dtscd bits are output to auto bit. the AK4115 detects the 14-bit sync word and the 16-bit sync word of a dts-cd bitstream, the detection function can be set on/off by dts14 and dts16 bits in serial mode. in parallel mode, the logical or value of the auto and dts-cd bits are outputted to the int1 pin. the dts-cd bit detects both the 14-bit sync word and the 16-bit sync word. ? 216khz clock recovery the integrated low jitter pll has a wide lock range from 22khz to 216khz. the AK4115 has a sampling frequency detection function (22.05khz, 24khz, 32khz, 44.1khz, 48khz, 64khz, 88.2khz, 96khz, 176.4khz and 192khz) that uses either a clock comparison against the x?tal oscillator from the setting of xtl1-0, or the channel status information. the pll loses lock when the received sync interval is incorrect. ? reference clock for pll the reference clock for the pll can select the bi-phase signal or the clock supplied from the elrck pin. the bi-phase signals are supplied to rx7-0 pins and the elrck pin is supplied to a sampled clock (1fs) from the word clock (typically used by studio equipment). this is selected by the psel bit or the psel pin. psel bit and psel pin are ored internally. psel reference clock for pll 0 rx input default 1 elrck input table 1. setting of pll reference clock ? pll lock time the lock time at psel = ?0? depends on sampling frequency (fs) and fast bit (see table 2). fast bit is useful at lower sampling frequency and is fixed to ?1? in parallel mode. when psel is ?1?, the lock time is 35ms (max) and is not related to the setting of the fast bit. the lock time in table 2 does not include the power-up time of vcom voltage. therefore, the power-up time of vcom voltage must be added when pdn pin changes from ?l? to ?h?. the power-up time of vcom voltage is max. 15ms (capacitor value of vcom pin = 4.7 f). psel fast bit pll lock time 0 0 (20ms + 384/fs) default 0 1 (20ms + 1/fs) 1 - 35ms table 2. pll lock time (fs: sampling frequency)
asahi kasei [AK4115] ms0573-e-00 2006/12 - 17 - ? word clock (studio sync clock) the word clock is used to synchronize clocks among studio equipment and is always synchronized to the sampling frequency (1fs). the internal pll generates mclk, bick and lrck from the word clock supplied to the elrck pin. the pll lock range is 22khz to 216khz. the word clock (elrck pin) can receive signal levels of 0.5vpp(min) when ac coupled. in master mode, the clock phase between elrck pin and lrck pin is within 5%. when the AK4115 is supplied with a bi-phase signal and a word clock (elrck), the phase error between the lrck and elrck is within 1/(128fs). therefore, use lrck and not elrck for the serial data output stream. when the word clock is not synchronized to the bi-phase signal, wsync bit should be set to ?0?. ? dit/dir mode the AK4115 operates in either synchronous mode or asynchronous mode. in synchronous mode, transmitter and r eceiver are operated by the same clock source. in asynchronous mode, transmitter and receiver are operated by different a sampling frequencies that are selected by the async bit. frequency multiples are not required in asynchronous mode. 1. synchronous mode: async bit = ?0? psel and cm1-0 select the clock source and the data source for sdto. in mode 2, the clock source is switched from pll to x'tal when the pll goes to the unlock state. in mode 3, the clock source is fixed to x?tal, but pll is also operation and the recovered data such as channel status bit can be monitored. for mode 2 and mode 3, it is recommended that the frequency of x?tal is different from the recovered frequency of the pll. in modes 4-6, the pll source is elrck and mcko1/2, bick and lrck are generated by the pll. the data source of sdto is always daux. mode psel cm1 cm0 unlock pll status x'tal status clock source clock i/o sdto 0 0 0 0 - on on (note 16) pll (rx) note 17 rx 1 0 0 1 - off on x'tal note 17 daux 0 on on pll (rx) note 17 rx 2 0 1 0 1 on on x'tal note 17 daux 3 0 1 1 - on on x?tal note 17 daux 4 1 0 0 - on on (note 16) pll (elrck) note 17 daux 5 1 0 1 - off on x?tal note 17 daux 0 on on pll (elrck) note 17 daux 6 1 1 0 1 on on x'tal note 17 daux note 15. on: oscillation (power-up), off: stop (power-down) note 16: when the x?tal is not used as clock comparison for fs detection (i.e. xtl1,0= ?1,1?), the x?tal is off. note 17. mcko1/2, bick, lrck table 3. clock operation for dit/dir in synchronous mode
asahi kasei [AK4115] ms0573-e-00 2006/12 - 18 - in p ut selector clock recovery clock generator daif decoder dem audio i/f for rx/tx x'tal oscillator lrck bick sdto daux mcko2 xto1 xti1 mcko1 rx1 rx2 rx3 rx4 rx5 rx6 rx7 dit tx0 txp1 8 to 3 rxn0 rxp0 txn1 x'tal oscillator xto2 clock selector (cm1-0) acks xti2 xsel figure 14. clocks for dit/dir in synchronous mode (psel bit = ?0?) in p ut selector clock recovery clock generator a udio i/f for rx/tx x'tal oscillator lrck bick sdto daux mcko2 xto1 xti1 mcko1 rx1 rx2 rx3 rx4 rx5 rx6 rx7 dit tx0 txp1 8 to 2 rxn0 rxp0 txn1 x'tal oscillator xto2 clock selector ( cm1-0 ) acks xti2 xsel elrck figure 15. clocks for dit/dir in synchronous mode (psel bit = ?1?)
asahi kasei [AK4115] ms0573-e-00 2006/12 - 19 - 2. asynchronous mode: async bit = ?1?, psel = ?0? when async bit is ?1?, dit and dir can operate at different sample rates(non-multiples). in mode1, mode2 (when the pll is the unlock state) and mode3, sdto is fixed ?l?. the input timing of daux should be synchronized with elrck and ebcik. the master clock of tx can be selected to either x?tal or emck by the msel bit (see table 4). msel bit master clock 0 x?tal defalut 1 emck table 4. master clock setting for tx in asynchronous mode. rx tx mode cm1 cm0 unlock pll status x'tal status clock source clock i/o sdto clock source clock i/o 0 0 0 - on on (note 19) pll (rx) note 20 rx x?tal or emck (note 22) note 21 1 0 1 - off on x'tal note 20 ?l? x?tal or emck note 21 0 on on pll (rx) note 20 rx x?tal or emck note 21 2 1 0 1 on on x'tal note 20 ?l? x?tal or emck note 21 3 1 1 - on on x'tal note 20 ?l? x?tal or emck note 21 note 18. on: oscillation (power-up), off: stop (power-down) note 19 when the x?tal is not used as clock comparison for sampling frequency detection (i.e. xtl1,0 = ?1,1?), the x?tal is off. note 20: mcko1/2, bick, lrck note 21. emck or x?tal, ebick, elrck, daux note 22. when x?tal is off, the clock source supports emck only. table 5. clock operation for dit/dir in asynchronous mode in p ut selector clock recovery clock generator daif decoder dem a udio i/f for rx x'tal oscillator lrck bick sdto emck mcko2 xto1 xti1 mcko1 rx1 rx2 rx3 rx4 rx5 rx6 rx7 dit tx0 txp1 8 to 3 rxn0 rxp0 txn1 x'tal oscillator xto2 clock selector ( cm1-0 ) acks xti2 xsel a udio i/f for tx elrck ebick daux ?l? msel figure 16. clocks for dit/dir in asynchronous mode
asahi kasei [AK4115] ms0573-e-00 2006/12 - 20 - ? block start, channel status bit, user bit and validity bit the AK4115 can control and monitor block start, channel status bits, user bits and validity bit for rx and tx. b, c and u pins are bi-directional and the direction of input/output can be selected by the bcu_io bit. b, c, u and vout pins become ?l? (bcu_io bit = ?1?) in an unlocked state of mode 2. a. serial mode & except aes3 mode (p/sn pin = ?l?, aes3 bit = ?0?) rx tx async bit bcu_io bit block start (b pin) channel status bit user bit validity bit channel status bit user bit validity bit 0 input cr191-0 bits n/a vout pin vrx bit (note 24) c pin ct191-0 bits (note 25) u pin vin pin vtx bit (note 26) 0 1 output c pin cr191-0 bits (note 23) u pin vrx bit vout pin (note 24) ct191-0 bits all ?0? data (note 27) vin pin vtx bit (note 26) 0 input cr191-0 bits n/a vrx bit c pin ct191-0 bits (note 25) u pin vin pin vtx bit (note 26) 1 1 output c pin cr191-0 bits (note 23) u pin vout pin vrx bit (note 24) ct191-0 bits all ?0? data vtx bit note 23. channel status bit for rx can be monitored by both c pin and cr191-0 bits. note 24. validity bit for rx can be monitored by both vout pin and vrx bit. note 25. c pin and ct191-0 bits are ored internally. note 26. vin pin and vtx bit are ored internally. note 27. when udit bit is ?1?, the recovered u bits are used for dit(dir-dit loop mode of u bit). table 6. block start, channel status bit, user bit and validity bit in serial mode except aes3 mode (n/a: not available)
asahi kasei [AK4115] ms0573-e-00 2006/12 - 21 - b. serial mode & aes3 mode (p/sn pin = ?l?, aes3 bit = ?1?, async bit = ?0?) rx tx dif1 bit bcu_io bit block start (b pin) channel status bit user bit validity bit channel status bit user bit validity bit 0 input cr191-0 bits sdto pin (note 28) sdto pin vout pin vrx bit sdto pin (note 31) c pin ct191-0 bits (note 32) u pin vin pin vtx bit (note 34) 0 1 output c pin cr191-0 bits sdto pin (note 29) u pin sdto pin (note 30) vout pin vrx bit sdto pin (note 31) ct191-0 bits all ?0? data (note 35) vin pin vtx bit (note 34) 0 input cr191-0 bits sdto pin (note 28) sdto pin vout pin vrx bit sdto pin (note 31) ct191-0 bits daux pin (note 33) daux pin daux pin 1 1 output c pin cr191-0 bits sdto pin (note 29) u pin sdto pin (note 30) vout pin vrx bit sdto pin (note 31) ct191-0 bits daux pin (note 33) daux pin daux pin note 28. channel status bit for rx can be monitored by cr191-0 bits and sdto pin. note 29. channel status bit for rx can be monitored by c pin, cr191-0 bits and sdto pin. note 30. user bit for rx can be monitored by u pin and sdto pin. note 31. validity bit for rx can be monitored by vout pin, vrx bit and sdto pin. note 32. c pin and ct191-0 bits are ored internally. note 33. channel status bit can select either ct191-0 bits or daux pin by the setting of ctx bit. note 34. vin pin and vtx bit are ored internally. note 35. when udit bit is ?1?, the recovered u bits are used for dit(dir-dit loop mode of u bit). table 7. block start, channel status bit, user bit and validity bit in serial mode & aes3 mode c. parallel mode (p/sn pin = ?h?) rx tx block start (b pin) channel status bit user bit validity bit channel status bit user bit validity bit output c pin u pin vout pin default value of ct191-0 bits all ?0? data vin pin table 8. block start, channel status bit, user bit and validity bit in parallel mode
asahi kasei [AK4115] ms0573-e-00 2006/12 - 22 - 1. channel status bit 1-1. rx the data recovered from the bi-phase input signal is stored in cr191-0 bits. when the bcu_io bit = ?1?, the channel status bits are available on the c pin according to the block signal timing. the channel status bits are outputted from sdto pin with audio data in aes3 mode. 1-2. tx the channel status bit can controlled by the ct191-0 bits. when bcu_io bit is ?0?, the channel status bits are also controlled by c pin. ct191-0 bits and the signal on the c pin are ored internally. the input to c pin is ignored in aes3 mode. when ctx bit is set to ?0?, the channel status bits on daux pin are outputted with audio data from tx. when ctx bit is set to ?1?, the values of ct191-0 bits are outputted with audio data from tx. when the ccre bit is ?1? and AK4115 is in professional mode (bit0 = ?1?), the crc code can be generated according to the professional mode definition in the aes3 standard. when the ccre bit is ?0?, the crc data is not generated and the data from the ct191-0 bits is passed to the tx directly. in the consumer mode (bit0 = ?0?), the crc code is not generated. in the consumer mode (bit0 = ?0?), bits20-23(audio channel) must be controlled by the ct20 bit. when the ct20 bit is ?1?, the AK4115 corresponds to ?stereo mode?, bits20-23 are set to ?1000?(left channel) in sub-frame 1, and is set to ?0100?(right channel) in sub-frame 2. when the ct20 bit is ?0?, bits20-23 is set to ?0000? in both sub-frame 1 and sub-frame 2. all cr191-0 bits are transferred to ct191-0 bits when the ctran bit changes from ?0? to ?1?. the transferred ct191-0 bits are valid after the next block start signal is detected. ctran bit goes to ?0? after finishing the transfer. don?t write to the ct191-0 bits when the ctran bit = ?1?. 2. user bit 2-1. rx when the bcu_io bit is ?1?, the recovered user bit is available on the u pin according to block start timing. the user bits are outputted from sdto pin with audio data in aes3 mode. 2-2. tx when the bcu_io bit is ?0?, the user bit is sent to the u pin according to block start timing. when bcu_io bit is ?1? and the async bit is ?0?(synchronous mode), the user bit is controlled by the udit bit. when the udit bit is ?0?, user bit is set to ?0?. when the udit bit is ?1?, the recovered u bits are used for dit( dir-dit loop mode of u bit). this mode (udit bit = ?1?) is enabled when the pll is locked. the input to u pin is ignored in aes3 mode and the user bits on daux pin are outputted with audio data from tx.
asahi kasei [AK4115] ms0573-e-00 2006/12 - 23 - 3. validity bit 3-1. rx in synchronous mode, the validity bit is available on the vout pin according to block start timing. in asynchronous mode, the validity bit is available on the vout pin according to lrck timing. the vrx bit is available in both modes. the validity bit is outputted from sdto pin with audio data in aes3 mode. 3-2. tx the validity bit is controlled by the vin pin or the vtx bit. since the validity bit does not usually update every sub-frame cycle, it can be controlled by the vin pin according to lrck timing in synchronous mode. in asynchronous mode, it can be controlled by the vin pin according to elrck timing. when the validity bit timing is synchronized with the block start timing , the bcu_io bit should be ?0?. in asynchronous mode, the validity bit cannot be controlled by the vin pin when bcu_io bit is set to ?0?. the input to vin pin and vtx bit are ignored in aes3 mode and the validity bit on daux is outputted with audio data from tx. 4. block start signal timing in synchronous mode, the block start signal timing depends on lrck. in asynchronous mode, it depends on elrck. the channel status, user and validity bits are captured with the current audio sample. when the block start signal is an input (bcu_io bit = ?0?), the block start signal should stay high for more than one sub-frame. when the block start signal is an output (bcu_io bit = ?1?), the block start signal goes high at the start of frame 0 and remains high until the end of frame 39. the input to b pin is ignored in aes3 mode and the b bit on daux is used as the block start timing. b (output) c (or u,v) c(l0) c( r0) c( l 1) c( r39 ) c(l38) c(l40) c(r191) sdto (da ux) lrck( el rck) (i 2 s) l0 r0 l38 r3 9 r1 91 l1 l40 lrck( el rck) (except i 2 s) b (input) don?t car e don?t c ar e figure 17. b, c, u, v input/output timings
asahi kasei [AK4115] ms0573-e-00 2006/12 - 24 - ? master clock output the AK4115 has two master clock outputs, mcko1 and mcko2. mcko2 has two modes. these modes can be selected by the xmck bit. 1) when xmck bit = ?0? these clocks are derived from either the recovered clock or the x'tal oscillator. the frequencies of the master clock outputs (mcko1 and mcko2) are set by ocks0 and ocks1 as shown in table 9. the 512fs clock is changed into the 256fs clock when sampling frequency is 96khz or 192khz. the 512fs or 256fs clock is changed into the 128fs clock when sampling frequency is 192khz. no. ocks1 ocks0 mcko1 pin mcko2 pin x?tal fs (max) 0 0 0 256fs 256fs 256fs 96 khz 1 0 1 256fs 128fs 256fs 96 khz 2 1 0 512fs 256fs 512fs 48 khz 3 1 1 128fs 64fs 128fs 192 khz default table 9. master clock output frequency 2) when xmck bit = ?1? mcko2 outputs the input clock of the xti pin. the settings of cm1-0 and ocks1-0 bits are ignored. the output frequency can be set by the div bit. mcko1 outputs a clock that is selected by the cm1-0 bits and ocks1-0 bits. xmck bit div bit mcko2 clock source mcko2 frequency 1 0 x?tal (note 36) x 1 1 1 x?tal (note 36) x 1/2 note 36. mcko2 clock source is selected by xsel bit. table 10. select output frequency of mcko2 ? master clock auto setting mode the master clock auto setting mode detects the mclk/lrck ratio (selects normal/double/quad automatically). when acks is ?1?, this mode is enabled. the frequencies of mcko1 and mcko2 are shown in table 11. in this mode, the settings of ocks1-0 are ignored. this mode is only supported when the sampling frequency detection circuit is enabled in pll mode.(refer to ?sampling frequency and pre-emphasis detection? section.) when elrck is selected and xtl1-0 = ?11?, this mode is not supported. in x?tal mode, the frequencies of mcko1/mcko2 depend upon ocks1-0. the acks pin and acks bit are ored internally. mode mcko1 mcko2 sampling frequency range normal speed 512fs 256fs 22khz to 48khz double speed 256fs 128fs 64khz to 96khz quad speed 128fs 64fs 176.4khz to 216khz table 11. master clock frequency select (master clock auto setting mode)
asahi kasei [AK4115] ms0573-e-00 2006/12 - 25 - ? x?tal oscillator the AK4115 has two x?tal oscillators. they can not operate at the same time. the operation of the x?tal oscillator is selected by the xsel bit or the xsel pin. status xsel x?tal #1 x?tal #2 0 power-up power-down 1 power-down power-up table 12. setting of x?tal oscillator the following circuits are available to feed the clock to the xti1/2 pins of AK4115. 1) x?tal xti1/2 xto1/2 AK4115 note: external capacitance depends upon the crystal osc illator (typ. 5-10pf) figure 18. x?tal mode 2) external clock xti1/2 xto1/2 AK4115 external clock figure 19. external clock mode 3) fixed to the clock operation mode 0 xti1/2 xto1/2 AK4115 figure 20. off mode
asahi kasei [AK4115] ms0573-e-00 2006/12 - 26 - ? sampling frequency and pre-emphasis detection the AK4115 has two methods for detecting the sampling frequency: 1. clock comparison between the recovered clock and x?tal oscillator 2. sampling frequency information from channel status the method is selected by the xtl1,0 pins. when xtl1, 0 = ?1,1?, the sampling frequency is detected by the channel status sampling frequency information. the detected frequency is available on the fs3-0 bits. x?tal frequency xtl1 xtl0 x?tal #1 x?tal #2 0 0 11.2896mhz 12.288mhz default 0 1 12.288mhz 11.2896mhz 1 0 24.576mhz 22.5792mhz 1 1 (use channel status) (use channel status) table 13. reference x?tal frequency except xtl1, 0 = ?1,1? xtl1, 0 = ?1, 1? register output fs consumer mode (note 38) professional mode (note 39) fs3 fs2 fs1 fs0 clock comparison (note 37) byte3 bit3,2,1,0 byte0 bit7,6 byte4 bit6,5,4,3 0 0 0 0 44.1khz 44.1khz 3% 0 0 0 0 0 1 0 0 0 0 0 0 0 1 reserved - 0 0 0 1 (others) 0 0 1 0 48khz 48khz 3% 0 0 1 0 1 0 0 0 0 0 0 0 1 1 32khz 32khz 3% 0 0 1 1 1 1 0 0 0 0 0 1 0 0 22.05khz 22.05khz 3% 0 1 0 0 0 0 1 0 0 1 0 1 1 0 24khz 24khz 3% 0 1 1 0 0 0 0 0 0 1 1 0 1 1 64khz 64khz 3% 1 0 0 0 88.2khz 88.2khz 3% 1 0 0 0 0 0 1 0 1 0 1 0 1 0 96khz 96khz 3% 1 0 1 0 0 0 0 0 1 0 1 1 0 0 176.4khz 176.4khz 3% 1 1 0 0 0 0 1 0 1 1 1 1 1 0 192khz 192khz 3% 1 1 1 0 0 0 0 0 1 1 note 37: at least 3% range is identified as the value in the table 14. in case of intermediate frequency of those two, fs3-0 bits indicate no value. when the frequency is 3% over 192khz or 3% under 22khz, fs3-0 bits may indicate ?0001?, ?0101?, ?0111? or ?1001?. note 38: in consumer mode, byte3 bit3-0 are copied to fs3-0 bits. note 39. in professional mode, fs3-0 bit indicates ?0001? except for frequency shown by table 14. table 14. fs information
asahi kasei [AK4115] ms0573-e-00 2006/12 - 27 - the pre-emphasis information is detected and reported on pem bit. this informations is extracted from channel 1 by default. it can be switched to channel 2 by the cs12 bit in control register. pem pre-emphasis byte 0 bits 3-5 0 off 0x100 1 on 0x100 table 15. pem in consumer mode pem pre-emphasis byte 0 bits 2-4 0 off 110 1 on 110 table 16. pem in professional mode ? de-emphasis filter control the AK4115 includes a digital de-emphasis filter (tc=50/15 s). this is an iir filter corresponds to four sampling frequencies (32khz, 44.1khz and 48khz). when deau bit=?1?, the de-emphasis filter is enabled automatically by the sampling frequency and pre-emphasis information in the channel status. the AK4115 is in this mode by default. in parallel control mode, the AK4115 is always placed in this mode and the status bits in channel 1 control the de-emphasis filter. in serial control mode, dem0/1 bits control the de-emphasis filter when the deau bit is ?0?. the internal de-emphasis filter is bypassed and the recovered data is available without any change if either the pre-emphasis or de-emphasis mode is off. when the pem bit is ?0?, the internal de-emphasis filter is always bypassed. pem fs3 fs2 fs1 fs0 mode 1 0 0 0 0 44.1khz 1 0 0 1 0 48khz 1 0 0 1 1 32khz 1 (others) off 0 x x x x off table 17. de-emphasis auto control at deau bit = ?1? (default) pem dem1 dem0 mode 1 0 0 44.1khz 1 0 1 off default 1 1 0 48khz 1 1 1 32khz 0 x x off table 18. de-emphasis manual control at deau bit = ?0?
asahi kasei [AK4115] ms0573-e-00 2006/12 - 28 - ? system reset and power-down the AK4115 has a power-down mode for all circuits by pdn pin and can be partially powerd-down by pwn bit. the rstn bit initializes the register and resets the internal timing. in parallel mode, only the control by pdn pin is enabled. the AK4115 should be reset once by bringing pdn pin = ?l? upon power-up. pdn pin: all analog and digital circuits are placed in power-down and reset mode by bringing pdn pin= ?l?. all the registers are initialized, and clocks are stopped. reading/writing to the registers is disabled. rstn bit (address 00h; d0): all the registers except pwn and rstn bits are initialized by bringing rstn bit = ?0?. the internal timing is also initialized. writing to registers is not available except the pwn and rstn bits. reading from the registers is disabled. pwn bit (address 00h; d1): the clock recovery is initialized by bringing pwn bit = ?0?. in this case, the clocks are stopped. the registers are not initialized and the mode settings are maintained. writing and reading to the registers are enabled. ? bi-phase input eight receiver inputs (rx7-0) are available in serial mode and four receiver inputs (rx3-0) are available in parallel mode. each input includes an amplifier for unbalanced mode that can accept a signal of 200mvpp or more. ips2-0 selects the receiver channel. ips2 bit ips1 bit ips0 bit input data 0 0 0 rx0 default 0 0 1 rx1 0 1 0 rx2 0 1 1 rx3 1 0 0 rx4 1 0 1 rx5 1 1 0 rx6 1 1 1 rx7 table 19. recovery data select in serial mode ips1 pin ips0 pin input data 0 0 rx0 0 1 rx1 1 0 rx2 1 1 rx3 table 20. recovery data select in parallel mode
asahi kasei [AK4115] ms0573-e-00 2006/12 - 29 - ? bi-phase output the AK4115 has two transmitter outputs, tx0 and tx1. tx0 is a loop-through output that is selected from the rx input. tx0 output is selected from rx7-0 by the ops00, ops01 and ops02 bits. in parallel mode, the source of the loop-through output from tx0 is fixed to rx0. tx1 accepts output from rx7-0 or the transmitter (dit; the data from daux is transformed to iec60958 format.). tx1 also has a true rs422 line driver (differential output). the source of the loop-through output from tx1 is selected from rx7-0 by the ops10, ops11 and ops12 bits. when the dit bit is set to ?1?, tx1 is transmitted to daux data. in parallel mode, tx1 is fixed to dit. ops02 ops01 ops00 output data 0 0 0 rx0 default 0 0 1 rx1 0 1 0 rx2 0 1 1 rx3 1 0 0 rx4 1 0 1 rx5 1 1 0 rx6 1 1 1 rx7 table 21. output data select for tx0 dit ops12 ops11 ops10 output data 0 0 0 0 rx0 0 0 0 1 rx1 0 0 1 0 rx2 0 0 1 1 rx3 0 1 0 0 rx4 0 1 0 1 rx5 0 1 1 0 rx6 0 1 1 1 rx7 1 x x x daux default table 22. output data select for tx1
asahi kasei [AK4115] ms0573-e-00 2006/12 - 30 - ? bi-phase signal input circuit rx AK4115 0.1uf 75 ? coax 75 ? figure 21. consumer input circuit (coaxial input) note: for coaxial input, if a coupling level to this input from the next rx input line pattern exceeds 50mv, there may be an incorrect operation. in this case, it is possible to lower the coupling level by adding this decoupling capacitor. rx AK4115 470 o/e optical receiver optical fiber figure 22. consumer input circuit (optical input) rxp AK4115 0.1uf 110 ? twisted pair 110 ? table 23. professional input circuit (balanced input) note. when rxn pin is unused, rxn pin must be ac-coupled to ground. for coaxial input in serial mode, the input level of rx line is small, so care must be taken to avoid crosstalk among the rx input lines. in this case, a shield is recommended between the input lines. in parallel mode, rx3-0 is available and rx7-4 change to other pins for audio format control. those pins must be fixed to ?h? or ?l?.
asahi kasei [AK4115] ms0573-e-00 2006/12 - 31 - ? bi-phase signal output circuit the AK4115 includes two tx output buffers. the output level is proportional to tvdd voltage. the t1 in figure 23, figure 24, figure 25 and figure 26 is a transformer of 1:1. the resistor values should use 1% accuracy. 1. line driver of tx0 the output level of tx0 is 0.5v 20% using the external resistor network in consumer mode. tx0 tvss r2 t1 75 ? ? 150 ? 3.0v 220 ? 150 ? 5.0v 430 ? 150 ? figure 23. tx0 external resistor network 1 note: when the AK4115 is in the power-down mode (pdn pin = ?l?), power supply current can be reduced by using an ac coupling capacitor as shown in figure 24, since tx1 output is undetermined in power-down mode. tx0 tvss r2 t1 75 ? cable r1 0.1uf tvdd r1 r2 3.3v 240 ? 150 ? 3.0v 220 ? 150 ? 5.0v 430 ? 150 ? figure 24. tx0 external resistor network 2 2. line driver of tx1 2-1. professional mode (tvdd = 4.5v 5.5v) the tx1 has an rs422 line driver when tvdd is 5v 10%. the aes3 specification states that the line driver shall have a balanced output with an internal impedance of 110 ohms 20% and also requires a balanced output drive capability of 2 to 7 volts peak-to-peak into 110 ohm load. the internal impedance of the rs422 driver along with a series resistors of 75 ohms realizes this requirement. txp1 txn1 t1 110 ? cable 75 ? 0.1uf figure 25. professional output driver circuit
asahi kasei [AK4115] ms0573-e-00 2006/12 - 32 - 2-2. consumer mode (tvdd = 2.7v 5.5v) for consumer use , the specifications require an output impedance of 75 ohms 20% and a driver level of 0.5 20% volts peak to peak. a combination of r1 in parallel with r2 meets this requirement. the outputs can be set to ground by resetting the device or a software mute. txp1 txn1 r2 t1 75 ? cable r1 0.1uf tvdd r1 r2 3.3v 270 ? 150 ? 3.0v 240 ? 150 ? 5.0v 430 ? 150 ? open figure 26. consumer output driver circuit at ac coupling ? pll loop filter c1 and r should be connected in series and attached between filt pin and avss in parallel with c2. the value of pll loop filter includes temperature deviation. be careful to minimize the noise into the filt pin. when the studio sync mode is not used, filt pin can be open. a k4115 c1 r filt avss c2 figure 27. pll loop filter r [ ? ] c1 [nf] c2 [pf] 24k 5% 10 30% 100 30% table 24. value of pll loop filter
asahi kasei [AK4115] ms0573-e-00 2006/12 - 33 - ? q-subcode buffers the AK4115 has a q-subcode buffer for cd applications. the AK4115 takes the q-subcode into registers by the following method. 1. the sync word (s0,s1) is constructed of at least 16 ?0?s. 2. the start bit is ?1?. 3. those 7bits q-w follows to the start bit. 4. the distance between two start bits are 8-16 bits. the qint bit in the control register goes to ?1? when the new q-subcode differs from old one, and goes to ?0? when the qint bit is read. 1 2 3 4 5 6 7 8 * s0 0 0 0 0 0 0 0 0 0? s1 0 0 0 0 0 0 0 0 0? s2 1 q2 r2 s2 t2 u2 v2 w2 0? s3 1 q3 r3 s3 t3 u3 v3 w3 0? : : : : : : : : : : s97 1 q97 r97 s97 t97 u97 v97 w97 0? s0 0 0 0 0 0 0 0 0 0? s1 0 0 0 0 0 0 0 0 0? s2 1 q2 r2 s2 t2 u2 v2 w2 0? s3 1 q3 r3 s3 t3 u3 v3 w3 0? : : : : : : : : : : (*) number of "0" : min=0; max=8. figure 28. configuration of u-bit(cd) q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 ctrl adrs track number index q26 q27 q28 q29 q30 q31 q32 q33 q34 q35 q36 q37 q38 q39 q40 q41 q42 q43 q44 q45 q46 q47 q48 q49 minute second frame q50 q51 q52 q53 q54 q55 q56 q57 q58 q59 q60 q61 q62 q63 q64 q65 q66 q67 q68 q69 q70 q71 q72 q73 zero absolute minute absolute second q74 q75 q76 q77 q78 q79 q80 q81 q82 q83 q84 q85 q86 q87 q88 q89 q90 q91 q92 q93 q94 q95 q96 q97 absolute frame crc g(x)=x^16+x^12+x^5+1 figure 29. q-subcode addr register name d7 d6 d5 d4 d3 d2 d1 d0 40h q-subcode address / control q9 q8 q3 q2 41h q-subcode track q17 q16 q11 q10 42h q-subcode index 43h q-subcode minute 44h q-subcode second 45h q-subcode frame 46h q-subcode zero 47h q-subcode abs minute 48h q-subcode abs second 49h q-subcode abs frame q81 q80 q75 q74 figure 30. q-subcode register q
asahi kasei [AK4115] ms0573-e-00 2006/12 - 34 - ? error handing for rx (psel = ?0?) the followings nine events the int0 and int1 pins to trigger the interrupt condition. when the pll is off (clock operation mode 1), int0 and int1 pins go to ?l?. 1. unlck : pll unlock state detect ?1? when the pll loses lock. the AK4115 loses lock when the time between two preambles is not correct or when those preambles are not correct. 2. par : parity error or bi-phase coding error detection ?1? when parity error or bi-phase coding error is detected, updated every sub-frame cycle. 3. auto : non-linear pcm or dts-cd bit stream detection the or function of npcm and dtscd bits.is available at the auto bit. 4. vrx : validity flag detection ?1? when validity flag is detected. updated every sub-frame cycle. 5. audion : non-audio detection ?1? when the ?audion? bit in recovered channel status indicates ?1?. updated every block cycle. 6. stc : sampling frequency or pre-emphasis information change detection when either fs3-0 bit or pem bit is changed, it maintains ?1? during 1 sub-frame. 7. qint : u-bit sync flag ?1? when the q-subcode differs from the old one. updated every sync code cycle for q-subcode. 8. cint : channel status sync flag ?1? when received c bit differs from the old one. updated every block cycle. 9. dat : dat start id detect ?1? when the category code indicates ?dat? and ?dat start id? is detected. when dcnt bit is ?1?, it does not indicate ?1? even if ?dat start id? is detected again within ?3841 x lrck?. when ?dat start id? is detected again after ?3840 x lrck? passed, it indicates ?1?. when dcnt bit is ?0?, it indicates ?1? every ?dat start id? detection.
asahi kasei [AK4115] ms0573-e-00 2006/12 - 35 - 1. parallel mode in parallel mode, the int0 pin outputs the ored signal between unlck and par. the int1 pin outputs the ored signal between auto and audion. once int0 goes ?h?, it maintains ?h? for 1024/fs cycles after all error events are removed. table 25 shows the state of each output pins when the int0/1 pin is ?h?. event pin unlck par auto audion int0 int1 sdto vout 1 x x x ?l? ?l? 0 1 x x ?h? previous data output 0 0 x x ?l? note 40 output output x x 1 x x x x 1 ?h? x x 0 0 note 41 ?l? note 42 note 43 note 40. int1 pin outputs ?l? or ?h? in accordance with the ored signal between auto and audion. note 41. int0 pin outputs ?l? or ?h? in accordance with the ored signal between unlck and par. note 42. sdto pin outputs ?l?, ?previous data? or ?normal data? in accordance with the ored signal between unlck and par. note 43. vout pin outputs ?l? or ?normal operation? in accordance with the ored signal between par and unclk. table 25. error handling in parallel mode (x: don?t care) 2. serial mode in serial mode, the int1 and int0 pins output an ored signal based on the above nine interrupt events. when masked, the interrupt event does not affect the operation of the int1-0 pins (the masks do not affect the registers in 07h and dat bit). once int0 pin goes to ?h?, it remains ?h? for 1024/fs (this value can be changed by the efh1-0 bits) after all events not masked by mask bits are cleared. int1 pin immediately goes to ?l? when those events are cleared. unlck, par, auto, audion and vrx bits in address=07h indicate the interrupt status events above in real time. once qint, cint and dat bits go to ?1?, it stays ?1? until the register is read. when the AK4115 loses lock, the channel status bit, user bit, pc and pd are initialized. in this initial state, int0 pin outputs the ored signal between unlck and par bits. int1 pin outputs the ored signal between auto and audion bits. event pin unlck par others sdto vout tx 1 x x ?l? ?l? output 0 1 x previous data output output x x x output output output table 26. error handling in serial mode (x: don?t care)
asahi kasei [AK4115] ms0573-e-00 2006/12 - 36 - error (unlock, par,..) int1 pin sdto (unlock) mcko,bick,lrck (unlock) previous data register (par,cint,qint) hold ?1? command read 07,08h mcko,bick,lrck (except unlock) sdto (par error) hold time = 0 reset (error) sdto (others) normal operation int0 pin hold time (max: 4096/fs) register (others) free run vout pin (unlock) vout pin (except unlock) (fs: around 6khz) figure 31. int0/1 pin timing
asahi kasei [AK4115] ms0573-e-00 2006/12 - 37 - int0/1 pin ="h" no ye s ye s initialize pdn pin ="l" to "h" read (07h, 08h) mute dac output read (0 7h, 08 h) no (each error handling) read 07h, 08h (res ets registers) int0/1 pin ="h" rele ase muting figure 32. error handling sequence example 1
asahi kasei [AK4115] ms0573-e-00 2006/12 - 38 - int1 pin ="h" no ye s initialize pdn pin ="l" to "h" read (07h, 08h) read (07h, 08h ) and detect qsub= ?1? no (read q-buffer) new data is vali d int1 pin ="l" qcrc = ?0? yes yes ne w data is invalid no figure 33. error handling sequence example (for q/cint)
asahi kasei [AK4115] ms0573-e-00 2006/12 - 39 - ? error handing for elrck (psel = ?1?) the followings two events cause the int0 and int1 pins to show the status of the interrupt conditions. when the pll is off (clock operation mode 1), the int0 and int1 pins go to ?l?. 1. unlck : pll unlock state detect ?1? when the pll loses lock. the AK4115 loses lock when the phase difference between the current elrck and the previous elrck is more than 5% after ?4 x fs?. the pll is locked when the phase difference between the current elrck and the pervious elrck is less than 2% after ?256 x fs?. when the pll loses lock, the pll goes to a free running state. the sampling frequency is typically 11khz in this case. 2. fs3-0 : sampling frequency detection fs3-0 bits are updated every ?128 x fs?. when fs3-0 bits are changed, the stc bit is not changed and the int0 and int1 pins go to ?h? after ?1 x fs? in this mode, int0 does not have the hold function. therefore, int0 and int1 go to ?l? at the same time when those events are removed. each int0/1 pins can mask those two events individually. 1. parallel mode in parallel mode, int0 triggers unlck, and int1 triggers when fs3-0 bits are changed. int0 and int1 go ?l? after each event is removed. 2. serial mode in serial mode, int1 and int0 outputs an ored signal based on the two interrupt events shown above. when masked, the interrupt event does not affect operation of the int1-0. event pin unlck change of fs3-0 bits sdto tx 1 x ?l? output 0 1 output output table 27. error handling (x: don?t care)
asahi kasei [AK4115] ms0573-e-00 2006/12 - 40 - ? audio serial interface format 1. lrck, bick, sdto and daux in serial mode, the dif2-0 bits can select eight serial audio data formats as shown in table 28. in parallel mode, the dif0 and dif1 pins can select four serial audio data format as shown in table 29. in mode0-7, the serial data is msb-first, 2's complement format. the sdto is clocked out on the falling edge of bick and daux is latched on the rising edge of bick. bick outputs 64fs clock in mode 0-5. mode 6-7 are slave modes, and bick is available up to 128fs at fs=48khz. if the data word length is equal or less than 20bit (mode0-2), the lsbs in the sub-frame are truncated. in mode 3-7, the last 4lsbs are auxiliary data (see figure 34). when the parity error, bi-phase error or frame length error occurs in a sub-frame, the AK4115 continues to output the last normal sub-frame data from sdto repeatedly until the error is removed. when the unlock error occurs, AK4115 outputs ?0? from sdto. if daux is used, the data is transformed and outputted from sdto. daux is used in clock operation mode 1, 3 and unlock state of mode 2. the input data format to daux should be left justified except in mode5 and 7(table 28). in mode5 or 7, both the input data format of daux and output data format of sdto are i 2 s. mode 6 and 7 are slave modes that corresponds to the master mode of mode4 and 5. in slave mode, lrck and bick should be synchronized with mcko1/2. when aes3 bit is set to ?1?, sdto becomes aes3 mode. the serial data is lsb-first, 2?s complement format. the v, c, u and b bits behind the audio data are added. the b bit goes to ?1? when the b-sync in preamble is detected (figure 39). when daux is sent to sdto, the data format depends on dif0 bit. when dif0 bit is set to ?0?, the received msb-first, 24bit msb justified is converted to lsb-first, 24bit msb justified. then the only audio data is converted and v, u, c and b bits set to ?0?. when dif0 bit is set to ?1?, the aes3 format received from daux pin is maintained and is sent to sdto pin. mode 8-9 support only synchronous mode (async bit = ?0?). 0 3 4 7 8 11 12 27 28 29 30 31 pr eamble aux. lsb msb vuc p sub-frame of iec958 0 23 AK4115 audio data (msb first) lsb msb figure 34. bit configuration
asahi kasei [AK4115] ms0573-e-00 2006/12 - 41 - lrck bick mode aes3 bit dif2 bit dif1 bit dif0 bit daux sdto i/o i/o 0 0 0 0 0 24bit, left justified 16bit, right justified h/l o 64fs o 1 0 0 0 1 24bit, left justified 18bit, right justified h/l o 64fs o 2 0 0 1 0 24bit, left justified 20bit, right justified h/l o 64fs o 3 0 0 1 1 24bit, left justified 24bit, right justified h/l o 64fs o 4 0 1 0 0 24bit, left justified 24bit, left justified h/l o 64fs o 5 0 1 0 1 24bit, i 2 s 24bit, i 2 s l/h o 64fs o 6 0 1 1 0 24bit, left justified 24bit, left justified h/l i 64-128fs i default 7 0 1 1 1 24bit, i 2 s 24bit, i 2 s l/h i 64-128fs i 8 1 0 0 0 24bit, left justified aes3 mode h/l o 64fs o 9 1 0 0 1 aes mode aes3 mode h/l o 64fs o table 28. audio data format in serial mode lrck bick mode dif1 pin dif0 pin daux sdto i/o i/o 4 0 0 24bit, left justified 24bit, left justified h/l o 64fs o 5 0 1 24bit, i 2 s 24bit, i 2 s l/h o 64fs o 6 1 0 24bit, left justified 24bit, left justified h/l i 64-128fs i 7 1 1 24bit, i 2 s 24bit, i 2 s l/h i 64-128fs i table 29. audio data format in parallel mode 2. emck, elrck, ebick and daux in asynchronous mode, the audio data format of daux is selected by edif1-0 bits. the clock source of master clock selects x?tal or emck by the msel bit. in parallel mode, this function is not supported. elrck ebick mode edif1 bit edif0 bit daux i/o i/o 4 0 0 24bit, left justified h/l o 64fs o 5 0 1 24bit, i 2 s l/h o 64fs o 6 1 0 24bit, left justified h/l i 64-128fs i default 7 1 1 24bit, i 2 s l/h i 64-128fs i table 30. audio data format in asynchronous mode in asynchronous mode, the frequecny of emck/x?tal selects 128fs, 256fs or 512fs. it is controlled by ecks1-0 bit. ecks1 ecks0 emck frequency fs(max) 0 0 512fs 54khz 0 1 256fs 108khz default 1 0 128fs 216khz 1 1 n/a - table 31. emck frequency
asahi kasei [AK4115] ms0573-e-00 2006/12 - 42 - lrck(0) bic k ( 0:64fs ) sdto ( 0 ) 012 31 0 1 15:msb, 0:lsb lch data rch data 15 17 16 15 31 0 1 2 17 16 010 1 15 14 14 15 figure 35. mode 0 timing lrck ( 0 ) bick ( 0:64fs ) sdto ( 0 ) 012 31 0 1 23:msb, 0:lsb lch data rch data 911 10 9 31 0 1 2 11 10 010 1 12 21 20 20 21 12 22 23 22 23 figure 36. mode 3 timing lrck elrck bick ebick ( 64fs ) sdto(0) daux ( i ) 0 1 2 31 0 1 23:msb, 0:lsb lch data rc h da t a 21 23 22 21 31 0 1 2 23 22 23 22 2 24 1 0 0 1 24 21 22 23 32 23 22 figure 37. mode 4, 6 timing mode4 : lrck, bick, elrck, ebick : output mode6 : lrck, bick, elrck, ebick: input lrck elrck bick ebick ( 64fs ) sdto(0) daux(i) 0 1 2 31 0 1 23:msb, 0:lsb lch data rc h da t a 23 22 21 31 0 1 2 23 22 23 22 24 1 0 24 32 23 25 2 0 1 21 22 23 25 figure 38. mode 5, 7 timing mode5 : lrck, bick, elrck, ebick : output mode7 : lrck, bick, elrck, ebick : input
asahi kasei [AK4115] ms0573-e-00 2006/12 - 43 - lrck ( o ) bick ( o ) ( 64fs ) sdto ( 0 ) 0 1 2 31 0 1 23:msb, 0:lsb lch data rch data 24 26 25 24 31 0 1 2 26 25 27 27 01 28 v: validity, c: c-bit, u:u-bit, b:b sync 23 u v 2 1 0 cb 23 u v 2 1 0 c b 28 daux ( i ) figure 39. aes3 mode ? serial control interface 1. 4-wire serial control mode (iic pin = ?l?) the internal registers may be either written or read by the 4-wire p interface pins: csn, cclk, cdti & cdto. the data on this interface consists of chip address (2-bits, c1-0 are fixed to ?00?), read/write (1bit), register address (msb first, 8-bits) and control data (msb first, 8-bits). address and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. for write operations, data is latched after the 24th rising edge of cclk, after a high-to-low transition of csn. for read operations, the cdto output goes high impedance after a low-to-high transition of csn. the maximum speed of cclk is 5mhz. pdn pin = ?l? resets the registers to their default values. when the state of p/sn pin is changed, the AK4115 should be reset by pdn pin = ?l?. csn should be brought ?h? after each word. cdti cclk csn c1 0 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23 d4 d5 d6 d7 0 0 0 0 0 c0 r/w d0 d1 d2 d3 cdto hi-z write cdti c1 d4 d5 d6 d7 0 0 0 0 0 c0 r/w d0 d1 d2 d3 cdto hi-z read d4 d5 d6 d7 d0 d1 d2 d3 hi-z a7 8 9 101112131415 a1 a2 a3 a4 a5 a6 a0 a7 a1 a2 a3 a4 a5 a6 a0 c1-c0: chip address (fixed to ?00?) r/w: read/write (0:read, 1:write) a7-a0: register address d7-d0: control data figure 40. 4-wire serial control i/f timing
asahi kasei [AK4115] ms0573-e-00 2006/12 - 44 - 2. i 2 c bus control mode (iic pin = ?h?) AK4115 supports a fast-mode i 2 c-bus system (max : 400khz). 2-1. data transfer all commands are preceded by a start condition. after the start cond ition, a slave address is sent. after the AK4115 recognizes the start condition, the device interfaced to the bus waits for the slave address to be transmitted over the sda line. if the transmitted slave address matches an address for one of the devices, the designated slave device pulls the sda line to low (acknowledge). the data transfer is always terminated by a stop condition generated by the master device. 2-1-1. data validity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low except for the start and the stop condition. scl sda data line stable : data valid change of data allowed figure 41. data transfer 2-1-2. start and stop condition a high to low transition on the sda line while scl is high indicates a start condition. all sequences start from the start condition. a low to high transition on the sda line while scl is high defines a stop condition. all sequences end by the stop condition. scl sda stop condition start condition figure 42. start and stop conditions
asahi kasei [AK4115] ms0573-e-00 2006/12 - 45 - 2-1-3. acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device will release the sda line (high) after transmitting eight bits. the r eceiver must pull down the sda line during the acknowledge clock pulse so that that it remains stable ?l? during ?h? period of this clock pulse. the AK4115 will generates an acknowledge after each byte has been received. in the read mode, the slave, AK4115 will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition. scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition clock pulse for acknowledge not acknowledge figure 43. acknowledge on the i 2 c-bus 2-1-4. first byte the first byte, which includes seven bits of slave address and one bit of r/w bit, is sent after the start condition. if the transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down the sda line. the most significant five bits of the slave address are fixed as ?00100?. the next two bits are cad1 and cad0 (device address bits). these two bits identify the specific device on the bus. the hard-wired input pins (cad1 pin and cad0 pin) set them. the eighth bit (lsb) of the first byte (r/w bit) defines whether a write or read condition is requested by the master. a ?1? indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. 0 0 1 0 0 cad1 cad0 r/w (those cad1/0 should match with cad1/0 pins.) figure 44. the first byte
asahi kasei [AK4115] ms0573-e-00 2006/12 - 46 - 2-2. write operations set r/w bit = ?0? for the write operation of AK4115. after receipt the start condition and the first byte, the AK4115 generates an acknowledge, and awaits the second byte (register address). the second byte consists of the address for control registers of AK4115. the format is msb first, 8-bits. a7 a6 a5 a4 a3 a2 a1 a0 figure 45. the second byte after receipt of the second byte, the AK4115 generates an acknowledge, and awaits the third byte. those data after the second byte contain control data. the format is msb first, 8-bits. d7 d6 d5 d4 d3 d2 d1 d0 figure 46. byte structure after the second byte the AK4115 is capable of more than one byte write operation by one sequence. after receipt of the third byte, the AK4115 generates an acknowledge, and awaits the next data again. the master can transmit more than one word instead of terminating the write cycle after the first data word is transferred. after the receipt of each data, the internal 5-bit address counter is incremented by one, and the next data is taken into next address automatically. if the address exceed 49h prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. sda s t a r t a c k a c k s slave address a c k register address(n) data(n) p s t o p data(n+x) a c k data(n+1) figure 47. write operation
asahi kasei [AK4115] ms0573-e-00 2006/12 - 47 - 2-3. read operations set r/w bit = ?1? for the read operation of AK4115. after transmission of a data, the master can read next address?s data by generating the acknowledge instead of terminating the write cycle after the receipt the first data word. after the receipt of each data, the internal 5-bit address counter is incremented by one, and the next data is taken into next address automatically. if the address exceed 49h prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the AK4115 supports two basic read operations: current address read and random read. 2-3-1. current address read the AK4115 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ?1?, the AK4115 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the AK4115 discontinues transmission. sda s t a r t a c k a c k s slave address a c k data(n) data(n+1) p s t o p data(n+x) a c k data(n+2) figure 48. current address read 2-3-2. random read random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues the start condition, slave address(r/w=?0?) and then the register address to read. after the register address?s acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to ?1?. then the AK4115 generates an acknowledge, 1byte data and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the AK4115 discontinues transmission. sda s t a r t a c k a c k s s s t a r t slave address word address(n) slave address a c k data(n) a c k p s t o p data(n+x) a c k data(n+1) figure 49. random read
asahi kasei [AK4115] ms0573-e-00 2006/12 - 48 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h clk & power down control cs12 bcu cm1 cm0 ocks1 ocks0 pwn rstn 01h format & de-em control aes3 dif2 dif1 dif0 deau dem1 dem0 acks 02h input/ output control 0 tx1e ops12 ops11 ops10 tx0e ops02 ops01 ops00 03h input/ output control 1 efh1 efh0 udit bcu_io dit ips2 ips1 ips0 04h int0 mask mqit0 maut0 mcit0 mulk0 mv0 mstc0 maud0 mpar0 05h int1 mask mqit1 maut1 mcit1 mulk1 mv1 mstc1 maud1 mpar1 06h dat mask & dts detect div xmck fast dcnt dts16 dts14 mdat1 mdat0 07h receiver status 0 qint auto cint unlck vrx stc audion par 08h receiver status 1 fs3 fs2 fs1 fs0 pem dat dtscd npcm 09h receiver status 2 0 0 0 0 0 0 qcrc ccrc 0ah clock control tx1ne 0 mck2e mck1e async wsync xsel psel 0bh tx control msel ecks1 ecks0 edif1 edif0 ctran ccre vtx 0ch rx channel status byte 0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 ? ? ? ? ? ? ? ? ? ? 23h rx channel status byte 23 cr191 cr190 cr189 cr188 cr187 cr186 cr185 cr184 24h tx channel status byte 0 ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 ? ? ? ? ? ? ? ? ? ? 3bh tx channel status byte 23 ct191 ct190 ct189 ct188 ct187 ct186 ct185 ct184 3ch burst preamble pc byte 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 3dh burst preamble pc byte 1 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 3eh burst preamble pd byte 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 3fh burst preamble pd byte 1 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 40h q-subcode address / control q9 q8 q7 q6 q5 q4 q3 q2 41h q-subcode track q17 q16 q15 q14 q13 q12 q11 q10 42h q-subcode index q25 q24 q23 q22 q21 q20 q19 q18 43h q-subcode minute q33 q32 q31 q30 q29 q28 q27 q26 44h q-subcode second q41 q40 q39 q38 q37 q36 q35 q34 45h q-subcode frame q49 q48 q47 q46 q45 q44 q43 q42 46h q-subcode zero q57 q56 q55 q54 q53 q52 q51 q50 47h q-subcode abs minute q65 q64 q63 q62 q61 q60 q59 q58 48h q-subcode abs second q73 q72 q71 q70 q69 q68 q67 q66 49h q-subcode abs frame q81 q80 q79 q78 q77 q76 q75 q74 4ah optional control 0 0 0 0 0 0 ctx 0 notes: when pdn pin goes ?l?, the registers are initialized to their default values. when rstn bit goes ?0?, the internal timing is reset and the registers are initialized to their default values. all data can be written to the register even if pwn bit is ?0?. data must not be written to addresses 4bh through ffh.
asahi kasei [AK4115] ms0573-e-00 2006/12 - 49 - ? register definitions reset & initialize addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h clk & power down control cs12 bcu cm1 cm0 ocks1 ocks0 pwn rstn r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 0 0 0 0 1 1 rstn: timing reset & register initialize 0: reset & initialize 1: normal operation (default) pwn: power down 0: power down 1: normal operation (default) ocks1-0: master clock frequency select (see table 9) cm1-0: master clock operation mode select (see table 3 and table 5) bcu: block start & c/u output mode when bcu_io bit is ?1? 0: b, c and u pins output ?l?. 1: b, c, and u pins output the data recovered from biphase signal. (default) when bcu_io bit is ?0?, bcu bit is ignored. cs12: channel status select 0: channel 1 (default) 1: channel 2 selects which channel status is used to derive c-bit buffers, audion, pem, fs3, fs2, fs1, fs0, pc and pd. the de-emphasis filter is controlled by channel 1 in the parallel mode. format & de-emphasis control addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h format & de-em control aes3 dif2 dif1 dif0 deau dem1 dem0 acks r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 1 0 1 0 1 0 acks: master clock auto setting mode 0: disable (default) 1: enable dem1-0: 32, 44.1, 48khz de-emphasis control (see table 18) deau: de-emphasis auto detect enable 0: disable 1: enable (default) dif2-0, aes3: audio data format control (see table 28)
asahi kasei [AK4115] ms0573-e-00 2006/12 - 50 - input/output control addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h input/ output control 0 tx1e ops12 ops11 ops10 tx0e ops02 ops01 ops00 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 1 0 0 0 ops02-00: output through data select for tx0 pin (see table 21) tx0e: tx0 output enable 0: disable. tx0 outputs ?l?. 1: enable (default) ops12-10: output through data select for tx1 pin (see table 22) tx1e: txp1/txn1 pins output enable 0: disable. txp1 pin outputs ?l?. txn1 pin outputs ?h?. 1: enable (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h input/ output control 1 efh1 efh0 udit bcu_io dit ips2 ips1 ips0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 0 1 1 0 0 0 ips2-0: input recovery data select (see table 19) dit: through data/transmit data select for txp1/n1 pins 0: through data (rx data). 1: transmit data (daux data). (default) bcu_io: select i/o of b, c and u pins 0: input 1: output (default) udit: u bit control for dit 0: u bit is fixed to ?0?. (default) 1: recovered u bit is used for dit (loop mode for u bit) efh1-0: interrupt 0 pin hold count select 00: 512 lrck 01: 1024 lrck (default) 10: 2048 lrck 11: 4096 lrck
asahi kasei [AK4115] ms0573-e-00 2006/12 - 51 - mask control for int0 addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h int0 mask mqit0 maut0 mcit0 mulk0 mvrx0 mstc0 maud0 mpar0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 0 1 1 1 0 mpar0: mask enable for par bit 0: mask disable (default) 1: mask enable maud0:mask enable for audion bit 0: mask disable 1: mask enable (default) mstc0: mask enable for stc bit 0: mask disable 1: mask enable (default) mvrx0:mask enable for vrx bit 0: mask disable 1: mask enable (default) mulk0:mask enable for unlck bit 0: mask disable (default) 1: mask enable mcit0: mask enable for cint bit 0: mask disable 1: mask enable (default) maut0:mask enable for auto bit 0: mask disable 1: mask enable (default) mqit0: mask enable for qint bit 0: mask disable 1: mask enable (default) when mask is set to ?1?, corresponding event does not affect int0 pin operation.
asahi kasei [AK4115] ms0573-e-00 2006/12 - 52 - mask control for int1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h int1 mask mqit1 maut1 mcit1 mulk1 mvrx1 mstc1 maud mpar1 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 1 1 1 1 0 1 mpar1: mask enable for par bit 0: mask disable 1: mask enable (default) maud1:mask enable for audion bit 0: mask disable (default) 1: mask enable mstc1: mask enable for stc bit 0: mask disable 1: mask enable (default) mvrx1:mask enable for vrx bit 0: mask disable 1: mask enable (default) mulk1:mask enable for unlck bit 0: mask disable 1: mask enable (default) mcit1: mask enable for cint bit 0: mask disable 1: mask enable (default) maut1:mask enable for auto bit 0: mask disable (default) 1: mask enable mqit1: mask enable for qint bit 0: mask disable 1: mask enable (default) when mask is set to ?1?, corresponding event does not affect int1 pin operation.
asahi kasei [AK4115] ms0573-e-00 2006/12 - 53 - dat mask & dts detect addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h dat mask & dts detect div xmck fast dcnt dts16 dts14 mdat1 mdat0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 1 1 1 1 mdat0: mask enable for dat bit 0: mask disable 1: mask enable (default) the factor which mask bit is set to ?0? affects int0 pin operation. mdat1: mask enable for dat bit 0: mask disable 1: mask enable (default) the factor which mask bit is set to ?0? affects int1 pin operation. dts14: dts-cd 14bit sync word detect 0: disable 1: enable (default) dts16: dts-cd 16bit sync word detect 0: disable 1: enable (default) dcnt: dat start id counter 0: disable 1: enable (default) fast: select pll lock time when the biphase signal is recovered. 0: (20ms + 384/fs) (default) 1: (20ms + 1/fs) xmck: select output frequency of mcko2 (see table 10) 0: depends on cm1-0 bits and ocks1-0 bits (default) 1: fixed to x?tal mode div: mcko2 output frequency select at x?tal mode (see table 10) 0: same frequency as x?tal (default) 1: half frequency of x?tal
asahi kasei [AK4115] ms0573-e-00 2006/12 - 54 - receiver status 0 addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h receiver status 0 qint auto cint unlck vrx stc audion par r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 par: parity error or bi-phase error status 0: no error 1: error this bit goes to ?1?, if a parity error or biphase error is detected in the sub-frame. audion: audio bit output 0: audio 1: non audio this bit is made by encoding channel status bits. stc: sampling frequency or pre-emphasis information change detection 0: no detect 1: detect this bit goes to ?1? when either the fs3-0 or pem bit changes. vrx: validity of channel status for rx 0: valid 1: invalid unlck: pll lock status 0: lock 1: unlock cint: channel status buffer interrupt 0: no change 1: changed this bit goes to ?1? when c-bit stored in register addresses 0ch to 24h changes. auto: non-pcm auto detect 0: no detect 1: detect qint: q-subcode buffer interrupt 0: no change 1: changed this bit goes to ?1? when q-subcode stored in register addresses 40h to 49h changes. stc, qint, cint and par bits are initialized when 07h is read.
asahi kasei [AK4115] ms0573-e-00 2006/12 - 55 - receiver status 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h receiver status 1 fs3 fs2 fs1 fs0 pem dat dtscd npcm r/w rd rd rd rd rd rd rd rd default 0 0 0 1 0 0 0 0 npcm: non-pcm bit stream auto detection 0: no detect 1: detect dtscd: dts-cd bit stream auto detection 0: no detect 1: detect dat: dat start id detect 0: no detect 1: detect dat bit is initialized when 08h is read. pem: pre-emphasis detect 0: off 1: on this bit is made by encoding channel status bits. fs3-0: sampling frequency detection (see table 14) receiver status 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h receiver status 1 0 0 0 0 0 0 qcrc ccrc r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 ccrc: cyclic redundancy check for channel status 0: no error 1: error this bit is enabled only in professional mode and only for the channel selected by the cs12 bit. qcrc: cyclic redundancy check for q-subcode 0: no error 1: error
asahi kasei [AK4115] ms0573-e-00 2006/12 - 56 - clock control addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah clock control tx1ne 0 mck1e mck1e async wsync xsel psel r/w r/w rd r/w r/w r/w r/w r/w r/w default 1 0 1 1 0 0 0 0 psel: setting of pll reference clock (see table 1) xsel: setting of x?tal oscillator (see table 12) wsync: synchronization between the biphase signal and elrck 0: disable (default) 1: enable async: setting of synchronous / asynchronous mode for dit/dir 0: synchronous mode (default) 1: asynchronous mode mck1e: setting of mcko1 output 0: disable. output ?l?. 1: enable (default) mck2e: setting of mcko2 output 0: disable. output ?l?. 1: enable (default) tx1ne: setting of txn1 pin. 0: disable. output ?l?. this mode is useful for consumer. 1: enable (default) tx control addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh tx control msel ecks1 ecks0 edif1 edif0 ctran ccre vtx r/w rd rd r/w r/w r/w r/w r/w r/w default 0 0 1 1 0 0 1 0 vtx: setting of validity bit for tx 0: valid (default) 1: invalid ccre: ccrc enable at professional mode 0: ccrc data is not generated. 1: ccrc data is generated in professional mode. in consumer mode, ccrc data is not generated. (default) ctran: transfer mode of cr191-0 bits 0: not transfer or finish to transfer (default) 1: transfer all cr191-0 bits is transferred to ct191-0 bits when ctran bit changes ?0? to ?1?. the transferred ct191-0 bits are valid after next block start signal is detected. ctran bit goes to ?0? after finishing the transfer. edif1-0: setting of audio interface mode in asynchronous mode. (see table 30) eck1-0: setting of emck input frequency (see table 31) msel: master clock setting for tx in asynchronous mode (see table 4)
asahi kasei [AK4115] ms0573-e-00 2006/12 - 57 - receiver channel status addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch rx channel status byte 0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 ? ? ? ? ? ? ? ? ? ? 23h rx channel status byte 23 cr191 cr190 cr189 cr188 cr187 cr186 cr185 cr184 r/w rd default not initialized cr191-0: receiver channel status byte 23-0 transmitter channel status addr register name d7 d6 d5 d4 d3 d2 d1 d0 24h tx channel status byte 0 ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 r/w r/w default 0 0 0 0 0 1 0 0 25h tx channel status byte 1 ct15 ct14 ct13 ct12 ct11 ct10 ct9 ct8 ? ? ? ? ? ? ? ? ? ? 3bh tx channel status byte 23 ct191 ct190 ct189 ct188 ct187 ct186 ct185 ct184 r/w r/w default 0 ct7-0: transmitter channel status byte 0 default: ?00000100? ct191-8: transmitter channel status byte 23-1 default: ?00000000? burst preamble pc/pd in non-pcm encoded audio bitstreams addr register name d7 d6 d5 d4 d3 d2 d1 d0 3ch burst preamble pc byte 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 3dh burst preamble pc byte 1 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 3eh burst preamble pd byte 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 3fh burst preamble pd byte 1 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 r/w rd default not initialized pc15-0: burst preamble pc byte 0 and 1 pd15-0: burst preamble pd byte 0 and 1
asahi kasei [AK4115] ms0573-e-00 2006/12 - 58 - q-subcode buffer addr register name d7 d6 d5 d4 d3 d2 d1 d0 40h q-subcode address / control q9 q8 q7 q6 q5 q4 q3 q2 41h q-subcode track q17 q16 q15 q14 q13 q12 q11 q10 42h q-subcode index q25 q24 q23 q22 q21 q20 q19 q18 43h q-subcode minute q33 q32 q31 q30 q29 q28 q27 q26 44h q-subcode second q41 q40 q39 q38 q37 q36 q35 q34 45h q-subcode frame q49 q48 q47 q46 q45 q44 q43 q42 46h q-subcode zero q57 q56 q55 q54 q53 q52 q51 q50 47h q-subcode abs minute q65 q64 q63 q62 q61 q60 q59 q58 48h q-subcode abs second q73 q72 q71 q70 q69 q68 q67 q66 49h q-subcode abs frame q81 q80 q79 q78 q77 q76 q75 q74 r/w rd default not initialized optional control addr register name d7 d6 d5 d4 d3 d2 d1 d0 4ah optional control 0 0 0 0 0 0 ctx 0 r/w rd rd rd rd rd rd r/w rd default 0 0 0 0 0 0 0 0 ctx: setting of channel status information for aes3 mode 0: channel status information on daux is sent from tx (default) 1: channel status information in control registers (ctx191-0 bits) is sent from tx.
asahi kasei [AK4115] ms0573-e-00 2006/12 - 59 - ? burst preambles in non-pcm bitstreams 0 16 bits of bitstream 34 7 811 12 27 28 29 30 31 preamble aux. lsb msb v u c p sub-frame of iec958 015 pa pb pc pd burst_payload stuffing repetition time of the burst figure 50. data structure in iec60958 preamble word length of field contents value pa 16 bits sync word 1 0xf872 pb 16 bits sync word 2 0x4e1f pc 16 bits burst info see table 33 pd 16 bits length code numbers of bits table 32. burst preamble words bits of pc value contents repetition time of burst in iec60958 frames 0-4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-31 data type null data dolby ac-3 data reserved pause mpeg-1 layer1 data mpeg-1 layer2 or 3 data or mpeg-2 without extension mpeg-2 data with extension mpeg-2 aac adts mpeg-2, layer1 low sample rate mpeg-2, layer2 or 3 low sample rate reserved dts type i dts type ii dts type iii at r a c at r a c 2 / 3 reserved 4096 1536 384 1152 1152 1024 384 1152 512 1024 2048 512 1024 5, 6 0 reserved, shall be set to ?0? 7 0 1 error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors 8-12 data type dependent info 13-15 0 bit stream number, shall be set to ?0? table 33. fields of burst info pc
asahi kasei [AK4115] ms0573-e-00 2006/12 - 60 - ? non-pcm bitstream timing 1) when non-pcm preamble is not coming within 4096 frames, pa pc 1 pd 1 pb pa pc 2 pd 2 pb pa pc 3 pd 3 pb ?0? pc 1 pc 2 ?0? pd 1 pd 2 pd 3 pc 3 pdn pin bit stream auto bit pc register pd register re p etition time >4096 frames figure 51. timing example 1 2) when non-pcm bitstream stops (when mulk0=0), pa pc 1 pd 1 pb stop pa pc n pd n pb pc 0 pc 1 pd 0 pd 1 pd n pc n int0 pin bit stream auto bit pc register pd re g iste r int0 hold time 2~3 syncs (b,m or w) < pll lock time asahi kasei [AK4115] ms0573-e-00 2006/12 - 61 - system design figure 53 shows the example of system connection diagram for 4-wire serial mode. rx5 1 2 3 4 5 6 7 8 9 10 11 test(avss) rx6 pdn rx7 dvdd vin daux dvss mcko1 mcko2 top view rx4 64 63 62 avdd rx3 61 60 58 57 59 55 54 56 53 avss rx2 avdd rx1 avss rxp0 rxn0 acks p/sn 12 o vdd 13 ovss 14 bic k 15 sd to 16 lrc k 52 avdd 51 vcom 50 r 49 avss b 17 c 18 u 19 vout 20 tvdd 21 tx0 22 txp1 23 txn1 24 tvss 25 xti1 26 xto1 27 xti2 28 xto2 29 ovdd 30 ovss 31 ebick 32 44 43 42 41 40 39 38 37 36 35 34 33 iic bvss dvss dvdd csn cclk cdti cdto int1 int0 elrck emck 45 psel 46 xt l0 47 xt l1 48 filt 100p 24k ? up 10k ? 4.7 c1 10n dsp2 dsp1 up s/pdif sources s/pdif sources s/pdif out 5v 3.3v 3.3v 3.3v c1 c1 c2 c2 c1 c1 c1 c2 c c cc c1 c2 c1 c2 + + + + + + c1: 0.1 c2: 10 3.3v figure 53. typical connection diagram (4-wire serial mode) notes: - for setting of xtl0 and xtl1, refer the table 13. - ?c? depends on the crystal. - avss, bvss, tvss, ovss and dvss must be connected the same ground plane. - digital signals, especially clocks, should be kept away from the r and filt pins in order to avoid an effect to the clock jitter performance.
asahi kasei [AK4115] ms0573-e-00 2006/12 - 62 - package 1 16 64 17 10.0 12.0 0.3 10.0 12.0 0.3 0.22 0.05 64pin lqfp(unit:mm) 0.10 49 32 33 48 0.17 0.05 1.40 0.10 0.05 0 10 0.10 m 0.5 0.2 0.5 +0.05 -0.05 1.70max ? material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [AK4115] ms0573-e-00 2006/12 - 63 - marking 1 akm AK4115vq xxxxxxx xxxxxxx: date code identifier revision history date (yy/mm/dd) revision reason page contents 06/12/13 00 first edition
asahi kasei [AK4115] ms0573-e-00 2006/12 - 64 - important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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