View W110_889170.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 oki semiconductor W110 dual-speed ethernet controller 100mbps + 10mbps ethernet media access controller mega macrofunction description the W110 is a 100base-t ethernet media access controller (mac) mega macrofunction for dual-speed operation (100mbps/10mbps) and an mii interface. implemented in 0.5 m m and 0.8 m m technologies, the W110 supports a wide range of physical layer (phy) devices, including both 100mbps and 10mbps devices for wired, optical, and wireless networks, operating in half- or full-duplex mode. the W110 mega macrofunction is available in various configurations, depending upon customer parti- tioning requirements. the W110 contains two main submodules, called mac110 and pcs110. the mac110 submodule contains the key transmit/receive functions and performs the csma/cd function specified in iso/iec 8802-3: 1993 and the supplemental ieee standard 802.3u-1995. the pcs110 submod- ule contains various phy support modules and mii support. potential applications include network interface controllers (nics), multiport switches, switching routers, hubs, and test equipment. the mac110 submodule contains ~10.1k gates. the final top-level gate count is determined by which par- ticular pcs option is chosen by the user. the W110m option (transmit and receive function with mii inter- face only) contains ~7.1k gates. a gate-level model of the mega macrofunction is available in verilog or vhdl. features supported asic families family name technology family type msm38s0000 0.8 m m tlm sea of gates msm98s000 tlm customer structured array msm12r/32r0000 0.5 m m dlm sea of gates msm13r/30r0000 tlm sea of gates msm98r/92r000 tlm customer structured array support for 10 or 100 mbps mii-based phy devices, including: - 100base-tx - 100base-fx - 100base-t4 support for tp-pmd and fiber-pmd (fddi) devices complies with iso/iec 802-3:1993 and ieee std. 802.3u-1995 generates transmit/receive statistics vectors autonegotiation support support for endec devices full-duplex ethernet support pcs functions 4b/5b, and scrambling optimized for switching and multi-port applications generic interface supporting various buses, including isa, pci, mca, vlb, sbus, nubus, scsi, and multibus additional submodules available for packet filtering, statistics collection, and bus interface with fifo
n W110 dual-speed ethernet controller n 2 oki semiconductor recommended operating conditions (v ss = 0v) parameter symbol rated values unit min. typ. max. power supply voltage (5v operation) v dd 4.75 5.0 5.25 v power supply voltage (3v operation) v dd 2.7 3.3 3.6 v operating temperature t j -40 +25 +85 c mega macrofunction characteristics mega macrofunction description logic gate count logic pin count W110 dual-speed ethernet mac ~10,100 163 figure 1. logic symbol tx_clk txcen txd[3:0] tx_en tx_er crs col ppaden pcrcen phugen overr tpd[7:0] tpsf tpur tpef tpud tpdn tprt tpab tsvp tsv[25:0] transmit signals W110 rpd[7:0] rpsf rpdv rpef rsvp rsv[20:0] hclk hcs_l hrw ha[8:1] hdi[15:0] trst hdo[15:0] hrst_l receive signals host signals rrst rx_clk rxcen rxd[3:0] rx_dv rx_er mdc mdo mdoen mdi srxen crco[8:0] crcg bco mco mii management per-packet control miscellaneous signals auxiliary outputs mii signals
n W110 dual-speed ethernet controller n 3 oki semiconductor rfun tfun transmit status transmit data receive data receive status txd[3:0], tx_en, tx_er rx_clk, rxd[3:0], rx_dv, rx_er tx_clk, col, crs ptxen mac110 pcs110 100 mb interface 10 mb interface mii signals mii management autonegotiation pma phy user interface network interface W110 figure 2. W110 block diagram figure 3. example of W110 application: pci ethernet controller host write host cpu access W110 dual-speed mac network device i.e., 10/100 mii tp-pmd or endec communication signals management signals customer asic (including higher-level functions) host read
n W110 dual-speed ethernet controller n 4 oki semiconductor signal descriptions transmit byte stream signals the following table lists the transmit byte stream signals between host system and the W110 mega mac- rofunction. all signals are synchronous with the rising edge of tx_clk unless otherwise indicated. signal direction is with respect to the W110 function block. signal type assertion description tpd[7:0] input high transmit packet data. these eight signal lines transfer the transmit data byte from the asic? internal logic into the W110 mega macrofunction. tpsf input high transmit packet start of frame. when asserted high, this signal marks the availability of the first byte of a transmit packet on tpd[7:0]. tpur input high transmit packet data under-run. when asserted high, this signal discontinues transmission. tpef input high transmit packet end of frame. when asserted high, this signal indicates that the last byte of a transmit packet is available on tpd[7:0] tpud output high transmit packet use data. when asserted high, this signal indicates that data transmission has begun. tpdn output high transmit packet done. when asserted high, this signal indicates successful completion of the packet transmission process. tprt output high transmit packet retry. when asserted high, this signal indicates that a collision was encountered during the transmit attempt. tpab output high transmit packet abort. when asserted high, this signal indicates that the W110 has discontinued transmission. tsv[25:0 ] output transmit status vector. these 26 signals indicate the status of the transmit data byte, as shown below. bit meaning bit meaning 25 transmit ok. 12 collision count bit 0. 24 tx abort - late collision. 11 late collision. 23 tx abort - excessive deferral. 10 transmit byte count bit 10. 22 tx abort - excessive collisions. 9 transmit byte count bit 9. 21 tx abort due to under-run. 8 transmit byte count bit 8. 20 tx abort - jumbo. 7 transmit byte count bit 7. 19 packet deferred. 6 transmit byte count bit 6. 18 broadcast packet transmitted. 5 transmit byte count bit 5. 17 multicast packet transmitted. 4 transmit byte count bit 4. 16 crc error. 3 transmit byte count bit 3. 15 collision count bit 3. 2 transmit byte count bit 2. 14 collision count bit 2. 1 transmit byte count bit 1. 13 collision count bit 1. 0 transmit byte count bit 0. tsvp output high transmit status vector pulse. when asserted high, this signal indicates that the transmit byte stream status vector, on tsv[25:0], is valid.
n W110 dual-speed ethernet controller n 5 oki semiconductor
n W110 dual-speed ethernet controller n 6 oki semiconductor receive byte stream signals the following table lists the receive byte stream signals between the host system and the W110 mega mac- rofunction. all signals are synchronous with the rising edge of the rx_clk signal. signal direction is with respect to the W110 function block. signal type assertion description rpdv output high receive packet data valid. the W110 mega macrofunction asserts this output high to indicate that the data on rpd[7:0] is valid. rpsf output high receive packet start of frame. the W110 mega macrofunction asserts this output high to indicate that the first data byte of a received packet is available on rpd[7:0] rpef output high receive packet end of frame. the W110 mega macrofunction asserts this output high to indicate that the last byte of a received data packet is available on rpd[7:0] rpd[7:0] output high receive packet data. these eight signals carry the received data byte to the asic internal logic. rsv[20:0] output high receive status vector. these 21 bits indicate the status of the receive packet, as shown below. bit meaning bit meaning 20 carrier event previously seen. 10 packet length bit 10. 19 rxdv event previously seen. 9 packet length bit 9. 18 receive ok. 8 packet length bit 8. 17 broadcast packet. 7 packet length bit 7. 16 multicast packet. 6 packet length bit 6. 15 crc error. 5 packet length bit 5. 14 dribble nibble. 4 packet length bit 4. 13 receive code violation. 3 packet length bit 3. 12 long packet. 2 packet length bit 2. 11 short packet. 1 packet length bit 1. 0 packet length bit 0. rsvp output high receive status vector pulse. when asserted high, this output indicates that the receive packet status is valid on rsv[20:0]
n W110 dual-speed ethernet controller n 7 oki semiconductor host interface lines the following table lists the host interface lines that access the W110 mega macrofunction for interfacing to isa, pci, mca, vlb, s-bus, nubus, scsi, and multibus systems. signal direction is with respect to the W110 function block. auxiliary outputs the following table lists the control lines used in receive packet filtering. all signals are synchronous with the rx_clk rising edge. signal direction is with respect to the W110 function block. signal type assertion description hclk input host clock. the W110 mega macrofunction can use a 25mhz or 33mhz user- selectable clock frequency. hcs_l input low host chip select. when asserted low, this signal enable the host read or host write cycles. hrw input host read/write select. when asserted low, this signal selects a host write cycle. when asserted high, this signal selects a host read cycle. ha[8:1] input host address. this address bus selects the address for the host register. hdi[15:0] input host write data. data on this bus is written into the selected register during a host write cycle. hdo[15:0] output host read data. this bus carries the output data during the host read cycle. hrst_l input low host reset. when external logic asserts this signal low, the host resets the mac subsystem. trst output high transmit synchronized host reset. the W110 mega macrofunction asserts this signal high relative to tx_clk to indicate that the W110 has performed a reset after the assertion of hrst_l. rrst output high receive synchronized host reset. the W110 mega macrofunction asserts this signal high relative to rx_clk to indicate that the W110 has performed a reset after the assertion of hrst_l. signal type assertion description crco[8:0] output crc output. this signals contain crc data for external hash table lookup. see the W110 data sheet for more information. crcg output high crc qualifier. this signal validates the crc output to the external hash table. bco output high broadcast packet indicator. when asserted high, this signal indicates that the received data is a broadcast packet. mco output high multicast packet indicator. when asserted high, this signal indicates that the received data is a multicast packet.
n W110 dual-speed ethernet controller n 8 oki semiconductor mii signals the mii interface signals are listed below. signal direction is with respect to the W110 function block. see ieee 802.3u standard documentation for further information. signal type assertion description tx_clk input ? transmit symbol clock. this transmit nibble or symbol clock input is derived from the phy layer. the following table indicates the frequency and type of transmit symbol clock for various phy options. txcen output high transmit clock enable. in 10-mbps mode, txcen is the 10-mhz endec clock divided by four. in 100-mbps mode, the W110 asserts txcen high. txd[3:0] output transmit nibble data. this bus outputs data from the transmit function, synchronous with tx_clk tx_en output high transmit enable. the transmit function outputs this enable signal, synchronous with tx_clk. tx_er output high transmit error. when asserted high, this signal indicates a transmission error. this is a synchronous signal with the rising edge of tx_clk. crs input high carrier sense. this input receives information via the mii multiplex and is considered to be asynchronous. col input high collision. this input transmits information via the mii multiplex and is considered to be asynchronous. for half-duplex transceivers, the assertion of this signal indicates simultaneous transmission and reception. full-duplex transceivers never activate this signal. rx_clk input receive symbol clock. the phy layer produces this symbol clock or receive nibble input. the following table indicates the frequency and type of receive symbol clock for various phy options. rxcen output high receive clock enable. in 10-mbps mode, rxcen is the 10-mhz endec clock divided by four. in 100-mbps mode, the W110 assert srxcen high. rxd[3:0] input receive nibble data. this synchronous input indicates that nibble data has been received on the rising edge of rx_clk. rx_dv input high receive data valid. this synchronous input validates received data on the rising edge of rx_clk. rx_er input high receive error. the W110 reads this signal input on the rising edge of rx_clk. the presence of receive errors usually indicates bad wiring. mode tx_clk txcen 100-mbps mii phy 25 mhz high 10-mbps mii phy 2.5 mhz high 10-mbps endec 10 mhz 2.5 mhz ( 1 / 4 duty cycle) mode mrxc rxcen 100-mbps mii phy 25 mhz high 10-mbps mii phy 2.5 mhz high 10-mbps endec 10 mhz 2.5 mhz ( 1 / 4 duty cycle)
n W110 dual-speed ethernet controller n 9 oki semiconductor mii management signals the table below lists mii management signals. signal direction is with respect to the W110 function block. see the ieee 802.3u standard documentation for further information. per-packet control the following signals override the programmed configuration on a per-packet basis. signal direction is with respect to the W110. miscellaneous signals the following signals provide additional functionality for the W110 mega macrofunction. signal direction is with respect to the W110. signal type assertion description mdc output high management data clock. the W110 mega macrocell derives this signal from the hclk input. mdo output high management data output. to form the external bidirectional mii signal mdio, combine this signal with mdi in a chip i/o buffer. use the mdoen signal to 3-state the i/o buffer output. mdi input high management data input. to form the external bidirectional signal mdio, combine this signal with mdo in a chip i/o buffer. use the mdoen signal to 3-state the i/o buffer output. mdoen output high management data output enable. use this output to 3-state the mdio i/o buffer output, formed from combining the mdi input and mdo output. signal type assertion description ppaden input per-packet pad enable. if overr is ??then the value of ppaden is input to tfun. pcrcen input per-packet crc enable. if overr is ??then the value of pcrcen is input to tfun. phugen input per-packet huge enable. if overr is ??then the value of phugen is input to tfun. overr input per-packet override. when logic external to the W110 mega macrofunction sets this bit to ?? then the per-packet controls are input to tfun. when set to ?? then the values from an internal configuration register are gated to tfun instead. signal type assertion description srxen input synchronized receive enable. when logic external to the W110 mega macrofunction sets this bit to ?? then rfun outputs received frame data. when set to ?? then rfun does not output received frame data.
n W110 dual-speed ethernet controller n 10 oki semiconductor functional description the W110 consists of five function blocks which are partitioned into the two main submodules, mac110 and pcs110. the mac110 module contains the ethernet mac functions in two submodules, called tfun and rfun. - the mac110 tfun submodule contains the mac transmit functions. - the mac110 rfun submodule contains the mac receive functions. all asic implementations using the W110 must include both the tfun and rfun modules. the pcs110 module contains the i/o functions. the pcs110 module contains a collection of submodules that support connectivity to the network media through a variety of phy devices. a given implementation may require one or all of these submodules, depending on the flexibility required, to support a 100-mbps interface, 10-mbps interface, and/or mii. included in the mac110 and pcs110 modules is supporting logic for the host interface. if the W110 is used to create a multiport device like a switch, this interface will typically be to the embedded processor. in the case of an end-station implementation, this might be the end-station bus. again, the host interface needs to be created for the individual application. management statistics the W110 transmit and receive functions do not implement large numbers of counters for statistics collec- tion. the W110 mega macrocell uses the vector-generation method instead. the vector technique has the effect of simplifying the timing of lots of asynchronous events. the vector method is also more efficient in multiple-mac systems, because a single logic block can per- form statistics accumulation for all of the macs in the system, reducing gate count and improving pro- cessing efficiency. however, the designer must then create a statistics gathering mechanism outside the mac on a case-by-case basis. oki supports an optional module to perform statistics collection. please contact oki asic application engineering for more information.
n W110 dual-speed ethernet controller n 11 oki semiconductor applications switch building blocks oki has optimized the W110 for use in multiple-mac applications. these applications include switches, multi-port interface cards and routers. figure 4 shows a typical application where the W110 is used as a building block for an eight-port switch. figure 4. using the W110 in an eight-port ethernet switch the exact nature of the common sections for system data transport, address recognition and statistics will be application dependent. the W110 has enough built-in flexibility to cover almost any system concept. the phy devices are currently supported externally to the design. a logical mii supports the external interface for the network. network interface controllers the example in figure 5 below shows the W110 implemented in a network controller ic. the ic is used to create a pci-based network controller for pcs. figure 5. single mac implementation this application shows that address resolution for the W110 occurs after the data has left the mac as a byte stream. this approach makes little difference in a single-mac application. the approach does improve the design of multiple-mac applications. W110 W110 W110 W110 W110 W110 W110 W110 mii mii mii mii mii mii mii mii phy phy phy phy phy phy phy phy common system data transport common address recognition logic common statistics collection common host processor interface media media media media media media media media W110 dual-speed mac phy media host bus interface module address recognition statistics gathering end station bus
n W110 dual-speed ethernet controller n 12 oki semiconductor management statistics are generated as vectors by the W110. a mechanism is required externally to collect these vectors and parse the information appropriately. oki can provide an additional module to perform statistics collection. the generalized byte streams of data may be interfaced to any bus type. depending on the sophistication and the bus, the bus interface module might range from a trivial to a very complex implementation. the W110 can be implemented with isa, pci, mca, vlb, sbus, nubus, scsi, multibus and many more. physical layer options a logical mii forms the output from the mac, sending data to the network, and the input to the mac, receiving data from the network. the logical mii provides a uniform interface for all possible implemen- tations of the mac. a combination of the supporting i/o modules and the i/o multiplexer converts the logical mii signals to the appropriate driver levels. there are several different possible final interfaces, including true mii devices at 100 mbps or 10 mbps, tp-pmd devices such as the pdt/pdr combination, and 10 mbps endec devices. a given implementation of the W110 may use any combination of these outputs. the more output types used in the design, the more complex the multiplexing circuits must be. figure 6 shows the data flows for each type of device implementation. figure 6. mii and i/o multiplex data paths the diagrams below show the transmit packet data flow path and the receive packet data flow path. the host system supplies data for transmission to the network as a stream of bytes. the transmit function block performs the ethernet mac operations. the output of the transmit function flows across the logical mii lines to the mii multiplexer. if the external phy device is a mii-based phy, the mii multiplex and i/o multiplex blocks connect the internal mii lines directly to the output pins. when using an external tp- pmd phy device, the mii multiplexer routes the internal mii lines to the 100base-x submodule. the out- put of the 100base-x submodule is connected to the output pins via the i/o multiplexer. logical mii lines mii multiplex 10 mbps serializer/deserializer 10 mbps endec xcvr 100 mbps endec xcvr 100base-x submodule asic i/o pins (functions are multiplexed) tp-pmd devices 100base-t mii devices 10base-t devices 100base-tx media 100base-t4 media 10base-t media mii management mac110 module pcs110 module W110 mega macrofunction user interface
n W110 dual-speed ethernet controller n 13 oki semiconductor if an external 10base-t endec is being used, the mii multiplexer routes the internal mii lines to the 10base-t module. the i/o multiplexer connects the output of the module to the output pins. figure 7. transmit and receive data paths similarly, the receive data path flows through the appropriate modules, routed by the i/o multiplexer. the mii multiplexer then connects the appropriate module outputs to the receive function. the receive function performs the ethernet mac operations. the mii interface the W110 communicates with external phy devices through the logical mii interface. the logical mii is divided into two signal sets. one set handles data transmission and reception while the second set handles mii management functions. figure 8. mii data and management signal sets within the W110, the data function are handled by the tfun and rfun modules. the mii management set is handled by the mii module. host access to the management interface is on a word basis through the normal host interface. the interface between the mii and the external phy is a clocked serial interface as defined in the ieee 802.3u standard. transmit byte stream signals transmit function mii multiplex i/o multiplex 100base-x submodule 10base-t submodule external phy logical mii transmit lines 4b signals 4b signals 5b signals endec signals (a) transmit data path receive byte stream signals receive function mii multiplex i/o multiplex 100base-x submodule 10base-t submodule external phy logical mii receive lines 4b signals 4b signals 5b signals endec signals (b) receive data path tfun module rfun module W110 dual-speed mac phy media host system mii-data mii-management
n W110 dual-speed ethernet controller n 14 oki semiconductor statistics gathering and vectors most activity in a mac is centered around major events such as completion of packet reception or com- pletion of packet transmission attempts. when these major events occur, the W110 generates a statistics vector, summarizing the detailed results associated with the event. the vector can be latched into a sepa- rate statistics collection block. a vector is latched once for each major event. this vector approach reduces the requirement for individual synchronization of many individual events. the approach also reduces the gate count by eliminating the need for flip-flops scattered around the mac design. when multiple-mac designs are involved, the statistics collecting block may be common for all macs. again, the vector approach reduces the complexity of the design and the gate count. central statistics gathering is also easier than distributed gathering when it comes to parsing cumulative and derivative sta- tistics. there are generally two different vectors, one for receive and one for transmit. vectors may be designed to include or exclude as many different parameters as a customer requires. examples of vectors and parameters are shown in the following table. in the above implementation example, the transmit vector is 26 bits long and the receive vector is 21 bits long. vector implementations are not limited to these parameters or lengths. statistics vector parameters transmit status bit receive status bit transmit status bit bi t meaning bi t meaning bit meaning bi t meaning 25 transmit ok. 12 collision count bit 0. 20 carrier event previously seen. 10 packet length bit 10. 24 tx abort - late collision. 11 late collision. 19 rxdv event previously seen. 9 packet length bit 9. 23 tx abort - excessive deferral. 10 transmit byte count bit 10. 18 receive ok. 8 packet length bit 8. 22 tx abort - excessive collisions. 9 transmit byte count bit 9. 17 broadcast packet. 7 packet length bit 7. 21 tx abort due to under- run. 8 transmit byte count bit 8. 16 multicast packet. 6 packet length bit 6. 20 tx abort - jumbo. 7 transmit byte count bit 7. 15 crc error. 5 packet length bit 5. 19 packet deferred. 6 transmit byte count bit 6. 14 dribble nibble. 4 packet length bit 4. 18 broadcast packet transmitted. 5 transmit byte count bit 5. 13 receive code violation. 3 packet length bit 3. 17 multicast packet transmitted. 4 transmit byte count bit 4. 12 long packet. 2 packet length bit 2. 16 crc error. 3 transmit byte count bit 3. 11 short packet. 1 packet length bit 1. 15 collision count bit 3. 2 transmit byte count bit 2. 0 packet length bit 0. 14 collision count bit 2. 1 transmit byte count bit 1. 13 collision count bit 1. 0 transmit byte count bit 0.
n W110 dual-speed ethernet controller n 15 oki semiconductor address recognition the W110 does not perform address recognition in the body of the mac. address recognition is per- formed downstream on the receive byte stream. this arrangement improves the design of multiple-mac implementations. in multiple-mac implementations, the receive byte streams from several macs can be directed to a central address recognition logic block. this common arrangement reduces gate count, speeds processing and improves management access and control. oki does support a separate block to perform address recognition. please contact oki asic application engineering for more information. host interface options the W110 connects to a host system of a customer-specified type. many different types of host interface may be used. examples include sophisticated bus-mastering types such as pci, shared memory, ring- buffer, dma and fifo-based designs. in a switch system, the host generally is an embedded cpu or a backplane switching fabric. in a general network interface, the host might be a general purpose computer communicating over the computer bus. the W110 communicates to the host system using generalized receive and transmit byte streams. oki can provide an additional module for interfacing to 16-, 32-, or 64- bit host interfaces with dma and fifo. figure 9. example of W110 interface to host system testing oki semiconductor provides appropriate test vectors to verify the timing and functionality of each design implementation. oki also creates appropriate test bench modules during development. contact the oki asic application engineering department for more information. host system address recognition logic receive byte stream logic transmit byte stream logic host processor interface statistics vector interface W110 dual-speed mac transmit byte stream receive byte stream
n W110 dual-speed ethernet controller n 16 oki semiconductor glossary term definition 10base-t 10mbps utp transceiver type. iso/iec 8802-3 physical layer and media type specification for 10mbps baseband data rate using two pairs of utp wire. 100base- t 100mbps transceiver type. ieee 802.3u physical layer and media type specification for 100mbps baseband data rate using two or four pairs of category 5 or category 3 (respectively) utp wire. 4b 4 bit. 5b 5 bit. ansi american national standards institute. asic application specific integrated circuit. autoneg autonegotiation. the ability to differentiate between 10mbps and 100mbps connections, and automatically establish communications with the remote unit. cpu central processing unit. crc cyclic redundancy check. a logical coding system for error detection and correction on an established connection. dma direct memory access. a method of accessing memory where a peripheral will ?teal?bus cycles from the cpu. during these cycles, the peripheral will directly access memory. ecu embedded control unit. endec encoder-decoder. a device used to convert an ethernet bit stream into the manchester-encoded data required for transmission on a lan, and vice-versa. fddi fiber distributed data interface. a lan technology specifying a data rate of 100 mbps which has sophisticated redundancy features. the phy of fddi was used as the basis for the development of the x components of 100base-t (100base-tx and 100base-fx). fifo first-in first-out queue. a buffer mechanism that ensures the order of data is maintained. fifos are asynchronous. hdl hardware description language. term for logical descriptive languages used in chip design. ieee institute of electrical and electronics engineers. professional engineering society that promotes formal standards through the ieee standards board. the actual work of creating standards is conducted through a framework of committees, sub-committees and task forces. the most relevant committee for this document is the lams (lan-man standards committee) which is responsible for the ethernet standard ieee 802.3. i/o input/output. iso international organization for standardization. ietf internet engineering task force. the body charged with setting the operating standards for the internet. lan local area network. lams lan-man standards committee. mac media access control. protocol used to control access to the physical layer by upper communications layers. man metropolitan area network. mib management information base. a collection of management variables linked by some common factor. mii medium independent interface. the interface between the ethernet mac and phy layers as defined in ieee 802.3u. the mii separates the mac function (common to all implementations) from the phy components which vary with the type of medium being used. packet a collection of data and control information. a packet makes up a recognizable single unit that can be dealt with by lan and communications systems. packets generally have variable length as opposed to cells which are fixed length. rules for packet construction vary from system to system and protocol to protocol.
n W110 dual-speed ethernet controller n 17 oki semiconductor pdt/pdr physical data transmitter/physical data receiver. a pair of devices that provide parallel-to-serial and serial-to- parallel conversions. pdt accepts parallel input of 5b symbols and converts them into a serial nrzi data stream at 125m baud. the pdr provides the reverse function. phy physical layer device. a phy usually consists of the analog and supporting components of a transmission scheme associated with a particular medium. pld programmable logic device. pma physical medium attachment. a sublayer of the phy responsible for analog functions, such as transmit wave shaping (the t4 standard). pmd physical medium dependent (interface). a sublayer of the phy layer responsible for analog functions, such as receive data discrimination (tx/fx standards). pqfp plastic quad flat pack. rfc request for comments. the name given to standards and discussion documents in the ietf. rmon remote monitoring mib. a mib covering nine groups of management variables associated with network probe devices. rmon is defined by rfc 1757. sram static random access memory. tp twisted pair. used to describe copper cables where pairs of wires are twisted around each other to provide balanced electrical characteristics. tp-pmd twisted-pair pmd. the name given to the pmd layer of the copper version of the fddi specification. utp unshielded twisted pair. the standard wire interconnection medium used for thin ethernet 10mbps connectivity. vhdl very high-speed integrated circuit hardware description language. one of several hdls in use. vhdl has been standardized by the ieee. xcvr transceiver. glossary (continued) term definition
oki semiconductor the information contained herein can change without notice owing to product and/or technical improvements. please make sure before using the product that the information you are referring to is up-to-date. the outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. when you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. certain parts in this document may need governmental approval before they can be exported to certain countries. the purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. copyright 1995 oki semiconductor oki semiconductor reserves the right to make changes in specifications at anytime and without notice. this information furnished by oki semiconductor in this publication is believed to be accurate and reliable. however, no responsibility is assumed by oki semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. no license is granted under any patents or patent rights of oki.
northwest area 785 n. mary avenue sunnyvale, ca 94086 tel: 408/720-8940 fax:408/720-8965 southwest area 2302 martin street suite 250 irvine, ca 92715 tel: 714/752-1843 fax:714/752-2423 central area 2007 n. collins blvd. suite 303 richardson, tx 75080 tel: 214/690-6868 fax:214/690-8233 southeast area 1590 adamson parkway suite 220 morrow, ga 30260 tel: 404/960-9660 fax:404/960-9682 eastern area shattuck office center 138 river road andover, ma 01810 tel: 508/688-8687 fax:508/688-8896 automotive electronics 17177 n. laurel park drive suite 433 livonia, mi 48152 tel: 313/464-7200 fax:313/464-1724 oki r egional s ales o ffices corporate headquarters 785 n. mary avenue sunnyvale, ca 94086-2909 tel: 408/720-1900 fax:408/720-1918 for oki literature: call toll free 1-800-oki-6388 (6 a.m. to 5 p.m. pacific oki stock okifax service: (800) oki-6994 oki web site: http://www.okisemi.com 010111-001
n W110 dual-speed ethernet controller n 20 oki semiconductor

▲Up To Search▲

Price & Availability of W110

	To Download W110 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .