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1 features ? hardware ? supports programming for atmel at40k/at40kal and at94kalseries of sram-based programmable system level integration (psli) devices ? supports isp (in-system programming) for atmel at17 series configuration eeproms ? built-in clock source with gclk/fclk jumper settings ? supports modular docking platform for the atdh40d fpga daughter boards ? runs off portable 9v dc power supply or external power ? supports 5.0v or 3.3v supply ? designed to work with atmel ids 5.0 or above ? downloading for at40k/at17 devices direct from pc parallel port ? can be used to support fpslic system contents ? atdh2081 25-pin parallel to 10-pin header adapter ? ATDH40DXXX package-specific daughterboard (variable) ? atdh40m programming motherboard ? standard parallel cable (pc parallel port db25), 10-pin header cable, 9v dc/200 ma, 2.1 mm center positive power supply description the atmel atdh40m prototyping system allows designers to quickly and economi- cally evaluate atmel?s family of at40k/at40kal fpga and at94k field programmable system level integrated circuit (fpslic ? ) devices and atmel?s at17 fpga configuration memory devices. the atdh40m board connects to any x86 pc via parallel port through a 10-pin header cable to program the at40k/at40kal fpga/at94k fpslic, or through a parallel port cable to program the at17 fpga configuration eeproms. the motherboard interfaces with various daughter boards in order to program different package footprints (see table 1). table 1. daughter board support list part number description atdh40d84 84-pin plastic lead chip carrier atdh40d100 100-pin very thin quad flat pack atdh40d100r 100-pin rectangular quad flat pack atdh40d144 144-pin thin quad flat pack atdh40d160 160-pin plastic quad flat pack atdh40d208 208-pin plastic quad flat pack atdh40d240 240-pin plastic quad flat pack programmable system level integration prototyping system atdh40m ATDH40DXXX rev. 1402b?06/01
atdh40m/d 2 the at40k/at40kal fpga devices are pin-compatible in a given package footprint across the family. see table 2 for compatibility listings. the 208pqfp, for example, will sup- port all at40k family members. fpslic is pin-compatible with at40k/at40kal device families and is supported by the atdh40m prototyping system. note: 1. daughtercard not available for atdh40m. 2. not all devices are available in all package options. please check appropriate datasheet for a list of valid part/package combinations. programming setup figure 1 on page 3 is the board layout of the atdh40m motherboard. figure 2 shows the typical daughter board. to con- nect the two boards together, the daughter board fits on top of the motherboard by aligning the two arrows together. the two boards will only fit one way. table 2. part and package availability showing user i/o counts package ordering code at40k05/ at40k05al/ at94k05al at40k10 at40k10al at94k10al at40k20/ at40k20al at40k40/ at40k40al at94k40al pc84 aj 62 62 62 62 vq100 aq 78 78 - - rq100 rq 78 78 77 - tq144 bq 114 114 114 114 pq160 cq 128 130 130 - pq208 dq 128 161 161 161 bg225 (1) ag - 192 192 192 pq240 eq - 192 193 193 pq304 (1) fq - - 256 256 bg352 (1) bg - - 256 289 bg432 (1) cg---352
atdh40m/d 3 figure 1. motherboard layout ? atdh40m
atdh40m/d 4 figure 2. daughter board layout example ? atdh40d84 power configuration power for the motherboard can come from two sources. it can be supplied by either the jack inputs j1 and j2, or by a 9v power input p1. the source that will drive the mother- board is determined by switch sw3. power supplied by the jacks uses the external setting. power supplied by the 9v source uses the internal setting. voltage on the motherboard for the latter setting is regulated by switch sw2. lv parts use the 3.3v setting while the rest use the 5.0v setting. the led l1 will light up only when power is correctly supplied to vcc. table 3 lists the possible configurations. at40kal and at94kal devices must use 3.5v power setting. program/boot settings switches sw4 and sw5 determine the program and boot settings for the atdh40m. they are located on the bottom left corner. table 4 lists the switch combinations and their effects. sw4 controls the seren signal line of the mother- board to the 2:1 multiplexer (device u3) and the at17 (device u1). sw% connects signal d0 from the psli device to either the at17 configuration memory device only (down) or to the pc interface (up). table 3. motherboard power distribution sw1 sw2 sw3 voltage off x x 0.0v (no power) on x external variable on 3.3v internal 3.3v for at40kal/at94kal on 5.0v internal 5.0v for at40k table 4. programming modes sw4 sw5 effect up up program in slave serial from pc down up program at17 configuration memory up down program in master serial from at17
atdh40m/d 5 programming the at40k fpga device when sw4 and sw5 are set to up, the psli device can be programmed by the pc parallel interface. the atdh40m interfaces with the pc through the 10-pin header socket h1 located on the bottom right corner. programming the fpga is not possible by using the parallel port interface on the motherboard. located below the header h1 are the mode- select dip-switches dip-sw1. these control the mode set- tings for the psli device (switches m0, (m1), m2). the modes directly supported by the motherboard are only slave serial and master serial. programming the at40k fpga from the pc can be achieved from the ids desktop or by using the software downld40.exe . both tools accept ascii bitstream files generated by the ids software (.bst). programming the at17 configuration memory device when sw4 is set to down and sw5 is set to up, the at17 fpga configuration memory can be programmed by the parallel port interface located on the top left corner. programming the at17 fpga configuration eeprom is not possible by using the 10-pin header h1. programming the at17 fpga configuration eeprom from the pc can be achieved from the ids desktop or by using the configu- rator programming system (cps) software supplied by the ids software.this software accepts the ascii bitstream files (.bst) generated by ids. programming the psli device using the at17 configuration memory when sw4 is set to up and sw5 is set to down, the at17 configurator can program the fpga in master serial. to ensure reliable system power-up, set jumper jmp1 (located below the configurator socket). the configurator must be programmed prior to this setup. troubleshooting 1. check that the motherboard is connected to the pc either through the parallel port or through the 10-pin header. 2. check that the motherboard has power (sw1) and the power configuration switches sw2 and sw3 are correct. 3. make sure programming configuration switches sw4 and sw5 are correct. 4. verify that the daughter card is inserted correctly and that it receives power. 5. verify that the psli device and/or the psli. configurator are placed in their sockets correctly. 6. set the mode switches before downloading to the psli device. 7. set the gclk/fclk jumpers before verifying psli logic. technical support check each of the items listed in the troubleshooting section. contact your local atmel representative or distributor who provided the psli board for technical support. contact your local atmel fae (available at most sales offices). contact the atmel psli technical support hotline at (408) 436-4119. hours are monday-friday 9:00 a.m. ? 6:00 p.m. pst. e-mail atmel psli technical support at fpga@atmel.com . fax inquiries to ?fpga tech support? at (408) 487-2637
atdh40m/d 6 atdh40m functional schematics power supply sw 1 d c pow er pack p1 d c pw r 5.0v dc 500m a vcc user supplied power j1 j2 vc c g n d m aster power o n/o ff in o u t ad j vi vo g n d d 2 d 1 1n4001 1n 4001 sw 3 - spd t internal external 3.3v 5.0v sw 2 - spd t r3 220 o hm s l1 led u 1 7805t u2 lm 317t r 4 3.3k r 1 1.0k r2 2.4k c2 1uf c 1 .01uf vc c m otherboard /reset c 1 .01uf push button reset sw 6 r 13 4.7k atm el c orpo ratio n size: docum ent num ber: rev: 2 a ch w 5310 (atdh40m ) sheet: 1 o f 3 date: m ay 26, 1998 title: at40k m otherboard (power supply) install either r 4 or r 1 note: the voltage regulators lm317t & 7805t allow to switch between 3.3v and 5v.
atdh40m/d 7 mode and clock switches atmel corporation size: document number: rev: 2 a chw 5310 (atdh40m) sheet: 2 of 3 date: may 26, 1998 title: at40k motherboard (mode and clock switches) r11 4.7k r10 4.7k r9 4.7k r8 4.7k vcc 8 7 6 5 s1 sw dip-4 1 2 3 4 i(m0) o(m1) i(m2) i/o (cs0) pull-up gnd 1 3 5 7 9 2 4 6 8 10 h1 di ci do gnd nc con co err vcc check 1 3 5 7 9 2 4 6 8 10 h2 11 13 15 17 19 12 14 16 18 20 21 23 22 24 gck1 gck2 gck3 gck4 gck5 gck6 gck7 gck8 fck1 fck2 fck3 fck4 nc vcc out gnd 7 8 1 14 vcc q1 4.00 mhz note: the 12-pin header (h2) is used to connect the clocks with the jumpers. the dip switch (s1) is used to set the different m odes.
atdh40m/d 8 configuration and multiplexing atmel corporation size: document number: rev: 2 a chw 5310 (atdh40m) sheet: 3 of 3 date: may 26, 1998 title: at40k motherboard (configuration and multiplexing) 1 3 5 7 9 2 4 6 8 10 u1 11 13 15 17 19 12 14 16 18 20 data clk reset/oe* ce* gnd ceo* vcc 1a 1b 2a 2b 3a 1y 2y 3y u3 3b 4a 4b g 4y d0 clk reset/oe ce gnd vcc a*/b 4 7 9 12 2 3 5 13 14 10 11 6 gnd data_in sclk cclk reset/oe init ce con seren 1 15 16 8 74hct157 dip 16 20-pin plcc at17cxxx wp1 wp2 ready ser_en* vcc vcc vcc 1a1 1y1 1a2 1y2 1a3 1y3 1a4 1y4 2a1 2y1 2a2 2y2 1g 2g 3 5 7 9 11 13 2 4 6 10 12 14 1 15 clk reset/oe* ce* ack* data 74ls367 u2 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 25 13 24 12 strobe* auto feed* d0 error* d1 init* d2 select in* d3 gnd d4 gnd d5 gnd d6 gnd d7 gnd ack* gnd busy gnd pe gnd select db25 p1 init* select in* d7 c3 .01uf r6 4.7k r12 4.7k r7 4.7k r5 4.7k at40k cclk init con d0 reset up down sw5 - spdt motherboard d0 j1 jumper sw4 - spdt down - program up - fpga d0
atdh40m/d 9 atdh40m layout schematics configurator/multiplexing/buses 5 5 4 4 3 3 2 2 1 1 d d c c b b a a cs m0 m1 m2 d0 d0 sel_in sel_in init init d7 d7 ack ack data data data_in clk sclk reset/oe reset/oe ce ce up down ce# ce# reset/oe reset/oe# clk clk d0 up down fpga program seren seren ce0# ready (err) (do) (co) (ci) notes: 1) c4, c5, c6, & c8 added 2) c10 - cap on clk next to eeprom plcc20 see table for switches up 2) program configurator table 1 up sw5 up 1) mode 7 (from pc) 3) boot from configurator down sw4 down up cs m0 m1 m2 ce at40k fpga prototype board (5410) atdh40m configurator/multiplexing/busses 13 friday, december 11, 1998 atmel cad & hardware design services title size document number rev: 5 date: sheet of gnd cclk init con reset gnd reset cclk di check init vcc gck6 con gnd vcc vcc gck8 vcc dcio1 gnd gnd gnd vcc vcc dcio5 gnd gnd dcio4 gck7 dcio2 gnd gnd cclk d0 fck4 vcc gnd check gnd gnd vcc dcio3 vcc gck5 vcc vcc fck3 gnd gnd vcc gck6 reset fck3 gck6 dcio4 gck8 gck4 dcio5 gnd fck2 gck7 dcio2 d0 check fck4 dcio3 gck3 fck1 vcc dcio1 con gck1 init fck1 gck8 gck3 gck2 gck4 gck5 fck4 fck3 gck7 fck2 gck6 gck8 dcio4 gck4 gck7 fck1 vcc fck3 reset gck1 dcio1 con dcio5 gck3 vcc check gck2 fck4 gnd vcc vcc gck6 dcio3 d0 dcio2 init gnd gnd gnd gnd vcc vcc vcc gnd gnd gnd gnd gnd gnd vcc vcc gnd gnd gnd gnd vcc gnd vcc vcc gnd gck1 d0 di gnd gnd gnd gnd d1_io15 io_a13 io_a6 io_a8 d1_io16 d1_io18 d1_io3 d1_io9 io_gck 7_a1 io_cs1_a2 d1_io10 d1_io4 d1_io17 io_a11 io_a4 d1_io5 io_a0 d1_io11 d1_io12 d1_io7 iogck8 _a15 d1_io13 d1_io8 d1_io1 d1_io14 d1_io6 d1_io2 cclk io_d0 d2_io1 d2_io2 d2_io3 d2_io4 d2_io5 d2_io6 d2_io7 d2_io8 d2_io9 d2_io10 d2_io11 d2_io12 d2_io13 d2_io14 d2_io15 d2_io16 io_d1 io_fck4 io_d2 io_check io_d5 io_d6 io_d7 tstclk io_gck3 io_ldc io_init io_d13 io_d4 io_d5 io_d6 io_d7 io_a3 io_gck7_a1 cclk io_d0 io_a17 io_a18 io_a19 io_a20 io_a21 io_a22 io_a23 io_cs0 io_cs1_a2 io_gck 1_a16 io_gck1 _a16 io_gck 7_a1 io_d8 d3_io1 io_d10 d3_io2 d3_io3 d3_io4 d3_io5 d3_io6 d3_io7 d3_io8 io_init d3_io9 d3_io11 d3_io12 d3_io14 d3_io15 d3_io16 d3_io17 d3_io18 io_d11 io_d13 d3_io10 d3_io13 io_gck3 d4_io1 d4_io2 d4_io3 d4_io4 d4_io6 d4_io7 d4_io9 d4_io10 io_a22 d4_io12 d4_io13 io_a20 io_fck1 d4_io15 d4_io16 d4_io17 io_a14 d4_io18 io_gck2 d4_io5 io_a17 d4_io8 d4_io11 d4_io14 io_a10 io_a9 io_a3 d1_io21 d1_io27 d1_io19 io_a12 d1_io25 d1_io31 d1_io23 d1_io30 d1_io29 io_a7 io_a14 d1_io33 d1_io26 d1_io32 io_a5 d1_io22 d1_io20 d1_io28 d1_io24 reset io_gck5 d2_io17 d2_io18 d2_io19 d2_io20 d2_io21 d2_io22 io_fck3 io_cs0 d2_io23 d2_io24 d2_io25 d2_io26 d2_io27 d2_io28 d2_io29 d2_io30 d2_io31 d2_io32 d2_io33 d2_io34 iogck6_csout io_d3 io_d4 io_d1 io_d2 io_d3 io_d9 io_d10 io_d11 io_d12 io_d14 io_d15 con io_a17 io_a18 io_a19 io_a20 io_a21 io_a22 io_a4 io_a5 io_a6 io_a8 io_a9 io_a10 io_a11 io_a12 io_a13 io_a14 io_a7 io_ots o_m1 io_fck1 io_fck4 io_fck3 io_cs0 io_gck6_c sout io_a0 io_cs1_a2 io_gck8 _a15 io_gck2 io_a23 io_gck4 io_hdc i_m2 io_d0 io_d1 io_d2 io_d3 io_d4 io_d5 io_d6 io_d7 io_d9 io_d10 io_d11 io_d12 io_d13 io_d14 io_d15 io_a3 io_a4 io_a5 io_a6 io_a7 io_a8 io_a9 io_a10 io_a11 io_a12 io_a13 io_a14 io_fck1 io_fck2 io_fck3 io_fck4 io_gck6_c sout io_a0 io_gck 8_a15 io_gck4 io_hdc i_m2 io_gck3 io_ldc io_ots o_m1 cclk con io_gck4 d3_io35 io_d9 d3_io35 io_d9 d3_io34 d3_io32 d3_io31 d3_io30 d3_io29 d3_io28 d3_io27 io_d14 d3_io25 d3_io24 d3_io23 d3_io22 d3_io21 i_m2 io_hdc d3_io19 io_ldc d3_io20 d3_io33 io_d12 d3_io26 io_gck1 _a16 d4_io19 io_a18 d4_io20 d4_io21 d4_io22 d4_io23 io_a21 d4_io24 d4_io25 d4_io26 io_a23 d4_io27 d4_io29 d4_io30 d4_io28 d4_io31 d4_io32 io_fck2 d4_io33 d4_io34 d4_io35 d4_io36 d4_io37 io_qts o_m1 i_m0 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc r8 4.7k r9 4.7k r10 4.7k r11 4.7k r6 4.7k jmp1 h1 5x2header 1 3 5 7 9 2 4 6 8 10 u1 at17cxxx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 d1_out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 d2_out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 dc2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 o1 4mhz 1 45 8 r5 4.7k dc1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 d4_out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 d3_out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 sw4 spdt sw5 spdt db25 db25m 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 u2 74ls3 67 2 4 6 10 12 14 1 15 3 5 7 9 11 13 16 8 1a1 1a2 1a3 1a4 2a1 2a2 1g 2g 1y1 1y2 1y3 1y4 2y1 2y2 vcc gnd u3 74hct157 2 3 5 6 11 10 14 13 1 15 4 7 9 12 16 8 1a 1b 2a 2b 3a 3b 4a 4b a/b g 1y 2y 3y 4y vcc gnd c5 .1uf c4 .1uf c6 .1uf c3 .01uf h2 h2 12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 r7 4.7k dip_sw1 c10 .01uf
atdh40m/d 10 buses 5 5 4 4 3 3 2 2 1 1 d d c c b b a a at40k fpga prototype board (5410) atdh40m busses 23 friday, december 11, 1998 atmel cad & hardware design services title size document number rev: 5 date: sheet of vcc vcc vcc vcc gnd gnd gnd vcc vcc gnd gnd gnd d0 vcc gnd gnd gnd vcc vcc vcc vcc gnd gnd vcc vcc gnd gnd gnd gnd vcc vcc vcc gnd gnd gnd gnd gnd gnd vcc vcc gnd gnd gnd gnd vcc gnd vcc vcc gnd gnd gnd gnd gnd gnd gnd d1_io15 io_a13 io_a6 io_a8 d1_io16 d1_io18 d1_io3 d1_io9 io_gck7_a1 io_cs1_a2 d1_io10 d1_io4 d1_io17 io_a11 io_a4 d1_io5 io_a0 d1_io11 d1_io12 d1_io7 iogck8_a15 d1_io13 d1_io8 d1_io1 d1_io14 d1_io6 d1_io2 cclk io_d0 d2_io1 d2_io2 d2_io3 d2_io4 d2_io5 d2_io6 d2_io7 d2_io8 d2_io9 d2_io10 d2_io11 d2_io12 d2_io13 d2_io14 d2_io15 d2_io16 io_d1 io_fck4 io_d2 io_check io_d5 io_d6 io_d7 tstclk io_d8 d3_io1 io_d10 d3_io2 d3_io3 d3_io4 d3_io5 d3_io6 d3_io7 d3_io8 io_init d3_io9 d3_io11 d3_io12 d3_io14 d3_io15 d3_io16 d3_io17 d3_io18 io_d11 io_d13 d3_io13 d4_io1 d4_io2 d4_io3 d4_io4 d4_io6 d4_io7 d4_io9 d4_io10 io_a22 d4_io12 d4_io13 io_a20 io_fck1 d4_io15 d4_io16 d4_io17 io_a14 d4_io18 io_gck2 d4_io5 io_a17 d4_io8 d4_io11 d4_io14 d3_io10 io_gck3 io_a10 io_a9 io_a3 d1_io21 d1_io27 d1_io19 io_a12 d1_io25 d1_io31 d1_io23 d1_io30 d1_io29 io_a7 io_a14 d1_io33 d1_io26 d1_io32 io_a5 d1_io22 d1_io20 d1_io28 d1_io24 reset io_gck5 d2_io17 d2_io18 d2_io19 d2_io20 d2_io21 d2_io22 io_fck3 io_cs0 d2_io23 d2_io24 d2_io25 d2_io26 d2_io27 d2_io28 d2_io29 d2_io30 d2_io31 d2_io32 d2_io33 d2_io34 iogck6_csout io_d3 io_d4 con io_gck4 d3_io35 io_d9 d3_io35 io_d9 d3_io34 d3_io32 d3_io31 d3_io30 d3_io29 d3_io28 d3_io27 io_d14 d3_io25 d3_io24 d3_io23 d3_io22 d3_io21 i_m2 io_hdc d3_io19 io_ldc d3_io20 d3_io33 io_d12 d3_io26 io_gck1_a16 d4_io19 io_a18 d4_io20 d4_io21 d4_io22 d4_io23 io_a21 d4_io24 d4_io25 d4_io26 io_a23 d4_io27 d4_io29 d4_io30 d4_io28 d4_io31 d4_io32 d4_io33 d4_io34 d4_io35 d4_io36 d4_io37 io_qts o_m1 i_m0 io_fck2 vcc vcc vcc vcc d1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 d2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 d4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 d3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 c10 10pf
atdh40m/d 11 power supply 5 5 4 4 3 3 2 2 1 1 d d c c b b a a + - external external internal 5v 3.3v 500ma + + - - + - at40k fpga prototype board (5410) a 33 friday, december 11, 1998 atmel cad & hardware design services atdh40m power supply title size document number r ev: 5 date: sheet of reset vcc vcc p1 dcpower9v d2_in4001 in4001 d1_in4001 1n4001 l1 led j1 vcc j2 gnd r3 220 r2 2.4k r4 3.3k lm7805 1 2 in out gnd sw3 sw2 c8 100uf c2 1uf c9 100uf c1 .01uf sw1 master lm317t 3 2 1 in out adj r13 4.7k c7 1uf sw6
atdh40m/d 12 atdh2081 download cable (25- to 10-way adapter) atmel corporation size: document number: rev: 1 a atdh2081 sheet: 1 of 1 date: sep 1, 1998 title: download cable - 25 to 10 way adapter 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 25 13 24 12 auto feed* d0 init* select in* d7 ack* 1 3 5 7 9 2 4 6 8 10 di ci do gnd nc con co err vcc nc 10k 10k 4.7k 4.7k 4.7k 4.7k 4.7k pwr 74c14 gnd vdd pwr 0.1uf
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