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| d a t a sh eet product speci?cation file under integrated circuits, ic12 1998 may 11 integrated circuits pcf2103 family lcd controllers/drivers
1998 may 11 2 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family contents 1 features 2 applications 3 general description 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 lcd bias voltage generator 7.2 oscillator 7.3 external clock 7.4 power-on reset 7.5 power-down mode 7.6 registers 7.7 busy flag 7.8 address counter (ac) 7.9 display data ram (ddram) 7.10 character generator rom (cgrom) 7.11 character generator ram (cgram) 7.12 cursor control circuit 7.13 timing generator 7.14 lcd row and column drivers 7.15 reset function 8 instructions 8.1 clear display 8.2 return home 8.3 entry mode set 8.3.1 i/d 8.3.2 s 8.4 display control (and partial power-down mode) 8.4.1 d 8.4.2 c 8.4.3 b 8.5 cursor or display shift 8.6 function set 8.6.1 dl (parallel mode only) 8.6.2 m 8.6.3 h 8.7 set cgram address 8.8 set ddram address 8.9 read busy flag and address counter 8.10 write data to cgram or ddram 8.11 read data from cgram or ddram 8.12 extended function set instructions and features 8.12.1 new instructions 8.12.2 icon control 8.12.3 im 8.12.4 ib 8.12.5 screen configuration 8.12.6 display configuration 8.12.7 reducing current consumption 9 interface to microcontroller 9.1 parallel interface 9.2 i 2 c-bus interface 9.2.1 characteristics of the i 2 c-bus 9.2.2 i 2 c-bus protocol 9.2.3 definitions 10 limiting values 11 handling 12 dc characteristics 13 ac characteristics 14 timing characteristics 15 application information 15.1 8-bit operation, 1-line display using internal reset 15.2 4-bit operation, 1-line display using internal reset 15.3 8-bit operation, 2-line display 15.4 i 2 c-bus operation, 1-line display 16 bonding pad locations 17 definitions 18 life support applications 19 purchase of philips i 2 c components 1998 may 11 3 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 2 applications telecom equipment portable instruments point-of-sale terminals. 3 general description the pcf2103 family is a low power cmos lcd controller and driver, designed to drive a dot matrix lcd display of 2 line by 12 or 1 line by 24 characters with 5 8 dot format. all necessary functions for the display are provided in a single chip, including on-chip generation of lcd bias voltages, resulting in a minimum of external components and lower system current consumption. the pcf2103 interfaces to most microcontrollers via a 4 or 8-bit bus or via the 2-wire i 2 c-bus. the chip contains a character generator and displays alphanumeric and kana (japanese) characters. the letter x in pcf2103x characterizes the built-in character set. various character sets can be manufactured on request. 4 ordering information type number package name description version pcf2103eu/2/f2 - chip with bumps in tray - 1 features single-chip lcd controller/driver 2-line display of up to 12 characters + 120 icons, or 1-line display of up to 24 characters + 120 icons 5 7 character format plus cursor; 5 8 for kana (japanese syllabary) and user defined symbols icon mode: reduced current consumption while displaying icons only (1) icon blink function on-chip: C generation of intermediate lcd bias voltages C oscillator requires no external components (external clock also possible) display data ram: 80 characters character generator rom: 240, 5 8 characters character generator ram: 16, 5 8 characters; 3 characters used to drive 120 icons, 6 characters used if icon blink feature is used in application 4 or 8-bit parallel bus and 2-wire i 2 c-bus interface cmos compatible 18 row, 60 column outputs mux rates 1 : 18 (for normal operation) and 1 : 2 (for icon-only mode) uses common 11 code instruction set (extended) logic supply voltage range, v dd - v ss = 1.8 to 5.5 v; chip may be driven with two battery cells display supply voltage range, v lcd - v ss = 2.2 to 6.5 v very low current consumption (20 to 120 m a): C icon mode: <25 m a C power-down mode: <2.5 m a. (1) icon mode is used to save current. when only icons are displayed, a much lower operating voltage v lcd can be used and the switching frequency of the lcd outputs is reduced. in most applications it is possible to use v dd as v lcd . 1998 may 11 4 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 5 block diagram fig.1 block diagram. handbook, full pagewidth mgl259 cursor and data control shift register 5 12-bit data latches column drivers 60 5 60 character generator ram (128 5) (cgram) 16 characters character generator rom (cgrom) 240 characters display data ram (ddram) 80 characters/bytes address counter (ac) instruction decoder instruction register row drivers shift register 18-bit bias voltage generator busy flag data register (dr) i/o buffer oscillator timing generator display address counter power-on reset v dd v ss t1 v lcd c1 to c60 r1 to r18 osc pd pcf2103 db0 to db3/sa0 db4 to db7 e r/w rs scl sda 18 18 60 5 7 7 8 8 7 7 8 8 8 1998 may 11 5 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 6 pinning note 1. this is the voltage used for the generation of lcd bias levels. symbol die pad description v dd 1 supply voltage osc 2 oscillator/external clock input pd 3 power-down pad input t1 4 test pad (connected to v ss ) v ss 5 ground v lcd 6v lcd input; note 1 r9 to r16 7 to 14 lcd row driver outputs 9 to 16 r18 15 lcd row driver output 18 c60 to c1 16 to 23, 26 to 50, 53 to 77, 80, 81 lcd column driver outputs 60 to 1 r8 to r1 82 to 89 lcd row driver outputs 8 to 1 r17 90 lcd row driver output 17 scl 91 i 2 c-bus serial clock input sda 92 i 2 c-bus serial data input/output e 93 data bus clock input rs 94 register select input r/ w 95 read/write input db7 96 bit of bi-directional data bus db6 97 bit of bi-directional data bus db5 98 bit of bi-directional data bus db4 99 bit of bi-directional data bus db3/sa0 100 bit of bi-directional data bus/i 2 c-bus address pin db2 101 bit of bi-directional data bus db1 102 bit of bi-directional data bus db0 103 bit of bi-directional data bus 1998 may 11 6 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family table 1 pin functions; note 1 note 1. when the i 2 c-bus is used, the parallel interface pin e must be defined as e = 0. in i 2 c-bus read mode db7 to db0 should be connected to v dd or left open-circuit. a) when the parallel bus is used, pins scl and sda must be connected to v ss or v dd ; they may not be left unconnected. b) if the 4-bit interface is used without reading out from the pcf2103 (i.e. r/ w is set permanently to logic 0), the unused ports db0 to db3 can either be set to v ss or v dd instead of leaving them open. name function description rs register select rs selects the register to be accessed for read and write; there is an internal pull-up on this pin rs = 0 selects the instruction register for write and the busy flag and address counter for read rs = 1 selects the data register for both read and write r/ w read/write r/ w selects either the read (r/ w = 1) or write (r/ w = 0) operation; there is an internal pull-up on this pin e data bus clock pin e is set high to signal the start of a read or write operation; data is clocked in or out of the chip on the negative edge of the clock db7 to db0 data bus the bi-directional, 3-state data bus transfers data between the system controller and the pcf2103; db7 may be used as the busy ?ag, signalling that internal operations are not yet completed; in 4-bit operations the 4 higher order lines db7 to db4 are used; db3 to db0 must be left open-circuit; there is an internal pull-up on each of the data lines c1 to c60 column driver outputs these pins output the data for columns r1 to r18 row driver outputs these pins output the row select waveforms to the display; r17 and r18 drive the icons v lcd lcd power supply positive power supply for the liquid crystal display osc oscillator when the on-chip oscillator is used this pin must be connected to v dd ; an external clock signal, if used, is input at this pin scl serial clock line input for the i 2 c-bus clock signal sda serial data line i/o for the i 2 c-bus data line sa0 address pin the hardware sub-address line is used to program the device sub-address for two different pcf2103s on the same i 2 c-bus t1 test pad must be connected to v ss ; not user accessible pd power-down pad pd selects chip power-down mode; for normal operation pd = 0 1998 may 11 7 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 7 functional description 7.1 lcd bias voltage generator the intermediate bias voltages for the lcd display are generated on-chip. this removes the need for an external resistive bias chain and significantly reduces the system current consumption. the optimum value of v lcd depends on the multiplex rate, the lcd threshold voltage (v th ) and the number of bias levels and is given by the relationships given in tables 2 and 3. using a 5-level bias scheme for 1 : 18 maximum rate allows v lcd <5 v for most lcd liquids. table 2 optimum/maximum values for v op (off pixels start darkening; v off =v th ) table 3 minimum values for v op (on pixels clearly visible; v on >v th ) mux rate number of levels v on /v th v op /v th v op (typical; for v th = 1.4 v) 1 : 18 5 1.272 3.7 5.2 v 1 : 2 3 2.236 2.283 3.9 v mux rate number of levels v on /v th v op /v th v op (typical; for v th = 1.4 v) 1 : 18 5 1.12 3.2 4.6 v 1 : 2 3 1.2 1.5 2.1 v 7.2 oscillator the on-chip oscillator provides the clock signal for the display system. no external components are required and pin osc must be connected to v dd . 7.3 external clock if an external clock is to be used, it is input at the osc pin. the resulting display frame frequency is given by only in the power-down state is the clock allowed to be stopped (osc connected to v ss ), otherwise the lcd is frozen in a dc state. 7.4 power-on reset the on-chip power-on reset block initializes the chip after power-on or power failure. this is a synchronous reset and requires 3 oscillator cycles to be executed. afterwards, a clear display is initiated. 7.5 power-down mode the chip can be put into power-down mode where all static currents are switched off (no internal oscillator, no bias level generation, all lcd outputs are internally connected to v ss ) when pd = 1. f frame f osc 3072 ------------ - = during power-down, the whole chip is being reset and will restart with a clear display after power-down. therefore, the whole chip has to be initialized after a power-down as after an initial power-up. 7.6 registers the pcf2103 has two 8-bit registers, an instruction register (ir) and a data register (dr). the register select signal (rs) determines which register will be accessed. the instruction register stores instruction codes such as display clear and cursor shift, and address information for the display data ram (ddram) and character generator ram (cgram). the instruction register can be written from but not read by the system controller. the data register temporarily stores data to be read from the ddram and cgram. when reading, data from the ddram or cgram corresponding to the address in the instruction register is written to the data register prior to being read by the read data instruction. 7.7 busy ?ag the busy flag indicates the internal status of the pcf2103. logic 1 indicates that the chip is busy and further instructions will not be accepted. the busy flag is output at pin db7 when rs = 0 and r/ w = 1. instructions should only be written after checking that the busy flag is logic 0 or waiting for the required number of cycles. 1998 may 11 8 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 7.8 address counter (ac) the address counter assigns addresses to the ddram and cgram for reading and writing and is set by the commands set cgram address and set ddram address. after a read/write operation the address counter is automatically incremented or decremented by 1. the address counter contents are output to the bus (db6 to db0) when rs = 0 and r/ w=1. 7.9 display data ram (ddram) the ddram stores up to 80 characters of display data represented by 8-bit character codes. ram locations which are not used for storing display data can be used as general purpose ram. the basic ram-to-display addressing scheme is shown in fig.2. with no display shift the characters represented by the codes in the first 24 ram locations starting at address 00 in line 1 are displayed. figures 3 and 4 show the display mapping for right and left shift respectively. when data is written to or read from the ddram wrap-around occurs from the end of one line to the start of the next line. when the display is shifted each line wraps around within itself, independently of the others. thus all lines are shifted and wrapped around together. the address ranges and wrap-around operations for the various modes are shown in table 4. 7.10 character generator rom (cgrom) the character generator rom (cgrom) generates 240 character patterns in 5 8 dot format from 8-bit character codes. figure 6 shows the character set that is currently implemented. 7.11 character generator ram (cgram) up to 16 user defined characters may be stored in the cgram. some cgram characters (see fig.14) are also used to drive icons (6 if icons blink and both icon rows are used in application; 3 if no blink but both icon rows are used in application; 0 if no icons are driven by the icon rows). the cgrom and cgram use a common address space, of which the first column is reserved for the cgram (see fig.6). figure 7 shows the addressing principle for the cgram. 7.12 cursor control circuit the cursor control circuit generates the cursor (underline and/or cursor blink as shown in fig.5) at the ddram address contained in the address counter. when the address counter contains the cgram address the cursor will be inhibited. 7.13 timing generator the timing generator produces the various signals required to drive the internal circuitry. internal chip operation is not disturbed by operations on the data buses. 7.14 lcd row and column drivers the pcf2103 contains 18 row and 60 column drivers, which connect the appropriate lcd bias voltages in sequence to the display in accordance with the data to be displayed. r17 and r18 drive the icon rows. the bias voltages and the timing are selected automatically when the number of lines in the display is selected. figures 8, 9 and 10 show typical waveforms. unused outputs should be left unconnected. table 4 address space and wrap-around operation notes 1. moves to next line. 2. stays within line. mode address space read/write wrap-around (1) display shift wrap-around (2) 1 24 00h to 4fh 4fh to 00h 4fh to 00h 2 12 00h to 27h; 40h to 67h 27h to 40h; 67h to 00h 27h to 00h; 67h to 40h 1998 may 11 9 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family fig.2 ddram-to-display mapping: no shift. handbook, full pagewidth 00 01 02 03 04 15 16 17 18 19 4c 4d 4e 4f non-displayed ddram addresses 64 65 66 67 40 41 42 43 44 49 4a 4b 4c 4d 00 01 02 03 04 09 0a 0b 0c 0d 24 25 26 27 non-displayed ddram address line 1 line 2 mge991 ddram address 2-line display 12345 222324 12345 101112 12345 101112 display position ddram address 1-line display fig.3 ddram-to-display mapping: right shift. handbook, halfpage mge992 27 00 01 02 03 67 40 41 42 43 08 09 0a 48 49 4a ddram address line 1 line 2 2-line display 1 2 3 4 5 22 23 24 1 2 3 4 5 10 11 12 1 2 3 4 5 10 11 12 4f 00 01 02 03 14 15 16 display position ddram address 1-line display 1998 may 11 10 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family fig.4 ddram-to-display mapping: left shift. handbook, halfpage 01 04 05 41 42 43 44 45 0a 0b 0c 4a 4b 4c ddram address line 1 line 2 2-line display 1 2 3 4 5 22 23 24 1 2 3 4 5 10 11 12 1 2 3 4 5 10 11 12 01 04 05 02 03 02 03 16 17 18 display position ddram address 1-line display mge993 fig.5 cursor and blink display examples. mga801 cursor 5 x 7 dot character font alternating display cursor display example blink display example 1998 may 11 11 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family fig.6 character set e in cgrom. handbook, full pagewidth mgd689 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 upper 4 bits lower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 xxxx 1111 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1998 may 11 12 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family fig.7 relationship between cgram addresses and data and display patterns. character code bits 0 to 3 correspond to cgram address bits 3 to 6. cgram address bits 0 to 2 designate the character pattern line position. the 8th line is the cursor position and display is perfor med by logical or with the cursor. data in the 8th position will appear in the cursor position. character pattern column positions correspond to cgram data bits 0 to 4, as shown in fig.6. as shown in figs 6 and 7, cgram character patterns are selected when character code bits 4 to 7 are all logic 0. cgram data = logic 1 cor responds to selection for display. only bits 0 to 5 of the cgram address are set by the set cgram address command. bit 6 can be set using the set ddram address co mmand in the valid address range or by using the auto-increment feature during cgram write. all bits 0 to 6 can be read using the read bu sy flag and address counter command; see table 7. handbook, full pagewidth mge995 76543210 6543210 43210 higher order bits lower order bits lower order bits higher order bits lower order bits higher order bits 00000000 0000000 0 001 000 010 000 011 0 100 0 00 101 00 0 110 000 111 00000 000 000 001 0 0 0 010 00 00 011 100 101 00 00 110 00 00 111 00000 001 00000001 0001 00000010 00001111 00001111 00001111 00001111 01 0 0000 100 101 110 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 111 character codes (ddram data) cgram address character patterns (cgram data) 43210 0 000 111 000 0 00 10 00 0 1 000 1 1 1 00 1 1 1 111 1 1 1 1 000 1 101 000 111 0 11 11 01 0 0 010 0 1 0 00 0 1 1 010 0 1 0 0 000 character code (cgram data) character pattern example 1 cursor position character pattern example 2 1998 may 11 13 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family fig.8 typical lcd waveforms; character mode. handbook, full pagewidth mge996 state 1 (on) state 2 (off) frame n + 1 frame n 123 18123 18 row 1 v lcd v 2 v 3 /v 4 v 5 v ss row 9 v lcd v 2 v 3 /v 4 v 5 v ss row 2 v lcd v 2 v 3 /v 4 v 5 v ss col1 v lcd v 2 v 3 /v 4 v 5 v ss col2 v lcd v 2 v 3 /v 4 v 5 v ss 0 v state 1 v op 0.5v op 0.25v op - 0.25v op - 0.5v op - v op 0 v state 2 v op 0.5v op 0.25v op - 0.25v op - 0.5v op - v op r1 r2 r3 r4 r5 r6 r7 r8 r9 1998 may 11 14 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family fig.9 mux 1 : 2 lcd waveforms; icon mode. handbook, full pagewidth mge997 frame n + 1 frame n v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss v lcd 2/3 1/3 v ss col 4 off/off col 3 on/on col 2 off /on col 1 on/off row 1 to 16 row 18 row 17 only icons are driven (mux 1 : 2) 1998 may 11 15 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family fig.10 mu x1:2 lcd waveforms; icon mode. v on(rms) = 0.745 v op . v off(rms) = 0.333 v op . d v on v off ------------- 2.23 == handbook, full pagewidth mge998 frame n + 1 frame n v op 2/3 v op 1/3 v op 0 - 1/3 v op - 2/3 v op - v op v op 2/3 v op 1/3 v op 0 - 1/3 v op - 2/3 v op - v op v op 2/3 v op 1/3 v op 0 - 1/3 v op - 2/3 v op - v op state 3 col 1 - row 1 to 16 state 2 col 2 - row 17 state 1 col 1 - row 17 state 3 (off) r17 r18 r1-16 v pixel state 1 (on) state 2 (off) 1998 may 11 16 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 7.15 reset function the pcf2103 automatically initializes (resets) when power is turned on. the reset executes a clear display instruction, requiring 165 oscillator cycles. after the reset the chip has the state shown in table 5. table 5 state after reset step instruction reset state (bit/register) reset state (description) 1 clear display 2 entry mode set i/d = 1 +1 (increment) s = 0 no shift 3 display control d = 0 display off c = 0 cursor off b = 0 cursor character blink off 4 function set dl = 1 8-bit interface m = 0 1-line display h = 0 normal instruction set 5 default address pointer to ddram; the busy flag (bf) indicates the busy state (bf = 1) until initialization ends; the busy state lasts 2 ms; the chip may also be initialized by software; see tables 16 and 17 6 icon control im, ib = 00 icons/icon blink disabled 7 display/screen con?guration l, p, q = 000 default con?gurations 8i 2 c-bus interface reset 1998 may 11 17 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 8 instructions only two pcf2103 registers, the instruction register (ir) and the data register (dr) can be directly controlled by the microcontroller. before internal operation, control information is stored temporarily in these registers to allow interface to various types of microcontrollers which operate at different speeds or to allow interface to peripheral control ics. the format for instructions when i 2 c-bus control is used is shown in table 6. the pcf2103 operation is controlled by the instructions given in table 7 together with their execution time. details are explained in subsequent sections. instructions are of 4 types, those that: 1. designate pcf2103 functions such as display format, data length, etc. 2. set internal ram addresses 3. perform data transfer with internal ram 4. others. in normal use, instructions that perform data transfer with internal ram are used most frequently. however, automatic incrementing by 1 (or decrementing by 1) of internal ram addresses after each data write lessens the microcontroller program load. the display shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency. during internal operation, no instruction other than the read busy flag and address counter instruction will be executed. because the busy flag is set to logic 1 while an instruction is being executed, the user should verify that the busy flag is at logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in table 7. an instruction sent while the busy flag is logic 1 will not be executed. table 6 instruction set for i 2 c-bus commands note 1. r/ w is set together with the slave address. control byte command byte i 2 c-bus commands cors000000db7db6db5db4db3db2db1db0 note 1 1998 may 11 18 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... table 7 instruction set with parallel bus commands; note 1 instruction rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 description required clock cycles h=0or1 nop 0000000000no operation 3 function set 00001dl0m0h sets interface data length (dl) and number of display lines (m); extended instruction set control (h) 3 read busy ?ag and address counter 0 1 bf ac reads the busy flag (bf) indicating internal operating is being performed and reads address counter contents 0 read data 1 1 read data reads data from cgram or ddram 3 write data 1 0 write data writes data from cgram or ddram 3 h=0 clear display 0000000001 clears entire display and sets ddram address 0 in address counter 165 return home 0000000010 sets ddram address 0 in address counter; also returns shifted display to original position; ddram contents remain unchanged 3 entry mode set 00000001i/ds sets cursor move direction and speci?es shift of display; these operations are performed during data write and read 3 display control 0000001dcb sets entire display on/off (d), cursor on/off (c) and blink of cursor position character (b); d = 0 (display off) puts chip into power-down mode 3 cursor/display shift 000001s/cr/l00 moves cursor and shifts display without changing ddram contents 3 set cgram address 0001 a cg sets cgram address; bit 6 is to be set by the command set ddram address; look at the description of the commands 3 set ddram address 001 a dd sets ddram address 3 1998 may 11 19 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... note 1. x = dont care. h=1 reserved 0000000001do not use - screen con?guration 000000001l set screen con?guration 3 display con?guration 00000001pq set display con?guration 3 icon control 0000001imib0 set icon mode (im), icon blink (ib) 3 reserved 000001 xxxxdo not use - reserved 0001 xxxxxxdo not use - reserved 0 0 1 xxxxxxxdo not use - instruction rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 description required clock cycles 1998 may 11 20 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family table 8 speci?cation of mnemonics used in table 7 bit logic 0 logic 1 i/d decrement increment s display freeze display shift d display off display on c cursor off cursor on b cursor character blink off: character at cursor position does not blink cursor character blink on: character at cursor position blinks s/c cursor move display shift r/l left shift right shift dl 4 bits 8 bits h use basic instruction set use extended instruction set l (ignored, if m = 1) left/right screen: standard connection (as in pcf2114); 1st 12 characters of 24: columns are from 1 to 60; 2nd 12 characters of 24: columns are from 1 to 60 left/right screen: mirrored connection (as in pcf2116); 1st 12 characters of 24: columns are from 1 to 60; 2nd 12 characters of 24: columns are from 60 to 1 p column data: left to right (as in pcf2116); column data is displayed from 1 to 60 column data: right to left; column data is displayed from 60 to 1 q row data: top to bottom (as in pcf2116); row data is displayed from 1 to 16 and icon row data is in 17 and 18 row data: bottom to top; row data is displayed from 16 to 1 and icon row data is in 18 and 17 im character mode; full display icon mode; only icons displayed ib icon blink disabled icon blink enabled m 1-line by 24 display 2-line by 12 display c 0 last control byte; see table 6 another control byte follows after data/command 1998 may 11 21 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family fig.11 4-bit transfer example. mga804 rs e db7 r/w db6 db5 db4 instruction write busy flag and address counter read data register read ir7 ir3 bf ac3 dr7 dr3 ir6 ir2 ac6 ac2 dr6 dr2 ir5 ir1 ac5 ac1 dr5 dr1 ir4 ir0 ac4 ac0 dr4 dr0 fig.12 an example of 4-bit data transfer timing sequence. ir7 and ir3: instruction 7th and 3rd bit. ac3: address counter 3rd bit. d7 and d3: data 7th and 3rd bit. mga805 rs e internal db7 r/w internal operation ir7 ir3 ac3 d7 d3 not busy ac3 busy instruction write busy flag check busy flag check instruction write 1998 may 11 22 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family fig.13 example of busy flag checking timing sequence. mga806 instruction write busy flag check busy flag check busy flag check instruction write internal operation rs e internal db7 r/w data busy busy not busy data 8.1 clear display clear display writes character code 20h into all ddram addresses (the character pattern for character code 20h must be a blank pattern), sets the ddram address counter to logic 0 and returns display to its original position if it was shifted. thus, the display disappears and the cursor or blink position goes to the left edge of the display. sets entry mode i/d = 1 (increment mode). s of entry mode does not change. the instruction clear display requires extra execution time. this may be allowed by checking the busy flag (bf) or by waiting until the 165 clock cycles have elapsed. the latter must be applied where no read-back options are foreseen, as in some chip-on-glass (cog) applications. 8.2 return home return home sets the ddram address counter to logic 0 and returns display to its original position if it was shifted. ddram contents do not change. the cursor or blink position goes to the left of the first display line. i/d and s of entry mode do not change. 8.3 entry mode set 8.3.1 i/d when i/d = 1 (0) the ddram or cgram address increments (decrements) by 1 when data is written into or read from the ddram or cgram. the cursor or blink position moves to the right when incremented and to the left when decremented. the cursor underline and cursor character blink are inhibited when the cgram is accessed. 8.3.2 s when s = 1, the entire display shifts either to the right (i/d = 0) or to the left (i/d = 1) during a ddram write. thus it looks as if the cursor stands still and the display moves. the display does not shift when reading from the ddram, or when writing into or reading out of the cgram. when s = 0 the display does not shift. 1998 may 11 23 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 8.4 display control (and partial power-down mode) 8.4.1 d the display is on when d = 1 and off when d = 0. display data in the ddram are not affected and can be displayed immediately by setting d to logic 1. when the display is off (d = 0) the chip is in partial power-down mode: the lcd outputs are connected to v ss bias generator is turned off. 3 oscillator cycles are required after sending the display off instruction to ensure all outputs are at v ss , afterwards osc can be stopped. if the oscillator is running during partial power-down mode (display off) the chip can still execute instructions. even lower current consumption is obtained by inhibiting the oscillator (osc = v ss ). to ensure i dd <2 m a the parallel bus pins db7 to db0 should be connected to v dd ; rs and r/ w to v dd or left open-circuit and pd to v dd . recovery from power-down mode: put pd back to logic 0, if necessary put osc back to v dd and send a display control instruction with d = 1 to enable the display again. 8.4.2 c the cursor is displayed when c = 1 and inhibited when c = 0. even if the cursor disappears, the display functions i/d, etc. remain in operation during display data write. the cursor is displayed using 5 dots in the 8th line (see fig.5). 8.4.3 b the character indicated by the cursor blinks when b = 1. the cursor character blink is displayed by switching between display characters and all dots on with a period of approximately 1 s, with the cursor underline and the cursor character blink can be set to display simultaneously. 8.5 cursor or display shift cursor/display shift moves the cursor position or the display to the right or left without writing or reading display data. this function is used to correct a character or move the cursor through the display. in 2-line displays, the cursor moves to the next line when it passes the last position (40) of the line. when the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. f blink f osc 52224 ---------------- = the address counter (ac) content does not change if the only action performed is shift display, but increments or decrements with the cursor shift. 8.6 function set 8.6.1 dl ( parallel mode only ) sets interface data width. data is sent or received in bytes (db7 to db0) when dl = 1 or in two nibbles (db7 to db4) when dl = 0. when 4-bit width is selected, data is transmitted in two cycles using the parallel bus. in a 4-bit application db3 to db0 should be left open-circuit (internal pull-ups). hence in the first function set instruction after power-on n and h are set to logic 1. a second function set must then be sent (2 nibbles) to set n and h to their required values. function set from the i 2 c-bus interface sets the dl bit to logic 1. 8.6.2 m chooses either 1-line by 24 display (m = 0) or 2-line by 12 display (m = 1). 8.6.3 h when h = 0 the chip can be programmed via the standard 11 instruction codes used in the pcf2116 and other lcd controllers. when h = 1 the extended range of instructions will be used. these are mainly for controlling the display configuration and the icons. 8.7 set cgram address set cgram address sets bits 5 to 0 of the cgram address a cg into the address counter (binary a[5] to a[0]). data can then be written to or read from the cgram. attention: the cgram address uses the same address register as the ddram address and consists of 7 bits (binary a[6] to a[0]). with the set cgram address command, only bits 5 down to 0 are set. bit 6 can be set using the set ddram address command first, or by using the auto-increment feature during cgram write. all bits 6 to 0 can be read using the read busy flag and address counter command. when writing to the lower part of the cgram, ensure that bit 6 of the address is not set (e.g. by an earlier ddram write or read action). 1998 may 11 24 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 8.8 set ddram address set ddram address sets the ddram address a dd into the address counter (binary a[6] to a[0]). data can then be written to or read from the ddram. 8.9 read busy ?ag and address counter read busy flag and address counter reads the busy flag (bf) and address counter (ac). bf = 1 indicates that an internal operation is in progress. the next instruction will not be executed until bf = 0, so bf should be checked before sending another instruction. at the same time, the value of the address counter expressed in binary a[6] to a[0] is read out. the address counter is used by both cgram and ddram, and its value is determined by the previous instruction. 8.10 write data to cgram or ddram write data writes binary 8-bit data d[7] to d[0] to the cgram or the ddram. whether the cgram or ddram is to be written into is determined by the previous set cgram address or set ddram address command. after writing, the address automatically increments or decrements by 1, in accordance with the entry mode. only bits d[4] to d[0] of cgram data are valid, bits d[7] to d[5] are dont care. 8.11 read data from cgram or ddram read data reads binary 8-bit data d[7] to d[0] from the cgram or ddram. the most recent set address command determines whether the cgram or ddram is to be read. the read data instruction gates the content of the data register (dr) to the bus while pin e is high. after pin e goes low again, internal operation increments (or decrements) the ac and stores ram data corresponding to the new ac into the dr. it should be noted that there are only three instructions that update the data register (dr). these are: set cgram address set ddram address read data from cgram or ddram. other instructions (e.g. write data, cursor/display shift, clear display, return home) do not modify the data register content. 8.12 extended function set instructions and features 8.12.1 n ew instructions h = 1 sets the chip into alternate instruction set mode. 8.12.2 i con control the pcf2103 can drive up to 120 icons. see fig.14 for cgram to icon mapping. 8.12.3 im when im = 0 the chip is in character mode. in character mode characters and icons are driven (mux 1 : 18). when im = 1 the chip is in icon mode. in icon mode only the icons are driven (mux 1 : 2). 8.12.4 ib icon blink control is independent of the cursor/character blink function. when ib = 0 icon blink is disabled. icon data is stored in cgram character 0 to 2 (3 8 5 = 120 bits for 120 icons). when ib = 1 icon blink is enabled. in this case each icon is controlled by two bits. blink consists of two half phases (corresponding to the cursor on and off phases called even and odd phases hereafter). icon states for the even phase are stored in cgram characters 0 to 2 (3 8 5 = 120 bits for 120 icons). these bits also define the icon state when the icon blink is not used. icon states for the odd phase are stored in cgram character 4 to 6 (another 120 bits for the 120 icons). when icon blink is disabled cgram characters 4 to 6 may be used as normal cgram characters. 1998 may 11 25 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family table 9 blink effect for icons and cursor character blink parameter even phase odd phase cursor underline on off cursor character blink block (all on) normal (display character) icons state 1: cgram characters 0 to 2 state 2: cgram characters 4 to 6 fig.14 cgram-to-icon mapping. cgram data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off. data in character codes 0 to 2 define the icon states when icon blink is disabled or during the even phase when icon blink is enab led. data in character codes 4 to 6 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled). handbook, full pagewidth mgg001 116-120 odd (blink) 18/56-60 0 0 0 0 0 1 1 0 icon view 0 1 1 0 0 1 1 0 0 1 1 0 1-5 odd (blink) 17/1-5 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 116-120 even 18/56-60 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 0 1 61-65 even 18/1-5 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 0 56-60 even 17/56-60 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 1 11-15 even 17/11-15 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 6-10 even 17/6-10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1-5 even 17/1-5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 7 6 5 4 3 2 1 0 msb lsb lsb msb msb lsb 6 5 4 3 2 1 0 4 3 2 1 0 icon no. phase row/col character codes cgram address cgram data handbook, full pagewidth col 1 to 5 12345 61 62 63 64 65 display: row 17 row 18 block of 5 columns col 6 to 10 678910 66 67 68 69 70 col 56 to 60 56 57 58 59 60 116 117 118 119 120 mge999 1998 may 11 26 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 8.12.5 s creen configuration the default value for l is logic 0. in the event of l = 0 the two halves of a split screen are connected in a standard way i.e. column 1/61, 2/62 to 60/120. in the event of l = 1 the two halves of a split screen are connected in a mirrored way i.e. column 1/120, 2/119 to 60/61. this allows single layer pcb or glass layout. 8.12.6 d isplay configuration the default value for p and q is logic 0. p = 1 mirrors the column data whereas q = 1 mirrors the row data. 8.12.7 r educing current consumption reducing current consumption can be achieved by one of the options mentioned in table 10. table 10 reducing current consumption original mode alternative mode character mode icon mode (control bit im) display on display off (control bit d) 9 interface to microcontroller 9.1 parallel interface the pcf2103 can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. in 8-bit mode data is transferred as 8-bit bytes using the 8 data lines db7 to db0. three further control lines e, rs and r/ w are required; see table 1. in 4-bit mode data is transferred in two cycles of 4 bits each using pins db7 to db4 for transaction. the higher order bits (corresponding to db7 to db4 in 8-bit mode) are sent in the first cycle and the lower order bits (db3 to db0 in 8-bit mode) in the second. data transfer is complete after two 4-bit data transfers. note that two cycles are also required for the busy flag check. 4-bit operation is selected by instruction. see figs 11 to 14 for examples of bus protocol. in 4-bit mode pins db3 to db0 must be left open-circuit. they are pulled up to v dd internally. 1998 may 11 27 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 9.2 i 2 c-bus interface 9.2.1 c haracteristics of the i 2 c- bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high-level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. 9.2.2 i 2 c- bus protocol before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always carried out with the first byte transmitted after the start procedure. the i 2 c-bus configuration for the different pcf2103 read and write cycles is shown in figs 20 to 21. the slow down feature of the i 2 c-bus protocol (receiver holds scl low during internal operations) is not used in the pcf2103. 9.2.3 d efinitions transmitter: the device which sends the data to the bus receiver: the device which receives the data from the bus master: the device which initiates a transfer, generates clock signals and terminates a transfer slave: the device addressed by a master multi-master: more than one master can attempt to control the bus at the same time without corrupting the message arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted synchronization: procedure to synchronize the clock signals of two or more devices. 1998 may 11 28 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family fig.15 system configuration. mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig.16 bit transfer. handbook, full pagewidth mbc621 data line stable; data valid change of data allowed sda scl fig.17 definition of start and stop conditions. handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition fig.18 acknowledgement on the i 2 c-bus. handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master 1998 may 11 29 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... handbook, full pagewidth mgl250 s a 0 s p 011101 0a slave address control byte a 1 co data byte a control byte a r/w 0 co update data pointer 1 byte n 3 0 bytes 2n 3 0 bytes data byte a acknowledgement from pcf2103 rs rs s a 0 011101 0 pcf2103 slave address r/w fig.19 master transmits to slave receiver; write mode. 1998 may 11 30 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... fig.20 master reads after setting word address; write word address, set rs; read data. (1) last data byte is a dummy byte (may be omitted). agewidth mgg003 s a 0 s 011101 0 a slave address control byte a 1 co data byte a control byte a r/w 0 co co update data pointer update data pointer 1 byte n 3 0 bytes n bytes last byte 2n 0 bytes data byte (1) a acknowledgement s a 0 s 1a data byte a 1 p slave address data byte acknowledgement acknowledgement no acknowledgement r/w rs rs 1998 may 11 31 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family fig.21 master reads slave immediately after first byte; read mode (rs previously defined). d book, full pagewidth mgl251 co update data pointer update data pointer n bytes last byte s a 0 s 1a data byte a 1 p slave address data byte acknowledgement from pcf2103 acknowledgement from master no acknowledgement from master r/w fig.22 i 2 c-bus timing diagram. d book, full pagewidth sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat 1998 may 11 32 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 10 limiting values in accordance with the absolute maximum rating system (iec 134). 11 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter min. max. unit v dd supply voltage - 0.5 +6.5 v v lcd lcd supply voltage - 0.5 +7.5 v v i(1) input voltage on pins osc, rs, r/ w, e and db7 to db0 - 0.5 v dd + 0.5 v v i(2) input voltage on pins scl and sda - 0.5 +6.5 v v o output voltage on pins r1 to r18, c1 to c60 and v lcd - 0.5 v lcd + 0.5 v i i dc input current - 10 +10 ma i o dc output current - 10 +10 ma i dd ,i ss and i lcd v dd , v ss or v lcd current - 50 +50 ma p tot total power dissipation - 400 mw p/out power dissipation per output - 100 mw t stg storage temperature - 65 +150 c 1998 may 11 33 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 12 dc characteristics v dd = 1.8 to 5.5 v; v ss =0v; v lcd = 2.2 to 6.5 v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v dd supply voltage 1.8 - 5.5 v v lcd lcd supply voltage 2.2 - 6.5 v i ss supply current note 1 - 60 120 m a v dd =3v; v lcd =5v; notes 1 and 2 - 45 80 m a icon mode; v dd =3v; v lcd = 2.5 v; notes 1 and 2 - 25 45 m a power-down mode; v dd =3v; v lcd = 2.5 v; db7 to db0, rs and r/ w=1; osc = 0; pd = 1; note 1 - 26 m a v por power-on reset voltage note 3 - 1.3 1.6 v logic v il low-level input voltage on pins t1, e, rs, r/ w, db7 to db0 and sa0 0 - 0.3v dd v v ih high-level input voltage on pins t1, e, rs, r/ w, db7 to db0 and sa0 0.7v dd - v dd v v il(pd) low-level input voltage on pin pd 0 - 0.2v dd v v ih(pd) high-level input voltage on pin pd 0.8v dd - v dd v v il(osc) low-level input voltage on pin osc 0 - v dd - 1.5 v v ih(osc) high-input voltage on pin osc v dd - 0.1 - v dd v i ol(db) low-level output current on pins db7 to db0 v ol = 0.4 v; v dd = 5 v 1.6 4 - ma i oh(db) high-level output current on pins db7 to db0 v oh =4v; v dd =5v - 1 - 8 - ma i pu pull-up current on pins db7 to db0 v i =v ss 0.04 0.12 1 m a i l leakage current on pins osc, e, rs, r/ w, db7 to db0 and sa0 v i =v dd or v ss - 1 - +1 m a 1998 may 11 34 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family notes 1. lcd outputs are open-circuit; inputs at v dd or v ss ; bus inactive. 2. t amb =25 c; f osc = 200 khz. 3. resets all logic when v dd 1998 may 11 36 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 14 timing characteristics fig.23 parallel bus write operation sequence; writing data from microcontroller to pcf2103. handbook, full pagewidth rs e db0 to db7 v v v v v v v v v v v v v t ih il ih il ih il il il ih il ih il v il v ih il en(cy) h(d) t data valid mgl252 r/w t su(a) t su(d) t h(a) t h(a) t w(en) fig.24 parallel bus read operation sequence; reading data from pcf2103 to microcontroller. handbook, full pagewidth rs r/w e db0 to db7 v v v v v v v v v v ih il ih il ih il ih il v ol v oh il t en(cy) h(d) t t su(a) t h(a) t h(a) t w(en) ih v ol v oh t d(d) v ih mgl253 data valid 1998 may 11 37 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 15 application information fig.25 direct connection to 8-bit microcontroller; 8-bit bus. handbook, full pagewidth pcf2103 mgl254 p80cl51 2 12 character lcd display plus 120 icons 16 8 c1 to c60 60 2 rs p20 p21 e p22 db7 to db0 p17 to p10 r17, r18 r1 to r16 r/w fig.26 direct connection to 8-bit microcontroller; 4-bit bus. handbook, full pagewidth pcf2103 mgl255 p80cl51 2 12 character lcd display plus 120 icons 16 4 c1 to c60 60 2 rs p10 p11 e p12 db7 to db4 p17 to p14 r17, r18 r1 to r16 r/w fig.27 application example using parallel interface. handbook, full pagewidth mgl256 pcf2103 2 12 character lcd display plus 120 icons 16 8 c1 to c60 60 2 osc rs db7 to db0 e 100 nf 100 nf r17, r18 r1 to r16 v dd v ss v dd v lcd v ss r/w v lcd 1998 may 11 38 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family fig.28 application using i 2 c-bus interface. handbook, full pagewidth v dd v dd scl sda master transmitter pcf84c81a; p80cl410 pcf2103 2 12 character lcd display plus 120 icons 16 c1 to c60 60 2 osc scl sda db3/sao 100 nf 100 nf r17, r18 r1 to r16 v dd v dd v lcd v ss v dd v lcd v ss pcf2103 1 24 character lcd display plus 120 icons 16 c1 to c60 60 2 osc scl sda db3/sao 100 nf 100 nf r17, r18 r1 to r16 v ss v dd v ss v dd v lcd v ss mgl257 v lcd 1998 may 11 39 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 15.1 4-bit operation, 1-line display using internal reset the program must set functions prior to 4-bit operation; table 11 shows an example. when power is turned on, 8-bit operation is automatically selected and the pcf2103 attempts to perform the first write as an 8-bit operation. since nothing is connected to db0 to db3, a rewrite is then required. however, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see table 11 step 3). thus, db4 to db7 of the function set are written twice. 15.2 8-bit operation, 1-line display using internal reset table 12 shows an example of a 1-line display in 8-bit operation. the pcf2103 functions must be set by the function set instruction prior to display. since the ddram can store data for 80 characters, the ram can be used for advertising displays when combined with display shift operation. since the display shift operation changes display position only and ddram contents remain unchanged, display data entered first can be displayed when the return home operation is performed. 15.3 8-bit operation, 2-line display for a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. thus, if there are only 8 characters in the first line, the ddram address must be set after the eighth character is completed (see table 6). it should be noted that both lines of the display are always shifted together; data does not shift from one line to the other. 15.4 i 2 c-bus operation, 1-line display a control byte is required with most commands (see table 15). table 11 4-bit operation, 1-line display example; using internal reset step instruction display operation 1 power supply on (pcf2103 is initialized by the internal reset circuit) initialized; no display appears 2 function set rs r/ w db7 db6 db5 db4 sets to 4-bit operation; in this instance operation is handled as 8-bit by initialization and only this instruction completes with one write 000010 3 function set 000010 sets to 4-bit operation, selects 1-line display and v lcd =v 0 ; 4-bit operation starts from this point and resetting is needed 000000 4 display on/off control 000000 _ turns on display and cursor; entire display is blank after initialization 001110 5 entry mode set 000000 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the dd/cgram; display is not shifted 000110 6 write data to cgram/ddram 100101 p_ writes p; the ddram has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right 100000 1998 may 11 40 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... table 12 8-bit operation, 1-line display example; using internal reset (character set a) step instruction display operation 1 power supply on (pcf2103 is initialized by the internal reset function) initialized; no display appears 2 function set rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 sets to 8-bit operation, selects 1-line display 0000110000 3 display mode on/off control 0000001110 _ turns on display and cursor; entire display is blank after initialization 4 entry mode set 0000000110 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the dd/cgram; display is not shifted 5 write data to cgram/ddram 1001010000 p_ writes p; the ddram has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right 6 write data to cgram/ddram 1001001000 ph_ writes h 7to11 | | 12 write data to cgram/ddram 1001010011 philips_ writes s 13 entry mode set 0000000111 philips_ sets mode for display shift at the time of write 14 write data to cgram/ddram 1000100000 hilips _ writes space 15 write data to cgram/ddram 1001001101 ilips m_ writes m 16 | | | 1998 may 11 41 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 17 write data to cgram/ddram 1001001111 microko writes o 18 cursor/display shift 0000010000 microk o shifts only the cursor position to the left 19 cursor/display shift 0000010000 micro ko shifts only the cursor position to the left 20 write data to cgram/ddram 1001000011 icrok o writes c correction; the display moves to the left 21 cursor/display shift 0000011100 microk o shifts the display and cursor to the right 22 cursor/display shift 0000010100 microco_ shifts only the cursor to the right 23 write data to cgram/ddram 1001001101 icrocom_ writes m 24 | | | 25 return home 0000000010 philips m returns both display and cursor to the original position (address 0) step instruction display operation 1998 may 11 42 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... table 13 8-bit operation, 1-line display and icon example; using internal reset (character set a) step instruction display operation 1 power supply on (pcf2103 is initialized by the internal reset function) initialized; no display appears 2 function set rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 sets to 8-bit operation, selects 1-line display 0000110000 3 display mode on/off control 0000001110 _ turns on display and cursor; entire display is blank after initialization 4 entry mode set 0000000110 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the dd/cgram; display is not shifted 5 set cgram address 0001000000 _ sets the cgram address to position of character 0; the cgram is selected 6 write data to cgram/ddram 1000001010 _ writes data to cgram for icon even phase; icons appear 7 | | 8 set cgram address 0001110000 _ sets the cgram address to position of character 4; the cgram is selected 9 write data to cgram/ddram 1000001010 _ writes data to cgram for icon odd phase 10 | | 11 function set 0000110001 _ sets h = 1 12 icon control 0 0 0 0 0 0 1 0 1 0 _ icons blink 13 function set 0000110001 _ sets h = 0 1998 may 11 43 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 14 set ddram address 0 0 1 0 0 0 0 0 0 0 sets the ddram address to the ?rst position; ddram is selected 15 write data to cgram/ddram 1001010000 p_ writes p; the cursor is incremented by 1 and shifted to the right 16 write data to cgram/ddram 1001001000 ph_ writes h 17 to 20 | | 21 return home 0000000010 philips returns both display and cursor to the original position (address 0) step instruction display operation 1998 may 11 44 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... table 14 8-bit operation, 2-line display example; using internal reset step instruction display operation 1 power supply on (pcf2103 is initialized by the internal reset function) initialized; no display appears 2 function set sets to 8-bit operation; selects 2-line display and voltage generator off rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 0000111000 3 display on/off control turns on display and cursor; entire display is blank after initialization _ 0000001110 4 entry mode set sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the cg/ddram; display is not shifted _ 0000000110 5 write data to cgram/ddram writes p; the ddram has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right p_ 1001010000 6to10 | | | 11 write data to cgram/ddram writes s philips_ 1001010011 12 set ddram address sets ddram address to position the cursor at the head of the 2nd line philips 0011000000 _ 13 write data to cgram/ ddram writes m philips 1001001101 m_ 14 to 19 | | | 1998 may 11 45 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 20 write data to cgram/ddram writes o philips 1001001111 microco_ 21 write data to cgram/ddram sets mode for display shift at the time of write philips 0000000111 microco_ 22 write data to cgram/ddram writes m; display is shifted to the left; the ?rst and second lines shift together hilips 1001001101 icrocom_ 23 | | | 24 return home returns both display and cursor to the original position (address 0) philips 0000000010 microcom step instruction display operation 1998 may 11 46 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... table 15 example of i 2 c-bus operation; 1-line display (using internal reset, assuming sa0 = v ss ; note 1) step instruction display operation 1i 2 c-bus start initialized; no display appears 2 slave address for write sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/ w ack during the acknowledge cycle sda will be pulled-down by the pcf2103 011101001 3 send a control byte for function set co rs 0 0 0 0 0 0 ack control byte sets rs for following data bytes 000000001 4 function set db7 db6 db5 db4 db3 db2 db1 db0 ack selects 1-line display; scl pulse during acknowledge cycle starts execution of instruction 001x00001 5 display on/off control _ db7 db6 db5 db4 db3 db2 db1 db0 ack turns on display and cursor; entire display shows character 20h (blank in ascii-like character sets) 000011101 6 entry mode set _ db7 db6 db5 db4 db3 db2 db1 db0 ack sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the ddram or cgram; display is not shifted 000001101 7i 2 c-bus start _ for writing data to ddram, rs must be set to 1; therefore a control byte is needed 8 slave address for write _ sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/ w ack 011101001 9 send a control byte for write data _ co rs 0 0 0 0 0 0 ack 010000001 10 write data to ddram db7 db6 db5 db4 db3 db2 db1 db0 ack writes p; the ddram has been selected at power-up; the cursor is incremented by 1 and shifted to the right 010100001 p_ 1998 may 11 47 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 11 write data to ddram db7 db6 db5 db4 db3 db2 db1 db0 ack writes h 010010001 ph_ 12 to 15 | | | | 16 write data to ddram db7 db6 db5 db4 db3 db2 db1 db0 ack writes s 010100111 philips_ 17 (optional i 2 c-bus stop) i 2 c-bus start + slave address for write (as step 8) philips_ 18 control byte co rs 0 0 0 0 0 0 ack 100000001 philips_ 19 return home db7 db6 db5 db4 db3 db2 db1 db0 ack sets ddram address 0 in address counter (also returns shifted display to original position; ddram contents unchanged); this instruction does not update the data register (dr) 000000101 philips 20 i 2 c-bus start philips 21 slave address for read sa6 sa5 sa4 sa3 sa2 sa1 sa0 r/ w ack during the acknowledge cycle the content of the dr is loaded into the internal i 2 c-bus interface to be shifted out; in the previous instruction neither a set address nor a read data has been performed; therefore the content of the dr was unknown; r/ w has to be set to logic 1 while still in i 2 c-bus write mode 011101011 p hilips 22 control byte for read co rs 0 0 0 0 0 0 ack ddram content will be read from following instructions 011000001 philips step instruction display operation 1998 may 11 48 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... notes 1. x = dont care. 2. sda is left at high-impedance by the microcontroller during the read acknowledge. 23 read data: 8 scl + master acknowledge; note 2 db7 db6 db5 db4 db3 db2 db1 db0 ack 8 scl; content loaded into interface during previous acknowledge cycle is shifted out over sda; msb is db7; during master acknowledge content of ddram address 01 is loaded into the i 2 c-bus interface xxxxxxxx0 ph ilips 24 read data: 8 scl + master acknowledge; note 2 db7 db6 db5 db4 db3 db2 db1 db0 ack 8 scl; code of letter h is read ?rst; during master acknowledge code of i is loaded into the i 2 c-bus interface 010010000 phi lips 25 read data: 8 scl + no master acknowledge; note 2 db7 db6 db5 db4 db3 db2 db1 db0 ack no master acknowledge; after the content of the i 2 c-bus interface register is shifted out no internal action is performed; no new data is loaded to the interface register, data register (dr) is not updated, address counter (ac) is not incremented and cursor is not shifted 010010011 phi lips 26 i 2 c-bus stop phi lips step instruction display operation 1998 may 11 49 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... table 16 initialization by instruction, 8-bit interface (note 1) note 1. x = dont care. step description power-on or unknown state | wait 2 ms after v dd rises above v por | rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 bf cannot be checked before this instruction 0 0 0 0 1 1 x x x x function set (interface is 8 bits long) | wait 2 ms | rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 bf cannot be checked before this instruction 0 0 0 0 1 1 x x x x function set (interface is 8 bits long) | wait more than 40 m s | rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 bf cannot be checked before this instruction 0 0 0 0 1 1 x x x x function set (interface is 8 bits long) | | bf can be checked after the following instructions; when bf is not checked, the waiting time between instructions is the speci?ed instruction time (see table 4) rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 function set (interface is 8 bits long); specify the number of display lines 0000110m0h 0 0 0 0 0 0 1 0 0 0 display off 0 0 0 0 0 0 0 0 0 1 clear display 0 0 0 0 0 0 0 1 i/d s entry mode set | initialization ends 1998 may 11 50 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... table 17 initialization by instruction, 4-bit interface; not applicable for i 2 c-bus operation step description power-on or unknown state | wait 2 ms after v dd rises above v por | rs r/ w db7 db6 db5 db4 bf cannot be checked before this instruction 000011 function set (interface is 8 bits long) | wait 2 ms | rs r/ w db7 db6 db5 db4 bf cannot be checked before this instruction 000011 function set (interface is 8 bits long) | wait 40 m s | rs r/ w db7 db6 db5 db4 bf cannot be checked before this instruction 000011 function set (interface is 8 bits long) | bf can be checked after the following instructions; when bf is not checked, the waiting time between instructions is the speci?ed instruction time (see table 4) rs r/ w db7 db6 db5 db4 function set (set interface to 4 bits long) 000010 interface is 8 bits long 000010 function set (interface is 4 bits long) 0 0 0 m 0 h specify number of display lines 000000 001000 display off 000000 clear display 000001 000000 entry mode set 0001i/ds | initialization ends 1998 may 11 51 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 16 bonding pad locations fig.29 bonding pad locations. handbook, full pagewidth mgl258 1 105 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 v dd osc pd t1 v ss r9 v lcd r10 r11 r12 r13 r14 r15 r16 r18 c60 c59 c58 c57 c56 c55 c54 c53 c20 c21 c22 c23 c24 c25 c26 c27 c12 c13 c14 c15 c16 c17 c18 c19 c3 c4 c5 c6 c7 c8 c9 c10 c11 26 25 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 c52 c51 c50 c49 c48 c47 c46 c45 c44 c43 c42 c41 c40 c39 c38 c37 c36 c35 c34 c33 c32 c31 c30 c29 c28 53 52 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 80 79 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 c2 c1 r8 r7 r6 r5 r4 r3 r2 r1 r17 scl sda e rs db7 db6 db5 db4 db3 db2 db1 db0 c52(dummy) c28(dummy) c3(dummy) c27(dummy) rom xxx pcf2103-2 x y 0 0 ? 2.99 mm ? 3.18 mm r/w c2(dummy) db0(dummy) v dd(dummy) c53(dummy) 1998 may 11 52 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family table 18 bonding pad locations (dimensions in m m). all x/y coordinates are referenced to centre of chip (see fig.29) symbol pad x y v dd (dummy) 105 - 1228 - 1414 v dd 1 - 1048 - 1414 osc 2 - 958 - 1414 pd 3 - 868 - 1414 t1 4 - 778 - 1414 v ss 5 - 688 - 1414 v lcd 6 - 516 - 1414 r9 7 - 349 - 1414 r10 8 - 259 - 1414 r11 9 - 169 - 1414 r12 10 - 79 - 1414 r13 11 11 - 1414 r14 12 101 - 1414 r15 13 191 - 1414 r16 14 281 - 1414 r18 15 371 - 1414 c60 16 461 - 1414 c59 17 551 - 1414 c58 18 641 - 1414 c57 19 731 - 1414 c56 20 821 - 1414 c55 21 911 - 1414 c54 22 1001 - 1414 c53 23 1091 - 1414 c53 (dummy) 24 1181 - 1414 c52 (dummy) 25 1344 - 1254 c52 26 1344 - 1164 c51 27 1344 - 1074 c50 28 1344 - 948 c49 29 1344 - 812 c48 30 1344 - 722 c47 31 1344 - 632 c46 32 1344 - 542 c45 33 1344 - 452 c44 34 1344 - 362 c43 35 1344 - 272 c42 36 1344 - 182 c41 37 1344 - 92 c40 38 1344 - 2 c39 39 1344 88 c38 40 1344 178 c37 41 1344 268 c36 42 1344 358 c35 43 1344 448 c34 44 1344 538 c33 45 1344 628 c32 46 1344 718 c31 47 1344 808 c30 48 1344 898 c29 49 1344 1070 c28 50 1344 1160 c28 (dummy) 51 1344 1250 c27 (dummy) 52 1262 1414 c27 53 1172 1414 c26 54 1082 1414 c25 55 992 1414 c24 56 902 1414 c23 57 805 1414 c22 58 715 1414 c21 59 625 1414 c20 60 535 1414 c19 61 445 1414 c18 62 355 1414 c17 63 265 1414 c16 64 175 1414 c15 65 85 1414 c14 66 - 5 1414 c13 67 - 95 1414 c12 68 - 185 1414 c11 69 - 275 1414 c10 70 - 446 1414 c9 71 - 536 1414 c8 72 - 626 1414 c7 73 - 716 1414 c6 74 - 806 1414 c5 75 - 896 1414 symbol pad x y 1998 may 11 53 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family c4 76 - 986 1414 c3 77 - 1076 1414 c3 (dummy) 78 - 1166 1414 c2 (dummy) 79 - 1344 1303 c2 80 - 1344 1213 c1 81 - 1344 1123 r8 82 - 1344 1033 r7 83 - 1344 943 r6 84 - 1344 853 r5 85 - 1344 763 r4 86 - 1344 673 r3 87 - 1344 583 r2 88 - 1344 493 r1 89 - 1344 403 r17 90 - 1344 313 scl 91 - 1344 131 sda 92 - 1344 - 9 e93 - 1344 - 195 rs 94 - 1344 - 289 rw 95 - 1344 - 382 db7 96 - 1344 - 476 db6 97 - 1344 - 572 db5 98 - 1344 - 668 db4 99 - 1344 - 765 db3 100 - 1344 - 861 db2 101 - 1344 - 957 db1 102 - 1344 - 1054 db0 103 - 1344 - 1150 db0 (dummy) 104 - 1344 - 1240 rec. pat. c1 1335 - 1405 rec. pat. c2 - 1335 1405 rec. pat. f - 1340 - 1397 symbol pad x y table 19 bump speci?cations parameter specification unit bump variant n - type galvanic; pure aurum - bump width 60 6 m m bump length 90 6 m m bump height 17.5 5 m m height difference in one die <2 m m convex deformation <5 m m pad size; aluminium 80 100 m m passivation opening cbb 46 76 m m wafer thickness 380 25 m m minimum pitch 90 m m 1998 may 11 54 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family 17 definitions 18 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 19 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 1998 may 11 55 philips semiconductors product speci?cation lcd controllers/drivers pcf2103 family notes internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1998 sca60 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 415106/1200/01/pp56 date of release: 1998 may 11 document order number: 9397 750 02649 |
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