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corei2c v6.0 handbook
? 2009 actel corporation. all rights reserved. printed in the united states of america part number: 50200090-5 release: november 2009 no part of this document may be copied or reproduc ed in any form or by any means without prior written consent of actel. actel makes no warranties with respect to this docu mentation and disclaims any implied warranties of merchantability or fitness for a particu lar purpose. information in this document is su bject to change without notice. actel assumes no respon sibility for any errors that may appear in this document. this document contains confidential proprietary information that is not to be disclosed to any unauthorized person without prior written consent of actel corporation. trademarks actel, igloo, actel fusion, proasic, libero, pigeon poin t and the associated logos ar e trademarks or registered trademarks of actel corporation. al l other trademarks and service marks ar e the property of their respective owners.
corei2c v6.0 3 table of contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 core overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 core version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 supported interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 utilization and performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1 design description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 verilog/vhdl parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 serial and apb interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 functional block descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 operation details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 register map and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 tool flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 smartdesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 simulation flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 synthesis in libero ide: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 place-and-route in libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3 example application and hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 software driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 usage with cortex-m1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 hints on i/o pad requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 hints on configuring wired-and bidirectiona l buffers in rtl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 hints on meeting smbus/pmbus timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4 list of document changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 a product support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 customer service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 actel customer technical support center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 actel technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 contacting the customer technical support center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 index . . . . . . . . . . . . . . . . . . . . . . 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corei2c v6.0 5 introduction core overview intended use corei2c provides an apb-driven serial interface, supporting i 2 c, smbus, and pmbus data transfers. several verilog/vhdl parameters are available to minimize fpga fabric area for a given application. corei2c also allows for multiple i 2 c channels, reusing logic ac ross channels to reduce overall tile count. key features ? conforms to the philips inter-integrated circuit (i 2 c) v2.1 specification (7-bit addressing format at 100 kbps and 400 kbps data rates) ? supports smbus v2.0 specification ? supports pmbus v1.1 specification ? data transfers up to at least 400 kbps nomina lly; faster rates can be achieved depending on external load and/or i/o pad circuitry ? modes of operation configurable to minimize size ? advanced peripheral bus (apb) register interface ? multi-master collision de tection and arbitration ? own address and general call address detection ? second slave address decode capability ? data transfer in multiples of bytes ? smbus timeout and real-time idle condition counters ? ipmi 3 ms scl low timeout ? optional smbus signals, smbsus_n an d smbalert_n, controllable via apb if ? configurable spike suppression width ? multiple channel configuration option core version this handbook supports corei2c version 6.0. supported interfaces corei2c is available with the following interfaces: ? serial i 2 c/smbus/pmbus interface ? apb interface for register access these interfaces are further described in the "serial and apb interfaces" section on page 14 .
introduction 6 corei2c v6.0 utilization and performance corei2c has been implemented in several of actel?s device families using standard speed grades. a summary of various implemen tation data is listed in table 1 through table 5 on page 8 . table 1 ? corei2c device utilization and performance (slave-only i 2 c configuration) family tiles utilization performance mhz sequential combinatorial total device total % fusion 51 310 361 afs600 2.6 130 igloo ? /e 51 310 361 agle600v2 2.6 54 proasic ? 3/e 51 310 361 m1a3p250 5.9 127 proasic plus ? 58 355 413 apa075 13 68 axcelerator ? 58 199 257 ax250 6.1 135 rtax-s 58 299 257 rtax250s 6.1 101 note: data in this table were achieved using the verilog rtl with typical synthesis and layout settings. top-level parameters/generics were set as follows: i2c_num=1, operating_mode = 1, baud_rate_fixed = 1, baud_rate_va lue = 6, bclk_enabled = 0, glitchreg_num = 3, smb_en = 0, ipmi_en = 0, frequency = 0, fixed_slave0_addr_en = 1, fixed_slave0_addr_value = 0x20, add_slave1_address_en = 0, fixed_slave1_addr_en = 0, fixed_slave1_addr_value = 0. table 2 ? corei2c device utilization an d performance (master/slave i 2 c configuration) family tiles utilization performance mhz sequential combinatorial total device total % fusion 73 451 524 afs600 3.8 116 igloo/e 73 451 524 agle600v2 3.8 52 proasic3/e 73 451 524 m1a3p250 8.5 125 proasic plus 81 499 580 apa075 18.9 69 axcelerator 82 303 385 ax250 9.1 135 rtax-s 82 303 385 rtax250s 9.1 100 note: data in this table were achieved using the verilog rtl with typical synthesis and layout settings. top-level parameters/generics were set as follows: i2c_num=1, operating_mode = 0, baud_rate_fixed = 1, baud_rate_value = 6, bclk_enabled = 0, glitchreg_num = 3, smb_en = 0, ipmi_en = 0, freq uency = 0, fixed_slave0_addr_en = 1, fixed_slave0_addr_value = 0x20, add_slave1_address_en = 0, fixed_slave1_addr_en = 0, fixed_slave1_addr_value = 0.
utilization and performance corei2c v6.0 7 table 3 ? corei2c device utilization and performance (ipmi master-tx/slave-rx i 2 c configuration) family tiles utilization performance mhz sequential combinatorial total device total % fusion 92 492 584 afs600 4.2 121 igloo/e 92 492 584 agle600v2 4.2 52 proasic3/e 92 492 584 m1a3p250 9.5 118 proasic plus 96 556 652 apa075 21 65 axcelerator 101 325 426 ax250 10 111 rtax-s 101 325 426 rtax250s 10 86 note: data in this table were achieved using the verilog rtl with typical synthesis and layout settings. top-level parameters/generics were set as follows: i2c_num=1, operating_mode = 2, baud_rate_fixed = 1, baud_rate_value = 6, bclk_enabled = 0, glitchreg_num = 3, smb_en=0, ipmi_en = 1, frequency = 30, fixed_slave0_addr_en = 1, fixed_slave0_addr_value = 0x20 , add_slave1_address_en = 1, fixed_slave1_addr_en = 1, fixed_slave1_addr_value = 0x33. table 4 ? corei2c device utilization and perform ance (master/slave smbus configuration) family tiles utilization performance mhz sequential combinatorial total device total % fusion 117 587 704 afs600 5.1 112 igloo/e 117 587 704 agle600v2 5.1 46 proasic3/e 117 587 704 m1a3p250 11.5 111 proasic plus 125 673 798 apa075 26 54 axcelerator 127 400 527 ax250 12 109 rtax-s 127 400 527 rtax250s 12 80 note: data in this table were achieved using the verilog rtl with typical synthesis and layout settings. top-level parameters/generics were set as follows: i2c_num=1, operating_mode = 0, baud_rate_fixed = 1, baud_rate_value = 6, bclk_enabled = 0, glitchreg_num = 3, smb_en = 1, ipmi_en = 0, frequency = 30, fixed_slave0_addr_en = 1, fixed_slave0_addr_value = 0x20 , add_slave1_ad dress_en = 0, fixed_slave1_addr_en = 0, fixed_slave1_addr_value = 0.
introduction 8 corei2c v6.0 table 5 ? corei2c device utilization and perform ance (13 channel ipmi configuration) family tiles utilization performance mhz sequential combinatorial total device total % fusion 989 6,001 6,990 afs600 51 97 igloo/e 989 6,001 6,990 agle600v2 51 44 proasic3/e 989 6,001 6,990 m1a3p600 51 105 proasic plus 1,099 6,887 7,986 apa600 37 47 axcelerator 1,166 4,082 5,248 ax1000 29 69 rtax-s 1,166 4,082 5,248 rtax1000 29 64 note: data in this table were achieved using the verilog rtl with typical synthesis and layout settings. top-level parameters/generics were set as follows: i2c_num=13, operating_mode=2, baud_rate_fixed=1, baud_rate_value=7, bclk_enabled=1, glitchreg_num=3, smb_en=0, ipmi_en=1, frequency=30, fixe d_slave0_addr_en=0, fixed_slave0_addr_value=32, add_slave1_address_en=1, fixed_slave1_addr_en=1, and fixed_slave1_addr_value=20.
configuration example corei2c v6.0 9 configuration example figure 1 illustrates a typical application. co rtex?-m1, coupled with corei2c, masters communication with a smbus temperature sensor slave, and an i 2 c slave in fpga #2. in fpga #2, corei2c is configured in slave-only mode with coreabc as its control. figure 1 ? corei2c smbus application example v cc smbus host controller (master/slave mode) sda scl v cc v cc i2c intelligent device (slave-only mode) cortex-m1 core i2c apb sdao sdai scli sclo temperature sensor smbus device fpga #1 fpga #2 coreabc core i2c apb sdao sdai scli sclo smbus host controller source code r p r p smbalerti smbalerto r p smbalert

corei2c v6.0 11 1 ? design description i/o signals the port signals for the corei2c macro are illustrated in figure 1-1 and defined in table 1-1 . figure 1-1 ? corei2c i/o signal diagram table 1-1 ? corei2c i/o signal descriptions name type description apb interface pclk input apb system cl ock; reference clock fo r all internal logic presetn input apb active low asynchronous reset paddr[8:0] input apb address bus; address in ternal registers. bi ts 8 to 5 function as address pointers to one of the 16 channels. psel input apb slave select; select si gnal for register for reads or writes penable input apb strobe. this signal indica tes the second cycle of an apb transfer. pwrite input apb write/read. if high, a write occurs when an apb transfer takes place. if low, a read takes place. pwdata[7:0] input apb write data prdata[7:0] output apb read data int[i2c_num-1:0] output interrupt output; monitors status register. smba_int[i2c_num-1:0 ] output optional (if smbus enabled) in terrupt output; monitors assertion of smbalert_ni. level sensitive; hence only the deassertion of smbalert_ni will cl ear the interrupt. smbs_int[i2c_num-1:0] output optional (if smbus en abled) interrupt output; monitors assertion of smbsus_ni. level sensitive; hence only the deassertion of smbalert_ni will cl ear the interrupt. note: all signals are active high (logic 1) unless otherwise noted. presetn corei2c pclk penable paddr[8:0] prdata[7:0] int[i2c_num-1:0] pwrite scli[i2c_num-1:0] sclo[i2c_num-1:0] sdai[i2c_num-1:0] sdao[i2c_num-1:0] pwdata[7:0] psel apb if smbsus_ni[i2c_num-1:0] smbalert_ni[i2c_num-1:0] smbalert_no[i2c_num-1:0] smbus optional signals serial if smbsus_no[i2c_num-1:0] smba_int[i2c_num-1:0] smbs_int[i2c_num-1:0] bclk
design description 12 corei2c v6.0 verilog/vhdl parameters corei2c has parameters (verilog) or generics (v hdl) for configuring the rtl code, described in table 1-2 . all parameters and generics are integer types. serial interface scli[i2c_num-1:0] input wi red-and serial clock input sclo[i2c_num-1:0] output wire d-and serial clock output sdai[i2c_num-1:0] input wi red-and serial data input sdao[i2c_num-1:0] output wire d-and serial data output smbus optional signals smbalert_ni[i2c_num-1:0] input wired-and interrupt signal input; used in master/host mode to monitor if slave/devices want to force communication with the host. smbalert_no[i2c_num-1:0] output wired -and interrupt signal input; used in slave/device mode if the core wants to force co mmunication with a host. smbsus_ni[i2c_num-1:0] input suspend mode sign al input; used if core is slave/device. not a wired-and signal. smbsus_no[i2c_num-1:0] output suspend mode signal output; used if core is the master/host. not a wired-and signal. other signals bclk input pulse for scl speed control. used only if the configuration bits cr[2:0] = 111; otherwise, various divisions of pclk are used. table 1-1 ? corei2c i/o signal descriptions (continued) note: all signals are active high (logic 1) unless otherwise noted. table 1-2 ? corei2c parameters/gene rics descriptions parameter name valid range description default i2c_num 1 to 16 number of i 2 c channels 1 frequency 1 to 255 pclk frequency value in mhz. frequency parameter is only necessary to confi gure optional smbus or ipmi timeout counters. 30 operating_mode 0 to 3 0: full master/slave tx/rx modes. 1: slave tx/rx modes only. 2: master tx and slave rx modes only. 3: slave rx mode only. 0 bclk_enabled 0 or 1 0: bclk input is disabled, reducing tile count. 1: bclk input is enabled. 1 baud_rate_fixed 0 or 1 0: baud rate valu e (bits cr[2:0] in the control register) modified by an ap b-accessible register. 1: baud rate value [bits cr[2:0] in the control register) is fixed to the paramete r baud_rate value, reducing tile count. 0
verilog/vhdl parameters corei2c v6.0 13 baud_rate_value 0 to 7 fixed baud rate values bit value : scl frequency : 000 pclk frequency/256 001 pclk frequency/224 010 pclk frequency/192 011 pclk frequency/160 100 pclk frequency/960 101 pclk frequency/120 110 pclk frequency/60 111 bclk frequency/8 0 smb_en 0 or 1 1: generates the smbus logic: smbus register, real-time checks and timeout values. 0: smbus logic not generated . 0 ipmi_en 0 or 1 1: generates 3 ms scl low ipmi required timeout counter with error status and interrupt. 0: ipmi timeout counter not generated. 0 glitchreg_num 3 to 15 number of registe rs in the glitch filter. correct value to meet i 2 c fast mode (400 kbps) and fast mode plus (1 mbps). 50 ns spike suppression will depend on the pclk frequency. guideline: pclk freq (mhz) gli tchreg_num for 50 ns or less spike suppression freq ?? 60 3 60 < freq ? 80 4 80 < freq ? 100 5 100 < freq ?? 120 6 120 < freq ?? 140 7 140 < freq ? 160 8 160 < freq ?? 180 9 180 < freq ?? 200 10 3 fixed_slave0_addr_en 0 or 1 0: slave0 address has apb write access. 1: slave0 address is hardcoded, reducing tile count. 0 fixed_slave0_addr_value 0x00 to 0x7f hardcoded slave0 address value. 0 add_slave1_address_en 0 or 1 0: sla ve1 address is not enabled. 1: slave1 address is enabled. 0 fixed_slave1_addr_en 0 or 1 0: slave1 address has apb write access. 1: slave1 address is hardcoded, reducing tile count. 0 fixed_slave1_addr_value 0x00 to 0x7f hardcoded slave0 address value 0 table 1-2 ? corei2c parameters/generics descriptions (continued)
design description 14 corei2c v6.0 serial and apb interfaces serial interface a typical i 2 c/ipmi/smbus/pmbus 8-bit data transfer cycle is shown in figure 1-2 . a master start condition is signalled by the sda line going low wh ile the scl line is high. after a start condition, the master sends a slave address along with a read or write bit. the addressed slave acknowledges its address with an ack, and th en multiple bytes can be transfe rred with an ack/nack for each byte. eventually the master asserts a stop condit ion, which occurs when the sda line goes high while the scl line is high. a user of corei2c must configure the system (logic, i/o pads, extern al circuitry and pull-up resistors) to ensure that the serial interfa ce timings adhere to a given i 2 c/smbus/pmbus specification. note: to adhere to additional smbus/pmbus hold times and minimum clock high times, configure pclk to be within the 5 mhz to 20 mhz range . additionally, choose a baud rate value so that the serial scl clock will transfer data at or near the maximum frequency of 100 khz (fsmb- max) to ensure that other potential clock stret ching devices on the bus will not slow the clock frequency to below the minimum allowe d smbus clock of 10 khz (fsmb-min). for detailed timing info rmation, refer to the i 2 c/ipmi/smbus/pmbus spec ifications directly. apb interface figure 1-3 and figure 1-4 depict typical write cycle and read cycle timing relati onships relative to the system clock. figure 1-2 ? serial interface byte transfer scl sda msb lsb r/w ack s start s start p stop address data msb lsb ack figure 1-3 ? data write cycle figure 1-4 ? data read cycle p c lk p s el pwrite penable paddr[8:0] pwdata[7:0] re g ister a dd ress re g ister data p c lk p s el pwrite penable paddr[8:0] prdata[7:0] re g ister a dd ress re g ister data
functional block descriptions corei2c v6.0 15 functional block descriptions corei2c, as shown in figure 1-5 , consists of apb interface registe rs, serial inpu t spike filters, arbitration and synchronization logic, and a serial clock generation block. the following sections briefly describe each design block. apb interface corei2c supports the advanced peripheral bus (apb) interface , compatible with the actel core8051s and cortex-m1 processor cores, as well as the coreabc generic apb-based state machine controller. the apb registers are defined and usage detailed in the "register map and de scriptions" section on page 1-19 . input glitch/spike filters input signals are synchronized with the inte rnal clock, pclk. spik es shorter than the parameterizeable glitch regist er length are filtered out. arbitration and synchronization logic in master mode, the arbitration lo gic checks that every transmitted logic '1' actually appears as a logic '1' on the bus. if another device on the bus overrules a logic '1' and pulls the data line low, arbitration is lost and corei2c immediately chan ges from master transmitter to slave receiver. the figure 1-5 ? corei2c block diagram (single channel) scli[0:0] slave address registers slave address comparator shift register arbitration and synchronization logic serial clock generator control register status register smbus or ipmi register input glitch filter input glitch filter output output sclo[0:0] sdai[0:0] sdao[0:0] bclk paddr[8:0] pwdata[7:0] apb interface smba_int[0:0] smbs_int[0:0] int pwrite penable prdata[7:0] psel pclk presetn smbsus_ni[0:0] smbsus_no[0:0] smbalert_ni[0:0] smbalert_no[0:0] optional smbus or ipmi register smbus or ipmi timeout counters
design description 16 corei2c v6.0 synchronization logic synchronizes the serial cl ock generator block with the transmitted clock pulses coming from another master device. the arbitration and synchr onization logic also utilizes timeou t requirements set fo rth in the smbus specification version 2.0, or crea tes a 3 ms ipmi scl low timeout. serial clock generator this programmable clock pulse generator provides the serial bus clock pulses when corei2c is in master mode. the clock generator is switched off when corei2c is in save mode. the baud rate clock (bclk) is a pulse-for-transmi ssion speed control signal and is internally synchronized with the clock input. bclk may be used to set the serial cl ock frequency when the cr[2:0] bits in the control register are set to 111; otherwise, pclk divisions are used to dete rmine the serial clock frequency. the actual non-stretched serial bus clock frequency can be calculat ed based on the setting in the cr2-0 fields of the control register and th e frequencies of pclk and bclk. refer to table 1-5 on page 1-20 for configuration. address comparator the comparator checks the received seven-bit slave address with its own slave address, and optionally its own second address, slave1 (for dual-address applications). the comparator also compares the first received eight-bit byte with the general call address (00h). if a match is found, the status register is updated and an interrupt is requested. optional smbus/ipmi logic the optional smbus / ipmi logic includes the smbus sign als, clock-low timeou t counters, and reset logic; or when in ipmi mode, the optional 3 ms clock-low timeout counters (an smbus clock low master reset example is demonstrated in the "operation details" section on page 1-17 ). smbus/ipmi logic includes a to p-level prescale coun ter, which counts in increments of 215 microseconds. a second smaller co unter in each channel increments based on the prescale count of 215 microseconds. this design was chosen to reduce overall area at the expense of timeout precision (when the clock-low condition occurs in ipmi mode, the free running 215 microsecond counter may be anywhere in its count). as such, the 3 ms timeout flag will occur between 3.010 and 3.225 ms. the 35 ms smbus mast er-holding-clock-low flag will occur between 35.045 and 35.260 ms, and the 25 ms smbu s timeout flag wi ll occur between 25.155 and 25.370 ms.
operation details corei2c v6.0 17 operation details i 2 c operating modes corei2c logic can operate in the following four modes: 1. master transmitter mode: serial data output through sda wh ile scl outputs the serial clock. 2. master receiver mode: serial data is received via sda while scl outputs the serial clock. 3. slave receiver mode: serial data and the serial clock are received through sda and scl. 4. slave transmitter mode: serial data is transmitted via sda whil e the serial clock is input through scl. slave mode example after setting the ens1 bi t in the control register, the core is in the not addressed slave mode. in slave mode, the core looks for its own slave address and the general call address. if one of these addresses is detected, the core switches to ad dressed slave mode and generates an interrupt request. then the core can operate as a slave transmitter or a slave receiver. transfer example: ? microcontroller sets ens1 and aa bits ? core receives own address and 0. ? core generates interrupt request; status register = 0x60 ( table 1-11 on page 1-26 ) ? microcontroller prepares for rece iving data and then clears si bit. ? core receives next data byte and then gene rates interrupt request. the status register contains 0x80 or 0x88 value depending on aa bit ( table 1-11 on page 1-26 ). ? transfer is continued according to table 1-11 on page 1-26 . master mode example when the microcon troller wishes to become the bus master , the core waits until the serial bus is free. when the serial bus is free, the core generates a start condit ion, sends the slave address and transfers the direction bit. the core can operate as a master transmitter or as a master receiver, depending on the transfer direction bit. transfer example: ? microcontroller se ts ens1 and sta bits. ? core sends start condition and then generates interrupt request; status register = 0x08 ( table 1-9 on page 1-21 ). ? microcontroller writes the data register (7-bit slave address and 0) and then clears si bit. ? core sends data register contents and then gene rates interrupt request. the status register contains 0x18 or 0x20 value, depending on received ack bit ( table 1-9 on page 1-21 ). ? transfer is continued according to table 1-9 on page 1-21 .
design description 18 corei2c v6.0 smbus clock low reset example if the clock line is held low by a master who has initiated a bus reset with the smbus register, the following sequence should occur. refer to figure 1-6 . ? transfer example: ? the master device sets smbus reset bit, forcin g the clock line low; the master device enters the resetting state, 0xd0, and an interrupt is generated after 35 ms. ? a slave device will enter the reset state, 0xd8, after 25 ms and an interrupt will be generated. once the interrupt is asserted, the apb controller of the slave device will need to clear the interrupt within 10 ms per the smbus specification v.2. 0, and the slav e device will enter the idle state, 0xf8. ? after 35 ms, the master device?s interrupt will be asserted, and the apb controller of the master device will eventually clear the interr upt, forcing the master device into the idle state, 0xf8. figure 1-6 ? smbus bus reset sequence host (master) resets the bus scl host sets smbus reset bit; clock line goes low. 25 ms 35 ms slave reset status set master status xx 0xd0 0xf8 master int slave status xx 0xd8 0xf8 slave int slave apb controller must clear interrupt within 10 ms, i2c enters idle mode, 0xf8. host clears bit and releases bus, entering idle state, 0xf8. host 35 ms timeout interrupt bit set, still d0 state until cleared.
register map and descriptions corei2c v6.0 19 register map and descriptions paddr[8:5] bits determine which i 2 c channel is being addressed, as shown in table 1-3 . table 1-4 defines the register map and reset values of each channel's apb-accessible registers. 0x denotes hexadecimal, 0b denotes binary, and 0d denotes decimal format. "x" implies an unknown condition. "?"implies don't care condition. type designations: r is read-only, r/w is read/write. the following sections and tables detail the ap b-accessible registers with in each corei2c channel. table 1-3 ? corei2c per channel pointer addressing paddr[8:5] type reset va lue brief description channel id value n/a n/a bits 8 to 5 of padd r function as address pointers to one of the 16 channels. note that the chan nel id value does not apply to the addr0 and addr1 registers shown in table 1-4 . the values in those registers are the same for all channels. paddr[8:5] channel number 0000 0 0001 1 ?? ?. 1111 15 table 1-4 ? corei2c internal register address map paddr[4:0] register name type width reset value brief description 0x00 ctrl r/w 8 0x00 control register; used to configure each i 2 c channel. 0x04 stat r 8 0xf8 status register; read -only value yields the current state of the particular i 2 c channel. 0x08 data r/w 8 0x00 data register; i 2 c channel read/write data to/from the serial if. 0x0c addr0 r/w 8 0x00 slave0 address regi ster; contains the programmable slave0 address of all channels. note: the slave0 address register is a single register that is used in all channels. only paddr[4:0] are required to write addr0; paddr[8:5] are "don't care" bits. 0x10 smb r/w 8 0b01x1x000 smbus or ipmi register smbus context: configuration register for smbus timeouts and reset condit ion and for the optional smbus signals smbalert_n and smbsus_n. ipmi context: enable/disable ipmi scl low timeout 0x1c addr1 r/w 8 0x00 slave1 address regi ster; contains the programmable slave1 address of all channels. when this slave1 address is enabled yet fixed, the register will have a r/w bit to enable/disable slave1 comparisons. only the enable/disable bit will be r/w. the address is write only. note: the slave1 address register is a single register that is used in all channels. only the enable/disable bit is r/w. only paddr[4:0] are required to write addr0; paddr[8:5] are "don't care" bits.
design description 20 corei2c v6.0 control register the control register is described in table 1-5 and table 1-6 on page 1-20 . the cpu can read from and write to this 8-bit, directly addressable apb. two bits are affected by the corei2c: the si bit is set when a serial interrupt is re quested and the sto bit is cleared when a stop condition is present on the bus. table 1-5 ? control register paddr[4:0] register name type wi dth reset value description 0x00 ctrl r/w 8 0x00 control regist er; used to configure each i 2 c channel. table 1-6 ? control register bit fields bits name type description 7 cr2 r/w clock rate bit 2; refer to bit 0. 6 ens1 r/w enable bit. when ens1 = 0, the sda an d scl outputs are in a high impedance table and sda and scl input signals are ignored. wh en ens1 = 1, the channel is enabled. 5 sta r/w the start flag. when sta = 1, the channel checks the status of the serial bus and generates a start condition if the bus is free. 4 sto r/w the stop flag. when sto = 1 and the ch annel is in a master mo de, a stop condition is transmitted to the serial bus. 3 si r/w the serial interrup t flag. the si flag is set by the channel whenev er there is a serviceable change in the status register. after the regi ster has been updated, the si? bit must be cleared by software. the si bit is directly readable via the apb interrupt signal. 2 aa r/w the assert acknowledge flag. when aa= 1, an acknowledge (a ck) will be returned when: the "own slave address" has been received. the general call address has been received while the gc bit in the address register is set. a data byte has been received while the channel is in the ma ster receiver mode. a data byte has been received while the channel is in the slave receiver mode. when aa = 0, a not acknowledge (nack) will be returned when: a data byte has been received while the channel is in the ma ster receiver mode. a data byte has been received while the channel is in the slave receiver mode. 1 cr1 r/w serial clock rate bit 1; refer to bit 0. 0 cr0 r/w serial clock rate bit 0; clock rate is defined as follows: cr2 cr1 cr0 scl frequency 000pclk frequency/256 001pclk frequency/224 010pclk frequency/192 011pclk frequency/160 100pclk frequency/960 101pclk frequency/120 110pclk frequency/60 111bclk frequency/8
register map and descriptions corei2c v6.0 21 status register the status register is read-only. the status values are listed, de pending on mode of operation, in table 1-9 through table 1-13 on page 1-32 . whenever there is a change of state, an interrupt (int) is asserted. after updating any registers, the apb interface control must clear the interrupt (int) by clearing the si bit of the control register. table 1-9 through table 1-13 on page 1-32 define status register code descriptions and subsequent action based on the four possible operating modes. table 1-7 ? status register paddr[4:0] register name type width reset value description 0x04 stat r 8 0xf8 status register; read-only value yields the current state of each i 2 c channel. table 1-8 ? status register bit fields bits name type field description 7:0 status r read-only status code. refer to following tables for code descriptions based on operating mode. table 1-9 ? status register ? master transmitter mode status code status data register action control register bits next action taken by i 2 c channel sta sto si aa 0x08 a start condition has been transmitted. load sla + w ? 0 0 ? sla + w wi ll be transmitted; ack will be received. 0x10 a repeated start condition has been transmitted. load sla + w ? 0 0 ? sla + w wi ll be transmitted; ack will be received. or load sla + r ? 0 0 ? sla + r will be transmitted; channel will be switched to mst/rec mode. 0x18 sla + w has been transmitted; ack has been received. load data byte 0 0 0 ? data byte will be transmitted; ack will be received. or no action 1 0 0 ? repeated start will be transmitted. or no action 0 1 0 ? stop condition will be transmitted; sto flag will be reset. or no action 1 1 0 ? stop condition followed by a start condition will be trans mitted; sto flag will be reset. notes: 1. sla = slave address 2. slv = slave 3. rec = receiver 4. trx = transmitter 5. sla + w = master sends slave address, then writes data to slave. 6. sla + r = master sends slave addr ess, then reads data from slave.
design description 22 corei2c v6.0 0x20 sla + w has been transmitted; nack has been received. load data byte 0 0 0 ? data byte will be transmitted; ack will be received. or no action 1 0 0 ? repeated start will be transmitted. or no action 0 1 0 ? stop condition will be transmitted; sto flag will be reset. or no action 1 1 0 ? stop condition followed by a start condition will be trans mitted; sto flag will be reset. 0x28 data byte in data register has been transmitted; ack has been received. load data byte 0 0 0 ? data byte will be transmitte d; ack bit will be received. or no action 1 0 0 ? repeated start will be transmitted. or no action 0 1 0 ? stop condition will be transmitted; sto flag will be reset. or no action 1 1 0 ? stop condition followed by a start condition will be trans mitted; sto flag will be reset. 0x30 data byte in data register has been transmitted; nack has been received. no action 1 0 0 ? repeated start will be transmitted. or no action 0 1 0 ? stop condition will be transmitted; sto flag will be reset. or no action 1 1 0 ? stop condition followed by a start condition will be trans mitted; sto flag will be reset. 0x38 arbitration lost in sla + r/w or data bytes. no action 0 0 0 ? the bus will be released; not-addressed slave mode will be entered. or no action 1 0 0 ? a start condition will be transmitted when the bus becomes free. table 1-9 ? status register ? master transmitter mode (continued) status code status data register action control register bits next action taken by i 2 c channel sta sto si aa notes: 1. sla = slave address 2. slv = slave 3. rec = receiver 4. trx = transmitter 5. sla + w = master sends slave address, then writes data to slave. 6. sla + r = master sends slave addr ess, then reads data from slave.
register map and descriptions corei2c v6.0 23 0xd0 smb_en = 1: smbus master reset has been activated. no action ? ? ? ? wait 35 ms for interrupt to be set, clear interrupt and proceed to 0xf8 state. only valid when smb_en = 1. 0xd8 ipmi_en = 1: 3 ms scl low time has been reached. no action ? ? 0 ? 3 ms scl low time has been reached. only valid when ipmi_en = 1. table 1-9 ? status register ? master transmitter mode (continued) status code status data register action control register bits next action taken by i 2 c channel sta sto si aa notes: 1. sla = slave address 2. slv = slave 3. rec = receiver 4. trx = transmitter 5. sla + w = master sends slave address, then writes data to slave. 6. sla + r = master sends slave addr ess, then reads data from slave.
design description 24 corei2c v6.0 table 1-10 ? status register ? master receiver mode status code status apb config. register action control register bits next action taken by i 2 c channel sta sto si aa 0x08 a start condition has been transmitted. load sla + r ? 0 0 ? sla + r will be transmitted; ack will be received. 0x10 a repeated start condition has been transmitted. load sla + r ? 0 0 ? sla + r will be transmitted; ack will be received. or load sla + w ? 0 0 ? sla + w will be transmitted; corei2c will be switched to mst/trx mode. 0x38 arbitration lost. no action 0 0 0 ? the bus will be released; corei2c will enter slave mode. or no action 1 0 0 ? a start condition will be transmitted when the bus becomes free. 0x40 sla + r has been transmitted; ack has been received. no action 0 0 0 0 data byte will be received; nack will be returned. or no action 0 0 0 1 data byte will be received; ack will be returned. 0x48 sla + r has been transmitted; nack has been received. no action 1 0 0 ? repeated start condition will be transmitted. or no action 0 1 0 ? stop condit ion will be transmitted; sto flag will be reset. or no action 1 1 0 ? stop condition followed by a start condition will be transmitted; sto flag will be reset. 0x50 data byte has been received; ack has been returned. read data byte 0 0 0 0 data byte will be received; nack will be returned. or read data byte 0 0 0 1 data byte will be received; ack will be returned. notes: 1. sla = slave address 2. slv = slave 3. rec = receiver 4. trx = transmitter 5. sla + w = master sends slave address, then writes data to slave. 6. sla + r = master sends slave addr ess, then reads data from slave.
register map and descriptions corei2c v6.0 25 0x58 data byte has been received; nack has been returned. read data byte 1 0 0 ? repeated start condition will be transmitted. or read data byte 0 1 0 ? stop condition will be transmitted; sto flag will be reset. or read data byte 1 1 0 ? stop condition followed by a start condition will be transmitted; sto flag will be reset. 0xd0 smb_en = 1: smbus master reset has been activated. no action ? ? 0 ? wait 35 ms for in terrupt to be set; clear interrupt and proceed to 0xf8 state. only valid when smb_en = 1. 0xd8 ipmi_en = 1: 3 ms scl low time has been reached. no action ? ? 0 ? 3 ms scl low time has been reached. only valid when ipmi_en = 1. table 1-10 ? status register ? master receiver mode (continued) status code status apb config. register action control register bits next action taken by i 2 c channel sta sto si aa notes: 1. sla = slave address 2. slv = slave 3. rec = receiver 4. trx = transmitter 5. sla + w = master sends slave address, then writes data to slave. 6. sla + r = master sends slave addr ess, then reads data from slave.
design description 26 corei2c v6.0 table 1-11 ? status register ? slave receiver mode status code status data register action control register bits next action taken by i 2 c channel sta sto si aa 0x60 own sla + w has been received; ack has been returned. no action ? 0 0 0 data byte will be received and nack will be returned. or no action ? 0 0 1 data byte will be received and ack will be returned. 0x68 arbitration lost in sla + r/w as master; own sla + w has been received, ack returned. no action ? 0 0 0 data byte will be received and nack will be returned. or no action ? 0 0 1 data byte will be received and ack will be returned. 0x70 general call address (00h) has been received; ack has been returned. no action ? 0 0 0 data byte will be received and nack will be returned. or no action ? 0 0 1 data byte will be received and ack will be returned. 0x78 arbitration lost in sla + r/w as master; general call address has been received, ack returned. no action ? 0 0 0 data byte will be received and nack will be returned. or no action ? 0 0 1 data byte will be received and ack will be returned. 0x80 previously addressed with own slv address; data has been received; ack returned. read data byte ? 0 0 0 data byte will be received and nack will be returned. or read data byte ? 0 0 1 data byte will be received and ack will be returned. notes: 1. sla = slave address 2. slv = slave 3. rec = receiver 4. trx = transmitter 5. sla + w = master sends slave address, then writes data to slave. 6. sla + r = master sends slave addr ess, then reads data from slave.
register map and descriptions corei2c v6.0 27 0x88 previously addressed with own sla; data byte has been received; nack returned read data byte 0 0 0 0 switched to not-addressed slv mode; no recognition of own sla or general call address. or read data byte 0 0 0 1 switched to not-addressed slv mode; own sla or general call address will be recognized. or read data byte 1 0 0 0 switched to not-addressed slv mode; no recognition of own sla or general call address; start condition will be transmitted when the bus becomes free. or read data byte 1 0 0 1 switched to not-addressed slv mode; own sla or general call address will be recognized; start condition will be transmitted when the bus becomes free. 0x90 previously addressed with general call address; data has been received; ack returned. read data byte ? 0 0 0 data by te will be received and nack will be returned or read data byte ? 0 0 1 data byte will be received and ack will be returned. table 1-11 ? status register ? slave re ceiver mode (continued) status code status data register action control register bits next action taken by i 2 c channel sta sto si aa notes: 1. sla = slave address 2. slv = slave 3. rec = receiver 4. trx = transmitter 5. sla + w = master sends slave address, then writes data to slave. 6. sla + r = master sends slave addr ess, then reads data from slave.
design description 28 corei2c v6.0 0x98 previously addressed with general call address; data has been received; nack returned. read data byte 0 0 0 0 switched to not-addressed slv mode; no recognition of own sla or general call address. or read data byte 0 0 0 1 switched to not-addressed slv mode; own sla or general call address will be recognized. or read data byte 1 0 0 0 switched to not-addressed slv mode; no recognition of own sla or general call address; start condition will be transmitted when the bus becomes free. or read data byte 1 0 0 1 switched to not-addressed slv mode; own sla or general call address will be recognized; start condition will be transmitted when the bus becomes free. 0xa0 a stop condition or repeated start condition has been received. no action 0 0 0 0 switched to not-addressed slv mode; no recognition of own sla or general call address. or no action 0 0 0 1 switched to not-addressed slv mode; own sla or general call address will be recognized. or no action 1 0 0 0 switched to not-addressed slv mode; no recognition of own sla or general call address; start condition will be transmitted when the bus becomes free. or no action 1 0 0 1 switched to not-addressed slv mode; own sla or general call address will be recognized; start condition will be transmitted when the bus becomes free. table 1-11 ? status register ? slave re ceiver mode (continued) status code status data register action control register bits next action taken by i 2 c channel sta sto si aa notes: 1. sla = slave address 2. slv = slave 3. rec = receiver 4. trx = transmitter 5. sla + w = master sends slave address, then writes data to slave. 6. sla + r = master sends slave addr ess, then reads data from slave.
register map and descriptions corei2c v6.0 29 0xd8 smb_en = 1: 25 ms scl low time has been reached; device must be reset. no action ? ? 0 ? slave must proceed to reset state by clearing the inte rrupt within 10 ms, according to smbus specification 2.0. only valid when smb_en = 1. 0xd8 ipmi_en = 1: 3 ms scl low time has been reached. no action ? ? 0 ? 3 ms scl low time has been reached. only valid when ipmi_en = 1. table 1-11 ? status register ? slave re ceiver mode (continued) status code status data register action control register bits next action taken by i 2 c channel sta sto si aa notes: 1. sla = slave address 2. slv = slave 3. rec = receiver 4. trx = transmitter 5. sla + w = master sends slave address, then writes data to slave. 6. sla + r = master sends slave addr ess, then reads data from slave.
design description 30 corei2c v6.0 table 1-12 ? status register ? slave transmitter mode status code status data register action control register bits next action taken by i 2 c channel sta sto si aa 0xa8 own sla + r has been received; ack has been returned load data byte ? 0 0 0 last data byte will be transmitted; ack will be received. or load data byte ? 0 0 1 data byte will be transmitted; ack will be received. 0xb0 arbitration lost in sla + r/w as master; own sla + r has been received; ack has been returned. load data byte ? 0 0 0 last data byte will be transmitted; ack will be received. or load data byte ? 0 0 1 data byte will be transmitted; ack will be received. 0xb8 data byte has been transmitted; ack has been received. load data byte ? 0 0 0 last data byte will be transmitted; ack will be received. or load data byte ? 0 0 1 data byte will be transmitted; ack will be received. 0xc0 data byte has been transmitted; nack has been received. no action 0 0 0 0 switched to not-addressed slv mode; no recognition of own sla or general call address. or no action 0 0 0 1 switched to not-addressed slv mode; own sla or general call address will be recognized. or no action 1 0 0 0 switched to not-addressed slv mode; no recognition of own sla or general call address; start condition will be transmitted when the bus becomes free. or no action 1 0 0 1 switched to not-addressed slv mode; own sla or general call address will be recognized; start condition will be transmitted when the bus becomes free. notes: 1. sla = slave address 2. slv = slave 3. rec = receiver 4. trx = transmitter 5. sla + w = master sends slave address, then writes data to slave. 6. sla + r = master sends slave addr ess, then reads data from slave.
register map and descriptions corei2c v6.0 31 0xc8 last data byte has transmitted; ack has received. no action 0 0 0 0 switched to not-addressed slv mode; no recognition of own sla or general call address. or no action 0 0 0 1 switched to not-addressed slv mode; own sla or general call address will be recognized. or no action 1 0 0 0 switched to not-addressed slv mode; no recognition of own sla or general call address; start condition will be transmitted when the bus becomes free. or no action 1 0 0 1 switched to not-addressed slv mode; own sla or general call address will be recognized; start condition will be transmitted when the bus becomes free. 0xa0 a stop condition or repeated start condition has been received. no action 0 0 0 0 switched to not-addressed slv mode; no recognition of own sla or general call address. or no action 0 0 0 1 switched to not-addressed slv mode; own sla or general call address will be recognized. or no action 1 0 0 0 switched to not-addressed slv mode; no recognition of own sla or general call address; start condition will be transmitted when the bus becomes free. or no action 1 0 0 1 switched to not-addressed slv mode; own sla or general call address will be recognized; start condition will be transmitted when the bus becomes free. table 1-12 ? status register ? slave transmitter mode (continued) status code status data register action control register bits next action taken by i 2 c channel sta sto si aa notes: 1. sla = slave address 2. slv = slave 3. rec = receiver 4. trx = transmitter 5. sla + w = master sends slave address, then writes data to slave. 6. sla + r = master sends slave addr ess, then reads data from slave.
design description 32 corei2c v6.0 0xd8 smb_en = 1: 25 ms scl low time has been reached; device must be reset. no action ? ? 0 ? slave must proceed to reset state by clearing the inte rrupt within 10 ms, according to smbus specification 2.0. only valid when smb_en = 1. 0xd8 ipmi_en = 1: 3 ms scl low time has been reached. no action ? ? 0 ? 3 ms scl low time has been reached. only valid when ipmi_en = 1. table 1-13 ? status register ? miscellaneous states status code status data register action control register bits next action taken by i 2 c channel sta sto si aa 0x38 arbitration lost no action 0 0 0 ? bus will be released. or no action 1 0 0 ? a start condition will be transmitted when the bus becomes free. 0xf8 no relevant state information available; si = 0 no action no action idle 0x00 bus error during mst or selected slave modes. no action 0 1 0 ? only the intern al hardware is affected in the mst or addressed slv modes. in all cases, the bus is re leased and the state switched in non-addressed slave mode. stop flag is reset. table 1-12 ? status register ? slave transmitter mode (continued) status code status data register action control register bits next action taken by i 2 c channel sta sto si aa notes: 1. sla = slave address 2. slv = slave 3. rec = receiver 4. trx = transmitter 5. sla + w = master sends slave address, then writes data to slave. 6. sla + r = master sends slave addr ess, then reads data from slave.
register map and descriptions corei2c v6.0 33 data register the data register ( table 1-14 ) contains a byte of serial data to be transmitted or a byte that has just been received. the apb controller can read fro m and write to this 8-bi t, directly addressable register while it is not in the proc ess of shifting a byte (i.e., afte r an interrupt has been generated). the bit description in table 1-15 is listed in both data context an d addressing context. data context is the 8-bit data format from msb to lsb. addressing context is based on a master sending an address call to a slave on the bu s, along with a direct ion bit (i.e., master tr ansmit data or receive data from a slave). table 1-14 ? data register paddr[4:0] register name type width reset value description 0x08 data r/w 8 0x00 data register; read/write data to/from the serial if. table 1-15 ? data register bit fields bits name type data context description addressing context description 7 sd7 r/w serial data bit 7 (msb ) serial address bit 6 (msb) 6 sd6 r/w serial data bit 6 serial address bit 5 5 sd5 r/w serial data bit 5 serial address bit 4 4 sd4 r/w serial data bit 4 serial address bit 3 3 sd3 r/w serial data bit 3 serial address bit 2 2 sd2 r/w serial data bit 2 serial address bit 1 1 sd1 r/w serial data bit 1 serial address bit 0 (lsb) 0 sd0 r/w serial data bit 0 (lsb) direction bit: 0 = write; 1 = read
design description 34 corei2c v6.0 slave0 address register the slave0 address register (addr0, table 1-16 and table 1-17 ) is a read/write directly accessible register. if the parameter fixed_slave0_addr_en is enabled, the regist er is read-only. table 1-16 ? slave0 address register paddr [4:0] register name type width reset value description 0x0c addr0 r/w 8 0x00 slave0 address register; contains the programmable slave0 address of all channels. note: the slave0 address register is a single register that is used in all channels. table 1-17 ? slave0 address register bit fields bits name type description 7 adr6 r/w own slave0 address bit 6 6 adr5 r/w own slave0 address bit 5 5 adr4 r/w own slave0 address bit 4 4 adr3 r/w own slave0 address bit 3 3 adr2 r/w own slave0 address bit 2 2 adr1 r/w own slave0 address bit 1 1 adr0 r/w own slave0 address bit 0 0 gc r/w general call address acknowledge. if the gc bit is set, the general call address is recognized; otherwise it is ignored.
register map and descriptions corei2c v6.0 35 optional smbus/ipmi register the smbus register contains specific smbus relate d functionality and is read- or write-able as defined in table 1-19 on page 1-35 . configuration register for smbu s timeout reset condition and for the optional smbus si gnals smbalert_n and smbsus_n. if ipmi mode is selected, then this register reduces to one enables/di sables 3 ms ipmi scl low timeout. table 1-18 ? smbus/ipmi register paddr[4:0] register name type width reset value description 0x10 smb r/w 8 0b01x1x000 smbus or ipmi register smbus context: configuration register for smbus timeouts and reset condit ion and for the optional smbus signals smbalert_n and smbsus_n. ipmi context: enable/disable ipmi scl low timeout table 1-19 ? smbus/ipmi register bit fields bits name type smbus context (smb_en = 1) ipmi context (ipmi_en = 1) 7 smbus_reset w writing a on e to this bit will fo rce the clock line low until 35 ms has been exceeded , thus resetting the entire bus as per the smbus sp ecification version 2.0. usage: when the channel is used as a host controller (master), the user can decide to reset the bus by holding the clock line low 35ms. slaves must react to this event and reset themselves. not used. 6 smbsus_no r/w r/w smbsus_no control bit; used in master/host mode to force other devices into power down / suspend mode. active low. smbsus_no and smbsus_ni ar e separate signals (not wired-and). if the corei2c is part of a host-controller, smbsus_no could be used as an output; if corei2c is a slave to a host-controller that has implemented smbsus_n, then only smbs us_ni?s status would be relevant. not used. 5 smbsus_ni r read-only statu s of smbsus_ni signal. smbsus_no and smbsus_ni ar e separate signals (not wired-and). if the corei2c is part of a host-controller, smbsus_no could be used as an output; if corei2c is a slave to a host-controller that has implemented smbsus_n, then only smbs us_ni?s status would be relevant. not used. 4 smbalert_no r/w read/write smbalert_no control bit; used in slave/device mode to forc e communication with the master/host. wired-and. not used. 3 smbalert_ni r read-only status of sm balert_ni signal. wired-and. not used.
design description 36 corei2c v6.0 2 smb_ipmi_en r/w 0: smbus timeouts and status logic disabled, i.e., standard i 2 c bus operation; 1: smbus timeouts an d status logic enabled. 0: ipmi timeout and status logic disabled, i.e., standard i 2 c bus operation; 1: ipmi timeout and status logic enabled. 1 smbsus_ie r/w 0: smbsus interrupt signal (smbs) disabled. 1: smbsus interrupt signal (smbs) enabled. not used. 0 smbalert_ie r/w 0: smbsus interrupt signal (smba) disabled. 1: smbsus interrupt signal (smba) enabled. not used. table 1-19 ? smbus/ipmi register bit fields bits name type smbus context (smb_en = 1) ipmi context (ipmi_en = 1)
register map and descriptions corei2c v6.0 37 optional slave1 address register the slave1 address register (addr1, table 1-20 and table 1-21 ) is an 8-bit read/write directly accessible register with two separate cont exts depending on parameter configuration. note: if the parameter fixed_slave1_addr_en is enabled, the register is read-only. table 1-20 ? slave1 address register paddr[4:0] register name type width reset value description 0x1c addr1 r/w 8 0x00 slave1 address re gister; contains the programmable slave1 address of all channels. when this slave1 address is enabled yet fixed, the register will have a r/w bit to enable/disab le slave1 comparisons. note: the slave1 address register is a single register that is used in all channels. table 1-21 ? slave1 address register bit fields bits name type enabled, apb accessible slave1 context (add_slave1_address_en = 1 and fixed_slave1_addr_en = 0) enabled, fixed slave1 context (add_slave1_address_en = 1 and fixed_slave1_addr_en = 1) 7 adr6 r/w own slave1 address bit 6 not used. 6 adr5 r/w own slave1 address bit 5 not used. 5 adr4 r/w own slave1 address bit 4 not used. 4 adr3 r/w own slave1 address bit 3 not used. 3 adr2 r/w own slave1 address bit 2 not used. 2 adr1 r/w own slave1 address bit 1 not used. 1 adr0 r/w own slave1 address bit 0 not used. 0 gc_or_enadr r/w general call address acknowledge. if the gc bit is set, the general call address is recognized; otherwise it is ignored. 1: enable the fi xed slave1 address comparisons. 0: disable slave1 address comparisons.

corei2c v6.0 39 2 ? tool flows corei2c is licensed in two ways. depending on your license tool fl ow, functionality may be limited. obfuscated complete rtl code is provided fo r the core, allowing the core to be instantiated with smartdesign. simulation, synthesis, and layout can be performed within libero ? integrated design environment (ide). the rtl code for the core is obfuscated 1 and some of the testbench source files are not provided; they are precompiled into th e compiled simulation library instead. rtl complete rtl source code is prov ided for the core and testbenches. smartdesign corei2c ( figure 2-1 ) is preinstalled in the smartdesign ip deployment design environment. the core can be configured using the configuration gui within smartdesign, as shown in figure 2-2 on page 2-40 . callouts to asso ciated parameters are shown in red. for information on using smartdesign to inst antiate and generate cores, refer to the using directcore in libero? ide user's guide . 1. obfuscated means the rtl source file s have had formatting and comments re moved, and all instance and net names have been replaced with random character sequences. figure 2-1 ? corei2c full i/o view
tool flows 40 corei2c v6.0 figure 2-2 ? corei2c smartdesign configuration with callouts to associated parameters i2c_num operating_mode smb_en ipmi_en frequency fixed_baud_rate fixed_baud_rate_value bclk_enabled fixed_slave0_addr_en fixed_slave0_addr_value add_slave1_addr_en fixed_slave1_addr_en fixed_slave1_addr_value glitchreg_num
simulation flows corei2c v6.0 41 simulation flows the user testbench fo r corei2c is included in all releases. to run simulations, select the user testbench flow wi thin smartdesign and click save & generate on the generate pane. the user testbench is selected through the core testbench configuration gui. when smartdesign generates the li bero ide project, it will install the user testbench files. to run the user testbench, set the design root to the corei2c instantiation in the libero ide design hierarchy pane and click the simulation icon in the libero ide design flow window. this will invoke modelsim ? and automatically run the simulation. user testbench as shown in figure 2-3 , two instantiations of the corei2c macro are connected to an i 2 c bus. the second corei2c instance is configured in multi-channel mode and uses the 13th channel. the top- level test bench ( tb_user_corei2c ) includes the open drain (wired -and) connections. the testbench utilizes simple apb read/write fu nction calls to initialize each module and send example transmit bytes from instance0 to instance1 across the i 2 c serial bus. after each transmission, apb read checks are performed to ve rify valid byte transfers. note: the user testbench does not import the user?s own configuration parameters; only a single suite of predefined parameters are tested, so me of which my be altered directly in the tb_user_corei2c.v or tb_user_corei2c.vhd file . . synthesis in libero ide: having set the design rout e appropriately, click the synthesis icon in libero ide. the synthesis window appears, displaying the synplicity ? project. set synplicity to use the verilog 2001 standard if verilog is being used. to run synthesis, select the run icon. place-and-route in libero ide having set the design route appropriately and run synthesis, click the layout icon in the libero ide to invoke designer. corei2c requires no special place-and-route settings. figure 2-3 ? corei2c user testbench corei2c corei2c open drain open drain open drain open drain apb read/write function calls vdd vdd apb read/write function calls user testbench: tb_user_corei2c scl sda

corei2c v6.0 43 3 ? example application and hints this chapter provides various hints to ease the process of implementation and integration of corei2c into your own design. software driver drivers for corei2c are available via the firmware catalog tool provided wi th libero ide. for more information about the fi rmware catalog, refer to the actel web site: www.actel.com/products/softwar e/firmwarecat/default.aspx . usage with cortex-m1 corei2c may be used with cort ex-m1, actel?s soft ip version of the popular arm7tdmi-s? microprocessor that has been optimized for the m1 fusion flash-based fpga devices. to create a design using cortex-m1, internal flash memory, and corei2c, yo u should use the smartdesign intellectual property de ployment platform (idp) software. refer to the smartdesign user?s guide on how to create your cortex-m1?based design. hints on i/o pad requirements the i 2 c, smbus, and pmbus specifications set minimum and maximum i/o buffer and pad requirements based on type of implementation. figure 3-1 ? example system using cortex-m1 with co rei2c in a two channel configuration
example application and hints 44 corei2c v6.0 c orei2c can be used for all these potential appl ications, as long as the i/o buffer/pads are configured to comply with the specific i 2 c or smbus requirements. typically, for 100 kbps operation, standard default i/o buffer values are okay. for 400 kbps operation however, tighter buffer constraints may be necessar y to fully conform to a given i 2 c/smbus/pmbus requirement. refer to electrical characterist ics for each specificatio n type to correctly program the i/o pads: i 2 c specifications at http://www.i2c-bus.org / smbus specifications at http://smbus.org/specs/ pmbus specifications at http://pmbus.org/specs.html hints on configuring wired-and bidirectional buffers in rtl for an example on how to connect the wi red-and bidirectional scl and sda outputs in a design, refer to the verilog tb_u ser_corei2c.v and/or the vhdl tb_u ser_corei2c.vhd rtl user testbench. hints on meeting smbus/pmbus timing requirements refer to the "serial interface" section on page 1-14 for specific pclk requirements necessary to adhere to smbus and pmbus specifications.
corei2c v6.0 45 4 ? list of document changes the following table lists critical changes that we re made in the current version of the document. previous version changes in current do cument version (50200090-5) page 50200090-4 (november 2009) the "core version" was updated to v6.0 and the "core overview" section was updated to include information about the multiple i 2 c channel configuration option. 5 the utilization tables were updated. 6 signals and parameters in the "design description" section were updated in text and figures for multiple i 2 c channel functionality. 11 figure 1-4 ? data read cycle was updated. 14 the "optional smbus/ipmi logic" section is new. 16 table 1-4 ? corei2c internal register address map was updated. 19 table 1-6 ? control register bit fields was updated for r/w properties. 20 table 1-16 ? slave0 address register was updated for r/w properties. 34 table 1-20 ? slave1 address register was updated for r/w properties. 37 the "obfuscated" section was updated for smartdesign. 39 figure 2-1 ? corei2c full i/o view is new and figure 2-2 ? corei2c smartdesign configuration with callouts to associated parameters was updated. 39 , 40 the "simulation flows" section was updated for smartdesign. 41 the "user testbench" section was updated for the multiple i 2 c channel configuration. 41 removed ordering information section n/a figure 3-1 ? example system using cort ex-m1 with corei2c in a two channel configuration was updated 43 50200090-3 the "core version" was updated to v5.0. text , figures, signal names, parameters/generics, and register maps and descriptions have been revised accordingly. n/a coremp7 references were removed and replaced with cortex-m1. n/a "ordering codes" have been included. 43 50200090-2 the corei2c handbook and coresmbus handbook have been condensed and combined into the current document. n/a 50200090-1 the ?supported device families? section was added. 5 the "apb interface" section was updated to include the cortex-m1 processor. 14 the ?use with core8051s? section was updated to change core8051 to core8051s. 34 50200090-0 the data transfer rate and the slave_en_only parameter for master receiver mode were updated in the "key features" section section. 5 figure 1-5 ? corei2c block diagram (single channel) was updated. 15 the first two paragraphs of the ?i2c serial interface? section were updated. 16
list of document changes 46 corei2c v6.0 figure 1-1 ? corei2c i/o signal diagram was updated to remo ve the bclk signal. 11 figure 1-3 ? data write cycle was updated to change the signal prdata to pwdata. 14 the second table note, which stated the clock rate frequency of 100 kbps should not be exceeded, was removed from table 1-5 ? control register . 20 previous version changes in current do cument version (50200090-5) page
corei2c v6.0 47 a ? product support actel backs its products with va rious support se rvices including custome r service, a customer technical support center, a web site, an ftp site, electronic mail, and worl dwide sales offices. this appendix contains information about contacti ng actel and using these support services. customer service contact customer service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization. from northeast and north central u.s.a., call 650.318.4480 from southeast and so uthwest u.s.a., call 650. 318.4480 from south central u.s.a., call 650.318.4434 from northwest u.s.a., call 650.318.4434 from canada, call 650.318.4480 from europe, call 650.318.4252 or +44 (0) 1276 401 500 from japan, call 650.318.4743 from the rest of the world, call 650.318.4743 fax, from anywhere in the world 650.318.8044 actel customer technical support center actel staffs its customer technical support cent er with highly skille d engineers who can help answer your hardware, software, and design questions. the customer technical support center spends a great deal of time creating application notes and answers to faqs. so, before you contact us, please visit our online resources. it is very likely we have already answered your questions. actel technical support visit the actel custome r support website ( www.actel.com/support/search/default.aspx ) for more information and support. many answers availa ble on the searchable web resource include diagrams, illustration s, and links to other resour ces on the actel web site. website you can browse a variety of te chnical and non-technical inform ation on actel?s home page, at www.actel.com . contacting the customer technical support center highly skilled engineers staff the technical support center from 7:00 a.m. to 6:00 p.m., pacific time, monday through friday. several ways of contacting the center follow: email you can communicate your technical questions to our email address and receive answers back by email, fax, or phone. also, if you have design pr oblems, you can email your design files to receive assistance. we constantly moni tor the email account throughout the day. when sending your request to us, please be sure to include yo ur full name, company name, and your contact information for effi cient processing of your request.
product support 48 corei2c v6.0 the technical support email address is tech@actel.com . phone our technical support center answer s all calls. the center retrieves in formation, such as your name, company name, phone number and yo ur question, and then issues a case number. the center then forwards the information to a queue where the firs t available application engineer receives the data and returns your call. the phone hours are from 7:00 a.m. to 6:00 p.m., pacif ic time, monday through friday. the technical support numbers are: 650.318.4460 800.262.1060 customers needing assistance outs ide the us time zones can either contact technical support via email (tech@actel.com) or contact a local sales office. sales office listings can be found at www.actel.com/company/ contact/default.aspx .
index corei2c v6.0 index a actel electronic mail 47 telephone 48 web-based technical support 47 website 47 address comparator 16 apb interface 14 arbitration logic 15 b buffers, bidirectional 44 buffers, wired-and 44 c channel pointer addressing 19 channels, i2c 12 configuration example 9 contacting actel customer service 47 electronic mail 47 telephone 48 web-based technical support 47 control register 20 coreabc 9 corei2c features 5 version 5 cortex-m1 9 example use 43 customer service 47 d data register 33 data transfer cycle 14 f filters input glitch 15 input spike 15 functional bloc k description 15 i i/o full view 39 i/o pad requirements 43 i/o signal descriptions 11 i2c channels 12 interfaces supported 5 ipmi logic 16 l layout 41 m modes, i2c operating 17 multiple channel configuration 5 o obfuscated 39 operation details 17 optional slave1 address register 37 optional smbus/ipmi register 35 p performance 6 place-and-route 41 port signals 11 product support 48 customer service 47 electronic mail 47 technical support 47 telephone 48 website 47 r read cycle 14 register map 19 rtl 39 s scl line 14 serial clock generator 16 serial interface 14 serial interface byte transfer 14 simulation flows 41 slave mode example 17 slave0 address register 34 smartdesign 39 smbus clock low reset example 18 temperature sensor slave 9 smbus logic 16 smbus reset 18 software driver 43 status register 21 master receiver mode 24 master transmitter mode 21 miscellaneous states 32 slave receiver mode 26 slave transmitter mode 30 synchronization logic 15
index corei2c v6.0 synthesis 41 t technical support 47 timing requirements 44 u utilization 6 v verilog parameters 12 vhdl generics 12 w web-based technical support 47 write cycle 14

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