? 2006 fairchild semiconductor corporation fds6982as r ev b fds6982as dual notebook power supply n-channel powertrench ? syncfet ? general description the fds6982as is designed to replace two single so- 8 mosfets and schottky diode in synchronous dc:dc power supplies that provide various peripheral voltages for notebook computers and other battery powered electronic devices . fds6982as contains two unique 30v, n-channel, logic level, powertrench mosfets designed to maximize power conversion efficiency. the high-side switch (q1) is designed with specific emphasis on reducing switching losses while the low-side switch (q2) is optimized to reduce conduction losses. q2 also includes an integrated schottky diode using fairchild?s monolithic syncfet technology. applications ? notebook features ? q2 : optimized to minimize conduction losses includes syncfet schottky body diode 8.6a, 30v r ds(on) max= 13.5m ? @ v gs = 10v r ds(on) max= 16.5m ? @ v gs = 4.5v ? low gate charge (21nc typical) ? q1 : optimized for low switching losses 6.3a, 30v r ds(on) max= 28 .0m ? @ v gs = 10v r ds(on) max= 35 .0m ? @ v gs = 4.5v ? low gate charge (11nc typical) s2 so-8 g2 s1 g1 d2 d2 d1 d1 4 3 2 1 5 6 7 8 q1 q2 absolute maximum ratings t a = 25c unless otherwise noted symbol parameter q2 q1 units v dss drain-source voltage 30 30 v v gss gate-source voltage 20 20 v i d drain current - continuous (note 1a) 8.6 6.3 a - pulsed 30 20 p d power dissipation for dual operation 2 w power dissipation for single operation (note 1a) 1.6 (note 1b) 1 (note 1c) 0.9 t j , t stg operating and storage junction temperature range ?55 to +150 c thermal characteristics r ja thermal resistance, junction-to-ambient (note 1a) 78 c/w r jc thermal resistance, junction-to-case (note 1) 40 c/w package marking and ordering information device marking device reel size tape width quantity fds6982as fds6982as 13? 12mm 2500 units fds6982as fds6982as_nl (note 4) 13? 12mm 2500 units fds6982as fds6982as_nf40 (note 5) 13? 12mm 2500 units fds6982as tm dece mber 2006
fds6982as rev b electrical characteristics t a = 25c unless otherwise noted symbol parameter test conditions type min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 1 ma v gs = 0 v, i d = 250 ua q2 q1 30 30 v ? bv dss ? t j breakdown voltage temperature coefficient i d = 1 ma, referenced to 25 c i d = 250 a, referenced to 25 c q2 q1 28 24 mv/ c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v q2 q1 500 1 a i gss gate-body leakage v gs = 20 v, v ds = 0 v q2 q1 100 na on characteristics (note 2) v gs(th) gate threshold voltage v ds = v gs , i d = 1 ma v ds = v gs , i d = 250 a q2 q1 1 1 1.4 1.9 3 3 v i d = 1 ma, referenced to 25 c q2 ?3.1 ? v gs(th) ? t j gate threshold voltage temperature coefficient i d = 250 ua, referenced to 25 c q1 ?4.3 mv/ c v gs = 10 v, i d = 8.6 a v gs = 10 v, i d = 8.6 a, t j = 125 c v gs = 4.5 v, i d = 7.5 a q2 11 16 13 13.5 20.0 16.5 r ds(on) static drain-source on-resistance v gs = 10 v, i d = 6.3 a v gs = 10 v, i d = 6.3 a, t j = 125 c v gs = 4.5 v, i d = 5.6 a q1 20 26 25 28 33 35 m ? i d(on) on-state drain current v gs = 10 v, v ds = 5 v q2 q1 30 20 a g fs forward transconductance v ds = 5 v, i d = 8.6 a v ds = 5 v, i d = 6.3 a q2 q1 32 19 s dynamic characteristics c iss input capacitance q2 q1 1250 610 pf c oss output capacitance q2 q1 410 180 pf c rss reverse transfer capacitance v ds = 10 v, v gs = 0 v, f = 1.0 mhz q2 q1 130 85 pf r g gate resistance v gs = 15mv, f = 1.0 mhz q2 q1 1.4 2.2 ? switching characteristics (note 2) t d(on) turn-on delay time q2 q1 9 10 18 20 ns t r turn-on rise time q2 q1 6 7 12 14 ns t d(off) turn-off delay time q2 q1 27 24 44 39 ns t f turn-off fall time v dd = 15 v, i d = 1 a, v gs = 10v, r gen = 6 ? q2 q1 11 3 20 6 ns t d(on) turn-on delay time q2 q1 12 12 22 22 ns t r turn-on rise time q2 q1 13 14 23 25 ns t d(off) turn-off delay time q2 q1 19 15 34 27 ns t f turn-off fall time v dd = 15 v, i d = 1 a, v gs = 4.5v, r gen = 6 ? q2 q1 10 5 20 10 ns fds6982 a s
fds6982as rev b electrical characteristics (continued) t a = 25c unless otherwise noted symbol parameter test conditions type min typ max units switching characteristics (note 2) q g (tot) total gate charge at vgs=10v q2 q1 21 11 30 15 nc q g total gate charge at vgs=5v q2 q1 12 6 16 9 nc q gs gate?source charge q2 q1 3.1 1.8 nc q gd gate?drain charge q2: v ds = 15 v, i d = 11.5a q1: v ds = 15 v, i d = 6.3a q2 q1 3.6 2.4 nc drain?source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current q2 q1 3.0 1.3 a t rr reverse recovery time 19 ns q rr reverse recovery charge i f = 11.5 a, d if /d t = 300 a/s (note 3) q2 12 nc t rr reverse recovery time 20 ns q rr reverse recovery charge i f = 6.3 a, d if /d t = 100 a/s (note 3) q1 9 nc v sd drain-source diode forward voltage v gs = 0 v, i s = 3 a (note 2) v gs = 0 v, i s = 6 a (note 2) v gs = 0 v, i s = 1.3 a (note 2) q2 q2 q1 0.5 0.6 0.8 0.7 1.0 1.2 v notes: 1. r ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r jc is guaranteed by design while r ca is determined by the user's board design. a) 78c/w when mounted on a 0.5in 2 pad of 2 oz copper b) 125c/w when mounted on a 0.02 in 2 pad of 2 oz copper c) 135c/w when mounted on a minimum pad. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0% 3. see ?syncfet schottky body diode characteristics? below. 4. fds6982as_nl is a lead free product. the fds6982as_nl marking will appear on the reel label. 5. fds6982as_nf40 is a lead free product. the fds6 982as_nf40 marking will appear on the reel label. fds6982 a s
fds6982as rev b typical characteristics: q2 0 10 20 30 00 . 511 . 52 v ds , drain-source voltage (v) i d , drain current (a) 2.5v 3.0v 4.5v v gs = 10v 3.5v 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 0 102030 i d , drain current (a) r ds(on) , normalized drain-source on-resistance v gs = 2.5v 3.5v 4.0v 4.5v 6.0v 10v 3.0v figure 1. on-region characteristics. fi gure 2. on-resistance variation with drain current and gate voltage. 0.6 0.8 1 1.2 1.4 -50-25 0 255075100125 t j , junction temperature ( o c) r ds(on) , normalized drain-source on-resistance i d = 8.6a v gs = 10v 0 0.01 0.02 0.03 0.04 0.05 24681 0 v gs , gate to source voltage (v) r ds(on) , on-resistance (ohm) i d = 4.3 a t a = 125 o c t a = 25 o c figure 3. on-resistance variation with temperature. figure 4. on-resistance variation with gate-to-source voltage. 0 5 10 15 20 25 30 11 . 522 . 533 . 5 v gs , gate to source voltage (v) i d , drain current (a) t a = 125 o c -55 o c v ds = 5v 25 o c 0.01 0.1 1 10 0 0.2 0.4 0.6 0.8 v sd , body diode forward voltage (v) i s , reverse drain current (a) t a = 125 o c 25 o c -55 o c v gs = 0v figure 5. transfer characteristics. figure 6. body diode forward voltage variation with source current and temperature. fds6982 a s
fds6982as rev b typical characteristics: q2 0 2 4 6 8 10 0 5 10 15 20 25 q g , gate charge (nc) v gs , gate-source voltage (v) i d = 8.6a v ds = 10v 15v 20v 0 400 800 1200 1600 2000 0 5 10 15 20 25 30 v ds , drain to source voltage (v) capacitance (pf) c iss c rss c oss f = 1mhz v gs = 0 v figure 7. gate charge characteristics. figure 8. capacitance characteristics. 0.01 0.1 1 10 100 0.1 1 10 100 v ds , drain-source voltage (v) i d , drain current (a) dc 10s 1s 100ms 100 s r ds(on) limit v gs = 10v single pulse r ja = 135 o c/w t a = 25 o c 10ms 1ms 0 10 20 30 40 50 0.001 0.01 0.1 1 10 100 1000 t 1 , time (sec) p(pk), peak transient power (w) single pulse r ja = 135c/w t a = 25c figure 9. maximum safe operating ar ea. figure 10. single pulse maximum power dissipation. 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t 1 , time (sec) r(t), normalized effective transient thermal resistance r ja (t) = r(t) * r ja r ja = 135c/w t j - t a = p * r ja (t) duty cycle, d = t 1 / t 2 p (p k ) t 1 t 2 single pulse 0.01 0.02 0.05 0.1 0.2 d = 0.5 figure 11. transient thermal response curve. thermal characterization performed using the conditions described in note 1c. transient thermal response will cha nge depending on the circuit board design. fds6982as
fds6982as rev b typical characteristics q1 0 4 8 12 16 20 012 v ds , drain-source voltage (v) i d , drain current (a) 3.5v 3.0v v gs = 10v 4.0v 4.5v 6.0v 0.6 1 1.4 1.8 2.2 2.6 0 5 10 15 20 i d , drain current (a) r ds(on) , normalized drain-source on-resistance v gs = 3.0v 4.5v 4.0v 6.0v 10v 3.5v figure 12. on-region characteristics. fi gure 13. on-resistance variation with drain current and gate voltage. 0.6 0.8 1 1.2 1.4 1.6 -50 -25 0 25 50 75 100 125 150 t j , junction temperature ( o c) r ds(on) , normalized drain-source on-resistance i d = 6.3a v gs = 10v 0 0.02 0.04 0.06 0.08 0.1 24681 0 v gs , gate to source voltage (v) r ds(on) , on-resistance (ohm) i d = 3.15 a t a = 125 o c t a = 25 o c figure 14. on-resistance variation with temperature. figure 15. on-resistance variation with gate-to-source voltage. 0 5 10 15 20 11 . 522 . 533 . 5 v gs , gate to source voltage (v) i d , drain current (a) t a = 125 o c -55 o c v ds = 5v 25 o c 0.0001 0.001 0.01 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 v sd , body diode forward voltage (v) i s , reverse drain current (a) t a = 125 o c 25 o c -55 o c v gs = 0v figure 16. transfer characteristics. figure 17. body diode forward voltage variation with source current and temperature. fds6982 a s
fds6982as rev b typical characteristics q1 0 2 4 6 8 10 03691 2 q g , gate charge (nc) v gs , gate-source voltage (v) i d = 6.3a v ds = 10v 15v 20v 0 200 400 600 800 0 5 10 15 20 v ds , drain to source voltage (v) capacitance (pf) c iss c rss c oss f = 1mhz v gs = 0 v figure 18. gate charge characteristics. figure 19. capacitance characteristics. 0.01 0.1 1 10 100 0.1 1 10 100 v ds , drain-source voltage (v) i d , drain current (a) dc 10s 1s 100ms 100 s r ds(on) limit v gs = 10v single pulse r ja = 135 o c/w t a = 25 o c 10ms 1ms 0 10 20 30 40 50 0.001 0.01 0.1 1 10 100 1000 t 1 , time (sec) p(pk), peak transient power (w) single pulse r ja = 135c/w t a = 25c figure 20. maximum safe operating ar ea. figure 21. single pulse maximum power dissipation. 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t 1 , time (sec) r(t), normalized effective transient thermal resistance r ja (t) = r(t) * r ja r ja = 135c/w t j - t a = p * r ja (t) duty cycle, d = t 1 / t 2 p (p k ) t 1 t 2 single pulse 0.01 0.02 0.05 0.1 0.2 d = 0.5 figure 22. transient thermal response curve. thermal characterization performed using the conditions described in note 1c. transient thermal response will change depending on the circuit board design. fds6982 a s
fds6982as rev b typical characteristics (continued) syncfet schottky body diode characteristics fairchild?s syncfet process embeds a schottky diode in parallel with powertrench mosfet. this diode exhibits similar characteristics to a discrete external schottky diode in parallel with a mosfet. figure 23 shows the reverse recovery characteristic of the fds6982as. figure 23. fds6982as syncfet body diode reverse recovery characteristic. for comparison purposes, figure 24 shows the reverse recovery characteristics of the body diode of an equivalent size mosfet produced without syncfet (fds6982). figure 24. non-syncfet (fds6982) body diode reverse recovery characteristic. schottky barrier diodes exhibi t significant leakage at high temperature and high reverse voltage. this will increase the power in the device. 0.000001 0.00001 0.0001 0.001 0.01 0.1 0 5 10 15 20 25 30 v ds , reverse voltage (v) i dss , reverse leakage current (a) t a = 125 o c t a = 25 o c t a = 100 o c figure 25. syncfet body diode reverse leakage versus drain-source voltage and temperature fds6982 a s current: 1.6a/div time: 10ns/div time: 10ns/div current: 1.6a/div
fds6982as rev b typical characteristics v ds l figure 26. unclamped inductive load test circ uit figure 27. unclamped inductive waveforms figure 31. switching time waveforms r ge dut v gs i as 0.01? v dd + - tp 0v vary t p to obtain required peak i as v gs t av t p i as v ds v dd bv dss figure 30. switching time test circuit v ds r l r gen dut v dd v gs pulse width 1 s dut y cy cle 0. 1 % v gs + - t r t f t d(on) t d(off ) t on t off pulse width 10% 10% 90% 10% 90% 50% 90% 50% 0v 0v v gs v ds figure 28. gate charge test circuit figure 29. gate charge waveform v gs q gs q gd q g(tot) 10v charge, (nc) dut v dd v gs i g(ref + - + - same type as drain current 1 f 10 f 10v 50k ? fds6982as
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