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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com ? ? ? ? xrt71d00 e3/ds3/sts-1 jitter attenuator september 2001 rev. 1.2.0 general description the xrt71d00 is a single channel, single chip jitter attenuator, that meets the jitter transfer characteristic requirements specified in the etsi tbr-24, bellcore gr-499-core and gr-253-core standards. in addition, the xrt71d00 also meets the output jit- ter and wander specifications described in the ansi t1.105.03b 1997, bellcore gr-253-core and gr- 499-core standards. features ? meets e3/ds3/sts-1 jitter transfer requirements ? no external components required ? compliant with the jitter transfer characteristic requirements specified in itu g.751, g.752, and g.755 for e3 applications ? meets jitter transfer characteristic requirement as specified by etsi tbr24 (for e3 applications). ? meets the output jitter and wander specifications described in ansi t1.105.03b, bellcore gr-253- core and bellcore gr-499-core standards. ? selectable buffer size of 16 and 32 bits ? jitter attenuator can be disabled ? available in a 32 pin tqfp package. ? single 3.3v or 5.0v supply. ? operates over - 40 0 c to 85 0 c temperature range. applications ? e3/ds3 access equipment. ? dslams f igure 1. b lock d iagram of the xrt71d00 host/hw reset e3/ds3 16/32 bit fifo microprocessor serial interface timing control block / phase locked loop write clock read clock rrclk rrpos rrneg fl dja rclk clkes rpos rneg bws ict cs sdi sdo sclk mclk
xrt71d00 ? ? ? ? e3/ds3/sts-1 jitter attenuator rev. 1.2.0 2 ordering information f igure 2. p in o ut of the xrt71d00 (32 l ead tfqp p ackage ) nc rneg rclk gnd mclk gnd vdd sts-1 1 8 9 32 25 17 16 24 nc rrneg rrclk gnd ict reset dja/sdo nc nc rpos vdd e3 / ds3 / cs ch_addr_0 vdd rrpos nc nc clkes/sdi fss/clk host/hw nc fl bws/ch_addr_1 nc p art n umber p ackage o perating t emperature r ange xrt71d00iq 32 lead tqfp -40 0 c to +85 0 c
? ? ? ? xrt71d00 e3/ds3/sts-1 jitter attenuator rev. 1.2.0 i table of contents general description .................................................................................................. 1 f eatures .............................................................................................................................. ..................... 1 a pplications .............................................................................................................................. ............... 1 figure 1. block diagram of the xrt71d00 ...................................................................................... ..... 1 figure 2. pin out of the xrt71d00 (32 lead tfqp package) ............................................................. 2 ordering information ............................................................................................... 2 table of contents.............................................................................................................. ........................ i pin descriptions ........................................................................................................... 3 electrical characteristics ................................................................................... 9 ac e lectrical c haracteristics ............................................................................................................. 9 figure 3. input/output timing ................................................................................................ ................ 9 m icroprocessor s erial i nterface t iming ( see f igure 4 ) ................................................................. 10 figure 4. timing diagram for the microprocessor serial interface .................................................. 10 system description ................................................................................................... 12 figure 5. illustration of the xrt71d00 (configured to operate in the hardware mode) ............ 12 figure 6. illustration of the xrt71d00 (configured to operate in the host mode) ...................... 13 1.0 the jitter attenuator pll ................................................................................................. ..................... 13 1.1 t he j itter t ransfer c haracteristics of the j itter a ttenuator pll ..............................................................13 1.2 d efinition of j itter ............................................................................................................................... .................13 1.3 j itter t ransfer c haracteristics .........................................................................................................................13 figure 7. category 1 ds3 jitter transfer mask ................................................................................ .. 14 1.3.1 jitter tolerance: ........................................................................................................ ....................................14 1.3.2 jitter generation:....................................................................................................... ....................................14 1.3.3 jitter attenuation: ...................................................................................................... ....................................14 1.4 xrt71d00 j ittter t ransfer c haracteristics ....................................................................................................14 t able 1: xrt71d00 j itter t ransfer f unction .................................................................................. 15 t able 2: xrt71d00 j itter t ransfer f unction .................................................................................. 16 figure 8. ds3 jitter transfer characteristics ................................................................................ ..... 17 figure 9. e3 jitter transfer characteristics ................................................................................. ....... 17 figure 10. sts-1 jitter transfer characteristics ............................................................................. ... 18 t able 3: xrt71d00 m aximum j itter t olerance ................................................................................. 19 t able 4: xrt71d00 m aximum j itter t olerance ................................................................................. 20 2.0 operating mode ............................................................................................................ .......................... 21 2.1 h ardware m ode ............................................................................................................................... ......................21 t able 5: h ardware m ode p in f unctions ............................................................................................. 21 2.1.1 host mode: .............................................................................................................. .....................................21 t able 6: a ddress and b it f ormats of the c ommand r egisters ...................................................... 21 3.0 microprocessor serial interface ........................................................................................... ................. 21 3.1 s erial i nterface o peration ............................................................................................................................... ...21 3.1.1 bit descriptions ......................................................................................................... ....................................21 3.2 r ead o peration ............................................................................................................................... ......................22 3.3 w rite o peration ............................................................................................................................... .....................22 figure 11. microprocessor serial interface data structure ............................................................... 22 3.4 s implified i nterface o ption ............................................................................................................................... ...22 figure 12. timing diagram for the microprocessor serial interface ................................................ 23 package information ............................................................................................... 24 32 lead tqfp package dimensions ............................................................................................. 2 4 revisions ..................................................................................................................... .. 25 ordering information .......................................................................................................... ......... 25
xrt71d00 ? ? ? ? e3/ds3/sts-1 jitter attenuator rev. 1.2.0 3 pin descriptions pin description p in #n ame t ype d escription 1 nc *** this pin is not connected internally 2 rneg i receive negative data (jittery) input the input jittery negative data is sampled either on the rising or falling edge of rclk depending on the setting of clkes (pin 10). this data will ultimately be output via the rrneg output pin. if clkes is high, then rneg will be sampled on the falling edge of rclk. if clkes is low, then rpos will be sampled on the rising edge of rclk. this pin is typically tied to the rneg output pin of the liu. n otes : 1. for jitter attenuator applications, this pin is typically connected to the rneg output pin of the corresponding liu ic. 2. the user should tie this input pin to gnd for sonet de-synchronization and single-rail jitter attenuator applications. 3 rclk i receive clock (jittery) input the user is expected to supply the jittery clock signal (e.g., the clock signal that needs to be smoothed) to this input pin. for jitter attenuation applications: the user should connect the recovered line clock (rclk) output signal (of the ds3, e3 or sts-1 liu ic) to this input pin. for sonet de-synchronizer applications: the user should connect the receive ds3 output clock signal (of the oc-n to ds3 mapper/de-mapper ic) to this input pin. the xrt71d00 device will use this clock signal to latch the data, residing on the rpos and rneg input pins, into the chip. if the clkes input pin (or bit-field) is high, then the xrt71d00 device will sample the data on the rpos and rneg input pins, on the falling edge of the rclk clock signal. if the clkes input pin (or bit-field) is low, then the xrt71d00 device will sample the data on the rpos and rneg input pins, on the rising edge of the rclk clock sig- nal. 4 gnd *** digital ground 5 mclk i master clock input. this input pin functions as the reference clock for the internal pll. the user is expected to apply a 44.736mhz+/-20ppm (for ds3 applications), 34.368mhz+/- 20ppm (for e3 applications) or a 51.84mhz+/- 20ppm (for sts-1 applications) to this input pin. this clock must be continuous and jitter free with duty cycle between 30 to 70%. 6 gnd *** analog ground 7 vdd *** analog positive supply : 3.3v or 5.0v 5%
? ? ? ? xrt71d00 e3/ds3/sts-1 jitter attenuator rev. 1.2.0 4 8 sts-1 i sonet sts-1 mode select: this pin along with the e3/ds3* select pin (pin 29) configures the xrt71d00 either in e3, ds3 or sts-1 mode. a table relating the setting of these two input pins to the operating modee of the xrt71d00 device is given below: sts-1 e3/ds3* xrt71d00 operating mode 0 0 ds3 (44.736 mhz) 0 1 e3 (34.368 mhz) 1 0 sts-1 (51.84 mhz) 1 1 e3 (34.368 mhz) n otes : 1. for sonet de-synchronization applications, the user should configure the xrt71d00 device to operate in the ds3 mode. 2. this input pin is active only in the hardware mode 3. this pin contains an internal 50 k ohm pull-up resistor. 9 nc *** this pin is not connected internally pin description p in #n ame t ype d escription
xrt71d00 ? ? ? ? e3/ds3/sts-1 jitter attenuator rev. 1.2.0 5 10 clkes/(sdi) i clock edge select input/serial data input pin. the function of this pin depends on whether xrt71d00 is configured in harware or host mode. hardware modeclock edge select input this input pin permits the user to do the following. 1. to configure the xrt71d00 device to latch the data, on the rpos and rneg input pin, upon either the rising or falling edge of the rclk input signal. 2. to configure the xrt71d00 device to update the data, which is output via the rrpos and rrneg pins, upon either the rising or falling edge of the rrclk output signal. setting this input pin low configures the xrt71d00 device to do the following. 1. sample and latch the rpos and rneg input signals upon the rising edge of the rclk input signal. 2. update the data, output via the rrpos and rrneg output pins, upon the falling edge of the rrclk output signal. conversely, setting this input pin high configures the xrt71d00 device to do the fol- lowing. 1. same and latch the rpos and rneg input signals upon the falling edge of the rclk input signal. 2. update the data, output via the rrpos and rrneg output pins, upon the rising edge of the rrclk output signal. host modeserial data input when the microprocessor/microcontroller is executing a read operation, with the microprocessor serial interface (of the xrt71d00 device) then it is expected to apply the address value (of the target command register) to this input pin, in a serial man- ner. when the microprocessor/microcontroller is executing a write operation, with the microprocessor serial interface, then it is expected to do the following. 1. apply the address value (of the target command register) to this input pin, in a serial manner. 2. apply the data (to be written into the target command register) to this input pin. n ote : a detailed description on how to read and write data into the command regis- ters of the xrt71d00 device (via the microprocessor serial interface) is presented in section _. 11 fss/(sclk) i fifo size select input/serial clock input. the function of this input pin depends on whether xrt71d00 is configured in hard- ware or host mode. hardware modefifo size select input this input pin permits the user to select the operating depth of the on-chip fifo. when high: selects 32 bits fifo. when low: selects 16 bits fifo. n ote : for sonet de-synchronizer applications, the user is advised to configure the fifo depth to 32 bits. host modemicroprocessor serial interface clock signal this signal will be used to sample the data, on the sdi pin, on the rising edge of this signal. additionally, during read operations, the microprocessor serial interface will update the sdo output on the falling edge of this signal. pin description p in #n ame t ype d escription
? ? ? ? xrt71d00 e3/ds3/sts-1 jitter attenuator rev. 1.2.0 6 12 host/hw i host/hardware mode select: this input pin permits the user to configure the xrt71d00 device to operate in either the host or hardware mode. setting this input pin high configures the xrt71d00 device to operate in the host mode (e.g., enables the microprocessor serial interface). in this mode, the user is expected to configure the xrt71d00 device by writing data into the on-chip com- mand registers via the microprocessor serial interface. as a consequence, when the xrt71d00 device is operating in the host mode, then it will ignore the states of many of the discrete input pins. setting this input pin low configures the xrt71d00 device to operate in the hard- ware mode. when the xrt71d00 device is operating in the hardware mode, then the microprocessor serial interface will be disabled. in this mode, many of the external input control pins will be functional. 13 nc *** this pin is not connected internally. 14 fl o fifo limit alarm output indicator. this output pin is driven high whenever the internal fifo comes within two-bits of being completely full or completely depleted. when this output pin is asserted, it will be driven high for at least one rrclk cycle period. 15 bws/ ch_addr_1 i bandwidth select input/channel addr_1 assignment input. the function of this input pin depends on whether xrt71d00 is configured in host or hardware mode. hardware modebandwidth select input: this input pin permits the user to configure the pll (within the xrt71d00 device) to operate with either a wide or narrow bandwidth. setting this input pin high configures the pll to operate with a wide bandwidth conversely, setting this input pin low configures the pll to operate with a narrow- bandwidth. host modechannel_addr_1 assignment input: this input pin, along with pin 28 permits the user to assign a channel address to the xrt71d00 device. n ote : a detailed discussion on channel assignment is presented in section _. 16 nc *** this pin is not connected internally. 17 nc *** this pin is not connected internally. pin description p in #n ame t ype d escription
xrt71d00 ? ? ? ? e3/ds3/sts-1 jitter attenuator rev. 1.2.0 7 18 dja/ (sdo) i/(o) disable jitter attenuator input/serial data output pin: the function of this pin depends on whether xrt71d00 is configured in host or hard- ware mode. hardware modedisable jitter attenuator: this input pin permits the user to enable or disable the jitter attenuator function within the xrt71d00 device. setting this input pin high disables the jitter attenuator pll. whenever the jitter attenuator pll is disabled, the the signals/data which are applied to the rpos, rneg and rclk input pins will pass through to the rrpos, rrneg and rrclk output pins without any jitter attenuation. setting this input pin low enables the jitter attenuator pll. whenever the jitter attenuator pll is enabled then the signals/data which are applied to the rpos, rneg and rclk output pins will be routed to the narrow-band pll for jitter reduction. the outputs of the narrow-band pll will be routed to the rrpos, rrneg and rrclk output pins. host modeserial data output: this pin will serially output the contents of the specified command register, during read operations. the data, on this pin, will be updated on the falling edge of the sclk input signal. this pin will be tri-stated upon completion of data transfer. 19 reset i reset input. (active-low) a high-to-low transition will re-center and clear the contents of the internal fifo, and will clear the contents of the command registers (for host mode operation). resetting this pin may corrupt data within the device. n ote : for normal operation, this pin should be pulled high. 20 ict i in circuit testing input. active low. with this pin tied to ground, all output pins will be in high impedance mode for in-circuit- testing. n ote : for normal operation this input pin should be pulled high. 21 gnd *** digital ground: 22 rrclk o receive output (de-jittered) clock. this pin outputs the smoothed (e.g., de-jittered) 34.368mhz, 44.736mhz or 51.84mhz clock signal. further, this clock signal is also used to clock out the contents of the recovered data (via the rrpos and rrneg output pins). if the clkes pin (or bit-field) is low, then the xrt71d00 device will output data, via the rrpos and rrneg output pins, upon the falling edge of this clock signal. if the clkes pin (or bit-field) is high, then the xrt71d00 device will output data, via the rrpos and rrneg output pins, upon the rising edge of this clock signal. 23 rrneg o receive negative data (de-jittered) output. data which is input via the rneg input pin will be updated on the rising or falling edge of rrclk, depending upon the state of the clkes input pin (or bit-field setting). 24 nc *** this pin is not connected internally. 25 nc *** this pin is not connected internally. pin description p in #n ame t ype d escription
? ? ? ? xrt71d00 e3/ds3/sts-1 jitter attenuator rev. 1.2.0 8 26 rrpos o receive positive data (de-jittered) output. data which is input via the rpos input pin will be updated on the rising or falling edge of rrclk (see pin 9), depending upon the state of the clkes input pin (or bit-field setting). 27 vdd *** digital positive supply voltage : 3.3v or 5.0v 5% 28 ch_addr_0 i channel addr_0 assignment input. this input pin, along with pin 15 permits the user to assign a channel address to the xrt71d00. n otes : 1. a detailed discussion on channel assignment is presented in section _. 2. this input pin is only active whenever the xrt71d00 device has been config- ured to operate in the host mode. 29 e3/ds3 (cs ) i e3/ds3 select input/chip select input: the function of this pin depends on whether the xrt71d00 is configured in host or hardware mode. hardware modee3/ds3* select input : this pin along with the sts-1 mode select pin (pin 8) selects the operating mode. a table relating the settings of these two input pins to the operatintg mode of the xrt71d00 device is given below.: sts-1 e3/ds3* xrt71d00 operating mode 0 0 ds3 (44.736 mhz) 0 1 e3 (34.368 mhz) 1 0 sts-1 (51.84 mhz) 1 1 e3 (34.368 mhz) n ote : for sonet de-synchronization applications, the user should configure the xrt71d00 device to operate in the ds3 mode. host modechip select input: the local microprocessor must assert this input pin (e.g., set it to 0) in order to enable communication with the xrt71d00 device, via the microprocessor serial interface. 30 vdd *** digital positive supply voltage : 3.3v or 5.0v 5% 31 rpos i receive positive data (jittery) input. data that is input on this pin is sampled on either the rising or falling edge of rclk depending on the setting of the clkes pin (pin 10). this data will ultimately be output via the rrpos output pin. if clkes is high, then rpos will be sampled on the falling edge of rclk. if clkes is low, then rpos will be sampled on the rising edge of rclk. n ote : for jitter attenuation applications, this pin is typically connected to the rpos output pin of the corresponding liu ic. 32 nc *** this pin is not connected internally. pin description p in #n ame t ype d escription
xrt71d00 ? ? ? ? e3/ds3/sts-1 jitter attenuator rev. 1.2.0 9 electrical characteristics ac electrical characteristics s ymbol p arameter m in t yp m ax u nits . mclk duty cycle 30 50 70 % mclk frequency e3 34.368 mhz mclk frequency ds3 44.736 mhz mclk frequency sts-1 51.84 mhz rclk duty cycle 30 50 70 % rclk frequency (e3,ds3 or sts-1) -400 0 400 ppm rclk rise/fall time e3 ds3 sts-1 11.6 8.96 7.68 ns ns ns tsu rpos/rneg to rclk rise time setup 3 2 ns th rpos/rneg to rclk rising hold time 3 2 ns td rrpos/rrneg delay from rrclk rising 3 5 ns te rrpos/rrneg delay from rrclk falling 3 5 ns f igure 3. i nput /o utput t iming t h t su t d t e t su t h rclk rclk rpos/rneg rpos/rneg rclk rpos/rneg rpos/rneg rclk clkes = 0 clkes = 1
? ? ? ? xrt71d00 e3/ds3/sts-1 jitter attenuator rev. 1.2.0 10 microprocessor serial interface timing ( see figure 4 ) s ymbol p arameter m in t yp m ax u nits . t21 cs low to rising edge of sclk setup time 50 ns t22 sclk to cs hold time 20 ns t23 sdi to rising edge of sclk setup time 50 ns t24 sdi to rising edge of sclk hold time 50 ns t25 sclk low time 240 ns t26 sclk high time 240 ns t27 sclk period 500 ns t28 sclk to cs hold time 50 ns t29 cs inactive time 250 ns t30 falling edge of sclk to sdo valid time 200 ns t31 falling edge of sclk to sdo invalid time 100 ns t32 falling edge of sclk, or rising edge of cs to high z 100 ns f igure 4. t iming d iagram for the m icroprocessor s erial i nterface sdi r/w a1 a0 cs sclk cs sclk sdi sdo d0 d1 d2 d7 t22 t21 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 hi-z hi-z
xrt71d00 ? ? ? ? e3/ds3/sts-1 jitter attenuator rev. 1.2.0 11 dc electrical characteristics (ta = 25 0c, vdd = 3.3 v 5 % unless otherwise specified) p arameter s ymbol m in t yp m ax u nits power supply voltage vdd 3.135 3.3 3.465 v input high voltage vih 2.0 5.25 v input low voltage v il -0.5 0.8 v output high voltage @ ioh=-5ma voh 2.4 v output low voltage @ iol=5ma vol 0.4 v supply current ( e3) icc 25 40 ma supply current ( ds3 ) icc 30 45 ma supply current ( sts-1) icc 35 50 input leakage current(except input pins with pull-up resistor. il 10 m a input capacitance ci 5.0 pf output load capacitance c l 25 pf dc electrical characteristics (ta = 25 0c, vdd = 5.0 v 5 % unless otherwise specified) p arameter s ymbol m in t yp m ax u nits power supply voltage vdd 4.75 5.0 5.25 v input high voltage vih 2.0 5.25 v input low voltage v il -0.5 0.8 v output high voltage @ ioh=-5ma voh 2.4 v output low voltage @ iol=5ma vol 0.4 v supply current ( e3) icc 35 50 ma supply current ( ds3 ) icc 45 60 ma supply current ( sts-1) icc 50 65 input leakage current(except input pins with pull-up resistor. il 10 m a input capacitance ci 5.0 pf output load capacitance c l 25 pf a bsolute m aximum r atings : supply range -0.5 v to + 6.0 v esd rating > 2000 v on all pins operating temperature -40 0 c to +85 0 c storage temperature -65 c to + 150 c
? ? ? ? xrt71d00 e3/ds3/sts-1 jitter attenuator rev. 1.2.0 12 system description the xrt71d00 is a fully integrated and self-contained ds3, e3 and sts-1 jitter attenuator ic which was de- signed to function as either a jitter attenuator or as a clock smoother within sonet de-synchronizer ap- plications. more specifically, the xrt71d00 device was de- signed to do the following. 1. to attenuate the jitter (of the incoming clock and data) such that the users system will comply with the following jitter transfer characteristic require- ments. ? etsi tbr-24 (for e3 applications) ? itu-t g.751 (for e3 applications) ? itu-t g.752 (for e3 applications) ? itu-t g.755 (for e3 applications) ? bellcore gr-499-core (category i to category ii interface jitter transfer characteristic require- ments for ds3 applications). ? bellcore gr-253-core (for sonet sts-1 appli- cations) 2. to receive the gapped 51.84mhz clock and data signals, from an oc-n to ds3 mapper/de-map- per ic; and to smooth these signals to an un- gapped 44.736mhz clock and data signals. this particular application is often referred to as a sonet de-synchronizer application. in this application, the smoothed rrclk and rrpos signals could (potentially) be routed to a ds3 liu ic, for transmission to a remote terminal equip- ment, over coaxial cable. in addition, the xrt71d00 also meets both the map- ping and pointer adjustment jitter generation crite- ria for both category i and category ii interfaces as specified in bellcore gr-253. the xrt71d00 also meets the ds3 wander specifi- cation that apply to sonet and asynchronous inter- faces as specified in the ansi t1.105.03b 1997 stan- dard. figure 5 presents a simple block diagram of the xrt71d00 device, when it is configured to operate in the hardware mode. likewise figure 6 presents a simple block diagram of the xrt71d00 device, when it is configured to operate in the host mode. f igure 5. i llustration of the xrt71d00 ( configured to operate in the h ardware m ode ) 16/32 bit fifo timing control block / phase locked loop write clock read clock rrclk rrpos rrneg fl dja rclk clkes rpos rneg bws ict mclk jittery clock smoothed clock fss host/hw reset e3/ds3
xrt71d00 ? ? ? ? e3/ds3/sts-1 jitter attenuator rev. 1.2.0 13 the xrt71d00 ds3/e3/sts-1 jitter attenuator ic consists of the following functional blocks: ? jitter attenuator phase locked loop(pll) ? timing control ? 2-channel 16/32 bit fifo. ? microprocessor serial interface 1.0 the jitter attenuator pll the jitter attenuator pll is a narrow-band pll that accepts a jittery clock signal via the rclk input pin. the jitter attenuator pll locks onto the rclk input signal and synthesizes a same-rate signal. as the jitter attenuator pll synthesizes this signal, it elimi- nates much of the jitter that exists within the rclk in- put signal. the resulting smoothed clock signal is then output via the rrclk output signal. 1.1 t he j itter t ransfer c haracteristics of the j itter a ttenuator pll the jitter transfer characteristics of the xrt71d00 device is ultimately dictated by the jitter transfer characteristics of the jitter attenuator pll. the jitter transfer characteristics of the jitter attenuator pll is dictated by the following variables. 1. the operating mode/data rate of the xrt71d00 device. 2. the setting of the bws (bandwidth select) input pin or bit-field. 1.2 d efinition of j itter one of the most important and least understood mea- sures of clock performance is jitter. the international telecommunication union defines jitter as short term variations of the significant instants of a digita signal from their ideal positions in time. jitter can occur due to any of the following: 1) imperfect timing recovery circuit in the system 2) cross-talk noise 3) inter-symbol interference/signal distortion 1.3 j itter t ransfer c haracteristics the primary purpose of jitter transfer requirements is to prevent performance degradations by limiting the accummulation of jitter through the system such that it does not exceed the network interface jitter require- ments. thus, it is more important that a system meet the jitter transfer criteria for relatively high input jitter amplitudes. the jitter transferred through the system must be under the jitter mask for any input jitter ampli- tude within the range as shown in figure 7 f igure 6. i llustration of the xrt71d00 ( configured to operate in the h ost m ode ) host/hw reset 16/32 bit fifo microprocessor serial interface timing control block / phase locked loop write clock read clock rrclk rrpos rrneg fl rclk rpos rneg ict cs sdi sdo sclk mclk smoothed clock jittery clock
? ? ? ? xrt71d00 e3/ds3/sts-1 jitter attenuator rev. 1.2.0 14 1.3.1 jitter tolerance: the jitter tolerance in the network element is defined as the maximum amount of jitter in the incoming sig- nal that it can receive in an error-freemanner. 1.3.2 jitter generation: jitter generation is defined in section 7.3.3 of gr- 499-core. jitter generation criteria exists for both category i and ii interfaces, which consist of map- ping and pointer adjustment jitter generation. mapping jitter is the sum of the intrinsic payload map- ping jitter and the jitter that is generated as a result of the bit stuffing mechnisms used in all of the asynchro- nous dsn mapping into sts spe. 1.3.3 jitter attenuation: a digital jitter attenuation loop combined with the fifo provides jitter attenuation. the jitter attenuator requires no external components except for the refer- ence clock. data is clocked into the fifo with the associated clock signal (tclk or rclk) and clocked out of the fifo with the dejittered clock and data. when the fifo is within 2 bits of being completely full, the fifo limit (fl) will be set. in figure 5 and figure 6, this de-jittered clock is la- beled smoothed clock. this smoothed clock is now used to read out the recovered data from the 16/32 bit fifo. this smoothed clock will also be output to the terminal equipment via the rrclk output pin. likewise, the smoothed recovered data will output to the terminal equipment via the rrpos and rrneg output pins. the xrt71d00 device is designed to work as a com- panion device with xrt73l00 (sts-1/ds3/e3) line interface unit. etsi tbr24 specifies the maximum output jitter in loop timing must be no more than 0.4uipp when mea- sured between 100hz to 800khzwith upto 1.5ui input jitter at 100hz. this means a jitter attenuator with bandwidth less than 100hz is required to be compli- ant with the standard. itu g.751 is another applica- tion where low bandwidth jitter attenuator is needed to smooth the gapped clock output in the de-multi- plexer system. 1.4 xrt71d00 j ittter t ransfer c haracteris - tics table 1 and table 2 summarizes the results of jitter transfer characteristics testing, performed on the f igure 7. c ategory 1 ds3 j itter t ransfer m ask 0.1 jitter gain (db) acceptable range 40 frequency (hz) slope = -20 db/decade
xrt71d00 ? ? ? ? e3/ds3/sts-1 jitter attenuator rev. 1.2.0 15 xrt71d00. figure 8, figure 9 and figure 10 are graphs of the measure jitter transferr function of the xrt71d00. table 3 and table 4 summarize the re- sults of jitter tolerance testing, performed on the xrt71d00. t able 1: xrt71d00 j itter t ransfer f unction a pplication ds3 e3 bws l ow h igh l ow h igh l ow h igh l ow h igh i nput j itter 1ui pp 10ui pp 1ui pp 10ui pp f req . (hz) jitter gain (db) jitter gain (db) 5 0.02 -0.33 0.36 0.06 0.44 0.37 0.83 0.04 10 -0.10 -0.10 -0.30 -0.01 -0.15 0.20 -0.22 -0.02 20 -2.04 -0.24 -2.24 -0.13 -3.16 0.35 -3.24 -0.32 30 -3.63 -0.35 -4.33 -0.36 -5.51 0.05 -5.93 -0.73 40 -5.98 -0.53 -6.16 -0.72 -7.68 -0.68 -7.99 -1.24 50 -7.55 -1.00 -7.82 -1.12 -10.36 -1.15 -9.61 -1.85 60 -9.57 -1.46 -9.17 -1.66 -12.50 -2.53 -11.27 -2.45 80 -12.54 -2.25 -11.28 -2.64 -15.20 -3.56 -13.59 -3.76 100 -14.67 -3.07 -13.36 -3.52 -16.22 -4.69 -15.51 -5.02 125 -16.67 -3.88 -14.91 -4.76 -17.38 -5.78 -17.07 -6.50 150 -17.32 -5.74 -16.78 -5.89 -19.45 -7.43 -18.75 -7.74 200 -18.77 -7.75 -18.96 -7.90 -20.36 -10.71 -21.11 -9.94 300 -21.43 -12.04 -21.81 -10.89 -22.96 -13.58 -24.46 -13.23 500 -22.22 -16.74 -26.09 -14.98 -23.78 -17.66 -28.84 -17.16 >1000 -25.42 -21.13 -33.44 -20.66 -23.51 -20.96 -35.77 -23.35
? ? ? ? xrt71d00 e3/ds3/sts-1 jitter attenuator rev. 1.2.0 16 t able 2: xrt71d00 j itter t ransfer f unction a pplication sts-1 bws l ow h igh l ow h igh i nput j itter 1ui pp 10ui pp f req . (hz) jitter gain (db) 10 -0.92 -0.60 0.71 -0.15 20 -1.71 -0.14 -1.05. -0.17 30 -4.22 -1.03 -3.06 -0.24 40 -5.66 -1.09 -4.81 -0.61 50 -7.08 -1.23 -6.36 -0.97 60 -8.37 -1.54 -7.86 -1.30 80 -10.69 -2.55 -9.97 -2.02 100 -12.28 -3.44 -11.87 -2.91 125 -14.00 -4.29 -13.62 -4.02 150 -15.27 -5.04 -15.20 -5.01 200 -17.36 -6.77 -17.74 -6.93 300 -19.79 -9.25 -21.22 -9.94 500 -21.75 -13.20 -25.77 -14.06 1000 -24.18 -17.93 -32.92 -19.78 2000 -25.34 -21.29 -41.89 -25.25 5000 -27.14 -24.28 -45.57 -36.25
xrt71d00 ? ? ? ? e3/ds3/sts-1 jitter attenuator rev. 1.2.0 17 f igure 8. ds3 j itter t ransfer c haracteristics ds3 jitter transfer -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 100 1000 frequency (hz) jitter gain (db) 1uipp-lo 1uipp-hi 10uipp-lo 10uipp-hi ds3 mask cat2 f igure 9. e3 j itter t ransfer c haracteristics e3 jitter transfer -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 100 1000 jitter frequency (hz) jitter gain (db ) 1uipp-lo 1uipp-hi 10uipp-lo 10uipp-hi e3 mask
? ? ? ? xrt71d00 e3/ds3/sts-1 jitter attenuator rev. 1.2.0 18 f igure 10. sts-1 j itter t ransfer c haracteristics sts-1 jitter transfer -50 -40 -30 -20 -10 0 10 10 100 1,000 10,000 frequency (hz) jitter gain (db ) 1uipp - lo 1uipp - hi 10uipp - lo 10uipp - hi sts-1 mask
xrt71d00 ? ? ? ? e3/ds3/sts-1 jitter attenuator rev. 1.2.0 19 t able 3: xrt71d00 m aximum j itter t olerance a pplicatio n ds3 e3 bws l ow h igh l ow h igh l ow h igh l ow h igh f ifo s ize 16 32 16 32 f req . (hz) ui ( peak to peak )ui ( peak to peak ) 10 34.313 >64 >64 >64 26.689 >64 53.313 >64 20 21.439 >64 43.188 >64 18.564 52.188 37.438 >64 30 18.314 46.313 36.813 >64 16.689 36.688 33.938 >64 40 16.939 36.188 34.313 >64 16.064 29.314 32.688 58.438 50 16.314 30.314 33.188 60.313 15.689 25.064 32.063 50.438 60 16.064 26.689 32.563 53.188 15.564 22.564 31.689 45.438 80 15.689 22.314 31.814 44.813 15.314 19.689 31.314 39.688 100 15.439 20.064 31.439 40.434 15.314 18.064 31.189 36.813 125 15.439 18.439 31.314 37.313 15.189 17.064 31.064 34.813 150 15.314 17.564 31.189 35.438 15.189 16.564 31.064 33.688 200 15.314 16.464 31.064 33.563 15.189 15.939 30.939 32.438 300 15.189 15.814 30.939 32.063 15.064 15.564 30.939 31.564 500 15.189 15.439 30.939 31.314 15.064 15.314 30.939 31.189 >1000 15.0189 15.189 30.939 30.939 15.189 15.189 30.939 30.939
? ? ? ? xrt71d00 e3/ds3/sts-1 jitter attenuator rev. 1.2.0 20 t able 4: xrt71d00 m aximum j itter t olerance a pplicatio n sts-1 bws l ow h igh l ow h igh f ifo s ize 16 32 f req . (hz) ui ( peak to peak ) 10 38.939 >64.00 >64.00 >64.00 20 22.689 >64.00 44.938 >64.00 30 18.939 53.688 37.688 >64.00 40 17.439 41.563 34.938 >64.00 50 16.814 34.438 33.688 >64.00 60 16.314 29.939 32.938 59.063 80 15.939 24.689 32.188 48.938 100 15.814 21.814 31.814 43.438 125 15.689 19.814 31.564 39.438 150 15.564 18.564 31.439 37.063 200 15.564 17.314 31.314 34.688 300 15.439 16.314 31.189 32.813 500 15.439 15.814 31.189 31.689 1000 15.439 15.564 31.189 31.314 2000 15.439 15.439 31.189 31.189 3000 15.439 15.439 26.189 26.189 5000 15.439 15.439 16.189 16.189
xrt71d00 ? ? ? ? e3/ds3/sts-1 jitter attenuator rev. 1.2.0 21 2.0 operating mode 2.1 h ardware m ode the host/hw pin (pin 12) is used to select the oper- ating mode of the xrt71d00. in hardware mode (connect this pin to ground), the serial processor in- terface is disabled and hardwired pins are used to control configuration and report status. 2.1.1 host mode: in host mode ( connect the host/hw pin to vdd), the serial port interface pins are used to control con- figuration and status report. in this mode, serial inter- face pins : sdi, sdo, sclk and cs are used. a listing of these command registers, their address- es, and their bit-formats are listed below in table 6. 3.0 microprocessor serial interface the serial interface for the xrt71d00 and xrt73l00 e3/ds3/sts-1 liu are the same, which makes it easy to configure both the xrt71d00 and the liu with a single cs , sdi, sdo and sclk input and out- put pins. 3.1 s erial i nterface o peration . serial interface data structure and timings are provid- ed in figure 11 and figure 12 respectively. the clock signal is provided to the sclk and the cs is asserted for 50 ns prior to the first rising edge of the sclk. 3.1.1 bit descriptions 3.1.1.1 bit 1r/w (read/write) bit this bit will be clocked into the sdi input, on the first rising edge of sclk (after cs has been asserted). this bit indicates whether the current operation is a read or write operation. a 1 in this bit specifies a read operation, a 0 in this bit specifies a write operation. 3.1.1.2 bits 2 through 6 the five (5) bit address values (labeled a0, a1, a2 ,a3, and a4) the next four rising edges of the sclk signal will clock in the 5-bit address value for this particular read (or write) operation. the address selects the command register for reading data from, or writing data to. the address bits to the sdi input pin is applied in ascend- ing order with the lsb (least significant bit) first. bit 7---a5 a5 must be set to 0, as shown in figure 11. bit 8a6 t able 5: h ardware m ode p in f unctions p in #p in n ame h ardware m ode f unction 10 clkes/(sdi) clkes 11 fss/(sclk) fss 15 bws/ch_addr_1 bws 18 dja/(sdo) dja 28 ch_addr_0 none 29 e3/ds3 /(cs )e3/ds3 t able 6: a ddress and b it f ormats of the c ommand r egisters a ddr c ommand r egister c h _a ddr _1 c h _a ddr _0 t ype d7 d6 d5 d4 d3 d2 d1 d0 0x06 cr6 0 0 r/w *** *** sts-1 e3/ds3 dja bws clkes fss 0x07 cr7 0 0 ro *** *** *** *** *** *** *** fl 0x0e cr14 0 1 r/w *** *** sts-1 e3/ds3 dja bws clkes fss 0x0f cr15 0 1 ro *** *** *** *** *** *** *** fl 0x16 cr22 1 0 r/w *** *** sts-1 e3/ds3 dja bws clkes fss 0x17 cr22 1 0 ro *** *** *** *** *** *** *** fl
? ? ? ? xrt71d00 e3/ds3/sts-1 jitter attenuator rev. 1.2.0 22 the value of a6 is a dont care. once these first 8 bits have been written into the seri- al interface, the subsequent action depends upon whether the current operation is a read or write operation. 3.2 r ead o peration once the last address bit (a4) has been clocked into the sdi input, the read operation will proceed through an idle period, lasting three sclk periods. on the falling edge of sclk cycle #8 (see figure 11) the serial data output signal (sdo) becomes active. at this point the user can begin reading the data con- tents of the addressed command register (at ad- dress [a4, a3, a2, a1, a0]) via the sdo output pin. the serial interface will output this eight bit data word (d0 through d7) in ascending order (with the lsb first), on the falling edges of the sclk . the data (on the sdo output pin) is stable for reading on the very next rising edge of the sclk . 3.3 w rite o peration once the last address bit (a4) has been clocked into the sdi input, the write operation will proceed through an idle period, lasting three sclk periods. pri- or to the rising edge of sclk cycle #9 , the eight bit data word is applied to sdi input. data on sdi is latched on the rising edge of sclk. n otes : 1. a5 is always 0. 2. r/w = 1 for read operations 3. r/w = 0 for write operations 4. denotes a dont care value (shaded areas) 3.4 s implified i nterface o ption the user can simplify the design of the circuitry con- necting to the microprocessor serial interface by ty- ing both the sdo and sdi pins together, and reading data from and/or writing data to this combined sig- nal. this simplification is possible because only one f igure 11. m icroprocessor s erial i nterface d ata s tructure d0 d1 d2 d7 d6 d5 d4 d3 high z sdo a0 d0 r/w d1 a6 0 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 sdi 12345678910111213141516 sclk cs high z
xrt71d00 ? ? ? ? e3/ds3/sts-1 jitter attenuator rev. 1.2.0 23 of these signals are active at any given time. the in- active signal will be tri-stated. f igure 12. t iming d iagram for the m icroprocessor s erial i nterface sdi r/w a1 a0 cs sclk cs sclk sdi sdo d0 d1 d2 d7 t22 t21 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 hi-z hi-z
? ? ? ? xrt71d00 e3/ds3/sts-1 jitter attenuator rev. 1.2.0 24 package information 32 lead tqfp package dimensions
? ? ? ? xrt71d00 e3/ds3/sts-1 jitter attenuator rev. 1.2.0 25 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no represen- tation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys- tem or to significantly affect its safety or effectiveness. products are not authorized for use in such applica- tions unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corpo- ration is adequately protected under the circumstances. copyright 2001 exar corporation datasheet september 2001. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revisions rev. 1.0.1 to 1.1.0 pin 8 changed from internal pull-up resistor to pull-down resistor, removed the prelim- inary designation. edited electrical tables. rev. 1.2.0 removed reference to sts-1 to ds3 desyncronizer. added jitter transfer graphs, figures 8, 9 and 10. ordering information p art n umber p ackage o perating t emperature r ange xrt71d00iq 32 lead tqfp -40 0 c to +85 0 c

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