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publication# 19716 rev. a amendment /0 issue date: march 1995. www: 5/4/95 this document contains information on a product under development at advanced micro devices, inc. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. advanced micro devices AM29202 low-cost risc microcontroller with ieee-1284-compliant parallel interface advance information ? distinctive characteristics completely integrated system for cost-sensitive embedded applications requiring high performance full 32-bit risc architecture offers faster instruction execution and higher performance. e 32-bit instruction/data bus e 22-bit address bus e 192 general-purpose registers e fully pipelined, three-address instruction architecture e 104-mbyte address space e 12-, 16-, and 20-mhz operating frequencies e 16 vax mips sustained at 20 mhz glueless system interfaces with on-chip wait state control lower total system cost. e rom controller supports four banks of rom, each separately programmable for 8-, 16-, or 32-bit-wide interface. e dram controller supports four banks of dram, each separately programmable for 16- or 32-bit-wide interface. e 2-port peripheral interface adapter (pia) two-channel dma controller (one external) with queued reload for internal peripherals on-chip timer and interrupt controller ieee std 1284-1994-compliant parallel port interface (peripheral-side only) supports fast bidirectional data transfers. e compatibility, nibble, byte, and ecp modes e supports microsoft ? windows ? printing system bidirectional bit serializer/deserializer for direct connection to raster input and output devices 12-line programmable i/o port (8 lines interruptible) dram page-mode support improves memory access time. on-chip dram mapping reduces memory requirements. advanced debugging support e ieee std 1149.1-1990-compliant standard test access port and boundary scan architec- ture (jtag) for testing system hardware e instruction tracing e uart serial port software and hardware development tools widely available from amd ? and fusion29k ? partners binary compatibility with all 29k ? family of risc microcontrollers and microprocessors 132-pin plastic quad flat pack (pqfp) package general description the AM29202 ? risc microcontroller is a highly inte- grated, 32-bit embedded processor implemented in com- plementary metal-oxide semiconductor (cmos) technology. based on the 29k architecture, the AM29202 microcontroller is part of a growing family of risc micro- controllers, which includes the am29200 ? and am29205 ? microcontrollers, along with the high-perfor- mance am29240 ? , am29245 ? , and am29243 ? risc microcontrollers. a feature summary of the am29200 risc microcontroller family is included in table 1. with its 32-bit instruction and data bus, the AM29202 mi- crocontroller is functionally very similar to an am29200 microcontroller, operating with a reduced pin count and fewer peripherals. the low-cost AM29202 microcon- troller is well-suited for cost-sensitive embedded ap- plications requiring the enhanced performance of a 32-bit instruction/data bus and an ieee-1284-compliant parallel port interface. the AM29202 microcontroller in- corporates a complete set of system facilities commonly found in printing, imaging, graphics, and other em- bedded applications. the AM29202 microcontroller meets the common re- quirements of embedded applications such as laser printers, imaging applications, graphics processing, in- dustrial control, and general purpose applications re- quiring high performance in a compact design. specific applications include products based on microsoft's win- dows printing system, such as personal and workgroup 600-dpi laser printers and midrange inkjet printers, as well as scanners and multifunction peripherals, among others.
amd a d v a n c e i n f o r m a t i o n 2 AM29202 risc microcontroller AM29202 microcontroller block diagram dack interrupts dram space rom memory serial port parallel port controller dma controller programmable interrupt dram controller timer/counter i/o port controller serializer/ deserializer rom controller pia controller peripherals 22232 pia chip selects address bus instruction/data bus 4 4 2 12 2 4/4 rom chip selects serial data printer/scanner video i/o 10 2 parallel port control/status lines dreq 5 3 clock/ lines control jtag memclk am29000 ? cpu rom ras /cas customer service amd's customer service network includes u.s. offices, international offices, and a customer training center. ex- pert technical assistance is available from amd's world- wide staff of field application engineers and factory support staff. hotline, e-mail, and bulletin board support for answers to technical questions, amd provides a toll- free number for direct access to our engineering support staff. for overseas customers, the easiest way to reach the engineering support staff with your questions is via fax with a short description of your question. amd 29k family customers also receive technical support through electronic mail. this worldwide service is avail- able to 29k family product users via the international in- ternet e-mail service. also available is the amd bulletin board service, which provides the latest 29k family product information, including technical information and data on upcoming product releases. engineering support staff (800) 292-9263, ext. 2 toll-free for u.s. 0031-11-1163 toll-free for japan (512) 602-4118 direct dial worldwide 44-(0)256-811101 u.k. and europe hotline (512) 602-5031 fax epd.support@amd.com e-mail bulletin board (800) 292-9263, ext. 1 toll-free for u.s. (512) 602-7604 direct dial worldwide documentation and literature a simple phone call gets you free 29k family informa- tion, such as data books, user's manuals, data sheets, application notes, the fusion29k partner solutions catalog and newsletter, and other literature. interna- tionally, contact your local amd sales office for com- plete 29k family literature. literature request (800) 292-9263, ext. 3 toll-free for u.s. (512) 602-5651 direct dial worldwide (512) 602-7639 fax for u.s. (800) 222-9323, option 1 amd facts-on-demand ? fax information service toll-free for u.s.
amd a d v a n c e i n f o r m a t i o n 3 AM29202 risc microcontroller ordering information standard products amd standard products are available in several packages and operating ranges. valid order numbers are formed by a combination of the elements below. AM29202 12 c temperature range package type k = 132-lead plastic quad flat pack (pqb132) speed option device number/description AM29202 risc microcontroller valid combinations AM2920212 12 = 12.5 mhz 16 = 16.67 mhz 20 = 20 mhz k \w shipping option \w = trimmed and formed valid combinations valid combinations list configurations planned to be supported in volume. consult the local amd sales office to confirm availability of specific valid combinations, and check on newly released combinations. AM2920220 c = commercial (t c =0 c to +85 c) kc\w AM2920216
amd a d v a n c e i n f o r m a t i o n 4 AM29202 risc microcontroller table 1. product comparisoneam29200 microcontroller family feature am29205 controller AM29202 controller am29200 controller am29245 controller am29240 controller am29243 controller instruction cache e e e 4 kbytes 4 kbytes 4 kbytes data cache e e e e 2 kbytes 2 kbytes cache associativity e e e 2-way 2-way 2-way integer multiplier software software software software 32 x 32-bit 32 x 32-bit memory management unit (mmu) e e e 1 tlb 16 entry 1 tlb 16 entry 2 tlbs 32 entry data bus width internal external 32 bits 16 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits rom interface banks width rom size (max/bank) boot-up rom width burst-mode access 3 8, 16 bits 4 mbytes 16 bits not supported 4 8, 16, 32 bits 4 mbytes 8, 16, 32 bits not supported 4 8, 16, 32 bits 16 mbytes 8, 16, 32 bits supported 4 8, 16, 32 bits 16 mbytes 8, 16, 32 bits supported 4 8, 16, 32 bits 16 mbytes 8, 16, 32 bits supported 4 8, 16, 32 bits 16 mbytes 8, 16, 32 bits supported dram interface banks width size: 32-bit mode size: 16-bit mode video dram access cycles initial/burst dram parity 4 16 bits only e 8 mbytes/bank not supported 3/2 no 4 16, 32 bits 16 mbytes/bank 8 mbytes/bank not supported 3/2 no 4 16, 32 bits 16 mbytes/bank 8 mbytes/bank supported 3/2 no 4 16, 32 bits 16 mbytes/bank 8 mbytes/bank supported 2/1 no 4 16, 32 bits 16 mbytes/bank 8 mbytes/bank supported 2/1 no 4 16, 32 bits 16 mbytes/bank 8 mbytes/bank not supported 2/1 yes on-chip dma width (ext. peripherals) total number of channels externally controlled external master access external master burst external terminate signal 8, 16 bits 2 1 no no no 8, 16, 32 bits 2 1 no no no 8, 16, 32 bits 2 2 yes no yes 8, 16, 32 bits 2 2 yes yes yes 8, 16, 32 bits 4 4 yes yes yes 8, 16, 32 bits 4 4 yes yes yes double-frequency cpu option no no no no yes yes low voltage operation no no no yes yes yes peripheral interface adapter (pia) pia ports data width min. cycles access 2 8, 16 bits 3 2 8, 16, 32 bits 3 6 8, 16, 32 bits 3 6 8, 16, 32 bits 1 6 8, 16, 32 bits 1 6 8, 16, 32 bits 1 programmable i/o port (pio) signals signals programmable for interrupt generation 8 8 12 8 16 8 16 8 16 8 16 8 serial ports ports dsr /dtr 1 port pio signals 1 port pio signals 1 port supported 1 port supported 2 ports 1 port supported 2 ports 1 port supported interrupt controller external interrupt pins external trap and warn pins 2 0 2 0 4 3 4 3 4 3 4 3 parallel port controller 32-bit transfer ieee-1284 interface yes no no yes yes yes yes yes no yes yes no yes yes no yes yes no jtag debug support no yes yes yes yes yes serializer/deserializer yes yes yes yes yes no pin count and package 100 pqfp 132 pqfp 168 pqfp 196 pqfp 196 pqfp 196 pqfp voltage v cc i/o tolerance 5 v 5 v 5 v 5 v 5 v 5 v 3.3 v or 5 v 5 v 3.3 v or 5 v 5 v 3.3 v or 5 v 5 v processor clock rate 12, 16 mhz 12, 16, 20 mhz 16, 20 mhz 16 mhz 20, 25, 33 mhz 20, 25, 33 mhz
amd a d v a n c e i n f o r m a t i o n 5 AM29202 risc microcontroller related amd products 29k family devices part no. description am29000 32-bit risc microprocessor am29005 ? low-cost 32-bit risc microprocessor with no mmu and no branch target cache am29030 ? 32-bit risc microprocessor with 8-kbyte instruction cache am29035 ? 32-bit risc microprocessor with 4-kbyte instruction cache am29040 ? 32-bit risc microprocessor with 8-kbyte instruction cache and 4-kbyte data cache am29050 ? 32-bit risc microprocessor with on-chip floating point unit am29200 ? 32-bit risc microcontroller am29205 ? low-cost 32-bit risc microcontroller am29240 ? 32-bit risc microcontroller with 4-kbyte instruction cache and 2-kbyte data cache am29243 ? 32-bit data risc microcontroller with instruction and data caches and dram parity am29245 ? low-cost 32-bit risc microcontroller with 4-kbyte instruction cache 29k family development support products contact your local amd representative for information on the complete set of development support tools. the following software and hardware development products are available on several hosts: optimizing compilers for common high-level languages assembler and utility packages source- and assembly-level software debuggers target-resident development monitors simulators execution boards third-party development support products the fusion29k program of partnerships for application solutions provides the user with a vast array of products designed to meet critical time-to-market needs. prod- ucts and solutions available from the amd fusion29k partners include silicon products software generation and debug tools hardware development tools board level products laser printer solutions networking and communication solutions multiuser, kernel, and real-time operating systems graphics solutions manufacturing support custom software consulting, support, and training
amd a d v a n c e i n f o r m a t i o n 6 AM29202 risc microcontroller table of contents distinctive characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general description 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AM29202 microcontroller block diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . customer service 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ordering information 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . am29200 microcontroller family comparison 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . related amd products 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29k family development support products 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . third-party development support products 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . key features and benefits 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ieee-1284-compliant advanced parallel interface 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . windows printing system compatibility 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . complete set of common system peripherals 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . performance overview 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . debugging and testing 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . complete development and support environment 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin information connection diagram 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pqfp pin designations (sorted by pin number) 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pqfp pin designations (sorted by pin name) 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . logic symbol 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin descriptions 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional differences 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . advanced parallel interface 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory map changes 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin changes for the AM29202 microcontroller 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rom controller 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rom control register (rmct, address 80000000) 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dram controller 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dram control register (drct, address 80000008) 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . refresh control changes 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral interface adapter (pia) 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pia control register 0/1 (pict0/1, address 80000020/24) 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dma controller 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dma0 control register (dmct0, address 80000030) 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dma0 address register (dmad0, address 80000034) 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dma1 control register (dmct1, address 80000040) 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . programmable i/o port 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pio control register (poct, address 800000d0) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pio input register (pin, address 800000d4) 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pio output register (pout, address 800000d8) 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pio output enable register (poen, address 800000dc) 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
amd a d v a n c e i n f o r m a t i o n 7 AM29202 risc microcontroller serial port 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . serial port control register (spct, address 80000080) 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . serial port status register (spst, address 80000084) 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interrupts and traps 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . current processor status register (cps, register 2) 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interrupt control register (ict, address 80000028) 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vector numbers 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sequencing of interrupts and traps 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . exception reporting and restarting 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . debugging and testing 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . main data path 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ieee-1284-compliant advanced parallel interface 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . upgrading hardware and software 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . minimal system design 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . overview 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . communication modes 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external signals 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dedicated signal lines 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mode-allocated pio lines 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . software-driven status lines 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . registers 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . advanced parallel control register (apct, address 800000a0) 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . advanced parallel status register (apst, address 800000a4) 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . advanced parallel interrupt mask register (apim, address 800000a8) 52 . . . . . . . . . . . . . . . . . . . . . . advanced parallel interrupt status register (apis, address 800000ac) 53 . . . . . . . . . . . . . . . . . . . . . advanced parallel data register (apdt, address 800000b0) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . initialization 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . controlling the parallel port interface 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . polling 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interrupts 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . data transfers 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . data interrupts 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dma 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . full-word transfer 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ecp commands 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . using full-word transfer with ecp commands 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mode selection 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . communicating a mode choice to the host 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . configuring the api to support a negotiated mode 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . software control of handshaking 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . using software in ieee-1284 modes 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . compatibility mode 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . automatic handshakes 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . data transfers 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . preventing deadlocks during data transfer 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . enabling negotiation to another mode 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . negotiation phase 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . terminating a mode 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device id 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . idle mode 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nibble mode 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . data transfers 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . first nibble 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
amd a d v a n c e i n f o r m a t i o n 8 AM29202 risc microcontroller second nibble 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . changing modes 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nibble idle phase 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nibble id 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . byte mode 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . automatic handshakes 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . data transfers 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . using dma in byte mode 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . setting status information 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . changing modes 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . byte idle phase 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . byte id 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ecp forward 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . automatic handshakes 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . distinguishing commands from data 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . using cpe 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . handling deadlocks 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . changing modes 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ecp reverse 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . automatic handshakes 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . data transfers 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . distinguishing commands from data 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . changing modes 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ecp reverse id 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating ranges 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc characteristics over commercial operating range 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . capacitance 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . switching characteristics over commercial operating range 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . switching waveforms 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . switching test circuit 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . thermal characteristics 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . physical dimensions 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
amd a d v a n c e i n f o r m a t i o n 9 AM29202 risc microcontroller list of figures figure 1. rom control register 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 2. dram control register 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 3. pia control register 0 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 4. dma0 control register 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 5. dma0 address register 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 6. dma1 control register 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 7. pio control register 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 8. pio input register 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 9. pio output register 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 10. pio output enable register 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 11. serial port control register 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 12. serial port status register 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 13. current processor status register 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 14. interrupt control register 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 15. maximum external system design 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 16. minimal system design 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 17. advanced parallel control register 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 18. advanced parallel status register 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 19. advanced parallel interrupt mask register 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 20. advanced parallel interrupt status register 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 21. advanced parallel data register 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 22. example: using a control status condition to generate an interrupt in compatibility mode 56 . . . . . . figure 23. example: using the data status condition in compatibility mode 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 24. advanced parallel port buffer read cycle for forward transfers 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 25. advanced parallel port buffer write cycle for reverse transfers 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . list of tables table 1. product comparisoneam29200 microcontroller family 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 2. internal peripheral address ranges 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 3. internal peripheral address assignments 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 4. vector number assignments 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 5. interrupt and trap priority table 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 6. main data scan path 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 7. feature comparison of supported ieee-1284 communication modes 39 . . . . . . . . . . . . . . . . . . . . . . . . . table 8. ieee-1284 parallel interface signal names by mode 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 9. parallel port register summary 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 10. apmode values 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 11. using control status conditions in ieee-1284 modes 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table 12. pqfp thermal characteristics 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
amd a d v a n c e i n f o r m a t i o n 10 AM29202 risc microcontroller key features and benefits the AM29202 microcontroller offers the performance of the am29200 microcontroller with the slightly reduced feature set required for a smaller package. as an up- grade to the am29205 microcontroller, the low-cost AM29202 microcontroller offers the enhanced perfor- mance of a 32-bit instruction/data bus and an ieee-1284-compliant parallel interface. ieee-1284-compliant advanced parallel interface the AM29202 microcontroller includes a new parallel port interface, called the advanced parallel interface (api), that is compliant with ieee std 1284-1994. the ieee-1284 standard specifies the operation of an exten- sible, bidirectional, multimode parallel interface that pro- vides access to a variety of peripheral devices, such as printers, scanners, multifunction peripherals, storage devices, network interfaces, and others. this standard bidirectional protocol enables the development of new peripherals that can return significant data, as well as basic status, to the host. amd's implementation of this protocol on the AM29202 microcontroller supports a number of communications modes, allowing access to both high-speed and low- overhead communications. the supported modes in- clude: com patibility (standard centronics) mode, nibble (reverse) mode, byte (reverse) mode, and ecp (bidirec- tional) mode. the standard ieee-1284 communications modes are supported using a mixture of hardware and software controls. automatic hardware handshakes and hard- ware dma support are provided in all modes except nibble. full software control provides easy access to in- put status information with a variety of software strate- gies, including polling, interrupt service, and dma. the api supports peripheral-side designs only. windows printing system compatibility because of its high performance, full feature set, glue- less interfaces, and low total system cost, the AM29202 microcontroller was chosen by microsoft to be the refer- ence hardware design for its windows printing system. the windows printing system provides substantial per- formance improvements for a new class of printers that are optimized for the windows operating system. these new printers utilize features of the ieee-1284 parallel interface to provide a fast, bidirectional commu- nication channel that improves the transfer of data be- tween host and peripheral and also allows the printer to communicate status information back to the host pc. while not limited in functionality to a specific application, the AM29202 microcontroller has the performance and feature set ideally suited to meet the needs of these low- to mid-range laser printers. complete set of common system peripherals the AM29202 microcontroller minimizes system cost by incorporating a complete set of system facilities com- monly found in embedded applications, eliminating the cost of additional components. the on-chip functions in- clude: a rom controller, a dram controller, a peripheral interface adapter, a dma controller, a bidirectional ser- ializer/deserializer, a programmable i/o port, an ieee-1284-compliant parallel port interface, a serial port, an interrupt controller, and an ieee-1149.1-com- pliant jtag debug port. the AM29202 microcontroller provides a glueless at- tachment to external roms, drams, and other periph- eral components. processor outputs have edge-rate control that allows them to drive a wide range of load ca- pacitances with low noise and ringing. this eliminates the cost of external logic and buffering. the AM29202 microcontroller lets product designers capitalize on the very low system cost made possible by the integration of processor and peripherals. many sim- ple systems can be built using only the AM29202 micro- controller and external rom and/or dram memory. rom controller the rom controller supports four individual banks of rom or other static memory. each rom bank has its own timing characteristics, and each bank may be of a different size: either 8, 16, or 32 bits wide. the rom banks can appear as a contiguous memory area of up to 16 mbytes in size. the rom controller also supports writes to the rom memory space for devices such as flash eproms and srams. dram controller the dram controller supports four separate banks of dynamic memory, each of which can be a different size: either 16 or 32 bits wide. the dram banks can appear as a contiguous memory area of up to 64 mbytes in size. to support system functions such as on-the-fly data com- pression and decompression, four 64-kbyte regions of the dram can be mapped into a 16-mbyte virtual ad- dress space. peripheral interface adapter (pia) the peripheral interface adapter allows for additional system features implemented by external peripheral chips. the pia interface permits glueless interfacing from the AM29202 microcontroller to two external peripherals, each with a separate 4-mbyte address space.
amd a d v a n c e i n f o r m a t i o n 11 AM29202 risc microcontroller dma controller the dma controller in the AM29202 microcontroller pro- vides two channels for transfer of data between the dram and internal peripherals and one channel for ex- ternal transfers. one of the dma channels is double buffered to relax the constraints on the reload time. interrupt controller the interrupt controller generates and reports the status of interrupts caused by on-chip peripherals. programmable i/o port (pio) the AM29202 microcontroller's i/o port permits direct access to 12 individually programmable external input/ output signals. eight of these signals can be configured to cause interrupts. four of these signals are shared with the ieee-1284-compliant parallel port interface. serial port the serial port implements a full-duplex uart. serializer/deserializer the bidirectional bit serializer/deserializer (video inter- face) permits direct connection to a number of laser marking engines, video displays, or raster input devices such as scanners. performance overview the AM29202 microcontroller offers a significant margin of performance over cisc microprocessors in existing embedded designs, since the majority of pr ocessor fea- tures were defined for the maximum achievable per- formance at a very low cost. this section describes the features of the AM29202 microcontroller from the point of view of system performance. instruction timing the AM29202 microcontroller uses an arithmetic/logic unit, a field shift unit, and a prioritizer to execute most instructions. each of these is organized to operate on 32-bit operands and provide a 32-bit result. all opera- tions are performed in a single cycle. the performance degradation of load and store opera- tions is minimized in the AM29202 microcontroller by overlapping them with instruction execution, by taking advantage of pipelining, and by organizing the flow of external data into the processor so that the impact of ex- ternal accesses is minimized. pipelining instruction operations are overlapped with instruction fetch, instruction decode and operand fetch, instruction execution, and result write-back to the register file. pipeline forwarding logic detects pipeline dependencies and routes data as required, avoiding delays that might arise from these dependencies. pipeline interlocks are implemented by processor hard- ware. except for a few special cases, it is not necessary to rearrange instructions to avoid pipeline dependen- cies, although this is sometimes desirable for perfor- mance. instruction set overview the AM29202 microcontroller employs a three-address instruction set architecture. the compiler or assembly- language programmer is given complete freedom to al- locate register usage. there are 192 general-purpose registers, allowing the retention of intermediate calcula- tions and avoiding needless memory accesses. instruc- tion operands may be contained in any of the general-purpose registers, and the results may be stored into any of the general-purpose registers. the instruction set contains 117 instructions that are di- vided into nine classes. these classes are integer arith- metic, compare, logical, shift, data movement, constant, floating point, branch, and miscellaneous. the floating- point instructions are not executed directly, but are emu- lated by trap handlers. all directly implemented instructions are capable of executing in one processor cycle, with the exception of interrupt returns, loads, and stores. data formats the AM29202 microcontroller defines a word as 32 bits of data, a half-word as 16 bits, and a byte as 8 bits. the hardware provides direct support for word-integer (signed and unsigned), word-logical, word-boolean, half-word integer (signed and unsigned), and character data (signed and unsigned). word-boolean data is based on the value contained in the most significant bit of the word. the values true and false are represented by the msb values 1 and 0, respectively. other data formats, such as character strings, are sup- ported by instruction sequences. fl oating-point formats (single and double precision) are defined for the proces- sor; however, there is no direct hardware support for these formats in the AM29202 microcontroller. protection the AM29202 microcontroller offers two mutually exclu- sive modes of execution, the user and supervisor modes, that restrict or permit accesses to certain proces- sor registers and external storage locations. the register file may be configured to restrict accesses to supervisor-mode programs on a bank-by-bank basis.
amd a d v a n c e i n f o r m a t i o n 12 AM29202 risc microcontroller page-mode memories the AM29202 microcontroller uses the page-mode ca- pability of common drams to improve the access time in cases where page-mode accesses can be used. this is particularly useful in very low-cost systems with 16-bit-wide drams, where the dram must be ac- cessed twice for each 32-bit operand. dram mapping the AM29202 microcontroller provides a 16-mbyte re- gion of virtual memory that is mapped to one of four 64-kbyte blocks in the physical dram memory. this supports system functions such as on-the-fly data com- pression and decompression, allowing a large data structure such as a frame buffer to be stored in a com- pressed format while the application software operates on a region of the structure that is decompressed. using a mechanism that is analogous to demand paging, sys- tem software moves data between the compressed and decompressed formats in a way that is invisible to the application software. this feature can greatly reduce the amount of memory required for printing, imaging, and graphics applications. interrupts and traps when the microcontroller takes an interrupt or trap, it does not automatically save its current state information in memory. this lightweight interrupt and trap facility greatly improves the performance of temporary inter- ruptions such as simple operating-system calls that re- quire no saving of state information. in cases where the processor state must be saved, the saving and restoring of state information is under the control of software. the methods and data structures used to handle interruptseand the amount of state in- formation savedemay be tailored to the needs of a par- ticular system. interrupts and traps are dispatched through a 256-entry vector table which directs the processor to a routine that handles a given interrupt or trap. the vector table may be relocated in memory by the modification of a proces- sor register. there may be multiple vector tables in the system, though only one is active at any given time. the vector table is a table of pointers to the interrupt and trap handlers and requires only 1 kbyte of memory. the processor performs a vector fetch every time an inter- rupt or trap is taken. the vector fetch requires at least three cycles, in addition to the number of cycles required for the basic memory access. debugging and testing software debugging on the AM29202 microcontroller is facilitated by the instruction trace facility and instruction breakpoints. instruction tracing is accomplished by forc- ing the processor to trap after each instruction has been executed. instruction breakpoints are implemented by the halt instruction or by a software trap. a scan interface compliant with ieee std 1149.1-1990 (jtag) standard test access port and boundary-scan architecture is provided to test system hardware in a production environment. it contains extensions that al- low a hardware-development system to control and ob- serve the processor without interposing hardware between the processor and system. complete development and support environment a complete development and support environment is vi- tal for reducing a product's time-to-market. advanced micro devices has created a standard development en- vironment for the 29k family of processors. in addition, the fusion29k third-party support organization provides the most comprehensive customer/partner program in the embedded processor market. advanced micro devices offers a complete set of hard- ware and software tools for design, integration, debug- ging, and benchmarking. these tools, which are available now for the 29k family, include the following: high c 29k optimizing c compiler with assem- bler, linker, ansi library functions, and 29k archi- tectural simulator xray29k tm source-level debugger minimon29k tm debug monitor a complete family of demonstration and develop- ment boards in addition, advanced micro devices has developed a standard host interface (hif) specification for operating system services, the universal debug interface (udi) for seamless connection of debuggers to ices and target hardware, and extensions for the unix common object file format (coff). this support is augmented by an engineering hotline, an on-line bulletin board, and field application engineers.
amd a d v a n c e i n f o r m a t i o n 13 AM29202 risc microcontroller connection diagram 132-lead plastic quad flat pack top view 30 31 130 85 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 91 90 89 87 86 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 26 27 28 29 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 88 92 93 94 95 96 97 98 99 125 126 127 128 129 131 132 note: pin 1 is marked for orientation.
amd a d v a n c e i n f o r m a t i o n 14 AM29202 risc microcontroller pqfp pin designations (sorted by pin number) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 v cc 34 id7 67 piaoe 100 poe 2 memclk 35 id6 68 dack 1 101 pack 3 v cc 36 id5 69 a21 102 pbusy 4 gnd 37 id4 70 a20 103 pio15 5 inclk 38 id3 71 a19 104 pio14 6 gnd 39 id2 72 a18 105 pio13 7 v cc 40 id1 73 a17 106 gnd 8 id31 41 id0 74 a16 107 v cc 9 id30 42 gnd 75 a15 108 pio12 10 id29 43 v cc 76 a14 109 pio11 11 id28 44 rxd 77 a13 110 pio10 12 id27 45 uclk 78 a12 111 pio9 13 id26 46 txd 79 a11 112 pio8 14 id25 47 romcs 3 80 gnd 113 pio7/revoe 15 id24 48 romcs 2 81 v cc 114 pio6/datastrobe 16 id23 49 romcs 1 82 a10 115 pio5/selectin 17 id22 50 romcs 0 83 a9 116 pio4/init 18 id21 51 rswe 84 a8 117 tdo 19 id20 52 romoe 85 a7 118 vdat 20 id19 53 ras 3 86 a6 119 v cc 21 id18 54 ras 2 87 a5 120 gnd 22 id17 55 ras 1 88 a4 121 psync 23 id16 56 ras 0 89 a3 122 dreq1 24 v cc 57 cas 3 90 a2 123 intr 0 25 gnd 58 cas 2 91 a1 124 intr 2 26 id15 59 cas 1 92 a0 125 vclk 27 id14 60 cas 0 93 v cc 126 lsync 28 id13 61 we 94 gnd 127 tms 29 id12 62 v cc 95 bootw 128 trst 30 id11 63 gnd 96 wait /trist 129 tck 31 id10 64 piacs 1 97 pautofd 130 tdi 32 id9 65 piacs 0 98 pstrobe 131 reset 33 id8 66 piawe 99 pwe 132 gnd
amd a d v a n c e i n f o r m a t i o n 15 AM29202 risc microcontroller pqfp pin designations (sorted by pin name) pin name pin no. pin name pin no. pin name pin no. pin name pin no. a0 92 gnd 63 id27 12 ras 0 56 a1 91 gnd 80 id28 11 ras 1 55 a2 90 gnd 94 id29 10 ras 2 54 a3 89 gnd 106 id30 9 ras 3 53 a4 88 gnd 120 id31 8 reset 131 a5 87 gnd 132 inclk 5 romcs 0 50 a6 86 id0 41 intr 0 123 romcs 1 49 a7 85 id1 40 intr 2 124 romcs 2 48 a8 84 id2 39 lsync 126 romcs 3 47 a9 83 id3 38 memclk 2 romoe 52 a10 82 id4 37 pack 101 rswe 51 a11 79 id5 36 pautofd 97 rxd 44 a12 78 id6 35 pbusy 102 tck 129 a13 77 id7 34 piacs 0 65 tdi 130 a14 76 id8 33 piacs 1 64 tdo 117 a15 75 id9 32 piaoe 67 tms 127 a16 74 id10 31 piawe 66 trst 128 a17 73 id11 30 pio4/init 116 txd 46 a18 72 id12 29 pio5/selectin 115 uclk 45 a19 71 id13 28 pio6/datastrobe 114 v cc 1 a20 70 id14 27 pio7/revoe 113 v cc 3 a21 69 id15 26 pio8 112 v cc 7 bootw 95 id16 23 pio9 111 v cc 24 cas 0 60 id17 22 pio10 110 v cc 43 cas 1 59 id18 21 pio11 109 v cc 62 cas 2 58 id19 20 pio12 108 v cc 81 cas 3 57 id20 19 pio13 105 v cc 93 dack 1 68 id21 18 pio14 104 v cc 107 dreq1 122 id22 17 pio15 103 v cc 119 gnd 4 id23 16 poe 100 vclk 125 gnd 6 id24 15 pstrobe 98 vdat 118 gnd 25 id25 14 psync 121 wait /trist 96 gnd 42 id26 13 pwe 99 we 61
amd a d v a n c e i n f o r m a t i o n 16 AM29202 risc microcontroller logic symbol romcs 3romcs 0 a21a0 id31id0 psync intr 0 reset inclk 22 tdo 32 4 romoe rswe ras 3ras 0 4 cas 3cas 0 4 we piacs 1piacs 0 2 piaoe piawe memclk trst tdi tck tms wait dreq1 dack 1 pio15pio4 (4 shared) pstrobe pautofd pbusy pack poe pwe uclk rxd txd vclk lsync vdat 12 intr 2 bootw init (pio4) selectin (pio5) datastrobe (pio6) revoe (pio7)
amd a d v a n c e i n f o r m a t i o n 17 AM29202 risc microcontroller pin descriptions note: the uclk signal must be tied high if the serial port is not used. clocks inclk input clock (input) this is an oscillator input at twice the processor and sys- tem operating frequency. it can be driven at ttl levels. memclk memory clock (output) this is a clock output at one-half of the frequency of inclk. most processor outputs, and many inputs, are synchronous to memclk. memclk drives out with cmos levels. processor signals a21a0 address bus (output, synchronous) the address bus supplies the byte address for all ac- cesses, except for dram accesses. for dram ac- cesses, multiplexed row and column addresses are provided on a14a1. the signals a23a22 and burst- mode devices are not supported on the AM29202 micro- controller. id31id0 instruction/data bus (bidirectional, synchronous) the instruction/data bus (id bus) transfers instructions to, and data to and from the processor. intr 2, intr 0 interrupt requests 2 and 0 (input, asynchronous, internal pull-up transistors) these inputs generate prioritized interrupt requests. the interrupt caused by intr 0 has the highest priority, and the interrupt caused by intr 2 has the lower priority. the interrupt requests are masked in prioritized order by the interrupt mask field in the current processor status register and are disabled by the da and di bits of the current processor status register. these signals have special hardening against metastable states, allowing them to be driven with slow-transition-time signals. the intr 3 and intr 1 signals are not supported on the AM29202 microcontroller. reset reset (input, asynchronous) this input places the processor in the reset mode. this signal has special hardening against metastable states, allowing it to be driven with a slow-rise-time signal. wait /trist add wait states/three-state control (input, synchronous, weak internal pull-up) the wait signal may be asserted during a pia, rom, or dma access to extend the access indefinitely. the wait /trist pin is also used for three-state control dur- ing test. when asserted during a processor reset, all output pins go into a high impedance state. for normal operation, this pin must be pulled high during reset. rom interface bootw boot rom width (input, asynchronous) this input configures the width of rom bank 0, so the rom can be accessed before the rom configuration has been set by the system initialization software. the bootw signal is sampled during and after a processor reset. if bootw is high before and after reset (tied high), the boot rom is 32 bits wide. if bootw is low before and after reset (tied low), the boot rom is 16 bits wide. if bootw is low before reset and high after reset (tied to reset ), the boot rom is 8 bits wide. this sig- nal has special hardening against metastable states, al- lowing it to be driven with a slow-rise-time signal and permitting it to be tied to reset . romcs 3romcs 0 rom chip selects, banks 30 (output, synchronous) a low level on one of these signals selects the memory devices in the corresponding rom bank. romcs 3 se- lects devices in rom bank 3, and so on. the timing and access parameters of each bank are individually pro- grammable. romoe rom output enable (output, synchronous) this signal enables the selected rom bank to drive the id bus. it is used to prevent bus contention when switch- ing between different rom banks or switching between a rom bank and another device or dram bank. rswe rom space write enable (output, synchronous) this signal is used to write an alterable memory in a rom bank (such as an sram or flash eprom). rswe supports only writes of width equal to or greater than the width of the memory, and the memory must be at least 16 bits wide. the cas 3cas 0 signals can serve as indi- vidual byte strobes for writes to the rom space, if rom byte writes are enabled. dram interface cas 3cas 0 column address strobes, byte 30 (output, synchronous) a high-to-low transition on these signals causes the dram bank selected by ras 3ras 0 to latch the col- umn address and complete the access. to support byte and half-word writes, column address strobes are pro- vided for individual dram bytes. cas 3 is the column address strobe for the drams, in all banks, attached to
amd a d v a n c e i n f o r m a t i o n 18 AM29202 risc microcontroller id31id24. cas 2 is for the drams attached to id23id16, and so on. these signals are also used in other special dram cycles. the cas 3cas 0 signals can be enabled to act as indi- vidual byte strobes for byte writes to the rom space. in this configuration, rom accesses do not conflict with dram accesses or refresh even though cas 3cas 0 may be used by both the rom and dram. ras 3ras 0 row address strobe, banks 30 (output, synchronous) a high-to-low transition on one of these signals causes a dram in the corresponding bank to latch the row ad- dress and begin an access. ras 3 starts an access in dram bank 3, and so on. these signals are also used in other special dram cycles. we write enable (output, synchronous) this signal is used to write the selected dram bank. aearly writeo cycles are used so the dram data inputs and outputs can be tied to the common id bus. peripheral interface adapter (pia) piacs 1piacs 0 peripheral chip selects, regions 10 (output, synchronous) these signals are used to select individual peripheral devices. dma channel 1 may be programmed to use piacs 1. piacs 5piacs 2 are not supported on the AM29202 microcontroller. piaoe peripheral output enable (output, synchronous) this signal enables the selected peripheral device to drive the id bus. piawe peripheral write enable (output, synchronous) this signal causes data on the id bus to be written into the selected peripheral. dma controller dack 1 dma acknowledge, channel 1 (output, synchronous) this signal acknowledges an external transfer on dma channel 1. dma transfers can occur to and from internal peripherals independent of these acknowledgments. dack 0 is not supported on the AM29202 microcontroller. dreq1 dma request, channel 1 (input, asynchronous, internal pull-up) this signal requests an external transfer on dma channel 1). this request is individually programmable to be either level- or edge-sensitive for either polarity of level or edge. dma transfers can occur to and from in- ternal peripherals independent of these requests. dreq0 is not supported on the AM29202 microcontroller. i/o port pio15pio8, pio7/revoe, pio6/datastrobe, pio5/selectin, pio4/init programmable input/output (input/output, asynchronous) the pio signals are available for direct software control and inspection. pio15pio8 may be individually pro- grammed to cause processor interrupts. these signals have special hardening against metastable states, al- lowing them to be driven with slow-transition-time sig- nals. pio7pio4 are shared with the ieee-1284- compliant parallel port interface. the i/o port has control of these lines when the parallel port is not enabled. the signals pio3pio0 are not supported on the AM29202 microcontroller. advanced parallel interface (api) note: for more complete descriptions of these signals and their use, see the functional description of the ieee-1284-compliant parallel interface beginning on page 41. datastrobe/pio6 (output, synchronous) datastrobe causes incoming data from the host to be latched externally on the rising edge. it is generated by a number of different signals and edges in various ieee-1284 modes. init/pio4 (input, asynchronous) the init signal comes from the ieee-1284 signal ninit/ nreverserequest and can optionally cause control interrupts on either edge. pack parallel port acknowledge (output, synchronous) this signal is used by the microcontroller to acknowl- edge a transfer from the host or to indicate to the host that data has been placed on the port. pautofd parallel port autofeed (input, asynchronous) this signal is directly input from the ieee-1284 signal nautofd/hostbusy/hostack. it is used by the host in re- verse-channel modes to signal reverse data strobe. it is also used in other contexts in various modes. pautofd can optionally cause control interrupts on either edge. pbusy parallel port busy (output, synchronous) output to the ieee-1284 signal busy/ptrbusy/periphack, this signal comes from the api when it is enabled.
amd a d v a n c e i n f o r m a t i o n 19 AM29202 risc microcontroller poe parallel port output enable (output, synchronous) this signal enables latched data on the data bus, to be read by the processor under interrupt or dma control. pstrobe parallel port strobe (input, asynchronous) directly input from the ieee-1284 signal nstrobe/ hostclk, pstrobe is used in some forward modes to generate data strobe assertions and to signal data pres- ence. in other modes, pstrobe signals something other than a data transfer. the pstrobe signal can op- tionally cause control interrupts on either edge. pwe parallel port write enable (output, synchronous) this signal is used to latch the data bus for outgoing (peripheral-to-host) transmission. revoe/pio7 (output, synchronous) revoe is used to drive latched output data in the reverse direction, from peripheral to host. selectin/pio5 (input, asynchronous) selectin comes from the ieee-1284 signal nselectin/1284active. it transitions (along with pautofd) to signal the request to negotiate an ieee-1284 mode and to signal the termination from an ieee-1284 mode. selectin can optionally cause con- trol interrupts on either edge. serial port uclk uart clock (input) this is an oscillator input for generating the uart (seri- al port) clock. to generate the uart clock, the oscilla- tor frequency may be divided by any amount up to 65,536. the uart clock operates at 16 times the serial port's baud rate. as an option, uclk may be driven with memclk or inclk. it can be driven with ttl lev- els. uclk must be tied high if unused. txd transmit data (output, asynchronous) this output is used to transmit serial data. rxd receive data (input, asynchronous) this input is used to receive serial data. video interface vclk video clock (input, asynchronous) this clock is used to synchronize the transfer of video data. as an option, vclk may be driven with memclk or inclk. it can be driven with ttl levels. vdat video data (input/output, synchronous to vclk) this is serial data to or from the video device. lsync line synchronization (input, asynchronous) this signal indicates the start of a raster line. psync page synchronization (input/output, asynchronous) this signal indicates the beginning of a raster page. jtag 1149.1 boundary scan interface tck test clock input (asynchronous input, internal pull-up) this input is used to operate the test access port. the state of the test access port must be held if this clock is held either high or low. this clock is internally synchro- nized to memclk for certain operations of the test access port controller, so signals internally driven and sampled by the test access port are synchronous to pro- cessor internal clocks. tms test mode select (input, synchronous to tck, internal pull-up) this input is used to control the test access port. if it is not driven, it appears high internally. tdi test data input (input, synchronous to tck, internal pull-up) this input supplies data to the test logic from an external source. it is sampled on the rising edge of tck. if it is not driven, it appears high internally. tdo test data output (three-state output, synchronous to tck) this output supplies data from the test logic to an exter- nal destination. it changes on the falling edge of tck. it is in the high-impedance state except when scanning is in progress. trst test reset input (asynchronous input, internal pull-up) this input asynchronously resets the test access port. this input places the test logic in a state such that no out- put driver is enabled. the trst input must be asserted in conjunction with the reset input for correct proces- sor initialization, whether or not the jtag port is used.
amd a d v a n c e i n f o r m a t i o n 20 AM29202 risc microcontroller functional differences the AM29202 microcontroller is functionally very similar to the am29200 microcontroller, operating with a re- duced pin count and fewer peripherals. the major differ- ences include a new ieee-1284-compliant bidirectional parallel port interface, a new refresh scheme, a smaller address bus (22 bits), only one external dma channel, no direct dma, no video dram support, fewer pios, fewer pias, no burst-mode rom, no external traps, few- er interrupt request pins, and a new jtag scan path. this large section (through page 70) describes the tech- nical differences between the AM29202 and am29200 microcontrollers and omits much of the information common to both processors. for a complete description of the technical features, on-chip peripherals, program- ming interface, and instruction set, please refer to the am29200 and am29205 risc microcontrollers user's manual (order# 16362). note : all registers with bits designated as areservedo should be programmed with 0s to ensure compatibility. advanced parallel interface the parallel interface on the AM29202 microcontroller is completely different from the one included on the am29200 and am29205 microcontrollers. the new port is called the advanced parallel interface (api) and is de- scribed in considerable detail in the section aieee-1284-compliant advanced parallel interface,o be- ginning on page 41. memory map changes all addresses are in the microcontroller's instruction/ data memory address space. the address space is partitioned as shown in table 2. internal peripheral reg- isters are selected by offsets from address 80000000h. the address assignment of the various internal periph- erals and controllers is shown in table 3. the address assignments for the parallel port registers have changed from those assigned for the am29200 and am29205 microcontrollers. the following register addresses are not supported on the AM29202 micro- controller: parallel port control register 800000c0 parallel port data register 800000c4 parallel port status register 800000c8 accesses to addresses that are not supported on the AM29202 microcontroller will generate an unsupported peripheral address trap (see table 4). the new address assignments for the advanced parallel interface (api) registers are shown in table 3. pin changes for the AM29202 microcontroller the reduced pin count of the AM29202 microcontroller comes from having a smaller address bus and fewer ports on some of the peripherals. the following signals supported on the am29200 microcontroller are not available on the AM29202 microcontroller. processor signals: a23a22, r/w , warn , intr 1, intr 3, trap 1trap 0, stat2stat0 rom interface signals: burst dram interface signals: tr /oe pia signals: piacs 5piacs 2 dma signals: dreq0, dack 0, tdma, greq , gack i/o port signals: pio3pio0 serial port signals: dsr , dtr table 2. internal peripheral address ranges address range address range (hexadeximal) selection maximum physical size 0000000003ffffff 4000000043ffffff 5000000050ffffff 6000000063ffffff 80000000800000fc 9000000090ffffff 9100000091ffffff 9200000092ffffff 9300000093ffffff 9400000094ffffff 9500000095ffffff eall otherse rom banks (all) dram banks (all) mapped dram banks (all) vdram transfers internal peripherals/controllers pia region 0 (piacs 0) pia region 1 (piacs 1) pia region 2 (piacs 2) pia region 3 (piacs 3) pia region 4 (piacs 4) pia region 5 (piacs 5) reserved 16 mbyte 64 mbyte 16 mbyte not supported e 4 mbyte 4 mbyte not supported not supported not supported not supported
amd a d v a n c e i n f o r m a t i o n 21 AM29202 risc microcontroller table 3. internal peripheral address assignments address peripheral (hexadecimal) register rom controller 80000000 rom control register 80000004 rom configuration register dram controller 80000008 dram control register 8000000c dram configuration register dram mapping unit 80000010 dram mapping register 0 80000014 dram mapping register 1 80000018 dram mapping register 2 8000001c dram mapping register 3 peripheral interface adapter 80000020 pia control register 0 80000024 pia control register 1 ? interrupt controller 80000028 interrupt control register dma channel 0 80000030 dma0 control register 80000034 dma0 address register 80000070 dma0 address tail register 80000038 dma0 count register 8000003c dma0 count tail register dma channel 1 80000040 dma1 control register 80000044 dma1 address register 80000048 dma1 count register serial port 80000080 serial port control register 80000084 serial port status register 80000088 serial port transmit holding register 8000008c serial port receive buffer register 80000090 baud rate divisor register advanced parallel interface 800000a0 advanced parallel control register 800000a4 advanced parallel status register 800000a8 advanced parallel interrupt mask register 800000ac advanced parallel interrupt status register 800000b0 advanced parallel data register programmable i/o port 800000d0 pio control register 800000d4 pio input register 800000d8 pio output register 800000dc pio output enable register video interface 800000e0 video control register 800000e4 top margin register 800000e8 side margin register 800000ec video data holding register eall otherse reserved note: ? pia control register 1 is reserved on the AM29202 microcontroller.
amd a d v a n c e i n f o r m a t i o n 22 AM29202 risc microcontroller ws3 res dw3 figure 1. rom control register 31 23 15 7 0 dw0 res ws0 dw1 reserved ws1 res dw2 reserved ws2 res reserved lm bwe res rom controller the on-chip rom controller provides a glueless inter- face to static memory devices such as rom, eprom, sram, flash eprom, and memory-mapped peripher- als. the rom interface on the AM29202 microcontroller ac- commodates up to four banks of static memory space. these banks can be 8, 16, or 32 bits wide, with a maxi- mum address space of 4 mbytes per bank, instead of the 16 mbytes supported by the am29200 microcontroller. burst-mode rom accesses are not supported on the AM29202 microcontroller, since the burst pin is not present. rom control register (rmct, address 80000000) the rom control register (figure 1) controls the ac- cess of rom banks 0 through 3. bits controlling burst- mode on the am29200 microcontroller are now reserved on the AM29202 microcontroller. bit 31: reserved bits 3029: data width, bank 0 (dw0) ethis field indi- cates the width of the rom in bank 0, as follows: dw0 rom width 00 32 bits 01 8 bits 10 16 bits 11 reserved bit 28: large memory (lm) ethis bit controls the size of the rom banks and the total size of the rom address space. if the lm bit is 0, each rom bank is up to 1 mbyte in size, for placement within a 4 mbyte total rom ad- dress space. if the lm bit is 1, each rom bank is up to 4 mbytes in size, for placement within a 16-mbyte total rom address space. bit 27: byte write enable (bwe) ethis bit controls whether or not the cas 3cas 0 signals are used as byte strobes during writes to the rom address space. if bwe is 0, the cas 3cas 0 signals are not active during rom writes (unless there is a hidden refresh at the same time). if bwe is 1, the cas 3cas 0 signals are used as byte strobes during a rom write with hidden re- fresh prohibited during a rom read or write. bit 26: reserved bits 2524: wait states, bank 0 (ws0) ethis field specifies the number of wait states in a rom access (i.e., the number of cycles in addition to one cycle re- quired to access the rom). zero-wait-state cycles are supported for rom reads. writes to the rom address space have a minimum of one wait state, even when wait states are programmed at zero. other bits of this register have a definition similar to dw0 and ws0 for rom banks 1 through 3.
amd a d v a n c e i n f o r m a t i o n 23 AM29202 risc microcontroller dram controller the AM29202 microcontroller directly supports dram devices without any additional components, providing ras and cas generation, address multiplexing, and re- fresh generation. the on-chip dram controller utilizes page-mode accesses and cas-before-ras refresh to extract maximum performance from dram devices. the dram interface accommodates up to four banks of dram that can be configured as a contiguous memory. each bank is individually configurable in width. in addi- tion, four 64-kbyte regions of the dram can be mapped into a 16-mbyte virtual address space. for random accesses, the dram controller provides a fixed access time of 3 cycles plus 1 cycle of ras pre- charge after each access. sequential accesses use the dram page mode with 3 cycles for the first access, fol- lowed by 2 cycles for each additional access, followed by 1 cycle of precharge. to support a lower pin count, several signals used by the am29200 microcontroller for dram interfacing are not available on the AM29202 microcontroller. the tr /oe signal for normal dram output enable and video dram transfer is not available on the AM29202 microcontroller. any dram with an oe line should have this line either tied to the appropriate cas signal, or tied directly to ground (asserted) to always be enabled. this will not cause any circuit contention, since the dram's internal logic gates the external oe signal with the de- vice's internal chip select from the processor's ras. video dram transfers are not supported on the AM29202 microcontroller. dram control register (drct, address 80000008) the dram control register (figure 2) controls the ac- cess to and refresh of dram banks 0 through 3. bit 31: page-mode dram, bank 0 (pg0) ewhen this bit is 1, burst-mode accesses to dram bank 0 are per- formed using page-mode accesses for all but the first access. when this bit is 0, page-mode accesses are not performed. bit 30: data width, bank 0 (dw0) ethis field indicates the width of the dram in bank 0, as follows: dw value dram width 0 32 bits 1 16 bits bit 29: disable bank refresh, bank 0 (dbr0) ewhen this bit is 1, dram refresh does not occur for dram bank 0. bit 28: large memory (lm) ethis bit controls the size of the dram banks and the total size of the dram ad- dress space. if the lm bit is 0, each dram bank is up to 4 mbytes in size, for placement within a 16 mbyte total dram address space. if the lm bit is 1, each dram bank is up to 16 mbytes in size, for placement within a 64-mbyte total dram ad- dress space. other bits of this register have a definition similar to pg0, dbr0, dw0 for dram banks 1 through 3. bit 15: static-column dram (sc) ewhen this bit is 1, page-mode accesses to the dram are performed using static-column accesses. static column accesses differ from page-mode cycles only in that cas 3cas 0 are held low throughout a read access. the timing of the ac- cess is not affected, and write accesses are not affected. when this bit is 0, normal page-mode accesses are per- formed, if enabled. bits 149: reserved bits 80: refresh rate (refrate) ethis field indi- cates the number of memclk cycles between dram refresh intervals. a dram refresh interval is the time re- quired to refresh all enabled dram banks. cas-before- ras cycles are performed, overlapped in the background with other non-dram accesses when possible. if one or more banks have not been refreshed 31 23 15 7 0 pg0 refrate dw0 pg1 reserved dw1 pg2 reserved dw2 pg3 dw3 reserved lm dbr0 reserved sc figure 2. dram control register dbr1 dbr2 dbr3
amd a d v a n c e i n f o r m a t i o n 24 AM29202 risc microcontroller in the background when the refrate interval expires twice, the processor forces a panic-mode refresh of the unrefreshed banks. the minimum refrate count for the AM29202 micro- controller is 16. a zero in the refrate field disables re- fresh. on reset, this field is initialized to the value 1ffh. refresh control changes two basic improvements have been made to the refresh control mechanism over that implemented on the am29200 microcontroller. panic refresh has been redefined. selectable dram refresh by bank has been added. panic refresh a panic refresh will occur when the refrate field in the dram control register has decremented to 0 twice. rather than immediately refreshing all unrefreshed banks at the first available opportunity, these banks are refreshed in sequence, with each 4-cycle cas-before- ras refresh separated by 12 cycles from the next re- fresh. having gaps between the refreshes allows dma transfers to occur in between. the maximum interval be- tween refreshes on the same (enabled) bank is: ((number of rows/bank) 1) * refrate + (16 memclk cycles * number of enabled banks) this assumes each dram bank can be refreshed within 16 cycles of the preceding bank's refresh. hidden or non-panic refreshes are unchanged from the am29200 microcontroller. selectable dram refresh since unused dram banks need no refresh, the AM29202 microcontroller provides a selectable dram bank refresh option. this feature eliminates unneces- sary refresh cycles, reducing the likelihood of a panic re- fresh and speeding up the refresh process. four new bits have been added to the dram control register to support this feature. a single bit is present for each dram bank and, when set high, disables that dram bank from being refreshed. all dram banks are en- abled for dram refresh at processor reset.
amd a d v a n c e i n f o r m a t i o n 25 AM29202 risc microcontroller figure 3. pia control register 0 reserved 31 23 15 7 0 iowait1 iowait0 ioext0 ioext1 res res peripheral interface adapter (pia) pia space on the microcontroller is divided into regions, each of which can be directly attached to an off-chip pe- ripheral device. the microcontroller's dedicated pia chip select signals will assert a peripheral device's chip select pin when the associated pia region on the micro- controller is read or written. with two pia chip select signals and a smaller address bus, the AM29202 microcontroller supports up to two peripheral devices, each with its own 22-bit memory space, for a maximum size of 4 mbytes per pia region. the piacs 5piacs 2 signals are not supported on the AM29202 microcontroller. pia control register 0/1 (pict0/1, address 80000020/24) the pia control register 0 (figure 3) controls the ac- cess to pia regions 0 and 1 on the AM29202 microcon- troller. the pia control register 1 is not available on the AM29202 microcontroller, since this product does not support pia regions 2, 3, 4, or 5. bit 31: input/output extend, region 0 (ioext0) eif this bit is one, the end of a pia access is extended by one cycle after piaoe is deasserted or by two cycles af- ter piawe is deasserted. this provides one additional cycle of output disable time or data hold time for reads and writes, respectively. bits 3029: reserved bits 2824: input/output wait states, region 0 (iowait0) ethis field specifies the number of wait states taken by an access to pia region 0. an i/o read cycle takes at least three cycles (two wait states), and an i/o write cycle takes at least four cycles (three wait states). if the iowait0 field specifies an insufficient number of wait states for an access (for example, iowait0 = 00010b for a write), the processor takes the required minimum number of wait states instead of the specified number. other bits perform similar functions to ioext0 and iowait0 for pia region 1. bits 150: reserved . these bits are reserved on the AM29202 microcontroller and should be written with 0s to ensure compatibility.
amd a d v a n c e i n f o r m a t i o n 26 AM29202 risc microcontroller dma controller the AM29202 microcontroller supports two types of dma transfers: internal and external transfers. direct dma transfers between an external device and dram using an address supplied by the external device are not supported on the AM29202 microcontroller since the greq and gack pins are not available on this device. internal dma transfers can be requested by the parallel port, serial port, and video interface. each of these inter- nal peripherals has a field in its control register for speci- fying which of the two dma channels is to be used for the transfer. the dma-enable field for the ieee-1284-com- pliant parallel port is dmamode in the advanced paral- lel control (apct) register. external dma transfers are requested by off-chip peripherals using dreq1. dma channel 0 (dma0) is available to internal peripher- als only. dma channel 1 (dma1) can be requested by either internal or external peripherals. the am29200 microcontroller signals dreq0, dack 0, greq , gack , and tdma are not supported on the AM29202 microcontroller. dma0 control register (dmct0, address 80000030) the dma0 control register (figure 4) controls dma channel 0 on the AM29202 microcontroller. dma chan- nel 0 on the AM29202 microcontroller is available for transfers between internal peripherals and dram only; external transfers are not supported. bits 3124: reserved bits 2322: data width (dw) ethis field indicates the width of the data transferred by the dma channel, as fol- lows: dw value dma transfer width 00 32 bits 01 8 bits 10 16 bits 11 32 bits, address unchanged the value dw=11 is used to repeatedly transfer a fixed pattern from a single dram location to a peripheral. for example, it can be used with the video shifter to display a blank area of a printed page without requiring that a memory buffer be allocated for the blank area. bits 2110: reserved bit 9: transfer up/down (ud) ethis bit controls the addressing of memory for the series of dma transfers. if the ud bit is 1, the dma address (in the dma0 address register) is incremented after each transfer. if the ud bit is 0, the dma address is decremented after each trans- fer. the amount by which the address is incremented or decremented is determined by the width of the transfer. dw value address increment/decrement 00 (32 bits) +/ 4 01 (8 bits) +/ 1 10 (16 bits) +/ 2 11 (32 bits) +/ 0 bit 8: read/write (rw) ethis bit controls whether the dma transfer is to or from the dram. if the rw bit is 1, the dma channel transfers data from the dram to the peripheral. if the rw bit is 0, the dma channel transfers data from the peripheral to the dram. bit 7: enable (en) ethis bit enables the dma channel to perform transfers. a 1 enables transfers, and a 0 dis- ables transfers. bit 6: reserved bit 5: count terminate enable (cte) ethis bit, when 1, causes the dma channel to terminate the transfer when the dmacnt field of the dma count register decrements past zero. if this bit is 0, the dma transfer does not terminate, though the dma channel still decre- ments the count after every transfer. bit 4: queue enable (qen) ethis bit, when 1, enables the dma queuing feature (which is implemented only on dma channel 0). dma queuing allows the dma0 address register and dma0 count register to be reloaded automatically at the end of a dma transfer from the dma0 address tail register and the dma0 reserved reserved 31 23 15 7 0 dw ud rw en res cte cti res qen figure 4. dma0 control register
amd a d v a n c e i n f o r m a t i o n 27 AM29202 risc microcontroller reserved figure 5. dma0 address register 31 23 15 7 0 dramaddr count tail register, respectively. queuing permits a se- cond transfer to start immediately after a first transfer has terminated, greatly reducing the response-time re- quirement for software to set up and start the second transfer. when this bit is 0, dma queuing is disabled, and the dma0 address register and dma0 count reg- ister are set directly to initiate a transfer. bits 31: reserved bit 0: count terminate interrupt (cti) ethe cti bit is used to report that the dma channel has generated an interrupt because of count termination. if the cte bit is one and the dmacnt field decrements past zero, the cti bit is set and a processor interrupt occurs. dma0 address register (dmad0, address 80000034) the dma0 address register (figure 5) contains the ad- dresses for a transfer by dma channel 0. bits 3124: reserved bits 230: dram address (dramaddr) ethis field contains the dram address for the next dma transfer to or from the dram. the dramaddr field is increm- ented or decremented (based on the ud bit) by an amount determined by the width of the dma transfer. the increment or decrement amount is 1 for a byte transfer, 2 for a halfword transfer, and 4 for a word trans- fer. to support repeated transfers from the same word, the address can be left unchanged. the dramaddr field wraps from the value 000000h to ffffffh when decremented and from ffffffh to 000000h when incremented. addresses must be aligned with the data width of the transfer. dma1 control register (dmct1, address 80000040) dma1 control register (figure 6) controls dma chan- nel 1. queuing is not implemented on dma channel 1. bit 31: dma extend (dmaext) ethe dmaext bit serves a function very similar to the ioextx bits in the pia control registers. this bit is set to provide an addi- tional cycle of output disable time for a read or an addi- tional cycle of data hold time for a write. bits 3029: reserved bits 2824: dma wait states (dmawait) ethis field specifies the number of wait states taken by an external access by dma channel 1. an external dma read cycle takes at least three cycles (two wait states) and an exter- nal dma write cycle takes at least four cycles (three wait states). if the dmawait field specifies an insufficient number of wait states for an access (for example, dmawait = 00010b for a write), the processor takes the required minimum number of wait states instead of the specified number. bits 2322: data width (dw) ethis field indicates the width of the data transferred by the dma channel, as fol- lows: dw value dma transfer width 00 32 bits 01 8 bits 10 16 bits 11 32 bits, address unchanged the value dw=11 is used to repeatedly transfer a fixed pattern from a single dram location to a peripheral. bits 2120: dma request mode (drm) ethis field in- dicates how external dma requests are signaled by dreq1, as follows: drm value dreq1 request 00 active low 01 active high 10 high-to-low transition 11 low-to-high transition the drm field is set to 00 by a processor reset.
amd a d v a n c e i n f o r m a t i o n 28 AM29202 risc microcontroller 31 23 15 7 0 dmawait dw ud rw drm reserved en reserved cte cti res acs dmaext res figure 6. dma1 control register bit 19: assert chip select (acs) ethis bit controls whether dma channel 1 asserts piacs 1 during an ex- ternal peripheral access. if the acs bit is 1, the dma channel asserts piacs 1; if the acs bit is 0, the dma channel does not assert piacs 1. bits 1810: reserved bit 9: transfer up/down (ud) ethis bit controls the addressing of memory for the series of dma transfers. if the ud bit is 1, the dma address (in the dma1 address register) is incremented after each transfer. if the ud bit is 0, the dma address is decremented after each trans- fer. the amount by which the address is incremented or decremented is determined by the width of the transfer, as follows: dw value address increment/decrement 00 (32 bits) +/ 4 01 (8 bits) +/ 1 10 (16 bits) +/ 2 11 (32 bits) +/ 0 bit 8: read/write (rw) ethis bit controls whether the dma transfer is to or from the dram. if the rw bit is 1, the dma channel transfers data from the dram to the peripheral. if the rw bit is 0, the dma channel transfers data from the peripheral to the dram. bit 7: enable (en) ethis bit enables the dma channel to perform transfers. a 1 enables transfers, and a 0 dis- ables transfers. bit 6: reserved bit 5: count terminate enable (cte) ethis bit, when 1, causes the dma channel to terminate the transfer when the dmacnt field of the dma count register decrements past zero. if this bit is 0, the cte field does not terminate the dma transfer, though the dma chan- nel still decrements the count after every transfer. bits 41: reserved bit 0: count terminate interrupt (cti) ethe cti bit is used to report that the dma channel has generated an interrupt because of count termination. if the cte bit is one and the dmacnt field decrements past zero, the cti bit is set and a processor interrupt occurs.
amd a d v a n c e i n f o r m a t i o n 29 AM29202 risc microcontroller programmable i/o port the i/o port permits direct programmable access of up to twelve external pio signals, as either inputs, outputs, or open-drain outputs. when used as inputs, eight of these signals, pio15pio8, can be programmed to cause edge- or level-sensitive interrupts. the AM29202 microcontroller supports pio signals pio15pio4. four pio signals (pio7pio4) are shared with the ieee-1284-compliant parallel port interface. the ac- cess to these additional ieee-1284-specific input and output signals is controlled by the parallel port. to use revoe and datastrobe as outputs and selectin and init as inputs, the poct, pin, pout, and poen registers must be configured before the parallel inter- face is enabled. when the parallel port is enabled, it has control of the shared signals. the i/o port has control of the lines when the parallel port is not enabled or after a processor reset. the i/o port signals may be read at any time, irre- spective of the parallel port ownership of those signals. pio control register (poct, address 800000d0) the pio control register (figure 7) controls interrupt generation and determines the polarity of pio15pio4. note that irm15, value 11 is now reserved; it cannot be used to signal a change in the parallel port configuration to the host. bits 3130: interrupt request mode, pio15 (irm15) ethis field enables pio15 to generate an inter- rupt and indicates whether pio15 is level- or edge-sen- sitive in generating the interrupt. the irm15 field controls pio15 as follows: irm15 value pio15 interrupt 00 interrupt disabled 01 level-sensitive 10 edge-sensitive 11 reserved the invert field (see below) further conditions inter- rupt generation. if the invert bit for pio15 is 0, an in- terrupt, if enabled, is generated by a high level on pio15 (level-sensitive) or on a low-to-high transition (edge- sensitive) of pio15. if the invert bit for pio15 is 1, an interrupt, if enabled, is generated by a low level on pio15 (level-sensitive) or on a high-to-low transition (edge-sensitive) of pio15. bits 2916: irm14 through irm8 ethe irm14irm8 fields enable interrupts and specify level- or edge-sensi- tivity for pio14pio8, respectively. these fields are identical in definition to irm15. bits 154: pio inversion (invert) ethis field deter- mines how the level on each pio signal is reflected in the pio input and pio output registers, and how interrupts are generated. the most significant bit of the invert field determines the sense of pio15, the next bit deter- mines the sense of pio14, and so on. a 0 in this field causes the internal and external sense of the respective pio signal to be noninverted; a high external level is re- flected as a 1 internally, and a low is reflected as a 0 inter- nally. a 1 in this field causes the internal and external sense of the respective pio signal to be inverted; a high external level is reflected as a 0 internally, and a low is reflected as a 1 internally. bits 30: reserved . these bits are reserved on the AM29202 microcontroller and should be written with 0s to ensure compatibility. invert figure 7. pio control register 31 23 15 7 0 irm 15 irm 14 irm 13 irm 12 irm 11 irm 10 irm 9 irm 8 res
amd a d v a n c e i n f o r m a t i o n 30 AM29202 risc microcontroller pin figure 8. pio input register 31 23 15 7 0 reserved res pout figure 9. pio output register 31 23 15 7 0 reserved res poen figure 10. pio output enable register 31 23 15 7 0 reserved res pio input register (pin, address 800000d4) the pio input register (figure 8) reflects the external levels of pio15pio4. bits 3116: reserved bits 154: pio input (pin) ethis field reflects the lev- els on each pio signal. the most significant bit of the pin field reflects the level on pio15, the next bit reflects the level on pio14, and so on. the correspondence be- tween levels and bits in this register is controlled by the invert field. bits 30: reserved . these bits are reserved on the AM29202 microcontroller and will be read as 0s. pio output register (pout, address 800000d8) the pio output register (figure 9) determines the lev- els driven on the pio signals, for those signals enabled to be driven by the pio output enable register. bits 3116: reserved bits 154: pio output (pout) ethis field determines the levels on each pio signal, if so enabled by the pio output enable register. the most significant bit of the pout field determines the level on pio15, the next bit determines the level on pio14, and so on. the corre- spondence between levels and bits in this register is controlled by the invert field. bits 30: reserved . these bits are reserved on the AM29202 microcontroller and should be written with 0s to ensure compatibility. pio output enable register (poen, address 800000dc) the pio output enable register (figure 10) determines whether or not the pio signals are driven as outputs. bits 3116: reserved bits 154: pio output enable (poen) ethis field de- termines whether each pio signal is driven as an output. the most significant bit of the poen field determines whether pio15 is driven, the next bit determines wheth- er pio14 is driven, and so on. a 1 in a bit position en- ables the respective signal to be driven according to the associated pout and invert bits, and a 0 disables the signal as an output. bits 30: reserved . these bits are reserved on the AM29202 microcontroller and should be written with 0s to ensure compatibility.
amd a d v a n c e i n f o r m a t i o n 31 AM29202 risc microcontroller serial port the on-chip serial port is a uart that permits full-duplex, bidirectional data transfer using the rs-232 standard. serial port registers provide a programmable baud rate generator, odd/even parity capability, choice of word length, a test mode, and dma access. the operations of the serial port are similar on the am29200 and AM29202 microcontrollers, except that the dsr and dtr handshake signals are not available on the AM29202 microcontroller. these functions, if needed, can be recreated with available pio signals. serial port control register (spct, address 80000080) the serial port control register (figure 11) controls both the transmit and receive sections of the serial port. bits 3127: reserved bit 26: loopback (loop) esetting this bit places the serial port in the loopback mode. in this mode, the txd output is set high and the transmit shift register is con- nected to the receive shift register. data transmitted by the transmit section is immediately received by the re- ceive section. the loopback mode is provided for testing the serial port. bit 25: send break (brk) esetting this bit causes the serial port to send a break, which is a continuous low level on the txd output for a duration of more than one frame transmission time. the transmitter can be used to time the frame by setting the brk bit when the transmit- ter is empty (indicated by the temt bit of the serial port status register), writing the serial port transmit hold- ing register with data to be transmitted, and then wait- ing until the temt bit is set again before resetting the brk bit. bits 2422: reserved bits 2119: parity mode (pmode) ethis field speci- fies how parity generation and checking are performed during transmission and reception (the value axo is a don't care): pmode value parity generation and checking 0xx no parity bit in frame 100 odd parity (odd number of 1s in frame) 101 even parity (even number of 1s in frame) 110 parity forced/checked as 1 111 parity forced/checked as 0 bit 18: stop bits (stp) ea 0 in this bit specifies that one stop bit is used to signify the end of a frame. a 1 in this bit specifies that two stop bits are used to signify the end of a frame. bits 1716: word length (wlgn) ethis field indi- cates the number of data bits transmitted or received in a frame, as follows: wlgn value word length 00 5 bits 01 6 bits 10 7 bits 11 8 bits data words of less than eight bits are right-justified in the transmit holding register and receive buffer register. bits 1510: reserved bits 98: transmit mode (tmode) ethis field en- ables data transmission and controls the operational mode of the serial port for the transmission of data, as follows: tmode value effect on transmit section 00 disabled 01 generate interrupt requests for service 10 generate dma channel 0 requests 11 generate dma channel 1 requests requests for service are requests to write the transmit holding register with data to be transmitted. placing the transmit section into the disabled state causes all inter- nal state machines to be reset and holds the transmit section in an idle state with txd high. serial port pro- grammable registers are not affected when the transmit section is disabled. bits 73: reserved bit 2: receive status interrupt enable (rsie) ethis bit enables the serial port to generate an interrupt be- cause of an exception during reception. if this bit is 1 and the serial port receives a break or experiences a framing error, parity error, or overrun error, the serial port gener- ates a receive status interrupt.
amd a d v a n c e i n f o r m a t i o n 32 AM29202 risc microcontroller bits 10: receive mode (rmode) ethis field enables data reception and controls the operational mode of the serial port for the reception of data: rmode value effect on receive section 00 disabled 01 generate interrupt requests for service 10 generate dma channel 0 requests 11 generate dma channel 1 requests requests for service are requests to read data from the receive buffer register. placing the receive section into the disabled state causes all internal state machines to be reset and holds the receive section in an idle state. serial port programmable registers are not affected when the receive section is disabled. serial port status register (spst, address 80000084) the serial port status register (figure 12) indicates the status of the transmit and receive sections of the port. bits 3111: reserved bit 10: transmitter empty (temt) ethis bit is 1 when the transmitter has no data to transmit and the transmit shift register is empty. this indicates to software that it is safe to disable the transmit section. bit 9: transmit holding register empty (thre) when the thre bit is 1, the transmit holding register does not contain valid data and can be written with data to be transmitted. when the thre bit is 0, the transmit holding register contains valid data not yet copied to the transmit shift register for transmission and cannot be written. if so enabled by the tmode field, the thre bit causes an interrupt or dma request when it is set. the thre bit is reset automatically by writing the trans- mit holding register. this bit is read-only, allowing other bits of the serial port status register to be written (for example, resetting the brki bit) without interfering with the data request. bit 8: receive data ready (rdr) ewhen the rdr bit is 1, the receive buffer register contains data that has been received on the serial port, and can be read to ob- tain the data. when the rdr bit is 0, the receive buffer register does not contain valid data. if so enabled by the rmode field, the rdr bit causes an interrupt or dma request when it is set. the rdr bit is reset automatically by reading the receive buffer register. bits 74: reserved bit 3: break interrupt (brki) ethe brki bit is set to indicate that a break has been received. if the rsie bit is 1, the brki bit being set causes a receive status inter- rupt. the brki bit should be reset by the receive status interrupt handler. bit 2: framing error (fer) ethis bit is set to indicate that a framing error occurred during reception of data. if the rsie bit is 1, the fer bit being set causes a receive status interrupt. the fer bit should be reset by the re- ceive status interrupt handler. bit 1: parity error (per) ethis bit is set to indicate that a parity error occurred during reception of data. if the rsie bit is 1, the per bit being set causes a receive status interrupt. the per bit should be reset by the re- ceive status interrupt handler. bit 0: overrun error (oer) ethis bit is set to indicate that an overrun error occurred during reception of data. if the rsie bit is 1, the oer bit being set causes a re- ceive status interrupt. the oer bit should be reset by the receive status interrupt handler. 31 23 15 7 0 reserved reserved loop brk res wlgn pmode stp reserved tmode rmode rsie figure 11. serial port control register 31 23 15 7 0 thre rdr reserved per oer reserved brki fer temt figure 12. serial port status register
amd a d v a n c e i n f o r m a t i o n 33 AM29202 risc microcontroller interrupts and traps the AM29202 microcontroller employs a lightweight in- terrupt and trap facility that does not automatically save its current state in memory. saving and restoring state information is under software control. interrupts and traps are dispatched using a vector table that can be re- located in memory (see table 4). external traps, warn , intr 3, and intr 1 are not sup- ported on the AM29202 microcontroller. pio signals can be used as additional interrupts when more inputs are required. two new bits are defined in the interrupt con- trol register to support the ieee-1284 parallel port. current processor status register (cps, register 2) this protected special-purpose register (see figure 13) controls the behavior of the processor and its ability to recognize exceptional events. the im field values have changed for the AM29202 microcontroller. bits 3118: reserved bit 17: timer disable (td) ewhen the td bit is 1, the timer interrupt is disabled. when this bit is 0, the timer interrupt depends on the value of the ie bit of the timer reload register. note that timer interrupts may be dis- abled by the da bit regardless of the value of either td or ie. the intent of this bit is to provide a means of disab- ling timer interrupts without having to perform a non- atomic read-modify-write operation on the timer reload register. bits 1615: reserved bit 14: interrupt pending (ip) ethis bit allows soft- ware to detect the presence of interrupts while the inter- rupts are disabled. the ip bit is set if an interrupt request is active, but the processor is disabled from taking the resulting interrupt due to the value of the da, di, or im bits. if all interrupt requests are subsequently deacti- vated while still disabled, the ip bit is reset. bits 1312: trace enable, trace pending (te, tp) ethe te and tp bits implement a software-con- trolled, instruction single-step facility. single stepping is not implemented directly, but rather emulated by trap sequences controlled by these bits. the value of the te bit is copied to the tp bit whenever an instruction com- pletes execution. when the tp bit is 1, a trace trap oc- curs. bit 11: trap unaligned access (tu) ethe tu bit en- ables checking of address alignment for external data- memory accesses. when this bit is 1, an unaligned access trap occurs if the processor either generates an address for an external word not aligned on a word ad- dress-boundary (i.e., either of the least significant two bits is 1) or generates an address for an external half- word not aligned on a half-word address boundary (i.e., the least significant address bit is 1). when the tu bit is 0, data-memory address alignment is ignored. alignment is ignored for input/output accesses. the alignment of instruction addresses is also ignored (un- aligned instruction addresses can be generated only by indirect jumps). interrupt/trap vector addresses always are aligned properly by the processor. bit 10: freeze (fz) ethe fz bit prevents certain regis- ters from being updated during interrupt and trap pro- cessing, except by explicit data movement. the affected registers are: channel address, channel data, channel control, program counter 0, program counter 1, pro- gram counter 2, and the alu status register. when the fz bit is 1, these registers hold their values. an affected register can be changed only by a move-to- special-register instruction. when the fz bit is 0, there is no effect on these registers and they are updated by processor instruction execution as described in this manual. the fz bit is set whenever an interrupt or trap is taken, holding critical state in the processor so it is not modified unintentionally by the interrupt or trap handler. if the freeze (fz) bit of the current processor status register is reset from 1 to 0, two cycles are required be- fore all program state is reflected properly in the regis- ters affected by the fz bit. this implies that interrupts and traps cannot be enabled until two cycles after the fz bit is reset for proper sequencing of program state. there is no delay associated with setting the fz bit from 0 to 1. bits 98: reserved 31 23 15 7 0 tp ip te td reserved fz tu di wm sm im da figure 13. current processor status register res res res
amd a d v a n c e i n f o r m a t i o n 34 AM29202 risc microcontroller bit 7: wait mode (wm) ethe wm bit places the proces- sor in the wait mode. when this bit is 1, the processor performs no operations. the wait mode is reset by an interrupt or trap for which the processor is enabled, or by the assertion of the reset pin. bits 65: reserved bit 4: supervisor mode (sm) ethe sm bit protects certain processor context, such as protected special- purpose registers. when this bit is 1, the processor is in the supervisor mode and access to all processor con- text is allowed. when this bit is 0, the processor is in the user mode and access to protected processor context is not allowed. an attempt to access (either read or write) protected processor context causes a protection viola- tion trap. bits 32: interrupt mask (im) ethe im field is an en- coding of the processor priority with respect to external interrupts. the interpretation of the interrupt mask is specified as follows: im value result 00 intr 0 enabled 01 intr 0 enabled 10 intr 2 and intr 0 enabled 11 intr 2, intr 0, and internal peripheral interrupts enabled note that the intr 0 interrupt cannot be disabled by the im field. bit 1: disable interrupts (di) ethe di bit prevents the processor from being interrupted by internal peripheral requests and by external interrupt requests intr 2 and intr 0. when this bit is 1, the processor ignores all inter- nal and external interrupts. however, internal traps, tim- er interrupts, and trace traps may be taken. when this bit is 0, the processor takes any interrupt enabled by the im field, unless the da bit is 1. bit 0: disable all interrupts and traps (da) ethe da bit prevents the processor from taking any interrupts and most traps. when this bit is 1, the processor ignores interrupts and traps. when the da bit is 0, all traps are taken; interrupts are taken if otherwise enabled. interrupt control register (ict, address 80000028) two new bits, apdi and apci, have been added to inter- rupt control register (figure 14) to support the ieee-1284-compliant parallel port. the apdi interrupt occurs when a hardware handshake-supported data transfer mode receives (or is ready to transmit) a data byte and when interrupts are desired instead of dma. the apci interrupt occurs for a variety of combined mask-selectable events requiring processor interven- tion, such as mode changes and status input. semi-au- tomatic and manual modes utilize apci interrupts for some phase transitions, including data handling. bits 3128: reserved bit 27: video interrupt (vdi) ea 1 in this bit indicates the video interface has generated an interrupt request. bits 2624: reserved bits 2316: i/o port interrupt (iopi) ea 1 in this field indicates the respective pio signal has generated an in- terrupt request. a 1 in the most significant bit of the iopi field indicates pio15 has caused an interrupt, the next bit indicates pio14 has caused an interrupt, and so on. bit 15: reserved bit 14: dma channel 0 interrupt (dma0i) ea 1 in this bit indicates dma channel 0 has generated an interrupt request. bit 13: dma channel 1 interrupt (dma1i) ea 1 in this bit indicates dma channel 1 has generated an interrupt request. bit 12: advanced parallel port data transfer inter- rupt (apdi) ea 1 in this bit indicates that the ieee-1284 parallel port interface is requesting a data transfer. writing a 1 to the apds clears the data transfer request status that caused the apdi. this is usually not neces- sary, because a read or write (whichever is appropriate in a particular mode) to the advanced parallel data reg- figure 14. interrupt control register 31 23 15 7 0 iopi vdi dma1i dma0i rxsi rxdi res reserved res apci apdi res res txdi
amd a d v a n c e i n f o r m a t i o n 35 AM29202 risc microcontroller ister automatically clears the apds condition. clearing the apdi bit when the dmamode bit in the apct reg- ister is set is undefined and not recommended. bit 11: advanced parallel port control condition in- terrupt (apci) ea 1 in this bit indicates that the ieee-1284 parallel port interface has detected a valid control condition. this bit is the or of all the control condition interrupt bits in the apis register, (eci, deviniti, inithli, initlhi, selinhli, selinlhi, pautohli, pautolhi, pstbhl and pstblhi), which are in turn masked from the control condition bits in the apst register. the apci bit must be cleared separately from the bit or bits that caused the apci interrupt. writing a 1 to any of the control status bits in the apst register or to the interrupt bits in the apis register will clear the condition that caused the interrupt (if masked). all of the bits require such a condition clear action, ex- cept for the device initialization interrupt: it is cleared when the parallel port interface is returned to ieee-1284 compatibility mode. bits 108: reserved bit 7: serial port receive status interrupt (rxsi) ea 1 in this bit indicates the serial port has generated an inter- rupt request because of the status of the receive logic. bit 6: serial port receive data interrupt (rxdi) ea 1 in this bit indicates the serial port has generated an inter- rupt request because receive data is ready. bit 5: serial port transmit data interrupt (txdi) ea 1 in this bit indicates the serial port has generated an inter- rupt request because the transmit holding register is empty. bits 40: reserved vector numbers when an interrupt or trap is taken, the processor deter- mines an 8-bit vector number associated with the inter- rupt or trap. the vector number gives the number of a vector table entry. the physical address of the vector table entry is generated by replacing bits 92 of the val- ue in the vector area base address register with the vector number. vector numbers are either predefined or specified by an instruction causing the trap. the assignment of vector numbers is shown in table 4 (vector numbers are in dec- imal notation). an unsupported peripheral address trap has been add- ed for the AM29202 microcontroller. a vector 6 trap will occur for accesses to peripheral addresses other than those listed in table 2.
amd a d v a n c e i n f o r m a t i o n 36 AM29202 risc microcontroller table 4. vector number assignments number type of trap or interrupt cause 0 illegal opcode executing undefined instruction 1 1 unaligned access access on unnatural boundary, tu = 1 2 out-of-range overflow or underflow 34 reserved 5 protection violation invalid user-mode operation 2 6 unsupported peripheral address access to unsupported address 7 reserved 8 user instruction mapping miss no dram mapping for access 9 user data mapping miss no dram mapping for access 10 supervisor instruction mapping miss no dram mapping for access 11 supervisor data mapping miss no dram mapping for access 1213 reserved 14 timer timer facility 15 trace trace facility 16 intr 0 intr 0 input 17 reserved 18 intr 2 intr 2 input 19 internal internal peripheral 2021 reserved 22 floating-point exception unmasked floating-point exception 3 23 reserved 2429 reserved for instruction emulation (opcodes d8dd) 30 multm multm instruction 31 multmu multmu instruction 32 multiply multiply instruction 33 divide divide instruction 34 multiplu multiplu instruction 35 dividu dividu instruction 36 convert convert instruction 37 sqrt sqrt instruction 38 class class instruction 3941 reserved for instruction emulation (opcode e7e9) 42 feq feq instruction 43 deq deq instruction 44 fgt fgt instruction 45 dgt dgt instruction 46 fge fge instruction 47 dge dge instruction 48 fadd fadd instruction 49 dadd dadd instruction 50 fsub fsub instruction 51 dsub dsub instruction 52 fmul fmul instruction notes: 1. this vector number also results if an external device removes intr x before the corresponding interrupt or trap is taken by the processor. 2. some supervisor-mode operations cause protection violations to facilitate virtualization of certain operations. 3. the floating-point exception trap is not generated by the processor hardware. it is generated by the software that implements the virtual arithmetic interface.
amd a d v a n c e i n f o r m a t i o n 37 AM29202 risc microcontroller notes: (continued) 4. some of vector numbers 64255 are reserved for software compatibility. these are documented in the host interface (hif) specification (order# 11539) available from amd. table 4. vector number assignments (continued) number type of trap or interrupt cause 53 dmul dmul instruction 54 fdiv fdiv instruction 55 ddiv ddiv instruction 56 reserved for instruction emulation (opcode f8) 57 fdmul fdmul instruction 5863 reserved for instruction emulation (opcode faff) 64255 assert and emulate instruction traps see note 4 (vector number specified by instruction) sequencing of interrupts and traps to resolve conflicts, interrupts and traps are taken ac- cording to the priority shown in table 5. in this table, in- terrupts and traps are listed in order of decreasing priority. interrupts and traps fall into one of two catego- ries depending on the timing of their occurrence relative to instruction execution. the column labels inst and async have the following meanings: inst egenerated by the execution or attempted execution of an instruction. async egenerated asynchronous to and indepen- dent of the instruction being executed, although it may be a result of an instruction executed previously. the principle for interrupt and trap sequencing is that the highest priority interrupt or trap is taken first. other inter- rupts and traps either remain active until they can be tak- en or they are regenerated when they can be taken. this is accomplished depending on the type of interrupt or trap, as follows: 1. all traps in table 5 with priority 8 or 9 are regenerated by the re-execution of the causing instruction. 2. most of the interrupts and traps of priority 3 through 7 must be held by external hardware until they are tak- en. the exceptions to this are listed in item 3. 3. the exceptions to item 2 are the timer interrupt and the trace trap. these are caused by bits in various registers in the processor and are held by these reg- isters until taken or cleared. the two relevant bits are the interrupt (in) bit of the timer reload register for timer interrupts and the trace pending (tp) bit of the current processor status register for trace traps. 4. all traps of priority 1 and 2 in table 5, except for the un- aligned access trap, are not regenerated. these traps are mutually exclusive and are given high priority be- cause they cannot be regenerated: they must be tak- en if they occur. if one of these traps occurs at the same time as a reset, it is not taken and its occurrence is lost. 5. the unaligned access trap is regenerated internally when an external access is restarted by the channel address, channel data, and channel control regis- ters. note that this trap is not necessarily exclusive to the traps discussed in item 4 above. exception reporting and restarting the pc1 column in table 5 describes the value held in the program counter 1 register (pc1) when the inter- rupt or trap is taken. for traps in the inst category, pc1 contains either the address of the instruction causing the trap, indicated by curr, or the address of the instruc- tion following the instruction causing the trap, indicated by next . for interrupts and traps in the async category, pc1 con- tains the address of the first instruction not executed due to the taking of the interrupt or trap. this is the next instruction to be executed upon interrupt return, as indi- cated by next in the pc1 column.
amd a d v a n c e i n f o r m a t i o n 38 AM29202 risc microcontroller priority type of interrupt or trap user-mode data mapping miss supervisor-mode data mapping miss unsupported peripheral address inst/async pc1 channel regs inst inst inst next next next 2 unaligned access out-of-range assert instructions floating-point instructions integer multiply/divide instructions emulate inst inst inst inst inst inst next next next next next next 3 intr 0 async next multiple 4 intr 2 async next multiple 5 internal peripheral interrupts async next multiple 6 timer async next multiple 7 trace async next multiple 8 inst inst curr curr 9 (lowest) illegal opcode protection violation inst inst curr curr all all all all n/a n/a n/a n/a n/a n/a n/a n/a n/a user-mode inst mapping miss supervisor-mode inst mapping miss 1 (highest) table 5. interrupt and trap priority table
amd a d v a n c e i n f o r m a t i o n 39 AM29202 risc microcontroller debugging and testing the AM29202 microcontroller provides debugging and testing features at both the hardware and software lev- els. instruction tracing and instruction breakpoints are supported. however, the processor status outputs stat2stat0 are not available on the AM29202 micro- controller. a jtag-compliant test access port facilitates system testing in a production environment. a new main data scan path for the AM29202 microcontroller is provided below. the ictest1 and ictest2 data paths are un- changed. main data path table 6 shows a 160-cell path used to access the proces- sor pins. this path is divided into five sets of cells. where applicable, each set has a cell that enables the outputs of the set to be driven on the processor's pins. these cells are not connected to a processor pin. some of these cells affect outputs not normally enabled and disabled during normal system operation. the sets of cells are divided logically as follows: 1) clocks, requests, and reset, 2) miscellaneous periph- eral control signals, 3) memory and peripheral controls, 4) instruction/data bus. note that the greq , gack , stat2stat0, r/w , and tr pins are included in the main scan path for special emulation devices only; these external pins are not included on the AM29202 microcontroller. table 6. main data scan path bit cell name comments 1 memclk 2 reset 3 lsync 4 vclk 5 intr 2 6 intr 0 7 dreq1 8 greq 9 topdrv enables the drivers for psync through pwe 10 psynci psync input 11 psynco psync output 12 vdati vdat input 13 vdato vdat output 14 pioi4 pio4 input 15 pioo4 pioo4 output 16 pioi5 pio5 input 17 pioo5 pio5 output .. .. 36 pioi15 pio15 input 37 pioo15 pio15 output 38 pbusy 39 pack 40 poe 41 pwe 42 pstrobe 43 pautofd 44 wait 45 bootw 46 abidrv enables the driving of the a21a0 outputs 47 a0 48 a1 .. .. 68 a21
amd a d v a n c e i n f o r m a t i o n 40 AM29202 risc microcontroller table 6. main data scan path (continued) bit cell name comments 69 botdrv enables the drivers for dack 1 through rxd 70 dack 1 71 r/w 72 piaoe 73 piawe 74 piacs 0 75 piacs 1 76 gack 77 tr 78 we 79 cas 0 80 cas 1 81 cas 2 82 cas 3 83 ras 0 84 ras 1 85 ras 2 86 ras 3 87 romoe 88 rswe 89 romcs 0 90 romcs 1 91 romcs 2 92 romcs 3 93 txd 94 uclk 95 rxd 96 dbidrv enables the id bus drivers 97 idi0 id0 input 98 ido0 id0 output 99 idi1 id1 input 100 ido1 id1 output .. .. 159 idi31 id31 input 160 ido31 id31 output note: drive-enable cells are shown in boldface.
amd a d v a n c e i n f o r m a t i o n 41 AM29202 microcontroller ieee-1284-compliant advanced parallel interface the AM29202 microcontroller offers a new parallel port interface that is compliant with the ieee std 1284-1994 standard signaling method for a bidirectional parallel peripheral interface for personal computers. the new advanced parallel interface (api) replaces the parallel interface included on the am29200 and am29205 microcontrollers (referred to in this data sheet as the classic port). note: this data sheet has been written with the as- sumption that the reader has a thorough and complete understanding of the ieee-1284 standard and all the electrical and timing specifications it contains. ieee std 1284-1994 can be ordered directly from the ieee by calling 1-800-678-ieee (us) or 1-908-981-1393 and re- questing document #sh17335. upgrading hardware and software the advanced parallel interface has been designed to minimize the hardware and software changes required to upgrade from the classic port; however, some changes will be required to upgrade. the maximum external system circuitry needed to im- plement the api is shown in figure 15. the parallel port does not attach directly to the microcontroller, but is at- tached to the interface via buffers. to support the new ieee-1284-compliant parallel port, data must be latched in the interface using a bidirectional bus-driver/ latch such as a 74als652. the handshaking signals, pstrobe, pautofd, selectin, init, pack, and pbusy , are connected to the microcontroller via simple interface circuits. the inputs pstrobe, pautofd, selectin, and init should be connected to the pro- cessor via a schmitt-trigger inverter such as a 74hct14, and the outputs pack and pbusy should be connected to the host via an inverter/driver such as a 74ls240. perror , select , and fault are driven by software through programmer-defined pios or pias. the api also requires software/driver changes, since the programmable registers and their addresses have changed from those used on the classic port. these changes are described later in this section. AM29202 microcontroller 74als652 ab pack pbusy fault select perror pio4 init pio5 selectin pio6 datastrobe pio7 revoe pwe poe id7id0 id7id0 data8data1 select/xflag perror/ackdatareq/nackreverse nack/ptrclk/periphclk busy/ptrbusy/periphack pack pbusy pstrobe pautofd gab gba cab cba nstrobe/hostclk nautofd/hostbusy/hostack ninit/nreverserequest nselectin/1284active figure 15. maximum external system design nfault/ndataavail/nperiphrequest
amd a d v a n c e i n f o r m a t i o n 42 AM29202 microcontroller minimal system design while the new parallel interface on the AM29202 micro- controller adds considerable functionality, it is not re- quired that the port be operated in full ieee-1284 compliance. using a subset of the hardware and the register set, the designer can set up the api to operate in a mode similar to that of the classic port on the am29200 and am29205 microcontrollers. a minimal system de- sign for this configuration is shown in figure 16. host-to-peripheral data must be latched in the interface using a three-state latch such as a 74ls374. the hand- shaking signals, pstrobe, pautofd, pack, and pbusy , are connected to the microcontroller via simple interface circuits. the inputs pstrobe and pautofd should be connected to the processor via a schmitt-trig- ger inverter such as a 74hct14, and the outputs pack and pbusy should be connected to the host via an in- verter such as a 74ls240. pbusy pautofd id7id0 data8data1 pstrobe 74hct14 AM29202 microcontroller figure 16. minimal system design poe pack 74ls240 selectin init vcc 74ls374 datastrobe software can then minimally control the api to operate in a manner similar to the classic port on the am29200 and am29205 microcontrollers. this is accomplished by configuring the interface for compatibility mode (by set- ting apmode to 1) and leaving it there. interrupts will be received for data transfer in the forward direction. overview the ieee-1284 standard specifies the operation of an extensible, bidirectional, multimode parallel interface, providing access to a variety of peripheral devices, such as printers, scanners, storage devices, and network in- terfaces. it supports several different communications modes that allow access to both high-speed and low- overhead communications, providing a path for data to be sent from the peripheral device to the host and reduc- ing the amount of user interaction required to operate a peripheral. amd's implementation of the ieee-1284 standard on the AM29202 microcontroller provides: compatibility, nibble, byte, and ecp modes esupport for peripheral-side operation in these modes (host-side designs are not supported). automatic hardware handshakes ecorrectly timed requests to support data transfers that match ieee-1284 protocols; automatic in all modes except nibble. hardware dma support in all modes except nibble. external control lines eaccess to ieee-1284 con- trol lines through existing classic port signals and pio lines. registers and control logic are provided to easily support other required mode lines and con- trols in software. software control eeasy access to input status in- formation with a variety of software strategies, in- cluding polling, interrupt service, and dma. windows printing system compatibility ethe AM29202 microcontroller was chosen by microsoft as its hardware reference platform for this software. the AM29202 microcontroller supports the standard ieee-1284 communications modes using a mixture of hardware and software controls. hardware controls include fast automatic data transfer handshakes and real-time status lines, as well as inter- rupts and pollable status for software-driven operations. operations not directly supported in hardware include: mode transitions of any type, ieee-1284 negotiation and termination, mode approvals and denials, and nibble mode data transmission. these operations are handled using interrupts and application software. a special control interrupt in the ict register is provided to manage mode changes, negotiation, and termination. using this apci control interrupt, software modifies an api interrupt mask register at each stage of an ieee-1284 transition, selecting the edge required for the next interrupt (as well as doing the work required at that phase transition). this structure allows for easy control of modes without processor delay loops or polling. data handling is facilitated by a pollable status bit and a se- cond dedicated interrupt (apdi) in the ict register.
amd a d v a n c e i n f o r m a t i o n 43 AM29202 microcontroller table 7. feature comparison of supported ieee-1284 communication modes ieee-1284 modes feature compatibility (centronics) nibble byte ecp data path forward (host-to-peripheral) reverse (peripheral-to-host) reverse (peripheral-to-host) forward (host-to-peripheral) reverse (peripheral-to-host) bidirectional no (note 1) no (note 2) no (note 2) yes full-word transfer yes no no forward mode only hardware handshaking automatic semi-automatic automatic automatic hardware dma support yes no yes yes notes: 1. bidirectional when used with nibble or byte mode with transfer direction controlled by host. 2. bidirectional when used with compatibility mode. these two modes cannot be active simultaneously. communication modes amd's implementation of the ieee-1284 standard on the AM29202 microcontroller supports the following ieee-1284 modes (see table 7). compatibility mode eprovides an asynchronous, byte-wide forward (host-to-peripheral) channel with data and status lines used according to their original (centronics) definitions. compatibility mode is back- ward compatible with many existing devices, includ- ing the pc parallel port and the classic parallel port on the am29200 and am29205 microcontrollers. nibble mode eprovides an asynchronous, reverse (peripheral-to-host) channel, under control of the host. data bytes are transmitted as two sequential, four-bit nibbles using four peripheral-to-host status lines. nibble mode is used with compatibility mode to implement a bidirectional channel. these two modes cannot be active simultaneously. byte mode eprovides an asynchronous, byte-wide reverse (peripheral-to-host) channel using the eight data lines of the interface for data and the control/ status lines for handshaking. byte mode is used with compatibility mode to implement a bidirectional channel, with transfer direction controlled by the host, when the host and peripheral both support bi- directional use of the data lines. the two modes can- not be active simultaneously. extended capabilities port (ecp) mode epro- vides an asynchronous, byte-wide, bidirectional channel. for faster forward transfers, an interlocked handshake replaces compatibility mode's minimum timing requirements for its interface signals. a con- trol line is provided to distinguish between command and data transfers. a command may optionally be used to indicate data compression or a channel ad- dress (determined by the application). mode selection is made by the application software, based on mode requests made by the external ieee-1284 host. these mode requests are called ieee-1284 negotiations and are attempts to communi- cate beyond the base level (compatibility mode). the negotiations, responses, and mode changes are all moderated by the application software (an ieee-1284 driver), on interrupts caused by the ieee-1284 interface hardware, in response to ieee-1284 activity on the in- terface.
amd a d v a n c e i n f o r m a t i o n 44 AM29202 microcontroller external signals note: all ieee-1284 interface signal levels discussed in this document are inverted, from the ieee-1284 cable to the peripheral circuitry at the processor, and vice versa (see figure 15). signal names shown in this document in all upper case letters (e.g., pstrobe) are AM29202 microcontroller signals; they represent ieee std 1284-1994 signal names (e.g., nstrobe) that have been inverted at the processor/interface chip terminal. while many signals are named differently in each ieee-1284 communication mode, the primary reference in this data sheet is to the AM29202 microcontroller sig- nal name at the pin. to facilitate reference to timing dia- grams in the ieee standard document, the inverted ieee-1284 compatibility mode signal name is some- times listed in this data sheet in parentheses following the AM29202 microcontroller signal name, e.g., pstrobe (nstrobe). table 8 maps the AM29202 microcontroller signal names to all those used in the ieee-1284 stan- dard. dedicated signal lines pack (output) output through an inverting buffer to nack/ptrclk/ periphclk, this signal is active when the api is en- abled. pautofd (input) input via an inverting buffer from nautofd/hostbusy/ hostack, pautofd is used by the host in reverse- channel modes to signal reverse data strobe. it is also used in other contexts in various modes. the pautofd signal can optionally cause control inter- rupts on either edge. pbusy (output) output through an inverting buffer to busy/ptrbusy/ periphack, this signal comes from the advanced port when it is enabled. poe (output) made active by a read from address 8 00000b0, this signal enables latched data on the data bus, to be read by the processor under interrupt or dma control. pstrobe (input) input via an inverting buffer from nstrobe/hostclk, the pstrobe signal is used in some forward modes to generate data strobe assertions and to signal data presence. in other modes, pstrobe signals some- thing other than a data transfer. the pstrobe sig- nal can optionally cause control interrupts on either edge. pwe (output) made active by a write to address 800000b0, this signal is used to latch the data bus for outgoing (peripheral-to-host) transmission. mode-allocated pio lines extended ieee-1284 modes require dedicated control signal lines for their operation. some of these lines ap- pear as outputs or are read as inputs from existing pio lines. the function of these pins changes from general- purpose pio to specific-purpose ieee-1284 control line while the api is enabled. when the api is enabled, the api has control of the signal lines. if the api is not en- abled, the pio port has control of the lines. datastrobe/pio6 (output) the datastrobe line causes forward data to be latched in the external forward data latch during ap- propriate modes. this line supplies a strobe pulse with timing dependent upon the current api mode and controlled by the apmode field. init/pio4 (input) the init signal comes via an inverting buffer from ninit/nrevers erequest and can optionally cause control interrupts on either edge. revoe/pio8 (output) the revoe signal is controlled by hardware and is used in byte and ecp modes to force the data latch/ buffer to drive data in the peripheral-to-host direc- tion. this signal is used when the peripheral device has control of the ieee-1284 data bus. because of strict ieee-1284 specifications on reinitialization, this signal must be driven directly. selectin/pio5 (input) the selectin line comes via an inverting buffer from nselectin/1284active. it transitions (along with pautofd) to signal the request to negotiate an ieee-1284 mode and to signal the termination from an ieee-1284 mode. this line can optionally cause control interrupts on either edge. software-driven status lines only the signals that are required in hardware for ieee-1284 transfers are included in the mode-allocated pios. other parallel ieee-1284 status lines that are used during status outputs, mode transitions, or slow modes only are driven by software through program- mer-defined parallel lines. pias or pios are acceptable, since these are outputs modified by software only. fault (output) this signal is driven by software and output to nfault/ ndataavail/nperiphrequest. perror (output) this signal is driven by software and output to perror/ackdatareq/nackreverse. select (output) this signal is driven by software and output to select/ xflag.
amd a d v a n c e i n f o r m a t i o n 45 AM29202 microcontroller table 8. ieee-1284 parallel interface signal names by mode AM29202 microcontroller signal name 1 signal names as specified in ieee std 1284-1994 si gna l n ame 1 (inverted from ieee-1284 bus interface) compatibility mode nibble mode byte mode ecp mode pstrobe nstrobe e hostclk hostclk pautofd nautofd hostbusy hostbusy hostack selectin nselectin 1284active 1284active 1284active init ninit e e nreverserequest id7id0 data8data1 e data8data1 3 data8data1 3 pack nack ptrclk ptrclk periphclk pbusy busy ptrbusy/ data4, data8 ptrbusy periphack perror perror ackdatareq/ data3, data7 ackdatareq nackreverse select select xflag/ data2, data6 xflag xflag fault nfault ndataavail/ data1, data5 ndataavail nperiphrequest datastrobe 2 datastrobe e e datastrobe 4 revoe 2 e e revoe revoe 5 notes: 1. the primary form of reference in this data sheet is to the AM29202 microcontroller signal name at the pin, shown in all upper case letters. to facilitate reference to timing diagrams in the ieee-1284 standard document, the inverted ieee-1284 compatibility mode signal name is sometimes shown in parentheses following the AM29202 microcontroller signal name, e.g., pstrobe (nstrobe). 2. these signals are not called out in the ieee-1284 std document. however, they are used on the AM29202 microcontroller in the modes shown. 3. when reversed by revoe, these lines are bidirectional. 4. used on the AM29202 microcontroller in ecp forward mode only. 5. used on the AM29202 microcontroller in ecp reverse mode only.
amd a d v a n c e i n f o r m a t i o n 46 AM29202 microcontroller registers the parallel port interface is controlled through its five registers, which are summarized in table 9. the advanced parallel control (apct) register is used to enable and control the api, to change modes, and to directly or indirectly control operation of the internal hardware. this register can be written with control data, and the status of those bit fields can be read back. the advanced parallel status (apst) register supplies real-time status information on the opera- tion of the api and its incoming and outgoing signals. this register is comprised of three types of signals: status signals from within api hardware, real-time snooping bits of the output and input signals used by the api, and the real-time values of the interruptible condition bits prior to being masked into the ad- vanced parallel interrupt status register (apis). these values are then or'd into the interrupt control (ict) register for the microcontroller via the apci (advanced parallel control interrupt). the apst sig- nals provide access to the status from polling rou- tines or interrupt service. the advanced parallel interrupt mask (apim) register specifies the particular ieee-1284 signal inputs that are combined to cause the next apci in- terrupt; there also exists a mask for the single apdi data interrupt. (in this context, the mask allows the corresponding signal to pass through.) this allows easy programmer control as each ieee-1284 transi- tion occurs. also, a special ecp forward mode command interrupt and a device initialization inter- rupt is included in the interruptible signals. the advanced parallel interrupt status (apis) register reports the apst condition bits that have been masked in the apim register. this register is used by interrupt service routines to determine the condition that caused the latest apci interrupt. writ- ing to this register with a 1 in each appropriate bit position clears the condition latch for each interrupt. also writing to the same bit positions in the apst register clears the same condition bits, thus allow- ing polling routines to easily clear the same bits as interrupt routines would do in the apis. the advanced parallel data (apdt) register is a special register decode that addresses the external data latch. the register does not exist internal to the api; it causes the generation of the poe or pwe sig- nals that read external data, or latch it, respectively. table 9. parallel port register summary register name mnemonic function address advanced parallel control apct reads and writes values of control bits 800000a0 advanced parallel status apst reads interface status; reads interrupt edge bits; clears interrupts 800000a4 advanced parallel interrupt mask apim reads and writes mask bit values 800000a8 advanced parallel interrupt status apis reads enabled interrupt bits and clears interrupts 800000ac advanced parallel data apdt reads external latched parallel input data 800000b0 note: the address assignments for these registers are different from those assigned to the classic port registers on the am29200 and am29205 microcontrollers.
amd a d v a n c e i n f o r m a t i o n 47 AM29202 microcontroller advanced parallel control register (apct, address 800000a0) the advanced port is controlled via the advanced par- allel control register (figure 17). it contains the ap- mode field, dma channel select, and various control bits. all bits read back their written states, except for the afas bit, which reads back 0. bit 31: internal reverse output enable (intrevoe) setting this bit to 1 forces the external signal revoe high. revoe changes the data direction of the external bus buffer/latch device to peripheral-to-host to drive the ieee-1284 bus with data that has been captured from the processor. when the external parallel data direction must be reversed, software can modify this signal on en- tering and exiting different ieee-1284 modes or sub- modes. revoe is disabled by internal hardware when the inter- face receives a device initialization condition (signaled by init and selectin asserted). the return to compatibility mode automatically releases the revoe disable. software should determine and write the proper condition of intrevoe before return- ing to compatibility mode. there is no effect from a device initialization condition if intrevoe is set to 0. bits 3028: reserved bit 27: background status defer (bsd) ebackground status defer is used in nibble mode to disable a portion of the semi-automatic handshaking, allowing status signaling back to the host. while disabled, bsd allows pack (nack) deassertion semi-automatic handshakes to occur with an indefinite number of transfers. when written to a 1, bsd disables the next pack deassertion handshake-completion mechanism. when written to a 0, it releases the automatic handshake, but only after a delay of t ackdelay . this delay allows the re- quired data setup time for status information before al- lowing the pack deassertion to occur. bit 26: advanced full word transfer (afwt) ewhen afwt is set to 0, the data transfer logic will generate one data transfer request per input byte, and the exter- nal apdt will be defined as 8 bits wide. when afwt is set to 1 and the api is set to compatibility or ecp for- ward modes, the data transfer logic will generate a data transfer request cycle every fourth pstrobe (nstrobe), and the external apdt will be defined as 32 bits wide (4 transfers). the processor may read the bc field of the apst regis- ter to determine the number of complete handshakes that have occurred since the last full word transfer. the partial value in bc is cleared by clearing afwt. external logic must be used to concatenate the four for- ward transfer bytes into a single 32-bit big-endian packed word. bit 25: command polarity expected (cpe) ecpe is used with dma in ecp forward mode only to allow data and command bytes to be handled differently. if the command bit received with an ecp data byte does not equal cpe, then apds is asserted and dma is re- quested normally. if the command bit equals cpe, ecs is asserted, and, if masked (enabled), eci will cause an apci interrupt in the ict register. the ecs condition is not cleared auto- matically when the command byte is read; it must be cleared in the apis or apst register. the automatic handshake is not completed when the command byte is read; it is completed only when ecs is cleared. 31 23 15 7 0 intrevoe bsd acklen reserved afwt cpe abc afas apdc dmamode apdhha afack apdhhb afbusy apmode res figure 17. advanced parallel control register
amd a d v a n c e i n f o r m a t i o n 48 AM29202 microcontroller bit 24: asynchronous busy control (abc) eabc is used to force pbusy (busy) asserted, during compati- bility mode only. abc set to 1 forces pbusy asserted. abc set to 0 stops forcing pbusy asserted, and allows pbusy to return to the existing compatibility-mode busy status. whenever the peripheral can no longer ac- cept a byte, this bit is set by software to asynchronously force pbusy asserted. abc is only applicable in compatibility mode; pbusy transitions that are requested in other modes occur nor- mally and are output on pbusy . once the api is re- turned to compatibility mode, the abc-generated (or latch-full-generated) pbusy will still be in effect. bit 23: asynchronous force ack set (afas) eafas is used to generate special pulses during compatibility mode negotiations and delayed pack (nack) assertion edges in nibble mode. afas always reads back 0. in compatibility mode, a write of 1 to afas forces a pack pulse of length t acklen to be generated immedi- ately. this will not normally be required because reading data from the advanced parallel data register will gen- erate a correctly timed pack pulse automatically (whether from an interrupt-driven instruction or from dma). this afas assertion can be used to force a spe- cial pack pulse needed in negotiation. in nibble mode, a write of 1 to afas will cause a delay of length t ackdelay , and then a pack assertion only. a pautofd (nautofd) assertion (normal handshake) from the host then automatically clears the pack status in this mode. bit 22: advanced force busy (afbusy) eafbusy is an optional control bit for the pbusy pin in the ad- vanced port. whenever apdhhb is 1, afbusy set to 1 forces an active level on pbusy and afbusy set to 0 forces an inactive level on pbusy . the polarity from afbusy to pbusy is inverted. this bit should be set to the proper condition before activating apdhhb. afbusy is used when the api is in a mode that does not support hardware handshaking or in a handshaking mode where direct control is required. if apdhhb is 1, afbusy directly controls the level driv- en on pbusy , whether or not the api is active. this al- lows the pbusy pin to be used for an alternate output function if the parallel port is not used. bit 21: advanced port disable hardware handshake busy (apdhhb) ewhen the api is enabled, apdhhb set to 1 transfers control of pbusy to the afbusy (ad- vanced force busy) register bit. apdhhb set to 0 al- lows api hardware handshake logic to control pbusy. the afbusy bit must be set to the proper condition be- fore activating apdhhb. bit 20: advanced force ack (afack) eafack is an optional control bit for the pack pin in the advanced port. whenever apdhha is set to 1, afack set to 1 forces an active level on pack and afack set to 0 forces an inactive level on pack. the polarity from afack to pack is not inverted. this bit should be set to the proper condition before activating apdhha. afack is used when the api is in a mode that does not support hardware handshaking or in a handshaking mode where direct control is required (such as negoti- ation). if apdhha is 1, afack directly controls the level driven on pack, whether or not the api is active. this allows the pack pin to be used for an alternate output function if the parallel port is not used. bit 19: advanced port disable hardware handshake ack (apdhha) ewhen the api is enabled, apdhha set to 1 transfers control of pack to the afack (ad- vanced force ack) register bit. apdhha set to 0 allows api hardware handshake logic to control pack. the afack bit should be set to the proper condition before activating apdhha. when apdhha is 1, the internal pack logic will not start a pack cycle (delayed or pulsed). this allows transi- tions back to internal pack control without spurious pulses. for this reason, apdhha should only be cleared when returning to compatibility mode. bit 18: dma mode (dmamode) edmamode con- trols which mechanism services a data transfer request condition (apds) for modes that feature hardware handshaking. when set to 1, dma transfers are enabled to a channel selected by the apdc field. when set to 0, dmamode enables interrupts on apdi (if masked). bits 1716: advanced port dma channel select (apdc) eapdc selects the dma channel used to re- quest a data transfer. if the api is enabled, dmamode is set to 1, and a data transfer request (apds) occurs, then the dma request of channel specified by the apdc field will be asserted. apdc channel apdc1 apdc0 channel 0 0 0 channel 1 0 1 reserved 1 x bits 158: ack length/ack delay (acklen/ackde- lay) ethis field has two contexts: acklen in compat- ibility mode and ackdelay in all reverse modes. the period of time represented by this field is measured in memclk cycles and is proportional to clock speed.
amd a d v a n c e i n f o r m a t i o n 49 AM29202 microcontroller in compatibility mode, acklen is the length of the pack (nack) pulse generated by the automatic hand- shakes (or when afas is asserted for manual pack control). when a data byte is read from the apdt regis- ter or afas is written to a 1, a pulse is generated auto- matically on the pack output of length t acklen . for proper operation, this field's minimum count is 1, and the maximum is 255. in reverse modes, when a data byte is read or when afas is written to a 1, pack is asserted after a delay of length t ackdelay . ackdelay is the delay value from the time data is written to the advanced parallel data register to the time the pack signal is generated (signaling data transfer) automatically in hardware. it provides a minimum data setup time from when data is output to when the pack active edge signals the host that the transfer is ready. the minimum value specified for this time in the ieee standard is 500 ns. the number of cycles that this value represents will vary with the pro- cessor clock frequency. bit: 7 reserved bits 60: advanced parallel mode (apmode) ethe value in apmode (see table 10) sets the operating mode of the api including all the automatic functions, such as data transfer request timing, pack pulse delay and length timing, datastrobe source, pio alloca- tion, dma direction, and pbusy (busy) context changes. the mode selected will remain in effect until changed. mode changes are immediate when written. apmode is cleared at reset time. when set to 0, the api is disabled, and the pio port has control of the shared signal lines. interrupts from the api are disabled when apmode is 0, whether their individu- al masks are set or not. the hl and lh status conditions for init, selectin, pstrobe, and pautofd are not available in the apst register when apmode is 0. table 10. apmode values apmode mode description handshake mode dma support pios allocated 0 disabled none none none 1 compatibility mode automatic yes init/pio4 selectin/pio5 datastrobe/pio6 2 nibble mode (and id) semi- automatic no init/pio4 selectin/pio5 3 byte mode (and id) automatic yes init/pio4 selectin/pio5 revoe/pio7 4 ecp forward mode automatic yes init/pio4 selectin/pio5 datastrobe/pio6 5 ecp reverse mode (and id) automatic yes init/pio4 selectin/pio5 revoe/pio7
amd a d v a n c e i n f o r m a t i o n 50 AM29202 microcontroller advanced parallel status register (apst, address 800000a4) the status bits for the real-time signals used in commu- nication and negotiation are available in the advanced parallel status register (figure 18). all edge-detection and other control condition status bits for use in polling or interrupting can be read in this regis- ter, along with the data transfer status bit. these include the eight different control input signal conditions: high- to-low and low-to-high edge detection for each of the signals pstrobe, pautofd, selectin, and init; the ecp command condition, the device initialization condition, and the data transfer request condition. all condition status bits (bits 15-0) are reset-only. writing a 1 clears the condition, and writing a 0 does not affect the bit. writing to read-only status does not affect the bits. the hl and lh status conditions for init, selectin, pstrobe, and pautofd are not available in the apst register when apmode is 0. bit 31: pbusy ethis is the real-time value of the outgo- ing pbusy signal. this signal directly follows the pbusy pin. bit 30: pack ethis is the real-time value of the outgo- ing pack signal. this signal directly follows the pack pin. bit 29: init ethis is the real-time value of the init input pin. init is input to the device on pio4. bit 28: selectin ethis is the real-time value of the selectin input pin. selectin is input to the device on pio5. bit 27: pautofd ethis is the real-time value of the pautofd input pin. bit 26: pstrobe ethis is the real-time value of the pstrobe input pin. bits 2522: reserved bits 2120: byte count (bc) ewhen afwt is set to 1, the byte count field contains the number of bytes that have been received by the external logic for concatena- tion into a full-word transfer. this count is useful in han- dling partial-word transfers, such as data streams that are a non-afwt modulo length, or when an ecp com- mand occurs. bc is a read-only field and is cleared when afwt is cleared. bits 1916: reserved bit 15: advanced port data transfer status (apds) eapds signals the readiness for a byte (or full word, if afwt is set to 1) of data to be transferred, irre- spective of the data transfer method programmed, and may be polled. if dmamode is 0 and apdm is 1, then apdi is asserted and an apdi interrupt occurs in the ict register. (note that there is no apdi bit in the advanced parallel inter- rupt status register; an apds assertion masked by apdm causes an apdi interrupt in the ict directly.) if dmamode is 1 and apds is 1, then a dma request will be made to the channel specified by the apdc bit. writing a 1 to this bit will clear the data transfer request condition, although this is normally not recommended, since the data transfer request will be cleared automati- cally when data is read or written to the advanced paral- lel data register. clearing the apds bit when dmamode is true is undefined and not recommended. bit 14: ecp command status (ecs) eecs signals an ecp forward mode command byte within the data stream. this condition blocks the completion of the ecp forward data handshake to allow the processor time to interpret the command before more data is accepted. this handshake is held off only for command bytes; data bytes are transferred via apdi or dma. 31 23 15 7 0 reserved bc ecs apds reserved reserved devinits pstrobe pautofd selectin init pack pbusy inithls initlhs selinhls selinlhs pautohls pautolhs pstbhls pstblhs figure 18. advanced parallel status register
amd a d v a n c e i n f o r m a t i o n 51 AM29202 microcontroller this bit causes an eci interrupt bit to be asserted when the ecm bit is set to 1. writing a 1 to this bit will clear the ecs condition and allow the ecp forward data hand- shake to proceed. bit 13: device initialization status (devinits) ethis bit signals that the host has initiated an initialization cycle. the ieee-1284 specification requires that the in- terface proceed immediately to compatibility mode, ac- complished by software upon the deviniti interrupt. this bit causes a deviniti interrupt bit to be asserted when the devinitm bit is set to 1. (revoe is also cleared immediately in hardware.) writing a 1 to this bit will clear the devinits condition, but is not needed typi- cally, as the condition is cleared when the interface is re- turned to compatibility mode. bits 128: reserved bit 7: init high-to-low edge detection status (inithls) einithls signals that the init signal has changed from high-to-low (ninit has gone from low-to- high). this bit causes an inithli interrupt bit to be as- serted when the inithlm bit is set to 1. writing a 1 to this bit will clear the inithls condition. bit 6: init low-to-high edge detection status (initlhs) einitlhs signals that the init signal has changed from low-to-high (ninit has gone from high-to- low). this bit causes a initlhi interrupt bit to be as- serted when the initlhm bit is set to 1. writing a 1 to this bit will clear the initlhs condition. bit 5: selectin high-to-low edge detection status (selinhls) eselinhls signals that the selectin signal has changed from high-to-low (nselectin has gone from low-to-high). this bit causes a selinhli in- terrupt bit to be asserted when the selinhlm bit is set to 1. writing a 1 to this bit will clear the selinhls condi- tion. bit 4: selectin low-to-high edge detection status (selinlhs) eselinlhs signals that the selectin signal has changed from low-to-high (nselectin has gone from high-to-low). this bit causes a selinlhi in- terrupt bit to be asserted when the selinlhm bit is set to 1. writing a 1 to this bit will clear the selinlhs condi- tion. bit 3: pautofd high-to-low edge detection status (pautohls) epautohls signals that the pautofd signal has changed from high-to-low (nautofd has gone from low-to-high). this bit causes a pautohli interrupt bit to be asserted when the pautohlm bit is set to 1. writing a 1 to this bit will clear the pautohls condition. bit 2: pautofd low-to-high edge detection status (pautolhs) epautolhs signals that the pautofd signal has changed from low-to-high (nautofd signal has gone from high-to-low). this bit causes a pautolhi interrupt bit to be asserted when the pautolhm bit is set to 1. writing a 1 to this bit will clear the pautolhs condition. bit 1: pstrobe high-to-low edge detection status (pstbhls) epstbhls signals that the pstrobe signal has changed from high-to-low (nstrobe signal has gone from low-to-high). this bit causes a pstbhli interrupt bit to be asserted when the pstbhlm bit is set to 1. writing a 1 to this bit will clear the pstbhls condi- tion. bit 0: pstrobe low-to-high edge detection status (pstblhs) epstblhs signals that the pstrobe signal has changed from low-to-high (nstrobe signal has gone from high-to-low). this bit causes a pstblhi interrupt bit to be asserted when the pstblhm bit is set to 1. writing a 1 to this bit will clear the pstblhs condi- tion.
amd a d v a n c e i n f o r m a t i o n 52 AM29202 microcontroller advanced parallel interrupt mask register (apim, address 800000a8) the advanced parallel interrupt mask register (figure 19) contains the interrupt mask bits for each condition status bit in the apst register. when a mask bit is set to 1, it enables the corresponding condition status bit in the apst register into the corresponding interrupt status bit of the apis register. when the mask bit is set to 0, the corresponding interrupt status bit is 0. the mask reg- ister is read/writeable. all interrupt status bits in the apis are or'd together to form the aggregate advanced parallel control interrupt in the ict register. interrupts from the api are disabled when the apmode is 0, whether their individual masks are set or not. note that the apdm mask controls assertion of the apdi inter- rupt, while all other mask bits control the apci interrupt. bits 3116: reserved bit 15: advanced port data transfer interrupt mask (apdm) ewhen apdm is set to 1, an assertion of the apds bit directly causes an apdi interrupt in the ict register. when apdm is set to 0, there is no apdi inter- rupt. bit 14: ecp command interrupt mask (ecm) ewhen ecm is set to 1, an assertion of the ecs bit sets the eci interrupt bit, causing an apci interrupt. when emc is 0, the eci interrupt bit is not set. bit 13: device initialization interrupt mask (devinitm) ewhen devinitm is set to 1, an assertion of the devinits bit sets the deviniti interrupt bit, causing an apci interrupt. when devinitm is 0, the deviniti interrupt bit is not set. bits 128: reserved bit 7: init high-to-low interrupt mask (inithlm) when inithlm is set to 1, an assertion of the inithls bit sets the inithli interrupt bit, causing an apci interrupt. when inithlm is 0, the inithli interrupt bit is not set. bit 6: init low-to-high interrupt mask (initlhm) when initlhm is set to 1, an assertion of the initlhs bit sets the initlhi interrupt, causing an apci inter- rupt. when initlhm is set to 0, the initlhi interrupt bit is not set. bit 5: selectin high-to-low interrupt mask (selinhlm) ewhen selinhlm is set to 1, an asser- tion of the selinhls bit sets the selinhli interrupt bit, causing an apci interrupt. when selinhlm is set to 0, the selinhli interrupt bit is not set. bit 4: selectin low-to-high interrupt mask (selinlhm) ewhen selinlhm is set to 1, an asser- tion of the selinlhs bit sets the selinlhi interrupt bit, causing an apci interrupt. when selinlhm is set to 0, the selinlhi interrupt bit is not set. bit 3: pautofd high-to-low interrupt mask (pautohlm) ewhen pautohlm is set to 1, an asser- tion of the pautohls bit sets the pautohli interrupt bit, causing an apci interrupt. when pautohlm is set to 0, the pautohli interrupt bit is not set. bit 2: pautofd low-to-high interrupt mask (pautolhm) ewhen pautolhm is set to 1, an asser- tion of the pautolhs bit sets the pautolhi interrupt bit, causing an apci interrupt. when pautolhm is set to 0, the pautolhi interrupt bit is not set. bit 1: pstrobe high-to-low interrupt mask (pstbhlm) ewhen pstbhlm is set to 1, an assertion of the pstbhls bit sets the pstbhli interrupt bit, causing an apci interrupt. when pstbhlm is set to 0, the pstbhli interrupt bit is not set. bit 0: pstrobe low-to-high interrupt mask (pstblhm) ewhen pstblhm is set to 1, an assertion of the pstblhs bit sets the pstblhi interrupt, causing an apci interrupt. when pstblhm is set to 0, the pstblhi interrupt bit is not set. 31 23 15 7 0 reserved ecm apdm reserved devinitm inithlm initlhm selinhlm selinlhm pautohlm pautolhm pstbhlm pstblhm figure 19. advanced parallel interrupt mask register
amd a d v a n c e i n f o r m a t i o n 53 AM29202 microcontroller advanced parallel interrupt status register (apis, address 800000ac) the advanced parallel interrupt status register (figure 20) contains the masked condition bits that make up the aggregate advanced parallel control interrupt in the ict register. the bits can be read to determine the source of the interrupt, and each bit can be written to a 1 to clear the corresponding condition and condition bit (writing to the condition bit in the apst register per- forms the same function). the apci is generated when the logical or of all control interrupt status bits is 1. bits 3116: reserved bit 15: reserved ethere is no apdi interrupt in the apis. since there is only one data transfer interrupt, it asserts the apdi bit in the ict register directly. the apds condition can be cleared in the apst register. bit 14: ecp command interrupt (eci) ethis interrupt bit indicates that an ecp forward command has been received. when this bit is a 1, the apci interrupt occurs. writing a 1 to this bit clears the ecs and eci conditions and releases the ecp forward handshake, allowing more ecp data or command bytes to be received. bit 13: device initialization interrupt (devini- ti) ewhen this bit is a 1, the apci interrupt occurs. when deviniti is written to a 1, the devinits and deviniti bits are cleared. bits 128: reserved bit 7: init high-to-low interrupt (inithli) ewhen this bit is a 1, the apci interrupt occurs. when inithli is written to a 1, inithls and inithli are cleared. bit 6: init low-to-high interrupt (initlhi) ewhen this bit is a 1, the apci interrupt occurs. when initlhi is written to a 1, initlhs and initlhi are cleared. bit 5: selectin high-to-low interrupt (selinhli) when this bit is a 1, the apci interrupt occurs. when selinhli is written to a 1, selinhls and selinhli are cleared. bit 4: selectin low-to-high interrupt (selinlhi) when this bit is a 1, the apci interrupt occurs. when selinlhi is written to a 1, selinlhs and selinlhi are cleared. bit 3: pautofd high-to-low interrupt (pautohli) when this bit is a 1, the apci interrupt occurs. when pautohli is written to a 1, pautohls and pautohli are cleared. bit 2: pautofd low-to-high interrupt (pautolhi) when this bit is a 1, the apci interrupt occurs. when pautolhi is written to a 1, pautolhs and pautolhi are cleared. bit 1: pstrobe high-to-low interrupt (pstbhli) when this bit is a 1, the apci interrupt occurs. when pstbhli is written to a 1, pstbhls and pstbhli are cleared. bit 0: pstrobe low-to-high interrupt (pstblhi) when this bit is a 1, the apci interrupt occurs. when pstblhi is written to a 1, pstblhs and pstblhi are cleared. 31 23 15 7 0 reserved eci reserved reserved deviniti inithli initlhi selinhli selinlhi pautohli pautolhi pstbhli pstblhi figure 20. advanced parallel interrupt status register
amd a d v a n c e i n f o r m a t i o n 54 AM29202 microcontroller 31 23 15 7 0 reserved apdata 31 23 15 7 0 apdata a. b. figure 21. advanced parallel data register advanced parallel data register (apdt, address 800000b0) the advanced parallel data register (figure 21) is used to read data from and write data to the parallel port. this register is not implemented directly on the proces- sor, but must be implemented by the user as an external bidirectional data latch. writing to the apdt address causes a decoded pwe output to write the current bus data byte or word to an external data register. reading from the apdt ad- dress causes a decoded poe output to read data from the external data register to the data bus. the decoder operates even when the api is disabled. reading data from or writing data to the apdt automati- cally causes data transfer requests to be cleared and continues the appropriate handshake for the current mode, except in nibble mode. bits 70: advanced port parallel data (apdata) for 8-bit transfers (figure 21a) or bits 310: advanced port parallel data (apdata) for 32-bit transfers (figure 21b)eapdata contains packed-byte data being transferred to the processor and from the ieee-1284 parallel bus. the register must exist external to the processor. the width of the field is dependent on the afwt bit. afwt is valid in compati- bility and ecp forward modes only. the instruction or dma channel must be programmed for the proper width access to read the apdt correctly. initialization during a processor reset, the apmode field is set to 0, disabling parallel port interrupts and giving control of the shared pio signals (pio7/revoe, pio6/data- strobe, pio5/selectin, and pio4/init) to the pio port. in the apct register, all fields are set to 0 except afbusy, apdhhb, and acklen. afbusy and apdhhb are set to 1, forcing pbusy (busy) low. the acklen field is set to all 1s. in the apst register, the pstblhs, pstbhls, pautolhs, pautohls, selinlhs, selinhls, initlhs, inithls, apds, ecs, and devinits bits are set to 0. in the apim register, all interrupt masks are set to 0. the poct, pin, poen, and pout registers must be configured before the parallel interface is enabled. bits 6 and 7 of the poen field must be set to 1; bits 4 and 5 of the poen field must be set to 0. the parallel port inter- face can then be programmed incrementally, as re- quired; there is no need to disable the interface before writing other registers.
amd a d v a n c e i n f o r m a t i o n 55 AM29202 microcontroller controlling the parallel port interface the api has been designed to allow easy access to in- put status information using a variety of software strate- gies, including polling, interrupt service, and dma. in its advanced parallel status (apst) register, the api reports a number of conditions that show either signal transitions or a data transfer request. these control and data transfer condition bits may be read and manipu- lated by software to control the operation of the parallel port interface (see figures 22 and 23). eight of the condition bits are generated directly from ex- ternal signal edges. the list below shows the signals whose edges are detected and that have corresponding edge-detection conditions in the apst register. these input signals have one condition for high-to-low transi- tions, and one for low-to-high. in general, pstrobe signals a forward data strobe. pautofd signals a reverse data strobe. selectin signals 1284active. init signals an ecp mode transition request or an initialization request. the other conditions in the control group are the ecs and devinits. the ecs condition signals a command byte during an ecp transfer. the devinits is a signal generated when the host wants to asynchronously rein- itialize the peripheral and set it back to compatibility mode. the apds condition bit signals the status of a data transfer request. apds indicates when a hardware handshake-supported data transfer mode receives (or is ready to transmit) a data byte. polling the condition bit values in the apst register can be used to request service for the conditions by polling from the support software. the specific condition can be cleared by writing a 1 to the corresponding condition bit in the apst register. interrupts if the particular condition requires faster response than polling can accomplish, an interrupt can be generated. there are two types of api interrupts: control and data transfer. each is supported with its own interrupt struc- ture. the control (apci) and data transfer (apdi) inter- rupts appear separately in the interrupt control (ict) register, allowing separate interrupt handlers for mode transition and data handling. the advanced parallel interrupt mask register (apim) specifies the particular ieee-1284 signal inputs that are combined to cause the next apci interrupt. there also exists a mask (enable bit) for the single apdi data trans- fer interrupt. this allows easy programmer control as each ieee-1284 transition occurs. to generate an interrupt, the corresponding mask bit in the advanced parallel interrupt mask register (apim) for each condition must be set. when a condition bit is true and its mask is set, the corresponding interrupt flag is asserted in the advanced parallel interrupt status register (apis). this register is used by interrupt ser- vice routines to determine the condition that caused the latest apci interrupt. all control condition interrupts and status bits must be reset manually, except for the devinit status/interrupt bits, which are cleared auto- matically on entering compatibility mode. data transfers once a communications mode that supports full hard- ware handshaking is entered, polled apds data trans- fer request bits, apdi interrupts, or dma requests will cause a move of data from the advanced parallel data (apdt) register to memory in forward modes, and from memory to the apdt for reverse modes. the advanced parallel data register is a special register decode that addresses the external data latch. the register does not exist internal to the api; it causes the generation of the poe or pwe signals that read external data, or latch it, respectively. in semi-automatically handshaked modes such as nibble mode, data is handled by a combination of apdi and apci interrupts. data transfer requests, whether serviced by polling, in- terrupts, or dma, are cleared automatically when the data is transferred (read or written); normally apds need not be cleared by software directly. figure 24 shows the timing of an external access. this external access is treated as either a dma access or a processor pia access for the purpose of prioritization with other accesses. figure 25 shows the timing for a buffer write. data interrupts the dmamode bit controls whether the data transfer request status bit (apds) causes an apdi data inter- rupt (if masked) or a dma request. when the data transfer condition bit apds is set to sig- nal a data transfer, when dmamode is 0, and when the data transfer interrupt mask bit apdm is 1, then the apdi interrupt bit in the ict register is set, interrupting the processor for a data transfer.
amd a d v a n c e i n f o r m a t i o n 56 AM29202 microcontroller figure 22. example: using a control status condition to generate an interrupt in compatibility mode pstrobe true edge (when apmode = 1 for compatibility mode) apst register 0 pstblhs 1 1 2 automatically sets the condition status bit pstblhs (available for polling). apim register 0 pstblhm 1 1 2 if the pstblhm mask bit is written to a 1, apis register 0 pstblhi 1 1 2 then a pstblhi interrupt ict register 11 apci 1 12 13 generates an apci interrupt. condition latch pstblhm control interrupt mask all other control interrupt bits inputs that cause condition apci interrupt pstblhs condition status pstblhi condition interrupt pstrobe true edge note: this example chain of events, based on pstrobe true edge, is true for compatibility mode when the value of apmode is set to 1.
amd a d v a n c e i n f o r m a t i o n 57 AM29202 microcontroller figure 23. example: using the data status condition in compatibility mode pstrobe true edge, signaling that data is available (when apmode = 1 for compatibility mode), 15 apds 1 16 17 automatically sets the condition status bit apds in the apst register (available for polling). 15 apdm 1 16 17 if the dmamode is written to a 0 and the apdm mask bit in the apim register is written to a 1, 12 apdi 1 13 14 then an apdi interrupt is generated in the ict register. apct register 18 dmamode 19 dmamode = 0 dmamode = 1 dma transfer occurs to a channel selected by the apdc field. no interrupt is generated, no matter the value of apdm. the type of access is set by the status of the dma controller. apdc 1716 note: this example chain of events, based on pstrobe true edge, is true for compatibility mode when the value of apmode is set to 1. condition latch apdm data transfer request interrupt mask inputs that cause data transfer request apdi interrupt apds condition status dma channel selector pstrobe true edge 0 1 dmamode
amd a d v a n c e i n f o r m a t i o n 58 AM29202 microcontroller data memclk a21a0 id7id0 or id31id0 poe pwe figure 24. advanced parallel port buffer read cycle for forward transfers note: please refer to ieee std 1284-1994 for complete timing requirements, transition event descriptions, and timing diagrams specific to the standard. memclk a21a0 id7id0 poe pwe data figure 25. advanced parallel port buffer write cycle for reverse transfers dma in all modes except nibble, data handling can also be supported with dma. when a data transfer condition (apds) is set and dmamode is 1, the apdi is not as- serted and a dma transfer request is issued instead. the apdc field selects a particular dma channel to re- quest. a special command interrupt allows separate handling of ecp-forward-mode commands in the dma data stream. full-word transfer a faster mode of data transfer in the forward direction is the full-word transfer. full-word transfers are valid only in compatibility and ecp forward modes. this feature allows the designer to latch input data into four external latches and to read the full word from the apdt at one time, reducing the demand placed on the processor and reducing bus bandwidth requirements. external hardware is used in full-word transfer systems to latch and concatenate the separately strobed data bytes into a 32-bit word. then, (in full-word transfer mode) when a 32-bit word has been assembled, the api automatically issues a single data request for the entire
amd a d v a n c e i n f o r m a t i o n 59 AM29202 microcontroller word. it does not issue data transfer requests for the in- tervening bytes; in fact, it acknowledges them without delay, speeding up the transfer greatly. it is inadvisable to read the external apdt register be- fore receiving a data byte, whether in afwt mode or not. in either case, a data byte may be lost. resetting the external byte counter for afwt operation whenever the apdt is read will guarantee synchronization through ecp command intervention. ecp commands ecp mode supports several advanced features to im- prove the effectiveness of the protocol for applications such as raster image devices. these include support for multiple channels of 8-bit bidirectional transfers, as well as support for compression using run-length encoding. to distinguish between commands and data, the con- text of the ecp forward data stream may be modified by the status of the pautofd (nautofd) signal at transfer time. this bit is known as the command bit. the ieee-1284 standard calls for optional changes in pe- ripheral handling of the data stream when the status of the command bit changes. these changes are com- pletely application-specific and are optional. the api on the AM29202 microcontroller provides three different features to facilitate automatic handling of com- mand conditions in ecp forward mode. these include: automatic hold-off of the data transfer mechanism by not asserting apds on the affected command byte. generation of a specialized command status (that can be masked to cause a command interrupt) called ecs (ecp command status). a way to set the expected polarity of the command bit that should cause the ecs condition. this bit is called cpe (command polarity expected). when the command bit (status of pautofd) is the same as cpe, the command status is set (ecs is as- serted; if masked, eci occurs). at this point, the normal data transfer request is disabled and does not occur. the data that is modified by the command bit must be handled by a separate command handler. even when the command data is read, the normal data handshake does not occur. this allows the peripheral to read the byte value and accomplish any actions that the com- mand implied, before allowing the data stream to restart. the data stream will restart and continue automatically when the interrupt handler clears the ecs condition (by writing a 1 to the ecs or eci bits). using full-word transfer with ecp commands when a command occurs during an ecp full-word transfer stream, the pending data count is ignored and the ecp command status (and if masked, an ecp command interrupt) bit is asserted. the software must utilize the byte count (bc) field to determine the actual location of the command within the full word being cap- tured and the amount of external data that is valid. then, a read of the apdt captures the partial word in the em- bedded command. the current (command) byte will not be handshaked un- til the ecs/eci status is cleared. however, this proce- dure should not be accomplished until the command has been interpreted, the remaining data left in the full word distributed to the appropriate buffer, and the bc field cleared. the bc field is cleared by clearing the afwt bit. the remaining full-word data requires that the afwt bit be set again and the dma controller addresses be reset for the new buffer locations affected by the intervening command. finally, the ecs bit is cleared to allow the in- terface to continue with the next afwt data byte.
amd a d v a n c e i n f o r m a t i o n 60 AM29202 microcontroller mode selection changing modes successfully involves performing two different kinds of operations in software: selecting an ieee-1284 mode and communicating that choice back to the host. setting up the AM29202 microcontroller's internal hardware to support the negotiated mode. communicating a mode choice to the host although the ieee-1284-compliant host initiates mode change requests, it is the software on the peripheral side that selects which mode the peripheral will support. when the peripheral receives a request (along with an ieee-1284 extensibility byte) from the host to enter a specific mode, the software evaluates the request and signals the host when the requested mode is one that the peripheral will support. this procedure is well docu- mented in ieee std 1284-1994 with phase transition diagrams, descriptions of signal transition events, and timing diagrams. configuring the api to support a negotiated mode setting up the AM29202 microcontroller hardware to support the negotiated mode is accomplished by writing a value to the apmode field in the apct register. the value of apmode (see table 10) tells the microcon- troller to interpret incoming and outgoing signals ac- cording to handshaking protocols particular to each mode. it also sets other functions, such as the allocation of pios and dma direction. note that setting apmode is completely independent of the mode negotiation process. the host and peripheral negotiate for a mutually acceptable mode, which may or may not match the current apmode setting. the pro- grammer must reset apmode at various times during negotiation into and out of the modes: immediately after the interrupt for negotiating to another mode is received, apmode should be set for compatibility mode. immediately before negotiation is ended, apmode should be set to the desired value for the new mode. when data-direction-change interrupts occur (from ecp forward to reverse, or ecp reverse to for- ward), apmode should be set for the appropriate submode. as a general rule, the desired apmode setting should not be enabled before the programmer is completely ready for the AM29202 microcontroller hardware to be- gin interpreting inputs according to the automatic hand- shake protocols for that particular mode. software control of handshaking if desired, the programmer can turn off all automatic handshaking and take direct control of all aspects of the api interface. register fields provide complete access to all the required controls to operate the parallel inter- face using software alone. when set to 1, the apdhha and apdhhb bits in the apct register turn over direct control of the pack and pbusy outputs to the afack and afbusy bits. the apds field contains all real-time input values. when the apmode field in the apct register is set to 0, no preset operating mode is defined. although the lh and hl status conditions for pstrobe, pau- tofd, selectin, and init are not available in the apst register when apmode is 0, the real-time status of these signals, as well as those for pbusy and pack, is available.
amd a d v a n c e i n f o r m a t i o n 61 AM29202 microcontroller using software in ieee-1284 modes the api hardware provides a rich set of controls that gives the programmer maximum flexibility. if desired, most of the api operation (except for negotiation) can be automatic. the programmer need only set up a few con- trols for the AM29202 microcontroller hardware to han- dle most handshakes automatically. the key to this control is the apci interrupt, generated on the edges of the four protocol signals and on the ecp command and device initialization conditions. this in- terrupt is used to manage mode changes, negotiation, and termination. application software must modify the advanced parallel interrupt mask register at each stage of an ieee-1284 transition, selecting the edges required for the next possible interrupts, as well as doing the work required at that phase transition. this section presents some minimal programming suggestions, not necessarily complete or in sequence, to differentiate between what happens automatically in the AM29202 microcontroller hardware and what should be programmed in software. the programmer should use the ieee std 1284-1994 document as the authoritative reference source. table 11, ausing control status conditions in ieee-1284 modes,o is presented to facilitate reference back and forth between the two doc- uments. compatibility mode this mode is the first, and most basic, of the ieee-1284 modes. it is similar to the classic (centronics) port in timing. the api interface should always be initialized to com- patibility mode by software. this is the default ieee-1284 communications mode for all hosts and pe- ripherals. this mode is maintained until the host has successfully verified that it is connected to an ieee-1284-compliant device. from compatibility mode, the host can either negotiate with the peripheral for another mutually supported mode or transmit data to the peripheral using compatibility mode. a peripheral-to-host transfer is requested by the host, negotiating with the peripheral for a mutually sup- ported communication mode. at the direction of the host, the api interface can be returned to compatibility mode at any time. in compatibility mode (apmode set to 1), the api inter- face provides automatically-handshaked data transfers with polling, interrupt, or dma support for forward byte (or full-word) transfers. automatic handshakes the api generates automatic handshakes in compati- bility mode as follows: on pstrobe (nstrobe) true edge, the pbusy (busy) signal goes active and the data transfer request bit (apds) is driven true. the datastrobe line is pulsed automatically when pstrobe is asserted. this causes the external low-to- high-triggered data latch to capture the data on the ac- tive edge of pstrobe. pack (nack) is driven true when data is read from apdt register, for a pulse length of t acklen . pbusy is set false when pack is set false (the pulse is completed). pautofd (nautofd) status is available in the apst register. the acknowledge length (acklen) field in the apct register sets the length of the pack pulse generated by the automatic handshakes. in software: set the acklen field to an appropriate length of time in memclk cycles. the ieee standard calls out a minimum pack (nack) pulse width of 500 ns, but a longer one may be desired. the acklen field can be programmed from 1 to 255 cycles in length. data transfers data transfer is requested on pstrobe (nstrobe) go- ing active. this sets the apds bit, for polling. to program interrupt-driven data transfers: set the apdm mask bit and clear dmamode, caus- ing an apdi interrupt in the ict register whenever the apds is set. no dma request will be issued. to enable dma transfers: set the dmamode bit to 1, causing a dma request to the channel set in the apdc field. no apdi is gen- erated, irrespective of the status of apdm. preventing deadlocks during data transfer deadlocks can occur when the forward channel has stalled because it is full and the host is requesting status information on the reverse channel. when using for- ward-channel data transfers in compatibility mode, the programmer should set up certain controls to ensure that clogging in the forward-channel does not preclude negotiation into a reverse mode. in order to prevent deadlocks, the programmer should be aware of what is happening with the internal buffer at all times. setting up an internal busy length that can be detected by the application allows software to determine when the internal buffer is nearing full. there should be enough space left over in the internal buffer so that, even though the internal process is shown as busy, an apds interrupt will still be accepted for the last byte. the last byte can then be rescued out of the external register and stuck on the end of the buffer, even though it is internally thought of as full. note that this requires the programmer to make a dis- tinction between an external busy, where the api is tech- nically busy (abuffer-fullo busy), and an internal
amd a d v a n c e i n f o r m a t i o n 62 AM29202 microcontroller status bit name in AM29202 microcontroller's apst register apst bit mnemonic signal state as shown on timing diagrams in ieee std 1284-1994 compatibility mode byte and nibble modes ecp mode pstblhs pstbhls pautolhs pautohls selinlhs selinhls initlhs inithls nstrobe true edge nstrobe false edge nautofd true edge nautofd false edge nselectin true edge nselectin false edge ninit true edge ninit false edge pstrobe low-to-high (true) edge detection status pstrobe high-to-low (false) edge detection status pautofd low-to-high (true) edge detection status pautofd high-to-low (false) edge detection status selectin low-to-high (true) edge detection status selectin high-to-low (false) edge detection status init low-to-high (true) edge detection status init high-to-low (false) edge detection status hostclk false edge hostclk true edge hostbusy false edge hostbusy true edge 1284active false edge 1284active true edge ninit true edge ninit false edge hostclk false edge hostclk true edge hostack false edge hostack true edge 1284active false edge 1284active true edge nreverserequest true edge nreverserequest false edge table 11. using control status conditions in ieee-1284 modes note: the lh and hl designations refer to the signal at the AM29202 microcontroller, inverted from the ieee-1284 bus.
amd a d v a n c e i n f o r m a t i o n 63 AM29202 microcontroller application-supported busy, where the application de- cides that no more data is going to be accepted for a period of time. in this situation, the advanced forced busy (afbusy) bit in the apct register can be used to control the pbusy pin for the external busy condition. the asynch- ronous busy control (abc) bit is used for the internal busy condition, to asynchronously force pbusy as- serted when the application needs to appear busy. when set, abc will throttle the host during those periods when the internal buffer is nearing full and the applica- tion wants the peripheral to appear busy. a simple way of preventing deadlocks is to: set abc asserted at any time to throttle host data. in- terrupts received for negotiation may continue to be accepted. enabling negotiation to another mode to enable ieee-1284 negotiation, in software: set selectin false-edge interrupt mask (selinhlm) and pautofd true-edge interrupt mask (pautolhm) to cause interrupts for transition to ieee-1284 negoti- ation mode. (such a transition normally happens only in the forward idle state.) when either interrupt occurs, check for real-time status of the other status value to signal the negotiation request. negotiation phase in amd's implementation of the ieee-1284 standard on the AM29202 microcontroller, the process of negotiation between host and peripheral for a mutually acceptable mode is handled completely by software. the basic steps of the negotiation process are always the same, no matter what mode is the final target or how many times the same negotiation has already occurred. the complete negotiation process is thoroughly de- scribed in ieee std 1284-1994. this section presents some minimal software recommendations that apply specifically to amd's implementation of the standard. negotiation starts from the selectin (nselectin) false- edge interrupt where pautofd is true, or from the pautofd true-edge interrupt where selectin is false. during negotiation, the software should take direct con- trol of the pack (nack) and pbusy (busy) status lines. on assertion of apdhha, pack internal status will be cleared, and pack will not be automatically generated in hardware. in software: set apdhha and apdhhb true. set the proper sta- tus for signaling ieee-1284 compliancy: perror (perror) true, pack (nack) true, fault (nfault) false, and select (select) true. to ensure that the forthcoming extensibility byte is not interpreted as data, disable data transfers by clearing the apdm and dmamode bits. clear the selinhlm and pautolhm bits, set the pstblhm bit, and return from interrupt. once in negotiation mode, the pstrobe high-to-low interrupt signals an extensibility byte on the data latch. in software: set the pstrobe false-edge interrupt mask (pstbhlm). at that interrupt, read the extensibility byte in the apdt register and determine if the mode can be supported (or, if the peripheral chooses to support it). apds is cleared automatically. set the status lines for the mode selected. set inter- nal pbusy status. set perror false and set fault (nfault) true if peripheral-to-host data is available. set the select (xflag) line to its ap- propriate value (corresponding to the extensibility feature requested), indicating approval for that mode. set apmode to the correct value for the new mode. before ending negotiation, enable a table of actions in the negotiation section of the driver. the applica- ble new mode will require a particular set of interrupt masks, data transfer modes, and status lines to be set. set the pack (nack) line false, ending the negoti- ation. if negotiation fails, the select (select) line is set false, host-to-peripheral busy status is placed on pbusy (busy), peripheral-to-host data available is set on fault (nfault), and pack (nack) is set false. terminating a mode the selinlhm interrupt edge mask should always be set when in any ieee-1284 mode, allowing driver sup- port for mode termination. to enable application-driven termination back to compatibility mode: set the selectin true-edge interrupt mask (selinlhm). at that interrupt, manually complete the valid-state-termination handshake described in the ieee standard and return from interrupt. a new interrupt on selectin false edge can start another negotiation. device id if the negotiated mode is a device id mode, then that mode is entered with data pending to be sent to the host. that data is the device id string, and it is inserted into the data stream ahead of anything else already pending. that mode is ended when the id string has been sent and must terminate for renegotiation.
amd a d v a n c e i n f o r m a t i o n 64 AM29202 microcontroller idle mode if the new mode is a reverse channel mode and there is no data pending (reverse idle mode), then after the sta- tus is latched on pack (nack), the host will either wait at busy, terminate, or force the peripheral into an idle mode. idle mode can be reached by the host assertion of pautofd (nautofd) while the host thinks there is no data available, but the interface need not switch to idle phase. internal data available status will change asynchronously through the application, but the host's knowledge of that status occurs only after it is signaled on fault (nfault) and only after being strobed in with pack (nack). to signal the presence of new reverse data: assert fault and pulse pack. once in idle mode, the interface can either stay in idle, or terminate normally. nibble mode nibble mode provides for slow software-driven reverse- channel communications only. nibble mode is the only one of the supported ieee-1284 modes that requires the programmer to handle data transfers completely in software. in order to set up the lines with status informa- tion in addition to data, the first and second nibbles are handled differently. data is carried on four status lines: fault (nfault), select (select), perror (perror), and pbusy (busy). no data is transferred on the signal lines used for forward-channel data. the forward channel continues to be driven by the host only, allowing unidirectional hosts to have access to a reverse channel. there is semi-automatic hardware handshake support. no dma transfers are available in this mode. selectin (nselectin) true-edge interrupts must be en- abled for application-driven termination back to com- patibility mode. the datastrobe line is not activated, once in this mode. data transfers all data transfers are signaled via apds status (and if masked, apdi interrupts) and are handled from soft- ware control. semi-automatic handshakes are gener- ated in this mode. to signal acknowledgment of data, pack (nack) is automatically deasserted on the deassertion of pautofd (nautofd). this partial hand- shake support (on pautofd false edge) is termed asemi-automatic.o in software: set apdhhb true and handle pbusy manually. to utilize the delayed pack mechanism, set the apdhha bit to 0. if fully manual control is desired, set apdhha to 1. load a delay value into ackdelay consistent with the ieee-1284 standard, or longer. first nibble when pautofd (nautofd) is asserted showing host not busy, the api hardware automatically generates an apds data transfer request. in software: distribute the bits of the low nibble of the first byte into the nibble consisting of: fault, select , perror , and pbusy for data1data4. immediately assert afas to force pack (nack) as- serted after a delay of length t ackdelay .
amd a d v a n c e i n f o r m a t i o n 65 AM29202 microcontroller the built-in delay means that the processor need not be interrupted again until the next pautofd (nautofd) assertion (showing ready for more data). pack (nack) is semi-automatically deasserted on the deassertion of pautofd (nautofd) (signaling acknowledgment of data). this completes the first nibble of the byte. second nibble for the second nibble, an extra step must be inserted at the very end of the transfer. before deasserting pack (nack), the peripheral must place status information on the lines previously used for data. then, after a data set- up time, pack (nack) can be deasserted, thus ending the transfer of the byte. for this to occur, the peripheral must do two things: block the automatic deassertion of pack (nack) after data is sent, and be interrupted when pautofd (nautofd) goes inactive. the series of steps to transfer the second nibble is shown below, in order: when pautofd (nautofd) is again asserted showing host not busy, the api hardware generates another apds data transfer request. in software: place the second nibble of the byte of data onto the nibble data lines as for the first nibble. also set pautohlm and background status defer (bsd) to 1. pautohlm will alert the service routine when to take the transferred data off the nibble data lines and when to put the return status information on them. bsd controls the semi-automatic handshake that deas- serts pack (nack), once asserted. when bsd is 0, pack (nack) deasserts on pautofd (nautofd) deassertion (handshake completes). when bsd is 1, pack (nack) is held asserted until bsd is again set to 0 (handshake deferred). when bsd is cleared, pack (nack) is deasserted after a delay of length t ackdelay (deferred handshake completes). once the mask and bsd are set to the correct levels, send the second nibble by again asserting afas. after t ackdelay , pack (nack) is asserted, and the host again deasserts pautofd (nautofd). this time the pack (nack) is not deasserted automatically. instead pautofd (nautofd) deassertion causes a control inter- rupt on apci. this bsd-based selection of the status- output phase increases interrupt efficiency over being interrupted every time pautofd deasserts and does not require constant rewrites to the apct register. in software: update pbusy (busy) to the peripheral host-to-pe- ripheral forward-channel-busy status (for the com- patibility mode channel), set reverse-data-available status on fault, set perror to track fault, and clear bsd, allowing the status phase to handshake. after the delay, pack (nack) deasserts and the inter- face is ready to send another byte or to change modes. changing modes to enable application-driven termination back to com- patibility mode: set the selectin true-edge interrupt mask (selinlhm). at that interrupt, set apmode to 1 for compatibility mode. manually complete the valid- state-termination handshake described in the ieee standard and return from interrupt. a new interrupt on selectin (nselectin) false edge can again start another negotiation. nibble idle phase in nibble idle phase, the peripheral must signal the pres- ence of new reverse data. in software: assert fault and pulse pack. nibble id nibble id mode is identical to nibble mode, except that nibble id mode is entered with data always pending, and that data is always the ieee-1284 id data message. even if there is other data available in the stream, the id message is sent before any other pending data. when the id message is sent, the host terminates the mode and renegotiates for any further data. this mode is dis- tinguished from nibble mode by software only.
amd a d v a n c e i n f o r m a t i o n 66 AM29202 microcontroller byte mode byte mode supports byte-wide reverse data transfers on the eight data lines used for forward channel data in compatibility mode. api support for byte mode is similar to that for nibble mode, but offers automatic hand- shakes, faster transmission, and less complicated pro- gramming. this mode, like ecp reverse, requires a special exter- nal signal to reverse the data direction, driving latched output data onto the ieee-1284 data bus. this line is called revoe and drives the external dual-direction bus driver/latch (ls652 or act652). the ieee-1284 handshake protocol allows for the time required to disable the host data-driver and enable the peripheral data-driver, as well as to enter the reverse mode. an opposite sequence is used for termination. data transfers are requested on pautofd (nautofd) assertion in this mode. dma transfers for data are enabled via the dmamode bit. selectin (nselectin) true-edge interrupts must be en- abled for application-driven termination back to com- patibility mode. the datastrobe line is not activated, once in this mode. automatic handshakes apds occurs on pautofd (nautofd) true edge and signals host readiness for reverse data. one data-setup time (500 ns) after the apdt data latch has been written, pack (nack) is automatically asserted (this is delayed through the ackdelay mechanism). the host will re- move pautofd (nautofd), acknowledging pack (nack). finally, pack (nack) deassertion occurs, com- pleting the handshake. the host will then send a pulse on the pstrobe (nstrobe) line signaling that the byte was accepted and processed. this pstrobe input will not cause a for- ward data latching on datastrobe. it signals the ac- knowledgment of a byte only. it can be ignored, or used as a flow control indicator. another assertion of the pautofd signal indicates that another byte should be sent; the host will only request if data is available. the acknowledge delay (ackdelay) field in the apct register is the minimum data setup time from when the data is output to the time the pack signal is generated (signaling data transfer) automatically in hardware. in software: load a delay value into ackdelay consistent with the ieee-1284 standard, or longer. data transfers data transfer is requested on pautofd (nautofd) go- ing active. this sets the apds bit. to program interrupt-driven data transfers: set the apdm mask bit and clear dmamode, caus- ing an apdi interrupt in the ict register whenever the apds is set. no dma request will be issued. to enable dma transfers: set the dmamode bit to 1, causing a dma request to the channel pointed to by the apdc field. no apdi is generated, irrespective of the status of apdm. using dma in byte mode note that when using dma in byte mode, the first byte cannot be transferred automatically. this is because the direction of the data driver must be reversed after the host has guaranteed disabling of its drivers. this occurs after the first byte has been requested. in software: set intrevoe immediately after pautofd (nautofd) assertion to set up reverse transfers. (the first pautofd assertion occurs after the host dis- ables its data drivers.) set an interrupt for pautofd (nautofd) false edge. program the dma controller, enable it, and return from interrupt. setting status information status lines are read by the host at the end of each byte transfer. peripheral-to-host data available on fault (nfault) and forward host-to-peripheral busy status on pbusy (busy) must be setup at least 500 ns before the automat- ic deassertion of pack (nack). the ndataavail flow control structure defined in the ieee-1284 standard requires a way to update the status on the fault (nfault) signal line. a simple procedure in software is to: set the dma channel length to n-1. set the count terminate enable (cte) bit in the dma control register. in the dma count-terminate interrupt handler, clear the status of data available by setting the fault sta- tus to false before the next byte is requested. load the last byte into the apdt register, causing that byte to transmit automatically. if the peripheral design requires a particular status func- tion to be explicitly forced with a guaranteed data setup time, then the processor may set an interrupt for pautofd deassertion and set background status de- fer (bsd). bsd is used the same way as in nibble mode.
amd a d v a n c e i n f o r m a t i o n 67 AM29202 microcontroller the hold-off procedure described below is available but not required. status lines can be updated by software at their activity times and will be interpreted by the proces- sor at the next byte completion (pack deassertion). in software: set bsd to hold off the pack (nack) deassertion that completes the handshake. have the interrupt service routine for the pautohli update the status values, then clear bsd and pautohlm (if it was a one-time update cycle), and return from interrupt. the clearing of bsd starts an ackdelay cycle and deasserts pack (nack) at the completion of that period automatically, thus guaranteeing data setup time. changing modes to enable application-driven termination back to com- patibility mode: set the selectin true-edge interrupt mask (selinlhm). at that interrupt, set apmode to 1 for compatibility mode. determine and write the proper condition of intrevoe. manually complete the val- id-state-termination handshake described in the ieee standard and return from interrupt. a new inter- rupt on selectin (nselectin) false edge can start another negotiation. byte idle phase in byte idle phase, the peripheral must signal the pres- ence of new reverse data. in software: assert fault and pulse pack. byte id byte id mode is identical to byte mode, except that byte id mode is entered with data always pending, and that data is always the ieee-1284 id data message. even if there is other data available in the stream, the id mes- sage is sent before any other pending data. when the id message is sent the host terminates the mode and rene- gotiates for any further data. this mode is distinguished from byte mode by software only.
amd a d v a n c e i n f o r m a t i o n 68 AM29202 microcontroller ecp mode a distinction of the ecp forward and reverse modes is that they can be transferred to and from each another without a renegotiation back to compatibility mode. they differ from nibble and byte modes in that respect. in order to set up the AM29202 microcontroller hard- ware for the correct automatic handshaking protocols, the programmer must set the apmode field to the cor- rect value when entering and leaving ecp forward and ecp reverse modes. ecp forward ecp forward mode operates similarly to the compati- bility mode, except that pbusy (busy) is used as re- verse ieee-1284 data strobe and pack is not used at all. the host signals that data is available by asserting pstrobe (nstrobe). the peripheral regulates data flow by delaying the acknowledgment of the pstrobe assertion when the channel is busy and the buffer is still full. this acknowledgment hold-off stops the host from continuing until the buffer is emptied. the apds bit is then set by pstrobe assertion. when the peripheral responds to the data transfer request (via polling, inter- rupt service, or dma), the api releases the hold and as- serts pbusy (busy). because the host data retrieval and access time is overlapped with the peripheral data transfer time, the total bus speed is high. the software must enable the control interrupt for init (ninit) assertion, to correctly transfer to the ecp re- verse mode. the perror (perror) line is used to signal the setup phases after negotiation and before the idle phases (the beginning of automatically handshaked data transfers). it also functions as the acknowledgment of the init (ninit) signal, and tells the host when it can send data. dma transfers may be enabled for forward data using the dmamode bit. fault (nfault) may be driven asynchronously to signal data available for transfer in ecp reverse mode. selectin (nselectin) true-edge interrupts must be en- abled for application-driven termination back to com- patibility mode. automatic handshakes the host signals that data is available by asserting pstrobe (nstrobe). once pstrobe asserts, hard- ware automatically asserts pbusy (busy), signaling acknowledgment and readiness to receive. if data has not yet been extracted from the data latch from the last data byte, the handshake mechanism will hold off pbusy (busy) assertion until the data is read from the apdt register (irrespective of the read mech- anism). the host then responds by deasserting pstrobe (nstrobe). a data transfer request is generated by the api hardware, along with the datastrobe, at pstrobe (nstrobe) deassertion. the datastrobe line is pulsed automatically on pstrobe (nstrobe) deassertion. finally, the peripheral automatically signals acceptance with pbusy (busy) deassertion. distinguishing commands from data ecp forward mode uses hardware handshaking to transfer eight data bits, but the context of the data is mo- dified by the pautofd (nautofd) signal at transfer time. the data is interpreted as a user-defined com- mand when pautofd is asserted and interpreted as target native data when pautofd is deasserted. the instance of a command byte automatically causes an ecp command status (ecs) condition instead of an apds condition. in software: set the ecm and the cpe bits to cause an apci in- terrupt. the hardware handshake is automatically disabled by the internal logic, and no data transfer requests occur for that byte (until the ecs/eci condition is cleared). in software: read the command, interpret it completely, and then re-enable hardware-handshaking by clearing the ecs or eci bits (in either the apst or apis regis- ters). using cpe the decision to interrupt the data stream (either dma- or interrupt-supported) for an exception byte is controlled by the command polarity expected bit. the use of the cpe bit in ecp forward situations with only single-byte commands in long data streams is very simple. in software: set cpe to 1, allowing interrupts when pautofd is high (nautofd or hostack is low). service the eci interrupt, read the command byte from apdt to de- termine its meaning, set proper application-specific context, clear interrupts (to set data stream going again), and return from interrupt. some systems may use the command identifiers as a means to transfer a second data stream (whether thought of as an extended command stream or a second data stream). in those conditions, where a series of command bytes (command bit set) will be transferred continuously between the non-command byte stream,
amd a d v a n c e i n f o r m a t i o n 69 AM29202 microcontroller the use of cpe can support easy dma handling of both streams. set cpe to 1 to detect the first command condition. in the interrupt service routine for eci, read the com- mand byte directly from the apdt (the handshake does not complete in this case), and set the context or condition required. then, reverse the polarity of cpe and load a new ad- dress and count into the dma controller to handle the second (command) data stream. move the first byte of the command stream to the buffer front and re- lease the channel by clearing ecs/eci, and return from interrupt. the dma will transfer the remaining bytes in the com- mand stream, and when the command bit changes again, the ecs/eci will once again occur. handle the transitions between conditions in the same way, alternating between dma pointers. handling deadlocks note that if the peripheral deadlocks during forward data transmission, the host will signal init (ninit), and then, expect a perror (perror) to allow a reverse mode transfer. to ensure proper handling of deadlocks: always accept inits in the middle of a handshake (ecp busy condition). they will only come if the pe- ripheral deadlocks (stays busy in the middle of a handshake for more than 35 ms). always clear the ecp forward channel busy status whenever init occurs. changing modes to transfer into ecp reverse mode: set init true-edge interrupt mask (initlhm). at that interrupt, set apmode to 5 for ecp reverse mode. set intrevoe, set up any dma control variables, reverse the polarity of the init interrupt, and assert perror (perror) to begin reverse data transfer. to enable application-driven termination back to com- patibility mode: set the selectin true-edge interrupt mask (selinlhm). at that interrupt, set apmode to 1 for compatibility mode. determine and write the proper condition of intrevoe. manually complete the val- id-state-termination handshake described in the ieee standard and return from interrupt. a new inter- rupt on selectin (nselectin) false edge can start another negotiation. ecp reverse ecp reverse mode, like byte mode, requires a special output line to reverse the data direction, driving latched output data onto the ieee-1284 data bus. this line is called revoe and drives the external bidirectional bus driver/latch (ls652 or act652). the ieee-1284 hand- shake protocol allows for the timing of host data-driver disabling and of peripheral data-driver enabling for en- tering reverse modes, and the opposite sequence for termination. the control interrupt for init (ninit) deassertion must be enabled to correctly transfer to the ecp forward mode. the perror (perror) line functions as the acknowl- edgment of the init (ninit) signal and tells the host when it can send data, in the reverse-to-forward phase. dma transfers for data are enabled via the dmamode bit. the host signals readiness for another byte of data by asserting pautofd (nautofd). selectin (nselectin) true-edge interrupts must be en- abled for application-driven termination back to com- patibility mode. the datastrobe line is not activated, once in this mode. automatic handshakes the host signals readiness for data by requesting ecp reverse mode. the api automatically generates apds upon entry and automatically asserts pack (nack) after the ackdelay period. pack (nack) assertion from the peripheral is answered by pautofd (nautofd) deassertion signaling acknowledgment. the api logic responds to pautofd (nautofd) deassertion by causing automatic pack (nack) deassertion handshake, and pack (nack) deassertion by the peripheral is answered by a pautofd (nautofd) assertion from the host, signaling an end to the hand- shake for the byte. this final phase causes another data transfer request. in software: set the acklen field to an appropriate data setup time in memclk cycles. data transfers a data transfer is automatically requested in two differ- ent situations. when the interface is first changed from ecp forward to ecp reverse, the data transfer request is set, allowing the programmer to setup the dma control variables and then transfer to ecp reverse without being required to aprime the pumpo (which entails writing the first byte into
amd a d v a n c e i n f o r m a t i o n 70 AM29202 microcontroller the apdt register from the program and loading the dma controller for n-1 bytes). once ecp reverse mode is established, pautofd (nautofd) assertion at the end of a transfer automatical- ly causes the next data transfer request. to enable reverse data transfers: set intrevoe immediately after the pautofd (nautofd) assertion. to program interrupt-driven data transfers: set the apdm mask bit and clear dmamode, caus- ing a apdi interrupt in the ict register whenever the apds is set. no dma request will be issued. to enable dma transfers: set the dmamode bit to 1, causing a dma request to the channel pointed to by the apdc field. no apdi is generated, irrespective of the status of apdm. distinguishing commands from data ecp reverse mode uses hardware handshaking to transfer eight data bits to the host, but the context of the data may be modified by the pbusy (busy) signal. to transfer data using dma, force afbusy to the condition required for the data stream, sending all bytes as data. to send commands using dma, set the dma byte count for the stretch of non-command data, allowing automatic handshaking and dma data support. set the cte bit in the dma control register. then, on the dma count-terminate interrupt, the proces- sor may assert the command bit and send a single com- mand byte by writing afbusy and writing the command byte directly to the apdt. program the next stretch of non-command data into the dma byte length for the next automatic hand- shaking period. if data transfer is handled by apdi interrupts only, then each individual request for data may be used to set both reverse data into the apdt, as well as the command sta- tus into afbusy. changing modes to transfer directly into ecp forward mode: set init false-edge interrupt mask (inithlm). at that interrupt, set apmode to 4 for ecp forward mode. set intrevoe to 0 and assert pstrobe (nstrobe) to begin forward data transfer. if the host transitions back to ecp forward mode with the init (ninit) deassertion, pending data transfer re- quests must be cleared before returning to ecp for- ward mode. in software: write a 1 to the apds (after disabling the dma con- troller if used). to enable application-driven termination back to com- patibility mode: set the selectin true-edge interrupt mask (selinlhm). at that interrupt, set apmode to 1 for compatibility mode. determine and write the proper condition of intrevoe. manually complete the val- id-state-termination handshake described in the ieee standard and return from interrupt. a new inter- rupt on selectin (nselectin) false edge can start another negotiation. ecp reverse id ecp reverse id mode is identical to ecp reverse mode, except that ecp reverse id mode is entered with data always pending, and that data is always the ieee-1284 id data message. even if there is other data available in the stream, the id message is sent before any other pending data. when the id message is sent, the host terminates the mode and renegotiates for any further data. this mode is distinguished from ecp re- verse mode by software only.
amd a d v a n c e i n f o r m a t i o n 71 AM29202 risc microcontroller absolute maximum ratings storage temperature 65 c to +125 c . . . . . . . . . . . . voltage on any pin with respect to gnd 0.5 to v cc +0.5 v . . . . . . . . . . maximum v cc 6.0 v dc . . . . . . . . . . . . . . . . . . . . . . . . . stresses outside the stated absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum rat- ings for extended periods may affect device functionality. operating ranges commercial (c) devices case temperature (t c )0 c to +85 c (c) . . . . . . . . . . supply voltage (v cc ) +4.75 to +5.25 v . . . . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating range advance information symbol parameter description test conditions notes min max unit v il input low voltage 1 0.5 0.8 v v ih input high voltage 1 2.0 v cc +0.5 v v ilinclk inclk input low voltage 0.5 0.8 v v ihinclk inclk input high voltage 2.4 v cc +0.5 v v ol output low voltage for all outputs except memclk i ol = 3.2 ma 0.45 v v oh output high voltage for all outputs except memclk i oh = 400 m a 2.4 v i li input leakage current 0.45 v v in v cc 0.45 v 2 10 or +10/200 m a i lo output leakage current 0.45 v v out v cc 0.45 v 10 m a i ccop operating power supply current v cc = 5.25 v, outputs floating; holding reset active 3 4 5 175 234 280 ma ma ma v olc memclk output low voltage i olc = 20 ma 0.6 v v ohc memclk output high voltage i ohc = 20 ma v cc 0.6 v notes: 1. all inputs except inclk . 2. the low input leakage current is 200 m a for the following inputs: tck, tdi, tms, trst , dreq1, wait , intr 2, and intr 0 . these pins have weak internal pull-up transistors. 3. i cc measured at 12.5 mhz, v cc =5.25 v, reset condition. 4. i cc measured at 16.7 mhz, v cc =5.25 v, reset condition. 5. i cc measured at 20.0 mhz, v cc =5.25 v, reset condition. capacitance advance information symbol parameter description test conditions min max unit c in input capacitance 15 pf c inclk inclk input capacitance 15 pf c memclk memclk capacitance fc = 10 mhz 20 pf c out output capacitance 20 pf c i/o i/o pin capacitance 20 pf note: limits guaranteed by characterization.
amd a d v a n c e i n f o r m a t i o n 72 AM29202 risc microcontroller switching characteristics over commercial operating range no. parameter description min max min max min max unit 1 inclk period (=0.5t) note 2, 9 25 62.5 30 62.5 40 62.5 ns 2 inclk high time note 2 9 53.5 9 53.5 12 53.5 ns 3 inclk low time note 2 9 53.5 9 53.5 12 53.5 ns 4 inclk rise time note 2 4 4 4 ns 5 inclk fall time note 2 4 4 4 ns 6 memclk delay from inclk 0 10 0 10 0 10 ns 7 synchronous output valid delay from memclk rising edge note 3a 1 11 1 11 1 15 ns 7a synchronous output valid delay from memclk rising edge note 3a 1 12 1 12 1 15 ns 7b synchronous output valid delay from memclk falling edge note 3b 1 10 1 10 1 15 ns 8 synchronous output disable delay from memclk rising edge note 8 1 10 1 10 1 15 ns 9 synchronous input setup time 10 10 12 ns 10 synchronous input hold time 0 0 0 ns 11 asynchronous pulse width note 4a, 9 4t 4t 4t ns 11a asynchronous pulse width note 4b ns 12 memclk high time note 5 0.5t3 0.5t+3 0.5t3 0.5t+3 0.5t3 0.5t+3 ns 13 memclk low time note 5 0.5t3 0.5t+3 0.5t3 0.5t+3 0.5t3 0.5t+3 ns 14 memclk rise time note 5 0 4 0 4 0 5 ns 15 memclk fall time note 5 0 4 0 4 0 5 ns 16 uclk, vclk period note 2 25 30 40 ns 17 uclk, vclk high time note 2, 8 9 9 12 ns 18 uclk, vclk low time note 2, 8 9 9 12 ns 19 uclk, vclk rise time note 2 4 4 4 ns 20 uclk, vclk fall time note 2 4 4 4 ns 21 synchronous output valid delay from vclk edge note 6 1 15 1 15 1 20 ns 22 input setup time to vclk edge note 6, 7 10 10 15 ns 23 input hold time to vclk edge note 6, 7 0 0 0 ns 24 tck frequency 2 2 2 mhz notes: 1. all outputs driving 80 pf, measured at v ol =1.5 v and v oh =1.5 v. for higher capacitance, add 1 ns output delay per 20 pf loading, up to 300 pf total capacitance. 2. inclk, vclk, and uclk can be driven with ttl inputs. if not used, uclk must be tied high. 3. a. parameter 7a applies only to the outputs pio15pio4 and dack 1 . parameter 7 applies to the remaining outputs. b. parameter 7b applies only to the outputs ras x , cas x , rswe , and romoe . some of these signals can also be asserted during the rising edge of memclk, depending on the type of access being performed. 4. a. parameter 11 applies to all asynchronous inputs except lsync and psync. b. the lsync and psync minimum width time is two bit-times. one bit-time corresponds to one internal video clock period. the internal video clock period is a function of the vclk period and the programmed vclk divisor. 5. memclk can drive an external load of 100 pf. 6. active vclk edge depends on the clki bit in the video control register. 7. lsync and psync may be treated as synchronous signals by meeting setup and hold times. the synchronization delay still applies. 8. not production tested but guaranteed by design or characterization. 9. t=1 memclk period, as defined by the actual frequency on the memclk pin. 20 mhz 16 mhz advance information 12 mhz test conditions (note 1)
amd a d v a n c e i n f o r m a t i o n 73 AM29202 risc microcontroller switching waveforms inclk memclk synchronous outputs synchronous inputs asynchronous inputs uclk, vclk vclk-relative outputs vclk-relative inputs 1.5 v note : video timing may be relative to vclk falling edge if clki = 1. 1.5 v 1.5 v 16 17 18 20 19 2.0 v 1.5 v 0.8 v 22 21 1.5 v 9 10 8 7 1.5 v 0.6 v 14 6 12 13 2.4 v 1.5 v 0.8 v 5 3 2 1 4 7b 11 11a 15 v cc 0.6 v 7a 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 23
amd a d v a n c e i n f o r m a t i o n 74 AM29202 risc microcontroller switching test circuit v v l i ol max = 3.2 ma v ref = 1.5 v i oh max = 400 m a c l v h AM29202 microcontroller pin under test model of dynamic test load note: c l is guaranteed to be a minimum 80-pf parasitic load. it represents the distributed load parasitic attributed to the test hardware and instrumentation present during production testing. thermal characteristics pqfp package the AM29202 microcontroller is specified for operation with case temperature ranges for a commercial temper- ature device. case temperature is measured at the top center of the package as shown in the figure below. q ja q ca q jc q ja = q jc + q ca thermal resistance ( c/watt) t c the various temperatures and thermal resistances can be determined using the following equations along with information given in table 12. (the variable p is power in watts.) q ja = q jc + q ca p=i ccop ? v cc t j =t c +p ? q jc t j =t a +p ? q ja t c =t j p ? q jc t c =t a +p ? q ca t a =t j p ? q ja t a =t c p ? q ca allowable ambient temperature curves for various air- flows are given in figures 26 and 27. these graphs assume a maximum v cc and a maximum power supply current equal to i ccop . all calculations made using the above information should guarantee that the operating case temperature does not exceed the maximum case temperature. since p is a function of operating frequen- cy, calculations can also be made to determine the am- bient temperature at various operating speeds.
amd a d v a n c e i n f o r m a t i o n 75 AM29202 risc microcontroller table 12. pqfp thermal characteristics ( c/watt) surface mounted airfloweft./min. (m/sec) AM29202 microcontroller 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) q ja junction-to-ambient 36 32 29 27 q jc junction-to-case 8 8 8 8 q ca case-to-ambient 28 24 21 19 0 10 20 30 40 50 60 70 80 90 0 200 400 600 0 10 20 30 40 50 60 70 80 90 0 200 400 600 t c at 85 c t c at 85 c air flow (ft./min.) maximum ambient ( c) air flow (ft./min.) 20 mhz 16.67 mhz 0 10 20 30 40 50 60 70 80 90 0 200 400 600 t c at 85 c air flow (ft./min.) maximum ambient ( c) 12.5 mhz figure 26. maximum allowable ambient temperature (data sheet limit, i ccopmax , v cc =+5.25 v, average thermal impedance) thermal resistance [ q ja ( c/w)] 0 5 10 15 20 25 30 35 40 45 0 200 400 600 air flow (ft./min.) figure 27. thermal impedance
amd a d v a n c e i n f o r m a t i o n 76 AM29202 risc microcontroller 0.020 0.040 s 0.947 0.953 1.075 1.085 1.097 1.103 0.947 0.953 1.075 1.085 1.097 1.103 0.008 0.012 pin 1 i.d. pin 1 pin 33 pin 66 pin 99 pin 132 a d b physical dimensions pqb 132, trimmed and formed plastic quad flat pack (measured in inches) see detail x seating plane c 0.025 basic top view side view 0.80 ref 0.160 0.180 0.130 0.150 s note: not to scale. for reference only.
amd a d v a n c e i n f o r m a t i o n 77 AM29202 risc microcontroller 0.010 pqb 132 (continued) 0.008 0.012 7 typ 0.010 min flat shoulder 0.045 x 45 chamfer 0 min 0.015 0.008 pin 99 gage plane 0 0 8 section ss detail x 7 typ 0.065 ref 0.006 0.008 0.036 0.046 note: not to scale. for reference only. trademarks amd, am29000 and fusion29k are registered trademarks; and 29k, am29005, am29030, am29035, am29040, am29050, am29200, AM29202, am29205, am29240, am29243, am29245, xray29k, and minimon29k are trademarks of advanced micro devices, inc. high c is a registered trademark of metaware, inc. microsoft and windows are registered trademarks of microsoft corp. product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ? 1995 advanced micro devices, inc.

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