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avpro? 5303b universal 3-input a/v switch interface data sheet page: 1 of 16 ? 2005 teridian semiconductor corporation rev 1.0 december 2005 description the avpro ? 5303b device is a universal three input a/v switch interface ic designed for tv and general-purpose a/v applications. the device provides interfaces for three full sets of tv scart input signals (red, green, blue, cvbs, r, l, fast blanking, and tv function) and also supports scart svhs video mode. in addition, the 5303b can be configured to support general-purpose a/v interface (yprpb, svhs, and cvbs) for tvs, dvd recorders, digital set-top boxes, and pvrs. video and audio gains are programmable. all switching and function settings are controlled via i 2 c. features three input a/v interface ? 3:1 video and audio mux ? programmable gain video drivers ? 0/6 db audio drivers ? tv scart interface - rgb+fb, svhs and cvbs video modes - 12v tv function pins mux ? general purpose a/v interface - yprpb, svhs and cvbs video modes i 2 c control power down mode configurable device address ? picture-in-picture application ? expandable multi-function inputs (up to 6 channels) power supply ? +5v, +12v package ? 48-qfn applications tv 3-scart interface tv a/v interface (yprpb/svhs/cvbs) dvd recorder a/v interface digital set-top box a/v interface pvr a/v interface fb2 fb_out fb3 fb1 mux func2 func3 func1 gn2 gn3 mux gn1 mux bl2 bl3 bl1 mux rd2 rd3 rd1 mux cvbs1 cvbs2 cvbs3 mux r1 r2 r3 l1 l2 l3 func_out gn_out bl_out rd_out cvbs_out r_out l_out mux mux gain sclk sdata serial port vref rbias tgen support circuits pdwn vcc vcc vdd vcc gnd gnd gnd gnd 0v/6v/12v 0/6db gain dev_addr green or y or cvbs blue or pb red or pr or c cvbs or y
avpro? 5303b universal 3-input a/v switch interface data sheet page: 2 of 16 ? 2005 teridian semiconductor corporation rev 1.0 functional description the 5303b is an analog a/v interface ic designed for tv and general-purpose a/v applications. the device accepts up to three sets of scart input signals (red, green, blue, cvbs, r, l, fast blanking, and tv function). by way of 3:1 mux, scart 1, 2, or 3 signals can be selected at the device?s output pins. the 5303b supports four scart video modes: rgb/cvbs, rgb- only, cvbs-only and svhs. the rgb and cvbs video driver gains are programmable from 2 to 1.4 in 0.2 steps, and the r/l audio driver gain can be 0db or 6db. the r/l audio drivers can accept signals from 0.5vrms to 2vrms. for general-purpose a/v applications, video switches and drivers can be configured to support component video (yprpb), s-video (svhs), and composite video (cvbs) signals. all switching and programmable functions of the device are controlled through a standard i 2 c serial interface dc restore for rgb, y, and cvbs: the device will generate a dc restore level on each video output based on timing referenced to a horizontal sync pulse. when the sync pulse is detected, the dc restore circuit will act to position the blank level to 1.2v at the respective rgb, y, or cvbs output pin(s). dc restore for svhs and yprpb: in the svhs mode, the cvbs pin is used as luma input and the red pin is used as chroma input. the dc restore function for luma signal is equivalent to cvbs signal. the dc restore circuit will position the output blank level to 1.2v at the respective luma output pin. for the chroma input, the on-chip clamp circuit will be used to position the output mid-scale dc level to 1.8v. in the yprpb mode, the mid-scale dc level for pr and pb outputs will also be at 1.8v. a/v input source selection the device accepts up to three sets of a/v input signals. bits 0 & 1 of register 0 determine which of the sets will be present at the device?s output pins. video mode selection the device supports four video modes for tv scart applications: rgb/cvbs, rgb-only, cvbs-only, and svhs. bits 2, 3, & 4 set the active video mode. rgb/cvbs video mode is a default mode. for general- purpose a/v applications, the device supports yprpb/cvbs and cvbs/svhs video modes. rgb gain the gain of the rgb outputs can be adjusted to one of four different levels. bits 0 & 1 register 1 set the gain of the rgb output amplifiers according to the following table: bit 1 bit 0 rgb amplifier gain 0 0 1 1 0 1 0 1 gain = 2 v/v gain = 1.8 v/v gain = 1.6 v/v gain = 1.4 v/v cvbs gain the gain of the cvbs output can be adjusted to one of four different levels. bits 2 & 3 register 1 set the gain of the cvbs output amplifier according to the following table: bit 3 bit 2 cvbs amplifier gain 0 0 1 1 0 1 0 1 gain = 2 v/v gain = 1.8 v/v gain = 1.6 v/v gain = 1.4 v/v audio gain the gain of the r/l audio amplifiers can be set to either 0db or 6db. bit 4 of register 1 sets the gain of the amplifiers according to the following table: bit 4 r/l amplifier gain 0 1 gain = 0 db gain = 6 db
avpro? 5303b universal 3-input a/v switch interface data sheet page: 3 of 16 ? 2005 teridian semiconductor corporation rev 1.0 tv function input the tv function feature generally supports three-level logic signal required for scart tv function switching: input voltage tv function switching mode 0-2v 4.5-7v 9.5-12v broadcast tv 16:9 peritelevision reproduction normal peritelevision reproduction in the avpro? 5303b device, the tv function feature works in pass through mode only. the three inputs, func1, func2 and func3 support the pass through mode of the tv function feature . a 100k ? load is recommended for typical operation at the func_out pin. fast blanking (fb) input the fb1, fb2 and fb3 inputs support two-level logic signal required for scart fast blanking: logic input voltage fast blanking mode 0 1 0-0.4v 1-3v cvbs active rgb active following a 3:1 input mux stage is a unity-gain fb video driver. the fb video driver is designed to match the video drivers of rgb in bandwidth and time delay and can support a minimum load of 300 ? . chip power down the whole chip (except negligible on-chip biasing circuit) can be powered down by setting pdwn pin to high (5v). configurable device address dev_addr pin sets the address of the 5303b device. there are two possible device addresses that the 5303b can have: device address description 10 01 000x 10 10 000x dev_addr pin left open (default) dev_addr pin connected to gnd in the case of picture-in-picture or 6-channel inputs application, a second device is required to have a different address from the first or original device. this can be done by connecting the dev_addr pin of the second device to gnd while leaving the dev_addr pin of the first device open or unconnected. serial port definition internal functions of the device are monitored and controlled by a standard inter-ic (i 2 c)bus with data being transferred msb first on the rising edge of the clock. the serial port operates in a slave mode only and can be written to or read from. the device uses 7-bit addressing, and does not support 10-bit addressing mode. the writ e register data is sent sequentially, such that if register 1 is to be programmed, then registers 0 and 1 need to be sent. if only register 0 needs to be programmed, then only registers 0 data needs to be sent. it will support standard and fast bus speed. the default address of the device is 1001000x (1001000 for write and 10010001 for read). the 5303b includes a read register in which the upper four bits identify the specific chip within the avpro ? family. this allows a single application platform and software to work with a wide variety of avpro ? chips. the id code for the 5303b is 0010. data transfers a data transfer starts when the sdata pin is driven from high to low by the bus master while the sclk pin is high. on the following eight clock cycles, the device receives the data on the sdata pin and decodes that data to determine if a valid address has been received. the first seven bits of information are the address with the eighth bit indicating whether the cycle is a read (bit is high) or a write (bit is low). if the address is valid for this device, on the falling sclk edge of the eighth bit of data, the device will drive the sdata pin low and hold it low until the next rising edge of the sclk pin to acknowledge the address transfer. the device will continue to transmit or receive data until the bus master has issued a stop by driving the sdata pin from low to high while the sclk pin is held high write operation: when the read/write bit (lsb) is low and a valid address is decoded, the device will receive data from the sdata pin. the device will continue to latch data into the registers until a stop condition is detected. the device generates an acknowledge after each byte of data written. read operation: when the read/write bit (lsb) is high and a valid address is decoded, the device will transmit the data from the internal register on the following eight sclk cycles. following the transfer of the register data and the acknowledge from the master, the device will release the data bus. reset: at power-up the serial port defaults to the states indicated in boldface type. the device also responds to the system level reset that is transmitted through the serial port. when the master sends the address 00000000 followed by the data 00000110, the device resets to the default condition.
avpro? 5303b universal 3-input a/v switch interface data sheet page: 4 of 16 ? 2005 teridian semiconductor corporation rev 1.0 serial port register tables read register device address = 10010001 (10100001 when dev_addr = 0) function bits description not used xxxx0000 not used device id code 0010xxxx this code identifies the device type as the 5303b. write registers : device address = 10010000 (10100000 when dev_addr = 0). bold indicates default setting. register 0: signal source selection register 0: register 1: audio/video gain control function bits description rbg gain xxxxxx 00 2 xxxxxx01 1.8 xxxxxx10 1.6 xxxxxx11 1.4 function bits description cvbs gain xxxx 00 xx 2 xxxx01xx 1.8 xxxx10xx 1.6 xxxx11xx 1.4 function bits description audio gain xxx 0 xxxx 0 db xxx1xxxx 6 db video mode bits description blue chroma/pr/pb enable xxxxxxx 0 blue input set for chroma/pr/pb xxxxxxx1 blue input set for y or blue(dc restore) red chroma/pr/pb enable xxxxxx 0 x red input set for chroma/pr/pb xxxxxx1x red input set for y or red(dc restore) fb_out set to 0v xxxxx 0 xx fb_out for normal operation xxxxx1xx fb_out set to 0v gn_out set to 0v xxxx 0 xxx gn_out for normal operation xxxx1xxx gn_out set to 0v audio/func source selection bits rout lout func_out 00 xxxxxx r1 l1 func1 01xxxxxx r2 l2 func2 10xxxxxx r3 l3 func3 11xxxxxx not used not used not used
avpro? 5303b universal 3-input a/v switch interface data sheet page: 5 of 16 ? 2005 teridian semiconductor corporation rev 1.0 register 2: xxxx xxxx. user must write to register 2 (contents written are a don?t care) prior to writing to register 3. register 3: video signal source selection video mode bits red_out red source selection xxxxx x00 rd1 xxxxxx01 rd2 xxxxxx10 rd3 xxxxxx11 0v video mode bits cvbs_out cvbs source selection xxxx 00 xx cvbs1 xxxx01xx cvbs2 xxxx10xx cvbs3 xxxx11xx 0v video mode bits blue_out blue source selection xx 00 xxxx bl1 xx01xxxx bl2 xx10xxxx bl3 xx11xxxx 0v video mode bits gn_out fb_out green source selection 00 xxxxxx gn1 fb1 01xxxxxx gn2 fb2 10xxxxxx gn3 fb3 11xxxxxx not used not used
avpro? 5303b universal 3-input a/v switch interface data sheet page: 6 of 16 ? 2005 teridian semiconductor corporation rev 1.0 pin descriptions name pin type description analog pins func1 25 i tv function input 1 func2 24 i tv function input 2 func3 23 i tv function input 3 fb1 48 i fast blanking input 1 fb2 5 i fast blanking input 2 fb3 36 i fast blanking input 3 gn1 2 i green input 1 gn2 7 i green input 2 gn3 38 i green input 3 bl1 3 i blue input 1 bl2 8 i blue input 2 bl3 39 i blue input 3 rd1 1 i red input 1 rd2 6 i red input 2 rd3 37 i red input 3 cvbs1 47 i cvbs input 1 cvbs2 4 i cvbs input 2 cvbs3 35 i cvbs input 3 r1 14 i right audio input 1 r2 16 i right audio input 2 r3 18 i right audio input 3 l1 15 i left audio input 1 l2 17 i left audio input 2 l3 19 i left audio input 3 func_out 22 o tv function output fb_out 45 o fast blanking output gn_out 41 o green output bl_out 40 o blue output rd_out 44 o red output cvbs_out 46 o cvbs output r_out 21 o right audio output l_out 13 o left audio output
avpro? 5303b universal 3-input a/v switch interface data sheet page: 7 of 16 ? 2005 teridian semiconductor corporation rev 1.0 pin descriptions (continued) name pin type description digital pins dev_addr 29 i device address input pdwn 28 i chip power down sclk 30 i serial clock input: this pin accepts a serial port clock input signal. sdata 31 i/o serial data input/output that can receive or transmit serial data. power/ground pins vcc 9, 33, 43 - +5 vdc power supply pins. vdd 27 - +12 vdc power supply pin for function switching circuits. vref 20 - internal voltage reference, bypass pin. add capacitor 0.1f(1.0 f for better psrr ) to ground. gnd 20, 26, 34, 42 - ground for all blocks. rbias 11 - bias point of internal current generator. add resistor 10.0k ? (+ 1%) to ground. tgen 32 - reference point for internal timing circuit. add capacitor 470pf to ground. n/c 12 - no connect.
avpro? 5303b universal 3-input a/v switch interface data sheet page: 8 of 16 ? 2005 teridian semiconductor corporation rev 1.0 electrical specifications absolute maximum ratings operation beyond the maximum ratings may damage the device parameter rating storage temperature -55 to 150 c junction operating temperature +125 c 5v supply voltage pins -0.3 v < vcc < 6v 12v supply pin -0.3 v < vdd < 13v voltage applied to digital and video inputs -0.3v to vcc+0.3 v voltage applied to video pins -0.3v to vcc+0.3 v voltage applied to audio pins -0.3 v < vdd < 13v voltage applied to fnc pin (input) -0.3 v < vdd < 13v specifications : unless otherwise specified: 0 < ta < 70 c; power supplies vcc = +5.0 v 5%, vdd = 12.0 v 5%. parameter condition min nom max unit operating characteristics power supply currents (default register setting) all outputs not loaded vcc (+5 vdc) vdd (+12 vdc) 16.5 4 20 5 ma ma power supply currents (default register setting) pdwn = 1 vcc (+5 vdc) vdd (+12 vdc) 2.3 10 3 100 ma a psrr f in = 100 hz, 0.3 vpp on vcc/ vdd 40 db switch time from serial data acknowledge 2.0 s wake time from power down condition 5 s serial port timing (set by i 2 c controller) sclk input frequency 400 khz sclk low time (t cl ) 1.3 s sclk high time (t ch ) 0.6 s rise time (t rt ) sclk and sdata 300 ns fall time (t ft ) sclk and sdata 300 ns data set-up time* (t dsu ) sdata change to sclk high 100 ns data hold time* (t dh ) sclk low to sdata change 30 ns start set-up time (t ssu ) 0.6 s start hold time (t sh ) 0.6 s stop set-up time (t psu ) 0.6 s glitch rejection maximum pulse on sclk and/or sdata 50 ns * these specifications also apply to an acknowledge generated by the device.
avpro? 5303b universal 3-input a/v switch interface data sheet page: 9 of 16 ? 2005 teridian semiconductor corporation rev 1.0 specifications (continued) digital i/o characteristics (sclk, sdata, pdwn, dev_addr) parameter condition min nom max unit high level input voltage 0.7* vcc vcc+0.3 v low level input voltage gnd-0.3 0.3* vcc v high level input current (sclk, pdwn, dev_addr) vin = vcc - 1.0v -10 10 a high level input current (sdata) vin = vcc - 1.0v -50 50 a low level input current (sclk, pdwn) vin = 1.0v -10 10 a low level input current (dev_addr) vin = 1.0v -300 10 a low level input current (sdata) vin = 1.0v -50 50 a low level output voltage (sdata) i ol = 3 ma 0.4 v fall time (t ft ) v ihmin to v ilmax (sdata) acknowledge or read with c l = 400pf 250 ns serial port timing (typical) sclk t ft t ch t cl t psu t dsu t dh t sh t ssu t rt sdata start msb lsb stop
avpro? 5303b universal 3-input a/v switch interface data sheet page: 10 of 16 ? 2005 teridian semiconductor corporation rev 1.0 video characteristics - unless otherwise noted, typical output loading on all video outputs is 150 ? . all video outputs are capable of withstanding a sustained 75 ? load to ground without damage. parameter condition min nom max unit input impedance all video inputs 100 k ? input dynamic range f in = 100 khz, thd < 0.15% 1.5 vpp rgb gain control a 0 = reading xx00xxxx gain 1.0 vpp input, f in = 100 khz; register 1 = xxxxxx00 register 1 = xxxxxx01 register 1 = xxxxxx10 register 1 = xxxxxx11 1.9 a 0 ?12% a 0 ?22% a 0 ?33% 2.0 a 0 ?10% a 0 ?20% a 0 ?30% 2.1 a 0 ?8% a 0 ?18% a 0 ?27% v/v v/v v/v v/v cvbs gain control a 0 = reading xx00xxxx gain 1.0 vpp input, f in = 100 khz; register 1 = xxxx00xx register 1 = xxxx01xx register 1 = xxxx10xx register 1 = xxxx11xx 1.9 a 0 ?12% a 0 ?22% a 0 ?33% 2.0 a 0 ?10% a 0 ?20% a 0 ?30% 2.1 a 0 ?8% a 0 ?18% a 0 ?27% v/v v/v v/v v/v output gain inequality rgb or svhs output channel to channel -2.5 2.5 % amplitude loss measured at 10mhz, a 0 = 2v/v 1.0 0.7 db video bandwidth 3db, a 0 = 2v/v 25 mhz output dc level rgb, cvbs or luma output 1.2 v blank level clamp voltage average level chroma, pr or pb output 1.8 v signal to noise ratio 1 vpp input 58 75 db cross talk f in = 4.43 mhz, 1 vpp -65 db output to output differential delay rgb signals, f in = 100 khz -20 20 ns differential phase cvbs output -2.5 2.5 deg. differential gain cvbs output -2.5 2.5 %
avpro? 5303b universal 3-input a/v switch interface data sheet page: 11 of 16 ? 2005 teridian semiconductor corporation rev 1.0 audio characteristics - unless otherwise noted, all audio outputs shall drive a load of 10.3 k ? . all audio outputs will withstand a sustained 300 ? to ground without damage. parameter condition min nom max unit input impedance 110 160 210 k ? output impedance 1.6 5 ? audio gain control f in = 1.0 khz register 1 = xxx0xxxx register 1 = xxx1xxxx 0 6 db db 0.5 vrms input, flat within 0.3 db 20 khz frequency response measured -3 db point 100 khz dynamic range a weighting filter f in = 1.0 khz, 2.0 vrms 90 100 db signal to noise ratio a weighting filter f in = 1.0 khz, 2.0 vrms 90 100 db distortion (thd) 0.5 vrms output 0.03 % 2 vrms output 0.1 % dc offset -250 250 mv output phase matching f in = 1.0 khz, 0.5 vrms 0.5 deg. cross talk f in = 1.0 khz, 2.0 vrms 75 100 db audio to video path skew video input = 1.0 vpp @ 100 khz audio input = 0.5 vrms @ 1.0 khz 150 ns tv function pin characteristics parameter condition min nom max unit output load @ func_out 10 k ? with output load, 10k ?, vin = 12v 290 500 ? with output load, 10k ?, vin = 9.5v 350 500 ? series resistance with output load, 10k ?, vin = 7v 220 500 ? fast blanking (fb) pin characteristics parameter condition min nom max unit input impedance fb1, fb2, fb3 100 k ? input logical ?0? 0.0 0.4 v blanking input level input logical ?1? 1.0 3.0 v blanking delay fb to rgb signals -50 50 ns output load @ fb_out 300 ? fb gain 1.0 v/v
avpro? 5303b universal 3-input a/v switch interface data sheet page: 12 of 16 ? 2005 teridian semiconductor corporation rev 1.0 application diagram : (for tv 2/3-scart application) 75 (sc1) fb2 fb_out fb3 fb1 mux func2 func3 func1 gn2 gn3 mux gn1 mux bl2 bl3 bl1 mux rd2 rd3 rd1 mux cvbs1 cvbs2 cvbs3 mux r1 r2 r3 l1 l2 l3 func_out gn_out bl_out rd_out cvbs_out r_out l_out mux mux gain sclk sdata serial port vref rbias tgen support circuits pdwn vcc vcc vdd vcc gnd gnd gnd gnd 0v/6v/12v 0/6db gain 1 2 19 20 21 0.01uf 75 0.01uf 75 0.01uf 75 0.01uf 75 0.1uf 10k 0.1uf 10k (sc2) (sc1) (sc3) (sc2) (sc3) (sc1) (sc2) (sc3) (sc2) (sc3) (sc2) (sc3) (sc2) (sc3) (sc1) (sc1) (sc2) (sc3) (sc2) (sc3) (sc1) (sc1) (sc1) (sc3) (sc2) 470pf 10k 1uf 10k 10uf 10k 10uf 75 75 75 75 75 75 100k 75 micro (sc1) 75 dev_addr 300
avpro? 5303b universal 3-input a/v switch interface data sheet page: 13 of 16 ? 2005 teridian semiconductor corporation rev 1.0 application diagram: (dual avpro? 5303b application) 5303b (device address = 1001000x) sclk sdata (sc3) (sc2) micro dev_addr (sc1) 5303b (device address = 1010000x) sclk sdata dev_addr input #1 input #1 input #1 output #1 output #2 not connected gnd
avpro? 5303b universal 3-input a/v switch interface data sheet page: 14 of 16 ? 2005 teridian semiconductor corporation rev 1.0 package pin designation (top view) fb1 gn_out rd_out cvbs1 cvbs_out fb_out bl_out vcc gnd gn3 rd3 bl3 fb3 cvbs3 gnd vcc tgen sdata sclk dev_addr pdwn vdd gnd func1 rd1 gn1 bl1 cvbs2 fb2 rd2 gn2 bl2 vcc gnd rbias n/c l_out l2 r3 l3 r_out r1 l1 r2 vref func3 func2 func_out 6 7 8 13 5 4 3 2 1 28 29 30 31 36 35 34 33 14 15 16 17 18 19 20 44 43 42 41 40 39 38 37 avpro 5303b 48 9 10 11 12 47 21 22 23 24 26 25 27 32 46 45
avpro? 5303b universal 3-input a/v switch interface data sheet page: 15 of 16 ? 2005 teridian semiconductor corporation rev 1.0 mechanical drawing 48qfn package top view 1.975 / 2.125 bottom view 0.24 / 0.6 0.24 / 0.6 0.4 0.65 nom. / 0.7max. 0.85 nom. / 0.9max. 0.00 / 0.005 0.20 ref. seating plane side view 12o max 1 2 3 3 2.875 6 5.75 2.875 3 6 5.75 1 2 3 0.45 0.35 min. 0.35 min. 3.95 / 4.25 1.975 / 2.125 1.975 / 2.125 0.15 / 0.25
avpro? 5303b universal 3-input a/v switch interface data sheet page: 16 of 16 ? 2005 teridian semiconductor corporation rev 1.0 ordering information part description order no. package mark avpro ? 5303b universal 3-input a/v switch interface (48 qfn) avpro ? 5303b-cm avpro ? 5303b-cm avpro ? 5303b universal 3-input a/v switch interface (48 qfn) tape and reel avpro ? 5303b-cmr avpro ? 5303b-cm avpro ? 5303b universal 3-input a/v switch interface (48 qfn) lead free avpro ? 5303b-cm/f avpro ? 5303b-cm avpro ? 5303b universal 3-input a/v switch interface (48 qfn) lead free, tape and reel avpro ? 5303b-cmr/f avpro ? 5303b-cm this product is sold subject to the term s and conditions of sale supplied at the ti me of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. teridi an semiconductor corporation (tsc) reserves the right to make changes in specifications at any time without notice. accordingly, the reader is cautioned to ve rify that a data sheet is current before p lacing orders. tsc assumes no liability for applications assistance. teridian semiconductor corporation, 6440 oak canyon road, irvine, ca 92618-5201 tel (714) 508-8800, fax (714) 508-8875, http://www.teridian.com ? 2005 ? teridian semiconductor corporation 12/16/05 ? rev 1.0

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